; RUN: clspv-opt --passes=replace-opencl-builtin,replace-llvm-intrinsics %s -o %t.ll
; RUN: FileCheck %s < %t.ll

; AUTO-GENERATED TEST FILE
; This test was generated by add_sat_test_gen.cpp.
; Please modify the that file and regenerate the tests to make changes.

target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
target triple = "spir-unknown-unknown"

define i64 @add_sat_long(i64 %a, i64 %b) {
entry:
 %call = call i64 @_Z7add_satll(i64 %a, i64 %b)
 ret i64 %call
}

declare i64 @_Z7add_satll(i64, i64)

; CHECK: [[add:%[a-zA-Z0-9_.]+]] = add i64 %a, %b
; CHECK: [[b_lt_0:%[a-zA-Z0-9_.]+]] = icmp slt i64 %b, 0
; CHECK: [[add_gt_a:%[a-zA-Z0-9_.]+]] = icmp sgt i64 [[add]], %a
; CHECK: [[add_lt_a:%[a-zA-Z0-9_.]+]] = icmp slt i64 [[add]], %a
; CHECK: [[min_clamp:%[a-zA-Z0-9_.]+]] = select i1 [[add_gt_a]], i64 -9223372036854775808, i64 [[add]]
; CHECK: [[max_clamp:%[a-zA-Z0-9_.]+]] = select i1 [[add_lt_a]], i64 9223372036854775807, i64 [[add]]
; CHECK: [[sel:%[a-zA-Z0-9_.]+]] = select i1 [[b_lt_0]], i64 [[min_clamp]], i64 [[max_clamp]]
; CHECK: ret i64 [[sel]]