chip soc/intel/alderlake

	register "pmc_gpe0_dw0" = "GPP_B"
	register "pmc_gpe0_dw1" = "GPP_D"
	register "pmc_gpe0_dw2" = "GPP_E"

	register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)"
	register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)"
	register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)"
	register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)"
	register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)"
	register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)"
	register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # microSD card reader
	register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)"

	register "pch_pcie_rp[PCH_RP(1)]" = "{
		.clk_src = 0,
		.clk_req = 0,
		.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
	}"

	register "pch_pcie_rp[PCH_RP(7)]" = "{
		.clk_src = 1,
		.clk_req = 1,
		.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT | PCIE_RP_BUILT_IN,
		.pcie_rp_aspm = ASPM_L0S,
	}"

	register "pch_pcie_rp[PCH_RP(9)]" = "{
		.clk_src = 2,
		.clk_req = 2,
		.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT | PCIE_RP_BUILT_IN,
		.pcie_rp_aspm = ASPM_L0S,
	}"

	register "pch_pcie_rp[PCH_RP(10)]" = "{
		.clk_src = 3,
		.clk_req = 3,
		.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT | PCIE_RP_BUILT_IN,
		.pcie_rp_aspm = ASPM_L0S,
	}"

	register "pch_pcie_rp[PCH_RP(11)]" = "{
		.clk_src = 4,
		.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
		.pcie_rp_aspm = ASPM_L0S,
	}"

	register "pch_pcie_rp[PCH_RP(12)]" = "{
		.clk_src = 4,
		.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
		.pcie_rp_aspm = ASPM_L0S,
	}"

	register "ddi_ports_config" = "{
		[DDI_PORT_A] = DDI_ENABLE_HPD,
		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
	}"

	device domain 0 on
		device ref igpu on end
		device ref crashlog off end
		device ref xhci on end
		device ref shared_sram on end
		device ref pcie_rp1 on end
		device ref pcie_rp7 on end
		device ref pcie_rp9 on end
		device ref pcie_rp10 on end
		device ref pcie_rp11 on end
		device ref pcie_rp12 on end # M.2 E key port
		device ref pch_espi on
			register "gen1_dec" = "0x00fc0201"
			register "gen2_dec" = "0x003c0a01"
			register "gen3_dec" = "0x000c0081"
			chip superio/ite/it8613e
				register "FAN2.mode"   = "FAN_SMART_SOFTWARE" # CPU_FAN
				register "FAN3.mode"   = "FAN_SMART_SOFTWARE" # SYS_FAN
				device pnp 2e.0 off end
				device pnp 2e.1 on       # COM 1
					io 0x60 = 0x3f8
					irq 0x70 = 0x4
					irq 0xf0 = 0x1
				end
				device pnp 2e.4 on       # Environment Controller
                                        io 0x60 = 0x0a30
                                        io 0x62 = 0x0a20
                                        irq 0x70 = 0x00
                                        irq 0x71 = 0x80
				end
				device pnp 2e.5 off end  # Keyboard
				device pnp 2e.6 off end  # Mouse
				device pnp 2e.7 off end  # GPIO
				device pnp 2e.a off end  # CIR
			end
		end
		device ref hda on end
		device ref smbus on end
		chip drivers/crb
			device mmio 0xfed40000 on end
		end
	end
end