chip soc/intel/skylake

	# IGD Displays
	register "gfx" = "GMA_STATIC_DISPLAYS(0)"

	register "panel_cfg" = "{
		.up_delay_ms		= 200,
		.down_delay_ms		=  50,
		.cycle_delay_ms		= 600,
		.backlight_on_delay_ms	=   1,
		.backlight_off_delay_ms	= 200,
		.backlight_pwm_hz	= 200,
	}"

	# Deep Sx states
	register "deep_s3_enable_ac" = "false"
	register "deep_s3_enable_dc" = "false"
	register "deep_s5_enable_ac" = "true"
	register "deep_s5_enable_dc" = "true"
	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"

	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	register "gpe0_dw0" = "GPP_A"
	register "gpe0_dw1" = "GPP_B"
	register "gpe0_dw2" = "GPP_E"

	# Enable DPTF
	register "dptf_enable" = "true"

	# Enable S0ix
	register "s0ix_enable" = true

	# Disable Command TriState
	register "CmdTriStateDis" = "1"

	# FSP Configuration
	register "DspEnable" = "true"
	register "IoBufferOwnership" = "3"
	register "ScsEmmcHs400Enabled" = "1"
	register "SkipExtGfxScan" = "1"
	register "SaGv" = "SaGv_Enabled"
	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
	register "PmConfigSlpS4MinAssert" = "1"        # 1s
	register "PmConfigSlpSusMinAssert" = "1"       # 500ms
	register "PmConfigSlpAMinAssert" = "3"         # 2s

	register "power_limits_config" = "{
		.tdp_pl1_override = 7,
		.tdp_pl2_override = 15,
		.psys_pmax = 45,
	}"
	register "tcc_offset" = "10"

	# VR Settings Configuration for 4 Domains
	#+----------------+-------+-------+-------+-------+
	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
	#+----------------+-------+-------+-------+-------+
	#| Psi1Threshold  | 20A   | 20A   | 20A   | 20A   |
	#| Psi2Threshold  | 2A    | 2A    | 2A    | 2A    |
	#| Psi3Threshold  | 1A    | 1A    | 1A    | 1A    |
	#| Psi3Enable     | 1     | 1     | 1     | 1     |
	#| Psi4Enable     | 1     | 1     | 1     | 1     |
	#| ImonSlope      | 0     | 0     | 0     | 0     |
	#| ImonOffset     | 0     | 0     | 0     | 0     |
	#| IccMax         | set by SoC code per CPU SKU   |
	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
	#| AcLoadline     | 16.20 | 5.24  | 4.62  | 4.62  |
	#| DcLoadline     | 14.2  | 4.94  | 4.25  | 4.25  |
	#+----------------+-------+-------+-------+-------+
	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(2),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.voltage_limit = 1520,
		.ac_loadline = 1620,
		.dc_loadline = 1420,
	}"

	register "domain_vr_config[VR_IA_CORE]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(2),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.voltage_limit = 1520,
		.ac_loadline = 524,
		.dc_loadline = 494,
	}"

	register "domain_vr_config[VR_GT_UNSLICED]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(2),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.voltage_limit = 1520,
		.ac_loadline = 462,
		.dc_loadline = 425,
	}"

	register "domain_vr_config[VR_GT_SLICED]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(2),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.voltage_limit = 1520,
		.ac_loadline = 462,
		.dc_loadline = 425,
	}"

	# Intel Common SoC Config
	#+-------------------+---------------------------+
	#| Field             |  Value                    |
	#+-------------------+---------------------------+
	#| GSPI0             | cr50 TPM. Early init is   |
	#|                   | required to set up a BAR  |
	#|                   | for TPM communication     |
	#|                   | before memory is up       |
	#| I2C0              | Touchscreen               |
	#| I2C2              | Trackpad                  |
	#| I2C3              | Camera                    |
	#| I2C4              | Audio                     |
	#| pch_thermal_trip  | PCH Trip Temperature      |
	#+-------------------+---------------------------+
	register "common_soc_config" = "{
		.i2c[0] = {
			.speed = I2C_SPEED_FAST,
			.rise_time_ns = 98,
			.fall_time_ns = 38,
		},
		.i2c[2] = {
			.speed = I2C_SPEED_FAST,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST,
				.scl_lcnt = 186,
				.scl_hcnt = 93,
				.sda_hold = 36,
			},
		},
		.i2c[3] = {
			.speed = I2C_SPEED_FAST,
			.rise_time_ns = 98,
			.fall_time_ns = 38,
		},
		.i2c[4] = {
			.speed = I2C_SPEED_FAST,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST,
				.scl_lcnt = 176,
				.scl_hcnt = 95,
				.sda_hold = 36,
			}
		},
		.gspi[0] = {
			.speed_mhz = 1,
			.early_init = 1,
		},
		.pch_thermal_trip = 75,
	}"
	# Touchscreen
	register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"

	# Trackpad
	register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"

	# Camera
	register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"

	# Audio
	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"

	register "SerialIoDevMode" = "{
		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
		[PchSerialIoIndexSpi0]  = PchSerialIoPci,
		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled,
		[PchSerialIoIndexUart0] = PchSerialIoSkipInit,
		[PchSerialIoIndexUart1] = PchSerialIoDisabled,
		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
	}"

	device domain 0 on
		device ref igpu			on  end
		device ref sa_thermal		on  end
		device ref imgu			on  end
		device ref south_xhci		on
			register "usb2_ports" = "{
				[0] = USB2_PORT_LONG(OC0),	// Type-C Port 1
				[2] = USB2_PORT_SHORT(OC_SKIP),	// Bluetooth
				[4] = USB2_PORT_LONG(OC1),	// Type-C Port 2
			}"

			register "usb3_ports" = "{
				[0] = USB3_PORT_DEFAULT(OC0),	// Type-C Port 1
				[1] = USB3_PORT_DEFAULT(OC1),	// Type-C Port 2
			}"

			chip drivers/usb/acpi
				register "desc" = ""Root Hub""
				register "type" = "UPC_TYPE_HUB"
				device usb 0.0 on
					chip drivers/usb/acpi
						register "desc" = ""USB Type C Port 1""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						device usb 2.0 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Bluetooth""
						register "type" = "UPC_TYPE_INTERNAL"
						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E2)"
						device usb 2.2 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB Type C Port 2""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						device usb 2.4 on end
					end
				end
			end
		end
		device ref south_xdci		on  end
		device ref thermal		on  end
		device ref cio			on  end
		device ref i2c0			on
			chip drivers/i2c/hid
				register "generic.hid" = ""ACPI0C50""
				register "generic.desc" = ""STM Touchscreen""
				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
				register "generic.speed" = "I2C_SPEED_FAST"
				register "generic.has_power_resource" = "1"
				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)"
				# 2ms for load switch slew + 5 ms for touchscreen
				register "generic.enable_delay_ms" = "7"
				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)"
				register "generic.reset_delay_ms" = "20"
				register "generic.reset_off_delay_ms" = "1"
				register "hid_desc_reg_offset" = "0xab"
				device i2c 0x49 on end
			end
		end
		device ref i2c2			on
			chip drivers/i2c/hid
				register "generic.hid" = ""ACPI0C50""
				register "generic.desc" = ""ELAN Touchpad""
				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A19_IRQ)"
				register "generic.wake" = "GPE0_DW0_23" # GPP_A23
				register "hid_desc_reg_offset" = "0x01"
				device i2c 0x15 on end
			end
		end
		device ref i2c3			on  end # Camera
		device ref heci1		on  end
		device ref uart2		on  end
		device ref i2c4			on
			chip drivers/i2c/max98373
				register "vmon_slot_no" = "4"
				register "imon_slot_no" = "5"
				register "uid" = "0"
				register "desc" = ""RIGHT SPEAKER AMP""
				register "name" = ""MAXR""
				device i2c 31 on end
			end
			chip drivers/i2c/max98373
				register "vmon_slot_no" = "6"
				register "imon_slot_no" = "7"
				register "uid" = "1"
				register "desc" = ""LEFT SPEAKER AMP""
				register "name" = ""MAXL""
				device i2c 32 on end
			end
			chip drivers/i2c/da7219
				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)"
				register "btn_cfg" = "50"
				register "mic_det_thr" = "200"
				register "jack_ins_deb" = "20"
				register "jack_det_rate" = ""32ms_64ms""
				register "jack_rem_deb" = "1"
				register "a_d_btn_thr" = "0xa"
				register "d_b_btn_thr" = "0x16"
				register "b_c_btn_thr" = "0x21"
				register "c_mic_btn_thr" = "0x3e"
				register "btn_avg" = "4"
				register "adc_1bit_rpt" = "1"
				register "micbias_lvl" = "2600"
				register "mic_amp_in_sel" = ""diff""
				device i2c 1a on end
			end
		end
		device ref pcie_rp1		on
			# WLAN
			register "PcieRpClkReqSupport[0]" = "1"
			register "PcieRpClkReqNumber[0]" = "1"
			register "PcieRpClkSrcNumber[0]" = "1"
			register "PcieRpAdvancedErrorReporting[0]" = "1"
			register "PcieRpLtrEnable[0]" = "true"
			chip drivers/wifi/generic
				register "wake" = "GPE0_DW1_07" # GPP_B7
				device pci 00.0 on end
			end
		end
		device ref uart0	 	on  end
		device ref gspi0		on
			chip drivers/spi/acpi
				register "hid" = "ACPI_DT_NAMESPACE_HID"
				register "compat_string" = ""google,cr50""
				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
				device spi 0 on end
			end
		end
		device ref emmc 		on  end
		device ref lpc_espi		on
			# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
			register "gen1_dec" = "0x00fc0801"
			register "gen2_dec" = "0x000c0201"
			# EC memory map range is 0x900-0x9ff
			register "gen3_dec" = "0x00fc0901"

			chip ec/google/chromeec
				device pnp 0c09.0 on end
			end
		end
		device ref hda 			on  end
		device ref smbus	 	on  end
		device ref fast_spi	 	on  end
	end
end