chip soc/intel/cannonlake

	# FSP configuration
	register "SaGv" = "SaGv_Enabled"
	register "ScsEmmcHs400Enabled" = "1"

	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
	register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
	register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"

	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"

	register "PchHdaDspEnable" = "true"
	register "PchHdaAudioLinkHda" = "1"

	register "PcieClkSrcUsage[0]" = "1"
	register "PcieClkSrcUsage[1]" = "8"
	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
	register "PcieClkSrcUsage[3]" = "13"
	register "PcieClkSrcUsage[4]" = "4"
	register "PcieClkSrcUsage[5]" = "14"

	register "PcieClkSrcClkReq[0]" = "0"
	register "PcieClkSrcClkReq[1]" = "1"
	register "PcieClkSrcClkReq[2]" = "2"
	register "PcieClkSrcClkReq[3]" = "3"
	register "PcieClkSrcClkReq[4]" = "4"
	register "PcieClkSrcClkReq[5]" = "5"

	# Disable S0ix
	register "s0ix_enable" = "false"

	device domain 0 on
		device ref igpu on  end
		device ref dptf on  end
		device ref thermal on  end
		device ref xhci on  end
		device ref sdxc on  end
		device ref uart0 on  end
		device ref lpc_espi on
			chip drivers/pc80/tpm
				device pnp 0c31.0 on end
			end
		end
		device ref hda on  end
		device ref smbus on  end
	end
end