chip soc/intel/cannonlake

	# FSP configuration
	register "RMT" = "1"

	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)"
	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"
	register "usb2_ports[2]" = "USB2_PORT_MID(OC2)"
	register "usb2_ports[3]" = "USB2_PORT_MID(OC5)"
	register "usb2_ports[4]" = "USB2_PORT_MID(OC5)"
	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
	register "usb2_ports[6]" = "USB2_PORT_MID(OC1)"
	register "usb2_ports[7]" = "USB2_PORT_MID(OC1)"
	register "usb2_ports[9]" = "USB2_PORT_MID(OC3)"
	register "usb2_ports[10]" = "USB2_PORT_MID(OC3)"
	register "usb2_ports[11]" = "USB2_PORT_MID(OC6)"
	register "usb2_ports[12]" = "USB2_PORT_MID(OC6)"

	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)"
	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"
	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC5)"
	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC5)"
	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
	register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC1)"
	register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC1)"
	register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
	register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC3)"

	register "SataSalpSupport" = "1"
	register "SataPortsEnable[0]" = "1"
	register "SataPortsEnable[1]" = "1"
	register "SataPortsEnable[2]" = "1"
	register "SataPortsEnable[3]" = "1"
	register "SataPortsEnable[4]" = "1"
	register "SataPortsEnable[5]" = "1"
	register "SataPortsEnable[6]" = "1"
	register "SataPortsEnable[7]" = "1"

	register "PchHdaDspEnable" = "false"
	register "PchHdaAudioLinkHda" = "1"

	register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
	register "PcieClkSrcUsage[1]" = "8"
	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
	register "PcieClkSrcUsage[3]" = "0x6"
	register "PcieClkSrcUsage[4]" = "0x18"
	register "PcieClkSrcUsage[5]" = "1"
	register "PcieClkSrcUsage[6]" = "0x8"
	register "PcieClkSrcUsage[8]" = "0x40"
	register "PcieClkSrcUsage[9]" = "PCIE_CLK_NOTUSED"
	register "PcieClkSrcUsage[10]" = "0x14"

	register "PcieClkSrcClkReq[0]" = "0"
	register "PcieClkSrcClkReq[1]" = "1"
	register "PcieClkSrcClkReq[2]" = "2"
	register "PcieClkSrcClkReq[3]" = "3"
	register "PcieClkSrcClkReq[4]" = "4"
	register "PcieClkSrcClkReq[5]" = "5"
	register "PcieClkSrcClkReq[6]" = "6"
	register "PcieClkSrcClkReq[8]" = "8"
	register "PcieClkSrcClkReq[9]" = "9"
	register "PcieClkSrcClkReq[10]" = "10"

	device domain 0 on
		device ref cnvi_wifi on
			chip drivers/wifi/generic
				register "wake" = "PME_B0_EN_BIT"
				device generic 0 on end
			end
		end
		device ref i2c0 on  end
		device ref i2c1 on  end
		device ref i2c2 on  end
		device ref i2c3 on  end
		device ref sata on  end
		device ref uart2 on  end
		device ref emmc on  end
		device ref pcie_rp1 on
			register "PcieRpSlotImplemented[0]" = "true"
		end
		device ref pcie_rp5 on
			register "PcieRpSlotImplemented[4]" = "true"
		end
		device ref pcie_rp9 on	# x4 SLOT 1
			register "PcieRpSlotImplemented[8]" = "true"
		end
		device ref pcie_rp17 on
			register "PcieRpSlotImplemented[16]" = "true"
		end
		device ref pcie_rp18 on
			register "PcieRpSlotImplemented[17]" = "true"
		end
		device ref pcie_rp19 on
			register "PcieRpSlotImplemented[18]" = "true"
		end
		device ref pcie_rp20 on
			register "PcieRpSlotImplemented[19]" = "true"
		end
		device ref pcie_rp21 on	# x4 SLOT 2
			register "PcieRpSlotImplemented[20]" = "true"
		end
		device ref gbe on  end
	end
end