chip soc/intel/skylake

	# Enable deep Sx states
	register "deep_s5_enable_ac" = "false"
	register "deep_s5_enable_dc" = "false"
	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"

	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	register "gpe0_dw0" = "GPP_B"
	register "gpe0_dw1" = "GPP_D"
	register "gpe0_dw2" = "GPP_E"

	# Enable DPTF
	register "dptf_enable" = "true"

	# FSP Configuration
	register "IoBufferOwnership" = "0"
	register "ScsEmmcHs400Enabled" = "1"
	register "SkipExtGfxScan" = "1"
	register "SaGv" = "SaGv_Enabled"
	register "PchHdaVcType" = "Vc1"

	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
	register "PmConfigSlpS3MinAssert" = "2"

	# SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
	register "PmConfigSlpS4MinAssert" = "4"

	# SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
	register "PmConfigSlpSusMinAssert" = "3"

	# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
	register "PmConfigSlpAMinAssert" = "3"


	# VR Settings Configuration for 4 Domains
	#+----------------+-------+-------+-------+-------+
	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
	#+----------------+-------+-------+-------+-------+
	#| Psi1Threshold  | 20A   | 20A   | 20A   | 20A   |
	#| Psi2Threshold  | 4A    | 5A    | 5A    | 5A    |
	#| Psi3Threshold  | 1A    | 1A    | 1A    | 1A    |
	#| Psi3Enable     | 1     | 1     | 1     | 1     |
	#| Psi4Enable     | 1     | 1     | 1     | 1     |
	#| ImonSlope      | 0     | 0     | 0     | 0     |
	#| ImonOffset     | 0     | 0     | 0     | 0     |
	#| IccMax         | 7A    | 34A   | 35A   | 35A   |
	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
	#+----------------+-------+-------+-------+-------+
	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(4),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0,
		.imon_offset = 0,
		.icc_max = VR_CFG_AMP(7),
		.voltage_limit = 1520
	}"

	register "domain_vr_config[VR_IA_CORE]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0,
		.imon_offset = 0,
		.icc_max = VR_CFG_AMP(34),
		.voltage_limit = 1520
	}"

	register "domain_vr_config[VR_GT_UNSLICED]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0,
		.imon_offset = 0,
		.icc_max = VR_CFG_AMP(35),
		.voltage_limit = 1520
	}"

	register "domain_vr_config[VR_GT_SLICED]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0,
		.imon_offset = 0,
		.icc_max = VR_CFG_AMP(35),
		.voltage_limit = 1520
	}"

	# Send an extra VR mailbox command for the PS4 exit issue
	register "SendVrMbxCmd" = "2"

	device domain 0 on
		device ref igpu		on  end
		device ref sa_thermal	on  end
		device ref south_xhci	on  end
		device ref thermal	on  end
		device ref i2c0		on  end
		device ref i2c1		on  end
		device ref i2c2		on  end
		device ref i2c3		on  end
		device ref heci1	on  end
		device ref uart2	on  end
		device ref i2c4		on  end
		device ref pcie_rp1	on  end
		device ref pcie_rp9	on  end
		device ref uart0	on  end
		device ref emmc		on  end
		device ref sdxc		on  end
		device ref smbus	on  end
		device ref lpc_espi	on
			# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
			register "gen1_dec" = "0x00fc0801"
		end
		device ref fast_spi	on  end
	end
end