chip northbridge/intel/sandybridge
	register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}"
	device domain 0 on
		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
			device ref pcie_rp7 on end # USB 3.0
		end
	end
end