/* SPDX-License-Identifier: GPL-2.0-only */

#include <memlayout.h>
#include <arch/header.ld>

/* Copied from Qualcomm previous generation SoC SC7280 and need cleanup */

/* SYSTEM_IMEM : 0x14680000 - 0x146AB000 */
#define SSRAM_START(addr) REGION_START(ssram, addr)
#define SSRAM_END(addr) REGION_END(ssram, addr)

/* BOOT_IMEM   : 0x14800000 - 0x14980000 */
#define BSRAM_START(addr) REGION_START(bsram, addr)
#define BSRAM_END(addr) REGION_END(bsram, addr)

/* AOP : 0x0B000000 - 0x0B100000 */
#define AOPSRAM_START(addr) REGION_START(aopsram, addr)
#define AOPSRAM_END(addr) REGION_END(aopsram, addr)

SECTIONS
{
	AOPSRAM_START(0x0B000000)
	REGION(aop_code_ram, 0x0B000000, 0x80000, 4096)
	REGION(aop_data_ram, 0x0B0E0000, 0x20000, 4096)
	AOPSRAM_END(0x0B100000)

	SSRAM_START(0x14680000)
	REGION(qcsdi, 0x14699000, 48K, 4K)
	REGION(shared_imem, 0x146A8000, 12K, 4K)
	SSRAM_END(0x146AB000)

	BSRAM_START(0x14800000)
	REGION(pbl_timestamps, 0x14800000, 84K, 4K)
	WATCHDOG_TOMBSTONE(0x14818FFC, 4)
	BOOTBLOCK(0x14819000, 60K)
	PRERAM_CBFS_CACHE(0x14828000, 103K)
	TIMESTAMP(0x14841C00, 1K)
	TTB(0x14842000, 56K)
	STACK(0x14850000, 16K)
	VBOOT2_WORK(0x14854000, 12K)
	DMA_COHERENT(0x14857000, 8K)
	REGION(qclib_serial_log, 0x1485B000, 4K, 4K)
	CBFS_MCACHE(0x1485C000,16K)
	REGION(ddr_information, 0x14860000, 1K, 1K)
	FMAP_CACHE(0x14860400, 2K)
	REGION(dcb, 0x14862000, 56K, 4K)
	REGION(dtb, 0x14870000, 32K, 4K)
	REGION(ddr_training, 0x14878000, 64K, 4K)
	REGION(qc_blob_meta, 0x14888000, 16K, 4K)
	REGION(qclib, 0x14897000, 1536K, 4K)
	PRERAM_CBMEM_CONSOLE(0x14A30000, 32K)
	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14A38000, 132K)
	REGION(auth_metadata,0x14A7D000 , 8K, 4K)
	REGION(debug_policy, 0x14A7F000, 4K, 4K)
	BSRAM_END(0x14A80000)

	REGION(shrm, 0x24040000, 128K , 4K)

	DRAM_START(0x80000000)
	POSTRAM_CBFS_CACHE(0x9F800000, 16M)
	RAMSTAGE(0xA0800000, 16M)
	BL31(0xC0000000, 1M)
}