]> &otherfile; BMG BMG OOBMSM PMT Telemetry aggregator samples definition and transformation rules 0x5E2F8211 BMG 0 Groupname 0x1090 64 This field indicates the maximum RP0 base frequency capability for the Integrated GFX Engine GT. Values are in units of 16.67 MHz bins. GT P0,P1,Pn Frequencies RP_STATE_CAP_0_0_0_PCU Snapshot 9 0 8 This field indicates the maximum RPN base frequency capability for the Integrated GFX Engine GT. Values are in units of 16.67 MHz bins. GT P0,P1,Pn Frequencie RP_STATE_CAP_0_0_0_PCU Snapshot 9 16 24 The efficient GT P-state in 16.67 MHz bins. Efficient frequency RPe for GT GT_RPE_FREQUENCY Snapshot 9 32 40 Groupname 0x1098 64 RAPL Frequency constraint for GT. GT_RPA_FREQUENCY Snapshot 9 0 8 HW reflects CV voltage of GT slice0 DomainID = 1 to this field, in 2.5mV granularity. GT_PERF_STATUS_0_2_0_GTTMMADR Snapshot 11 32 42 Present GT frequency and VID. GT_PERF_STATUS_0_2_0_GTTMMADR Snapshot 9 43 51 Present GT frequency and VID. GT_PERF_STATUS_0_2_0_GTTMMADR Snapshot 4 52 55 Present GT frequency and VID. GT_PERF_STATUS_0_2_0_GTTMMADR Snapshot 8 56 63 Groupname 0x10a0 64 If Frequency is clipped because of Prochot GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 0 0 If Frequency is clipped because of Package thermals either SoC die or ADM die or GDDR device GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 1 1 If frequency is clipped because VR is hitting FastVMode. GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 2 2 PCS_LIMIT: Limited via PCS GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 3 3 If frequency clipping is happening because of ICCMAX checks. GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 4 4 Running average thermal limit Status, If Frequency is clipped because of RATL thermal algorithm GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 5 5 Hot VR Status, RO, When set by PCODE indicates that Hot VR has cause GT frequency clipping. GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 6 6 VR TDC Thermal design current Status, RO, When set by PCODE indicates that VR TDC . Thermal design current has cause MEDIA frequency clipping. GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 7 7 If frequency clipping is happening because of PL4 checks GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 8 8 If frequency clipping is happening because of max. VID checks GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 9 9 If frequency clipping is happening because of Package/Psys PL1. GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 10 10 If frequency clipping is happening because of Package/Psys PL2/PL3. RO_V[/IntelRsvd] GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 11 11 If operating frequency is less than Rpe GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 12 12 MAX_TURBO_LIMIT: GT n-slice fused limit was hit, causing GT frequency clipping GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 13 13 Resolved Pkg PL1 power limit is less than advertised Minimum Value PACKAGE_POWER_SKU.PKG_MIN_PWR GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 14 14 If frequency clipping is happening because of psys_crit. GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 15 15 PROCHOT# Log, RW, When set by PCODE indicates that PROCHOT# has cause GT frequency clipping. Software should write to this bit to clear the status in this bit GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 16 16 Thermal Log, RW, When set by PCODE indicates that Package thermals either SoC die or ADM die or GDDR device non RATL/VR related thermal clipping have caused GT frequency clipping. Software should write to this bit to clear the status in this bit GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 17 17 PBM_DDR_LOG status GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 18 18 PCS_LIMIT status GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 19 19 Reserved GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 20 20 Running average thermal limit Log, RW, When set by PCODE indicates that Running average thermal limit has cause GT frequency clipping. Software should write to this bit to clear the status in this bit GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 21 21 Hot VR Log, RW, When set by PCODE indicates that Hot VR has cause GT frequency clipping. Software should write to this bit to clear the status in this bit GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 22 22 VR TDC Log, RW, When set by PCODE indicates that VR TDC . Thermal design current has cause GT frequency clipping. Software should write to this bit to clear the status in this bit GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 23 23 Other Status, RO, When set by PCODE, indicates that other checks IccMax, PL4 have caused GT frequency clipping. Software should write to this bit to clear the status in this bit GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 24 24 Max VID Status, RO, When set by PCODE, indicates that max VID checks have caused GT frequency clipping. Software should write to this bit to clear the status in this bit GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 25 25 PBM PL1 Log, RW, When set by PCODE indicates that PBM PL1 package or platform PL1 has cause GT frequency clipping. Software should write to this bit to clear the status in this bit GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 26 26 PBM PL2, PL3 pkg, platform Log, RW, When set by PCODE indicates that PBM PL2 or PL3 package or platform PL2 or PL3 has cause GT frequency clipping. Software should write to this bit to clear the status in this bit GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 27 27 Inefficient operation Log, RW, The current GT Frequency lower than the DCC target Frequency. Software should write to this bit to clear the status in this bit GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 28 28 MAX_TURBO_LIMIT status GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 29 29 Resolved Pkg PL1 power limit is less than advertised Minimum Value PACKAGE_POWER_SKU.PKG_MIN_PWR. Software should write to this bit to clear the status in this bit GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 30 30 PSYS_CRIT, RO, When set by PCODE, indicates that PSYS_CRIT has caused GT frequency clipping. Software should write to this bit to clear the status in this bit GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 31 31 This register contains the total RC6 residency time that GT was in since boot. The counter will wrap around. The time is given in units of 1.28 uSec. GT RC6 residency GT_GFX_RC6_0_2_0_GTTMMADR Counter 32 32 63 Groupname 0x10a8 64 GT C0 residency. GT C0 residency. PKG_GT_C0_ANY_0_2_0_GTTMMADR Counter 64 0 63 Groupname 0x10b0 64 Sum the cycles if EU is active. Sum the cycles if EU is active. PKG_GT_C0_ANY_SLICE_0_2_0_GTTMMADR Counter 64 0 63 Groupname 0x10b8 64 Useful for determining GT Average Frequency when it is in C0. Useful for determining GT Average Frequency when it is in C0. PKG_GT_C0_ANY_RATIO_0_2_0_GTTMMADR Counter 64 0 63 Groupname 0x10c0 64 Useful for determining GT Average Frequency when EU is active. Useful for determining GT Average Frequency when EU is active. PKG_GT_C0_ANY_SLICE_RATIO_0_2_0_GTTMMADR Counter 64 0 63 Groupname 0x10c8 64 GT Temperature SOC_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[2] Snapshot 32 0 31 Media P0,P1,Pn Frequencies. MEDIAP_STATE_CAP_0_0_0_PCU Snapshot 9 32 40 Media P0,P1,Pn Frequencies. MEDIAP_STATE_CAP_0_0_0_PCU Snapshot 9 48 56 Groupname 0x10d0 64 Efficient frequency RPe for Media MEDIA_EFFICIENT_FREQUENCY Snapshot 9 0 8 RAPL Frequency constraint for Media. MPA_FREQUENCY Snapshot 9 32 40 Groupname 0x10d8 64 HW reflects CV voltage of Media to this field, in 2.5mV granularity. MEDIA_PERF_STATUS_0_2_0_GTTMMADR Snapshot 11 0 10 Present Media frequency and VID. MEDIA_PERF_STATUS_0_2_0_GTTMMADR Snapshot 9 11 19 Present Media frequency and VID. MEDIA_PERF_STATUS_0_2_0_GTTMMADR Snapshot 4 20 23 Present Media frequency and VID. MEDIA_PERF_STATUS_0_2_0_GTTMMADR Snapshot 8 24 31 If Frequency is clipped because of Prochot MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 32 32 If Frequency is clipped because of Package thermals either SoC die or ADM die or GDDR device MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 33 33 If frequency is clipped because VR is hitting FastVMode. MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 34 34 PCS_LIMIT: Limited via PCS MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 35 35 If frequency clipping is happening because of ICCMAX checks. MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 36 36 Running average thermal limit Status, If Frequency is clipped because of RATL thermal algorithm MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 37 37 Hot VR Status, RO, When set by PCODE indicates that Hot VR has cause GT frequency clipping. [IntelRsvd]Was RO_VFW changed in CNL to be RO_V[/IntelRsvd] MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 38 38 VR TDC Status, RO, When set by PCODE indicates that VR TDC. Thermal design current has cause MEDIA frequency clipping. MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 39 39 If frequency clipping is happening because of PL4 checks MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 40 40 If frequency clipping is happening because of max. VID checks MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 41 41 If frequency clipping is happening because of Package/Psys PL1. MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 42 42 If frequency clipping is happening because of Package/Psys PL2/PL3. RO_V[/IntelRsvd] MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 43 43 If operating frequency is less than Rpe MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 44 44 MAX_TURBO_LIMIT: GT n-slice fused limit was hit, causing GT frequency clipping MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 45 45 Resolved Pkg PL1 power limit is less than advertised Minimum Value PACKAGE_POWER_SKU.PKG_MIN_PWR MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 46 46 If frequency clipping is happening because of psys_crit. MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 47 47 PROCHOT# Log, RW, When set by PCODE indicates that PROCHOT# has cause MEDIA frequency clipping. Software should write to this bit to clear the status in this bit MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 48 48 Thermal Log, RW, When set by PCODE indicates that Package thermals either SoC die or ADM die or GDDR device MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 49 49 PBM_DDR_LOG status MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 50 50 PCS_LIMIT status MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 51 51 Reserved MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 52 52 Running average thermal limit Log, RW, When set by PCODE indicates that Running average thermal limit has cause MEDIA frequency clipping. Software should write to this bit to clear the status in this bit MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 53 53 Hot VR Log, RW, When set by PCODE indicates that Hot VR has cause MEDIA frequency clipping. Software should write to this bit to clear the status in this bit MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 54 54 VR TDC Thermal design current Log, RW, When set by PCODE indicates that VR TDC .Thermal design current has cause MEDIA frequency clipping. Software should write to this bit to clear the status in this bit MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 55 55 Other IccMax, PL4, etc Status, RO, When set by PCODE, indicates that other checks have caused MEDIA frequency clipping. Software should write to this bit to clear the status in this bit MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 56 56 Max VID Status, RO, When set by PCODE, indicates that max VID checks have caused MEDIA frequency clipping. Software should write to this bit to clear the status in this bit MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 57 57 PBM PL1 Log, RW, When set by PCODE indicates that PBM PL1 has cause MEDIA frequency clipping. Software should write to this bit to clear the status in this bit MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 58 58 PBM PL2, PL3 Log, RW, When set by PCODE indicates that PBM PL2 or PL3, package or platform PL2 or PL3 has cause MEDIA frequency clipping. Software should write to this bit to clear the status in this bit MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 59 59 Inefficient operation Log, RW, The current MEDIA Frequency lower than the DCC target Frequency. Software should write to this bit to clear the status in this bit MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 60 60 MAX_TURBO_LIMIT status MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 61 61 Resolved Pkg PL1 power limit is less than advertised Minimum Value PACKAGE_POWER_SKU.PKG_MIN_PWR. Software should write to this bit to clear the status in this bit MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 62 62 PSYS_CRIT, RO, When set by PCODE, indicates that PSYS_CRIT has caused MEDIA frequency clipping. Software should write to this bit to clear the status in this bit MEDIA_PERF_LIMIT_REASONS_0_2_0_GTTMMADR Snapshot 1 63 63 Groupname 0x10e0 64 This register contains the total MC6 residency time that media was in since boot. The counter will wrap around. The time is given in units of 1.28 uSec. Media MC6 residency. MEDIA_MC6_0_2_0_GTTMMADR Counter 32 0 31 Media Temperature SOC_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[3] Snapshot 32 32 63 Groupname 0x10e8 64 Media C0 residency Media C0 residency PKG_MEDIA_C0_ANY Counter 64 0 63 Groupname 0x10f0 64 Sum the cycles if any Media Engine is active. Sum the cycles if any Media Engine is active. PKG_MEDIA_C0_ANY_SLICE Counter 64 0 63 Groupname 0x10f8 64 Sum the cycles if any Media Engine is active with Media Count Sum the cycles if any Media Engine is active with Media Count PKG_MEDIA_C0_SLICES_SUM Counter 64 0 63 Groupname 0x1100 64 Useful for determining Media Average Frequency when it is in C0 Useful for determining Media Average Frequency when it is in C0 PKG_MEDIA_C0_ANY_RATIO Counter 64 0 63 Groupname 0x1108 64 Useful for determining Media Average Frequency when any Media Engine is active. Useful for determining Media Average Frequency when any Media Engine is active. PKG_MEDIA_C0_ANY_SLICE_RATIO Counter 64 0 63 Groupname 0x1110 64 The TDP package power setting allowed for this part. The units for this value are defined in PACKAGE_POWER_SKU_MSR[PWR_UNIT]. PACKAGE_POWER_SKU_0_0_0_PCU Snapshot 15 0 14 The minimal package power setting allowed for this part. Lower values will be clamped to this value. The minimum setting is typical PACKAGE_POWER_SKU_0_0_0_PCU Snapshot 15 16 30 The maximal package power setting allowed for the SKU. Higher values will be clamped to this value. The maximum setting is typical not guaranteed. PACKAGE_POWER_SKU_0_0_0_PCU Snapshot 15 32 46 The maximal time window allowed for the SKU. Higher values will be clamped to this value. PACKAGE_POWER_SKU_0_0_0_PCU Snapshot 7 48 54 Groupname 0x1118 64 Package Energy Accumulator PACKAGE_ENERGY_STATUS_SKU_0_0_0_PCU Snapshot 32 0 31 Psys GPU Energy Accumulator PLATFORM_ENERGY_STATUS Snapshot 32 32 63 Groupname 0x1120 64 Number of Tachometer Pulses from PWM fan Number of Tachometer Pulses from PWM fan PWM_FAN_SPEED_0_2_0_GTTMMADR Counter 32 0 31 Number of Tachometer Pulses from PWM fan Number of Tachometer Pulses from PWM fan PWM_FAN_2_SPEED_0_2_0_GTTMMADR Counter 32 32 63 Groupname 0x1128 64 Worst Temperature across SoC Top die and ADM Package_Temperature_0_0_0_MCHBAR_PCU Snapshot 8 0 7 Worst case thermal margin available before thermal throttling can occur PACKAGE_THERM_MARGIN_0_0_0_MCHBAR_PCU Snapshot 16 32 47 Groupname 0x1130 64 Worst Temperature across ADM SOC_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[0] Snapshot 32 0 31 Worst Temperature across SoC TopDie. SOC_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[1] Snapshot 32 32 63 Groupname 0x1138 64 Worst Temperature across all GDDR devices VRAM_TEMPERATURE_0_2_0_GTTMMADR Snapshot 8 0 7 GDDR0 device temperature MEMORY_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[0] Snapshot 32 32 63 Groupname 0x1140 64 GDDR0 device temperature MEMORY_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[1] Snapshot 32 0 31 GDDR1 device temperature MEMORY_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[2] Snapshot 32 32 63 Groupname 0x1148 64 GDDR1 device temperature MEMORY_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[3] Snapshot 32 0 31 GDDR2 device temperature MEMORY_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[4] Snapshot 32 32 63 Groupname 0x1150 64 GDDR2 device temperature MEMORY_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[5] Snapshot 32 0 31 GDDR3 device temperature MEMORY_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[6] Snapshot 32 32 63 Groupname 0x1158 64 GDDR3device temperature MEMORY_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[7] Snapshot 32 0 31 GDDR4 device temperature MEMORY_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[8] Snapshot 32 32 63 Groupname 0x1160 64 GDDR4 device temperature MEMORY_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[9] Snapshot 32 0 31 GDDR5 device temperature MEMORY_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[10] Snapshot 32 32 63 Groupname 0x1168 64 GDDR5 device temperature MEMORY_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[11] Snapshot 32 0 31 Reserved field RESERVED_119 Snapshot 32 32 63 Groupname 0x1170 64 Reserved field RESERVED_120 Snapshot 32 0 31 Reserved field RESERVED_121 Snapshot 32 32 63 Groupname 0x1178 64 Reserved field RESERVED_122 Snapshot 32 0 31 Platform Ambient Temperature. Memory Thermal Sensor Calibrated Temperature written by pcode. PLATFORM_AMB_TEMPERATURE_0_2_0_GTTMMADR[0] Snapshot 32 32 63 Groupname 0x1180 64 Platform Ambient Temperature. Memory Thermal Sensor Calibrated Temperature written by pcode. PLATFORM_AMB_TEMPERATURE_0_2_0_GTTMMADR[1] Snapshot 32 0 31 MBVR Temperatures VCCGT. Memory Thermal Sensor Calibrated Temperature written by pcode. PLATFORM_VR_TEMPERATURE_0_2_0_GTTMMADR[0] Snapshot 32 32 63 Groupname 0x1188 64 MBVR Temperatures VCCADM_DIG. Memory Thermal Sensor Calibrated Temperature written by pcode. PLATFORM_VR_TEMPERATURE_0_2_0_GTTMMADR[1] Snapshot 32 0 31 MBVR Temperatures VCCDDR. Memory Thermal Sensor Calibrated Temperature written by pcode. PLATFORM_VR_TEMPERATURE_0_2_0_GTTMMADR[2] Snapshot 32 32 63 Groupname 0x1190 64 MBVR Temperatures VCCSA. Memory Thermal Sensor Calibrated Temperature written by pcode. PLATFORM_VR_TEMPERATURE_0_2_0_GTTMMADR[3] Snapshot 32 0 31 Policy for slice/unslice GT ratios: GT_P_REQ Snapshot 4 32 35 reserved bits GT_P_REQ Snapshot 9 36 44 Latest GT frequency Request GT_P_REQ Snapshot 1 45 45 reserved bits GT_P_REQ Snapshot 9 46 54 This field indicates the maximum P-State request for GT Unslice in units of 16.666MHz frequency request before entering RC6. It is determined by GT Driver. GT_P_REQ Snapshot 9 55 63 Groupname 0x1198 64 Policy for slice/unslice GT ratios: MEDIA_P_REQ Snapshot 4 0 3 reserved bits MEDIA_P_REQ Snapshot 9 4 12 Latest Media frequency Request MEDIA_P_REQ Snapshot 1 13 13 reserved bits MEDIA_P_REQ Snapshot 9 14 22 This field indicates the maximum P-State request for GT Unslice in units of 16.666MHz frequency request before entering RC6. It is determined by GT Driver. MEDIA_P_REQ Snapshot 9 23 31 Current state of the LTSSM. Encoding is defined as follows: PCIE_LINK_STATE Snapshot 6 32 37 PHY Link up/down indicator: PCIE_LINK_STATE Snapshot 1 38 38 Data link layer up/down indicator: This status from the flow control initialization state machine indicates that flow control has been initiated and the Data link layer is ready to transmit and receive packets. For multi-VC designs, this register indicates status for VC0 only. PCIE_LINK_STATE Snapshot 1 39 39 Reserved PCIE_LINK_STATE Snapshot 4 40 43 Reserved PCIE_LINK_STATE Snapshot 1 44 44 Reserved PCIE_LINK_STATE Snapshot 3 45 47 RADM VC0 queue is not empty. PCIE_LINK_STATE Snapshot 1 48 48 Reserved PCIE_LINK_STATE Snapshot 1 49 49 Reserved PCIE_LINK_STATE Snapshot 1 50 50 Reserved PCIE_LINK_STATE Snapshot 1 51 51 Reserved PCIE_LINK_STATE Snapshot 1 52 52 Reserved PCIE_LINK_STATE Snapshot 1 53 53 Reserved PCIE_LINK_STATE Snapshot 1 54 54 Reserved PCIE_LINK_STATE Snapshot 1 55 55 Indicator that PCIe controller register block is under reset or to be reset. When this register is 1, programming to PCIe controller register block might be reset. PCIE_LINK_STATE Snapshot 1 56 56 Link signaling rate. PCIE_LINK_STATE Snapshot 3 57 59 PHY power state. PCIE_LINK_STATE Snapshot 4 60 63 Groupname 0x11a0 64 Active State Power Management ASPM Control. PCIE_LINK_CONFIG Snapshot 2 0 1 Reserved for future use. PCIE_LINK_CONFIG Snapshot 1 2 2 Read Completion Boundary RCB. PCIE_LINK_CONFIG Snapshot 1 3 3 Link Disable. PCIE_LINK_CONFIG Snapshot 1 4 4 Retrain Link. PCIE_LINK_CONFIG Snapshot 1 5 5 Common Clock Configuration. When set, this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. PCIE_LINK_CONFIG Snapshot 1 6 6 Extended Synch. When set, this bit forces the transmission of additional Ordered Sets when exiting the L0s state and when in the Recovery state (see section 4.2.6.4.1 of PCI . This mode provides external devices monitoring the Link time to achieve bit and Symbol lock before the Link enters the L0 state and resumes communication. PCIE_LINK_CONFIG Snapshot 1 7 7 Enable Clock Power Management. PCIE_LINK_CONFIG Snapshot 1 8 8 Hardware Autonomous Width Disable. PCIE_LINK_CONFIG Snapshot 1 9 9 Link Bandwidth Management Interrupt Enable. When set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. PCIE_LINK_CONFIG Snapshot 1 10 10 Link Autonomous Bandwidth Management Interrupt Enable. PCIE_LINK_CONFIG Snapshot 1 11 11 Reserved for future use. PCIE_LINK_CONFIG Snapshot 2 12 13 DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: PCIE_LINK_CONFIG Snapshot 2 14 15 Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. PCIE_LINK_CONFIG Snapshot 4 16 19 Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. PCIE_LINK_CONFIG Snapshot 6 20 25 Reserved for future use. PCIE_LINK_CONFIG Snapshot 1 26 26 Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state, or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when the LTSSM exits the Configuration/Recovery state. PCIE_LINK_CONFIG Snapshot 1 27 27 Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a reference clock on the connector, this bit must be clear. PCIE_LINK_CONFIG Snapshot 1 28 28 Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state, 0b otherwise. PCIE_LINK_CONFIG Snapshot 1 29 29 Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: PCIE_LINK_CONFIG Snapshot 1 30 30 Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width, without the Port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable Link operation. PCIE_LINK_CONFIG Snapshot 1 31 31 Counter to detect PCIE link traning and downgrade Counter to detect PCIE link traning and downgrade PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REG Counter 32 32 63 Groupname 0x11a8 64 32 bits of received byte count in downstream path. For every n us time programmed in cfg_num_auxclks new value sampled into this register. 64 bits of rx byte counter reg_PCIESS_rx_bytecount Counter 64 0 63 Groupname 0x11b0 64 32 bits of transmitted byte count in Upstream path. For every n us time programmed in cfg_num_auxclks new value sampled into this register. 64 bits of tx byte counter reg_PCIESS_tx_bytecount Counter 64 0 63 Groupname 0x11b8 64 32 bits of received packet count in downstream path 64 bits of rx packet counter reg_PCIESS_rx_pktcount Counter 64 0 63 Groupname 0x11c0 64 32 bits of transmitted packet count in upstream path 64 bits of tx packet counter reg_PCIESS_tx_pktcount Counter 64 0 63 Groupname 0x11c8 64 32 bits of PCIe L0 state time counter. For every n us time programmed in cfg_num_auxclks new value sampled into this register. 64 bits of L0 residence counter reg_PCIESS_L0_residence_count Counter 64 0 63 Groupname 0x11d0 64 32 bits of PCIe L0s state time counter. For every n us time programmed in cfg_num_auxclks new value sampled into this register. 64 bits of L0s residence counter reg_PCIESS_L0s_residence_count Counter 64 0 63 Groupname 0x11d8 64 32 bits of PCIe L1 state time counter. For every n us time programmed in cfg_num_auxclks new value sampled into this register. 64 bits of L1 residence counter reg_PCIESS_L1_residence_count Counter 64 0 63 Groupname 0x11e0 64 32 bits of PCIe L1sub state time counter. For every n us time programmed in cfg_num_auxclks new value sampled into this register. 64 bits of L1sub residence counter reg_PCIESS_L1sub_residence_count Counter 64 0 63 Groupname 0x11e8 64 32 bits of PCIe L2 state time counter. For every n us time programmed in cfg_num_auxclks new value sampled into this register. 64 bits of L2 residence counter reg_PCIESS_L2_residence_count Counter 64 0 63 Groupname 0x11f0 64 Lower 16 bit represents tlp error corresponds to radm_trgt1_tlp_abort and upper 16 bits represents dllp error count. DLLP error count REG_PCIESS_RX_TLP_DLLP_ERR_CNT Counter 32 0 31 Lower 16 bit represents ECRCerror corresponds to radm_trgt1_ecrc_err and upper 16 bits Reserved PCIE RX CRC error REG_PCIESS_RX_ECRC_ERR_CNT Counter 32 32 63 Groupname 0x11f8 64 Lower 16 bit represents command parity error and upper 16 bits represents data parity error count. data packet error count reg_PCIESS_downstream_parity_err_cnt Counter 32 0 31 Upstream command and data parity error count Data Parity Error count. reg_PCIESS_PCIEP0_UPSTREAM_PARITY_ERR_CNT Counter 32 32 63 Groupname 0x1200 64 TimeStamp units in milliseconds TIMESTAMP GDDR_TELEM_CAPTURE_TIMESTAMP Counter 64 0 63 Groupname 0x1208 64 read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU0_CH0_AXI0_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1210 64 read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU0_CH0_AXI0_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1218 64 write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU0_CH0_AXI0_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x1220 64 write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU0_CH0_AXI0_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x1228 64 Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU0_CH0_AXI1_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1230 64 Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU0_CH0_AXI1_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1238 64 read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU0_CH0_AXI2_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1240 64 read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU0_CH0_AXI2_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1248 64 write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU0_CH0_AXI2_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x1250 64 write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU0_CH0_AXI2_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x1258 64 read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU0_CH1_AXI0_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1260 64 read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU0_CH1_AXI0_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1268 64 write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU0_CH1_AXI0_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x1270 64 write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU0_CH1_AXI0_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x1278 64 Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU0_CH1_AXI1_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1280 64 Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU0_CH1_AXI1_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1288 64 read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU0_CH1_AXI2_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1290 64 read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU0_CH1_AXI2_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1298 64 write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU0_CH1_AXI2_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x12a0 64 write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU0_CH1_AXI2_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x12a8 64 read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU1_CH0_AXI0_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x12b0 64 read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU1_CH0_AXI0_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x12b8 64 write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU1_CH0_AXI0_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x12c0 64 write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU1_CH0_AXI0_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x12c8 64 Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU1_CH0_AXI1_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x12d0 64 Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU1_CH0_AXI1_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x12d8 64 read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU1_CH0_AXI2_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x12e0 64 read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU1_CH0_AXI2_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x12e8 64 write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU1_CH0_AXI2_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x12f0 64 write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU1_CH0_AXI2_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x12f8 64 read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU1_CH1_AXI0_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1300 64 read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU1_CH1_AXI0_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1308 64 write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU1_CH1_AXI0_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x1310 64 write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU1_CH1_AXI0_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x1318 64 Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU1_CH1_AXI1_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1320 64 Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU1_CH1_AXI1_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1328 64 read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU1_CH1_AXI2_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1330 64 read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU1_CH1_AXI2_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1338 64 write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU1_CH1_AXI2_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x1340 64 write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU1_CH1_AXI2_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x1348 64 read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU2_CH0_AXI0_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1350 64 read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU2_CH0_AXI0_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1358 64 write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU2_CH0_AXI0_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x1360 64 write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU2_CH0_AXI0_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x1368 64 Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU2_CH0_AXI1_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1370 64 Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU2_CH0_AXI1_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1378 64 read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU2_CH0_AXI2_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1380 64 read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU2_CH0_AXI2_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1388 64 write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU2_CH0_AXI2_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x1390 64 write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU2_CH0_AXI2_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x1398 64 read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU2_CH1_AXI0_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x13a0 64 read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU2_CH1_AXI0_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x13a8 64 write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU2_CH1_AXI0_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x13b0 64 write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU2_CH1_AXI0_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x13b8 64 Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU2_CH1_AXI1_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x13c0 64 Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU2_CH1_AXI1_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x13c8 64 read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU2_CH1_AXI2_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x13d0 64 read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU2_CH1_AXI2_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x13d8 64 write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU2_CH1_AXI2_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x13e0 64 write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU2_CH1_AXI2_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x13e8 64 read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU3_CH0_AXI0_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x13f0 64 read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU3_CH0_AXI0_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x13f8 64 write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU3_CH0_AXI0_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x1400 64 write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU3_CH0_AXI0_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x1408 64 Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU3_CH0_AXI1_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1410 64 Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU3_CH0_AXI1_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1418 64 read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU3_CH0_AXI2_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1420 64 read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU3_CH0_AXI2_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1428 64 write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU3_CH0_AXI2_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x1430 64 write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU3_CH0_AXI2_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x1438 64 read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU3_CH1_AXI0_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1440 64 read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU3_CH1_AXI0_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1448 64 write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU3_CH1_AXI0_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x1450 64 write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU3_CH1_AXI0_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x1458 64 Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU3_CH1_AXI1_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1460 64 Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU3_CH1_AXI1_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1468 64 read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU3_CH1_AXI2_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1470 64 read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU3_CH1_AXI2_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1478 64 write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU3_CH1_AXI2_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x1480 64 write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU3_CH1_AXI2_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x1488 64 read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU4_CH0_AXI0_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1490 64 read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU4_CH0_AXI0_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1498 64 write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU4_CH0_AXI0_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x14a0 64 write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU4_CH0_AXI0_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x14a8 64 Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU4_CH0_AXI1_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x14b0 64 Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU4_CH0_AXI1_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x14b8 64 read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU4_CH0_AXI2_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x14c0 64 read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU4_CH0_AXI2_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x14c8 64 write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU4_CH0_AXI2_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x14d0 64 write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU4_CH0_AXI2_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x14d8 64 read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU4_CH1_AXI0_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x14e0 64 read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU4_CH1_AXI0_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x14e8 64 write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU4_CH1_AXI0_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x14f0 64 write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU4_CH1_AXI0_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x14f8 64 Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU4_CH1_AXI1_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1500 64 Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU4_CH1_AXI1_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1508 64 read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU4_CH1_AXI2_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1510 64 read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU4_CH1_AXI2_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1518 64 write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU4_CH1_AXI2_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x1520 64 write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU4_CH1_AXI2_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x1528 64 read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU5_CH0_AXI0_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1530 64 read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU5_CH0_AXI0_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1538 64 write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU5_CH0_AXI0_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x1540 64 write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU5_CH0_AXI0_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x1548 64 Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU5_CH0_AXI1_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1550 64 Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU5_CH0_AXI1_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1558 64 read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU5_CH0_AXI2_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1560 64 read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU5_CH0_AXI2_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1568 64 write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU5_CH0_AXI2_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x1570 64 write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU5_CH0_AXI2_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x1578 64 read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU5_CH1_AXI0_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x1580 64 read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU5_CH1_AXI0_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x1588 64 write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU5_CH1_AXI0_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x1590 64 write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU5_CH1_AXI0_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x1598 64 Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU5_CH1_AXI1_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x15a0 64 Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU5_CH1_AXI1_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x15a8 64 read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU5_CH1_AXI2_PERF_CTR__COUNT_REQ_RD_1BEAT Counter 64 0 63 Groupname 0x15b0 64 read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU5_CH1_AXI2_PERF_CTR__COUNT_REQ_RD_2BEAT Counter 64 0 63 Groupname 0x15b8 64 write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" MSU5_CH1_AXI2_PERF_CTR__COUNT_REQ_WR_1BEAT Counter 64 0 63 Groupname 0x15c0 64 write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" MSU5_CH1_AXI2_PERF_CTR__COUNT_REQ_WR_2BEAT Counter 64 0 63 Groupname 0x15c8 64 Reserved field Counter 64 0 63 Groupname 0x15d0 64 Reserved field Counter 64 0 63 Groupname 0x15d8 64 Reserved field Counter 64 0 63 Groupname 0x15e0 64 Reserved field Counter 64 0 63 Groupname 0x15e8 64 Reserved field Counter 64 0 63 Groupname 0x15f0 64 Reserved field Counter 64 0 63 Groupname 0x15f8 64 Reserved field Counter 64 0 63 Groupname 0x1600 64 Reserved field Counter 64 0 63 Groupname 0x1608 64 Reserved field Counter 64 0 63 Groupname 0x1610 64 Reserved field Counter 64 0 63 Groupname 0x1618 64 Reserved field Counter 64 0 63 Groupname 0x1620 64 Reserved field Counter 64 0 63 Groupname 0x1628 64 Reserved field Counter 64 0 63 Groupname 0x1630 64 Reserved field Counter 64 0 63 Groupname 0x1638 64 Reserved field Counter 64 0 63 Groupname 0x1640 64 Reserved field Counter 64 0 63 Groupname 0x1648 64 Reserved field Counter 64 0 63 Groupname 0x1650 64 Reserved field Counter 64 0 63 Groupname 0x1658 64 Reserved field Counter 64 0 63 Groupname 0x1660 64 Reserved field Counter 64 0 63 Groupname 0x1668 64 Reserved field Counter 64 0 63 Groupname 0x1670 64 Reserved field Counter 64 0 63 Groupname 0x1678 64 Reserved field Counter 64 0 63 Groupname 0x1680 64 Reserved field Counter 64 0 63 Groupname 0x1688 64 Reserved field Counter 64 0 63 Groupname 0x1690 64 Reserved field Counter 64 0 63 Groupname 0x1698 64 Reserved field Counter 64 0 63 Groupname 0x16a0 64 Reserved field Counter 64 0 63 Groupname 0x16a8 64 Reserved field Counter 64 0 63 Groupname 0x16b0 64 Reserved field Counter 64 0 63 Groupname 0x16b8 64 Reserved field Counter 64 0 63 Groupname 0x16c0 64 Reserved field Counter 64 0 63 Groupname 0x16c8 64 Reserved field Counter 64 0 63 Groupname 0x16d0 64 Reserved field Counter 64 0 63 Groupname 0x16d8 64 Reserved field Counter 64 0 63 Groupname 0x16e0 64 Reserved field Counter 64 0 63 Groupname 0x16e8 64 Reserved field Counter 64 0 63 Groupname 0x16f0 64 Reserved field Counter 64 0 63 Groupname 0x16f8 64 Reserved field Counter 64 0 63 Groupname 0x1700 64 Reserved field Counter 64 0 63 Groupname 0x1708 64 Reserved field Counter 64 0 63 Groupname 0x1710 64 Reserved field Counter 64 0 63 Groupname 0x1718 64 Reserved field Counter 64 0 63 Groupname 0x1720 64 Reserved field Counter 64 0 63 Groupname 0x1728 64 Reserved field Counter 64 0 63 Groupname 0x1730 64 Reserved field Counter 64 0 63 Groupname 0x1738 64 Reserved field Counter 64 0 63 Groupname 0x1740 64 Reserved field Counter 64 0 63 Groupname 0x1748 64 Reserved field Counter 64 0 63 Groupname 0x1750 64 Reserved field Counter 64 0 63 Groupname 0x1758 64 Reserved field Counter 64 0 63 Groupname 0x1760 64 Reserved field Counter 64 0 63 Groupname 0x1768 64 Reserved field Counter 64 0 63 Groupname 0x1770 64 Reserved field Counter 64 0 63 Groupname 0x1778 64 Reserved field Counter 64 0 63 Groupname 0x1780 64 Reserved field Counter 64 0 63 Groupname 0x1788 64 Reserved field Counter 64 0 63 Groupname 0x1790 64 Reserved field Counter 64 0 63 Groupname 0x1798 64 Reserved field Counter 64 0 63 Groupname 0x17a0 64 Reserved field Counter 64 0 63 Groupname 0x17a8 64 Reserved field Counter 64 0 63 Groupname 0x17b0 64 Reserved field Counter 64 0 63 Groupname 0x17b8 64 Reserved field Counter 64 0 63 Groupname 0x17c0 64 Reserved field Counter 64 0 63 Groupname 0x17c8 64 Reserved field Counter 64 0 63 Groupname 0x17d0 64 Reserved field Counter 64 0 63 Groupname 0x17d8 64 Reserved field Counter 64 0 63 Groupname 0x17e0 64 Reserved field Counter 64 0 63 Groupname 0x17e8 64 Reserved field Counter 64 0 63 Groupname 0x17f0 64 Reserved field Counter 64 0 63 Groupname 0x17f8 64 Reserved field Counter 64 0 63 Groupname 0x1800 64 Reserved field Counter 64 0 63 Groupname 0x1808 64 Reserved field Counter 64 0 63 Groupname 0x1810 64 Reserved field Counter 64 0 63 Groupname 0x1818 64 Reserved field Counter 64 0 63 Groupname 0x1820 64 Reserved field Counter 64 0 63 Groupname 0x1828 64 Reserved field Counter 64 0 63 Groupname 0x1830 64 Reserved field Counter 64 0 63 Groupname 0x1838 64 Reserved field Counter 64 0 63 Groupname 0x1840 64 Reserved field Counter 64 0 63 Groupname 0x1848 64 Reserved field Counter 64 0 63 Groupname 0x1850 64 Reserved field Counter 64 0 63 Groupname 0x1858 64 Reserved field Counter 64 0 63 Groupname 0x1860 64 Reserved field Counter 64 0 63 Groupname 0x1868 64 Reserved field Counter 64 0 63 Groupname 0x1870 64 Reserved field Counter 64 0 63 Groupname 0x1878 64 Reserved field Counter 64 0 63 Groupname 0x1880 64 Reserved field Counter 64 0 63 Groupname 0x1888 64 Reserved field Counter 64 0 63 Groupname 0x1890 64 Reserved field Counter 64 0 63 Groupname 0x1898 64 Reserved field Counter 64 0 63 Groupname 0x18a0 64 Reserved field Counter 64 0 63 Groupname 0x18a8 64 Reserved field Counter 64 0 63 Groupname 0x18b0 64 Reserved field Counter 64 0 63 Groupname 0x18b8 64 Reserved field Counter 64 0 63 Groupname 0x18c0 64 Reserved field Counter 64 0 63 Groupname 0x18c8 64 Reserved field Counter 64 0 63 Groupname 0x18d0 64 Reserved field Counter 64 0 63 Groupname 0x18d8 64 Reserved field Counter 64 0 63 Groupname 0x18e0 64 Reserved field Counter 64 0 63 Groupname 0x18e8 64 Reserved field Counter 64 0 63 Groupname 0x18f0 64 Reserved field Counter 64 0 63 Groupname 0x18f8 64 Reserved field Counter 64 0 63 Groupname 0x1900 64 Reserved field Counter 64 0 63 Groupname 0x1908 64 Reserved field Counter 64 0 63 Groupname 0x1910 64 Reserved field Counter 64 0 63 Groupname 0x1918 64 Reserved field Counter 64 0 63 Groupname 0x1920 64 Reserved field Counter 64 0 63 Groupname 0x1928 64 Reserved field Counter 64 0 63 Groupname 0x1930 64 Reserved field Counter 64 0 63 Groupname 0x1938 64 Reserved field Counter 64 0 63 Groupname 0x1940 64 Reserved field Counter 64 0 63 Groupname 0x1948 64 Reserved field Counter 64 0 63 Groupname 0x1950 64 Reserved field Counter 64 0 63 Groupname 0x1958 64 Reserved field Counter 64 0 63 Groupname 0x1960 64 Reserved field Counter 64 0 63 Groupname 0x1968 64 Reserved field Counter 64 0 63 Groupname 0x1970 64 Reserved field Counter 64 0 63 Groupname 0x1978 64 Reserved field Counter 64 0 63 Groupname 0x1980 64 Reserved field Counter 64 0 63 Groupname 0x1988 64 Reserved field Counter 64 0 63 Groupname 0x1990 64 Reserved field Counter 64 0 63 Groupname 0x1998 64 Reserved field Counter 64 0 63 Groupname 0x19a0 64 Reserved field Counter 64 0 63 Groupname 0x19a8 64 Reserved field Counter 64 0 63 Groupname 0x19b0 64 Reserved field Counter 64 0 63 Groupname 0x19b8 64 Reserved field Counter 64 0 63 Groupname 0x19c0 64 Reserved field Counter 64 0 63 Groupname 0x19c8 64 Reserved field Counter 64 0 63 Groupname 0x19d0 64 Reserved field Counter 64 0 63 Groupname 0x19d8 64 Reserved field Counter 64 0 63 Groupname 0x19e0 64 Reserved field Counter 64 0 63 Groupname 0x19e8 64 Reserved field Counter 64 0 63 Groupname 0x19f0 64 Reserved field Counter 64 0 63 Groupname 0x19f8 64 Reserved field Counter 64 0 63 Groupname 0x1a00 64 Reserved field Counter 64 0 63 Groupname 0x1a08 64 Reserved field Counter 64 0 63 Groupname 0x1a10 64 Reserved field Counter 64 0 63 Groupname 0x1a18 64 Reserved field Counter 64 0 63 Groupname 0x1a20 64 Reserved field Counter 64 0 63 Groupname 0x1a28 64 Reserved field Counter 64 0 63 Groupname 0x1a30 64 Reserved field Counter 64 0 63 Groupname 0x1a38 64 Reserved field Counter 64 0 63 Groupname 0x1a40 64 Reserved field Counter 64 0 63 Groupname 0x1a48 64 Reserved field Counter 64 0 63 Groupname 0x1a50 64 Reserved field Counter 64 0 63 Groupname 0x1a58 64 Reserved field Counter 64 0 63 Groupname 0x1a60 64 Reserved field Counter 64 0 63 Groupname 0x1a68 64 Reserved field Counter 64 0 63 Groupname 0x1a70 64 Reserved field Counter 64 0 63 Groupname 0x1a78 64 Reserved field Counter 64 0 63 Groupname 0x1a80 64 Reserved field Counter 64 0 63 Groupname 0x1a88 64 Reserved field Counter 64 0 63 Groupname 0x1a90 64 Reserved field Counter 64 0 63 Groupname 0x1a98 64 Reserved field Counter 64 0 63 Groupname 0x1aa0 64 Reserved field Counter 64 0 63 Groupname 0x1aa8 64 Reserved field Counter 64 0 63 Groupname 0x1ab0 64 Reserved field Counter 64 0 63 Groupname 0x1ab8 64 Reserved field Counter 64 0 63 Groupname 0x1ac0 64 Reserved field Counter 64 0 63 Groupname 0x1ac8 64 Reserved field Counter 64 0 63 Groupname 0x1ad0 64 Reserved field Counter 64 0 63 Groupname 0x1ad8 64 Reserved field Counter 64 0 63 Groupname 0x1ae0 64 Reserved field Counter 64 0 63 Groupname 0x1ae8 64 Reserved field Counter 64 0 63 Groupname 0x1af0 64 Reserved field Counter 64 0 63 Groupname 0x1af8 64 Reserved field Counter 64 0 63 Groupname 0x1b00 64 Reserved field Counter 64 0 63 Groupname 0x1b08 64 Reserved field Counter 64 0 63 Groupname 0x1b10 64 Reserved field Counter 64 0 63 Groupname 0x1b18 64 Reserved field Counter 64 0 63 Groupname 0x1b20 64 Reserved field Counter 64 0 63 Groupname 0x1b28 64 Reserved field Counter 64 0 63 Groupname 0x1b30 64 Reserved field Counter 64 0 63 Groupname 0x1b38 64 Reserved field Counter 64 0 63 Groupname 0x1b40 64 Reserved field Counter 64 0 63 Groupname 0x1b48 64 Reserved field Counter 64 0 63 Groupname 0x1b50 64 Reserved field Counter 64 0 63 Groupname 0x1b58 64 Reserved field Counter 64 0 63 Groupname 0x1b60 64 Reserved field Counter 64 0 63 Groupname 0x1b68 64 Reserved field Counter 64 0 63 Groupname 0x1b70 64 Reserved field Counter 64 0 63 Groupname 0x1b78 64 Reserved field Counter 64 0 63 Groupname 0x1b80 64 Reserved field Counter 64 0 63 Groupname 0x1b88 64 Reserved field Counter 64 0 63 Groupname 0x1b90 64 Reserved field Counter 64 0 63 Groupname 0x1b98 64 Reserved field Counter 64 0 63 Groupname 0x1ba0 64 Reserved field Counter 64 0 63 Groupname 0x1ba8 64 Reserved field Counter 64 0 63 Groupname 0x1bb0 64 Reserved field Counter 64 0 63 Groupname 0x1bb8 64 Reserved field Counter 64 0 63 Groupname 0x1bc0 64 Reserved field Counter 64 0 63 Groupname 0x1bc8 64 Reserved field Counter 64 0 63 Groupname 0x1bd0 64 Reserved field Counter 64 0 63 Groupname 0x1bd8 64 Reserved field Counter 64 0 63 Groupname 0x1be0 64 Reserved field Counter 64 0 63 Groupname 0x1be8 64 Reserved field Counter 64 0 63 Groupname 0x1bf0 64 Reserved field Counter 64 0 63 Groupname 0x1bf8 64 Reserved field Counter 64 0 63 Groupname 0x1c00 64 Reserved field Counter 64 0 63 Groupname 0x1c08 64 GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC0. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU0_MC_0_AM_WR_CMD Counter 32 0 31 GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register MSU0_MC_0_AM_WR_AP_CMD Counter 32 32 63 Groupname 0x1c10 64 GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC0. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge).Use MSU_BITMASK with MSU# to intrepret this register MSU0_MC_0_AM_RD_CMD Counter 32 0 31 GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register MSU0_MC_0_AM_RD_AP_CMD Counter 32 32 63 Groupname 0x1c18 64 The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit error. Use MSU_BITMASK with MSU# to intrepret this registercorrection counts. MSU0_MC_0_CFG_ECC_1BIT_INT_THRESH Counter 32 0 31 Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached. Use MSU_BITMASK with MSU# to intrepret this register MSU0_MC_0_STAT_ECC_SCRUB_ERROR_1BIT_CNT Counter 32 32 63 Groupname 0x1c20 64 GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC1. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU0_MC_1_AM_WR_CMD Counter 32 0 31 GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register MSU0_MC_1_AM_WR_AP_CMD Counter 32 32 63 Groupname 0x1c28 64 GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC1. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU0_MC_1_AM_RD_CMD Counter 32 0 31 GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register MSU0_MC_1_AM_RD_AP_CMD Counter 32 32 63 Groupname 0x1c30 64 The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit errorcorrection counts. Use MSU_BITMASK with MSU# to intrepret this register MSU0_MC_1_CFG_ECC_1BIT_INT_THRESH Counter 32 0 31 Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached MSU0_MC_1_STAT_ECC_SCRUB_ERROR_1BIT_CNT Counter 32 32 63 Groupname 0x1c38 64 GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC0. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU1_MC_0_AM_WR_CMD Counter 32 0 31 GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register MSU1_MC_0_AM_WR_AP_CMD Counter 32 32 63 Groupname 0x1c40 64 GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC0. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge).Use MSU_BITMASK with MSU# to intrepret this register MSU1_MC_0_AM_RD_CMD Counter 32 0 31 GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register MSU1_MC_0_AM_RD_AP_CMD Counter 32 32 63 Groupname 0x1c48 64 The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit error. Use MSU_BITMASK with MSU# to intrepret this registercorrection counts. MSU1_MC_0_CFG_ECC_1BIT_INT_THRESH Counter 32 0 31 Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached. Use MSU_BITMASK with MSU# to intrepret this register MSU1_MC_0_STAT_ECC_SCRUB_ERROR_1BIT_CNT Counter 32 32 63 Groupname 0x1c50 64 GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC1. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU1_MC_1_AM_WR_CMD Counter 32 0 31 GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register MSU1_MC_1_AM_WR_AP_CMD Counter 32 32 63 Groupname 0x1c58 64 GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC1. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU1_MC_1_AM_RD_CMD Counter 32 0 31 GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register MSU1_MC_1_AM_RD_AP_CMD Counter 32 32 63 Groupname 0x1c60 64 The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit errorcorrection counts. Use MSU_BITMASK with MSU# to intrepret this register MSU1_MC_1_CFG_ECC_1BIT_INT_THRESH Counter 32 0 31 Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached MSU1_MC_1_STAT_ECC_SCRUB_ERROR_1BIT_CNT Counter 32 32 63 Groupname 0x1c68 64 GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC0. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU2_MC_0_AM_WR_CMD Counter 32 0 31 GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register MSU2_MC_0_AM_WR_AP_CMD Counter 32 32 63 Groupname 0x1c70 64 GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC0. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge).Use MSU_BITMASK with MSU# to intrepret this register MSU2_MC_0_AM_RD_CMD Counter 32 0 31 GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register MSU2_MC_0_AM_RD_AP_CMD Counter 32 32 63 Groupname 0x1c78 64 The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit error. Use MSU_BITMASK with MSU# to intrepret this registercorrection counts. MSU2_MC_0_CFG_ECC_1BIT_INT_THRESH Counter 32 0 31 Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached. Use MSU_BITMASK with MSU# to intrepret this register MSU2_MC_0_STAT_ECC_SCRUB_ERROR_1BIT_CNT Counter 32 32 63 Groupname 0x1c80 64 GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC1. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU2_MC_1_AM_WR_CMD Counter 32 0 31 GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register MSU2_MC_1_AM_WR_AP_CMD Counter 32 32 63 Groupname 0x1c88 64 GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC1. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU2_MC_1_AM_RD_CMD Counter 32 0 31 GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register MSU2_MC_1_AM_RD_AP_CMD Counter 32 32 63 Groupname 0x1c90 64 The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit errorcorrection counts. Use MSU_BITMASK with MSU# to intrepret this register MSU2_MC_1_CFG_ECC_1BIT_INT_THRESH Counter 32 0 31 Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached MSU2_MC_1_STAT_ECC_SCRUB_ERROR_1BIT_CNT Counter 32 32 63 Groupname 0x1c98 64 GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC0. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU3_MC_0_AM_WR_CMD Counter 32 0 31 GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register MSU3_MC_0_AM_WR_AP_CMD Counter 32 32 63 Groupname 0x1ca0 64 GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC0. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge).Use MSU_BITMASK with MSU# to intrepret this register MSU3_MC_0_AM_RD_CMD Counter 32 0 31 GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register MSU3_MC_0_AM_RD_AP_CMD Counter 32 32 63 Groupname 0x1ca8 64 The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit error. Use MSU_BITMASK with MSU# to intrepret this registercorrection counts. MSU3_MC_0_CFG_ECC_1BIT_INT_THRESH Counter 32 0 31 Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached. Use MSU_BITMASK with MSU# to intrepret this register MSU3_MC_0_STAT_ECC_SCRUB_ERROR_1BIT_CNT Counter 32 32 63 Groupname 0x1cb0 64 GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC1. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU3_MC_1_AM_WR_CMD Counter 32 0 31 GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register MSU3_MC_1_AM_WR_AP_CMD Counter 32 32 63 Groupname 0x1cb8 64 GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC1. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU3_MC_1_AM_RD_CMD Counter 32 0 31 GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register MSU3_MC_1_AM_RD_AP_CMD Counter 32 32 63 Groupname 0x1cc0 64 The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit errorcorrection counts. Use MSU_BITMASK with MSU# to intrepret this register MSU3_MC_1_CFG_ECC_1BIT_INT_THRESH Counter 32 0 31 Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached MSU3_MC_1_STAT_ECC_SCRUB_ERROR_1BIT_CNT Counter 32 32 63 Groupname 0x1cc8 64 GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC0. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU4_MC_0_AM_WR_CMD Counter 32 0 31 GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register MSU4_MC_0_AM_WR_AP_CMD Counter 32 32 63 Groupname 0x1cd0 64 GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC0. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge).Use MSU_BITMASK with MSU# to intrepret this register MSU4_MC_0_AM_RD_CMD Counter 32 0 31 GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register MSU4_MC_0_AM_RD_AP_CMD Counter 32 32 63 Groupname 0x1cd8 64 The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit error. Use MSU_BITMASK with MSU# to intrepret this registercorrection counts. MSU4_MC_0_CFG_ECC_1BIT_INT_THRESH Counter 32 0 31 Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached. Use MSU_BITMASK with MSU# to intrepret this register MSU4_MC_0_STAT_ECC_SCRUB_ERROR_1BIT_CNT Counter 32 32 63 Groupname 0x1ce0 64 GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC1. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU4_MC_1_AM_WR_CMD Counter 32 0 31 GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register MSU4_MC_1_AM_WR_AP_CMD Counter 32 32 63 Groupname 0x1ce8 64 GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC1. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU4_MC_1_AM_RD_CMD Counter 32 0 31 GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register MSU4_MC_1_AM_RD_AP_CMD Counter 32 32 63 Groupname 0x1cf0 64 The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit errorcorrection counts. Use MSU_BITMASK with MSU# to intrepret this register MSU4_MC_1_CFG_ECC_1BIT_INT_THRESH Counter 32 0 31 Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached MSU4_MC_1_STAT_ECC_SCRUB_ERROR_1BIT_CNT Counter 32 32 63 Groupname 0x1cf8 64 GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC0. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU5_MC_0_AM_WR_CMD Counter 32 0 31 GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register MSU5_MC_0_AM_WR_AP_CMD Counter 32 32 63 Groupname 0x1d00 64 GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC0. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge).Use MSU_BITMASK with MSU# to intrepret this register MSU5_MC_0_AM_RD_CMD Counter 32 0 31 GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register MSU5_MC_0_AM_RD_AP_CMD Counter 32 32 63 Groupname 0x1d08 64 The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit error. Use MSU_BITMASK with MSU# to intrepret this registercorrection counts. MSU5_MC_0_CFG_ECC_1BIT_INT_THRESH Counter 32 0 31 Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached. Use MSU_BITMASK with MSU# to intrepret this register MSU5_MC_0_STAT_ECC_SCRUB_ERROR_1BIT_CNT Counter 32 32 63 Groupname 0x1d10 64 GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC1. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU5_MC_1_AM_WR_CMD Counter 32 0 31 GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register MSU5_MC_1_AM_WR_AP_CMD Counter 32 32 63 Groupname 0x1d18 64 GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC1. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register MSU5_MC_1_AM_RD_CMD Counter 32 0 31 GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register MSU5_MC_1_AM_RD_AP_CMD Counter 32 32 63 Groupname 0x1d20 64 The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit errorcorrection counts. Use MSU_BITMASK with MSU# to intrepret this register MSU5_MC_1_CFG_ECC_1BIT_INT_THRESH Counter 32 0 31 Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached MSU5_MC_1_STAT_ECC_SCRUB_ERROR_1BIT_CNT Counter 32 32 63 Groupname 0x1d28 64 Reserved field Counter 32 0 31 Reserved field Counter 32 32 63 Groupname 0x1d30 64 Reserved field Counter 32 0 31 Reserved field Counter 32 32 63 Groupname 0x1d38 64 Reserved field Counter 32 0 31 Reserved field Counter 32 32 63 Groupname 0x1d40 64 Reserved field Counter 32 0 31 Reserved field Counter 32 32 63 Groupname 0x1d48 64 Reserved field Counter 32 0 31 Reserved field Counter 32 32 63 Groupname 0x1d50 64 Reserved field Counter 32 0 31 Reserved field Counter 32 32 63 Groupname 0x1d58 64 Reserved field Counter 32 0 31 Reserved field Counter 32 32 63 Groupname 0x1d60 64 Reserved field Counter 32 0 31 Reserved field Counter 32 32 63 Groupname 0x1d68 64 Reserved field Counter 32 0 31 Reserved field Counter 32 32 63 Groupname 0x1d70 64 Reserved field Counter 32 0 31 Reserved field Counter 32 32 63 Groupname 0x1d78 64 Reserved field Counter 32 0 31 Reserved field Counter 32 32 63 Groupname 0x1d80 64 Reserved field Counter 32 0 31 Reserved field Counter 32 32 63 Groupname 0x1d88 64 GT Error was detected DEV_ERR_STAT_FATAL Snapshot 1 0 0 Command Parity Error detected in the MERT->SG IOSF interface DEV_ERR_STAT_FATAL Snapshot 1 1 1 The field 'Reserved' in register 'Device Error Source Fatal' does not have a description in the BXML DEV_ERR_STAT_FATAL Snapshot 2 2 3 Display Error was detected DEV_ERR_STAT_FATAL Snapshot 1 4 4 Command Parity Error detected in the DE->SG IOSF interface DEV_ERR_STAT_FATAL Snapshot 1 5 5 The field 'Reserved' in register 'Device Error Source Fatal' does not have a description in the BXML DEV_ERR_STAT_FATAL Snapshot 2 6 7 GSC Error was detected DEV_ERR_STAT_FATAL Snapshot 1 8 8 Command Parity Error detected in gSC -> SG IOSF interface DEV_ERR_STAT_FATAL Snapshot 1 9 9 The field 'Reserved' in register 'Device Error Source Fatal' does not have a description in the BXML DEV_ERR_STAT_FATAL Snapshot 2 10 11 SG unit Error was detected DEV_ERR_STAT_FATAL Snapshot 1 12 12 Command Parity Error detected in C-die -> SG interface DEV_ERR_STAT_FATAL Snapshot 1 13 13 The field 'Reserved' in register 'Device Error Source Fatal' does not have a description in the BXML DEV_ERR_STAT_FATAL Snapshot 2 14 15 SoC Error was detected DEV_ERR_STAT_FATAL Snapshot 1 16 16 CSC saw a fatal error DEV_ERR_STAT_FATAL Snapshot 1 17 17 The field 'Reserved' in register 'Device Error Source Fatal' does not have a description in the BXML DEV_ERR_STAT_FATAL Snapshot 2 18 19 MERT writes to this bit using the message offset on detecting command or data parity error in the SG->MERT interface, or completion parity errors on completions from MERT-> SG. DEV_ERR_STAT_FATAL Snapshot 1 20 20 The field 'Reserved' in register 'Device Error Source Fatal' does not have a description in the BXML DEV_ERR_STAT_FATAL Snapshot 4 21 24 Command Parity Error detected in SGMI IOSF interface DEV_ERR_STAT_FATAL Snapshot 1 25 25 The field 'Reserved' in register 'Device Error Source Fatal' does not have a description in the BXML DEV_ERR_STAT_FATAL Snapshot 6 26 31 1: Error occurred DEV_PCIEERR_STATUS Snapshot 1 32 32 1: Error occurred DEV_PCIEERR_STATUS Snapshot 1 33 33 1: Error occurred DEV_PCIEERR_STATUS Snapshot 1 34 34 The field 'Reserved' in register 'Device PCIe Error Status' does not have a description in the BXML DEV_PCIEERR_STATUS Snapshot 1 35 35 1: Error occurred DEV_PCIEERR_STATUS Snapshot 1 36 36 1: Error occurred DEV_PCIEERR_STATUS Snapshot 1 37 37 1: Error occurred DEV_PCIEERR_STATUS Snapshot 1 38 38 The field 'Reserved' in register 'Device PCIe Error Status' does not have a description in the BXML DEV_PCIEERR_STATUS Snapshot 1 39 39 1: Error occurred DEV_PCIEERR_STATUS Snapshot 1 40 40 1: Error occurred DEV_PCIEERR_STATUS Snapshot 1 41 41 1: Error occurred DEV_PCIEERR_STATUS Snapshot 1 42 42 The field 'Reserved' in register 'Device PCIe Error Status' does not have a description in the BXML DEV_PCIEERR_STATUS Snapshot 1 43 43 1: Error occurred DEV_PCIEERR_STATUS Snapshot 1 44 44 1: Error occurred DEV_PCIEERR_STATUS Snapshot 1 45 45 1: Error occurred DEV_PCIEERR_STATUS Snapshot 1 46 46 The field 'Reserved' in register 'Device PCIe Error Status' does not have a description in the BXML DEV_PCIEERR_STATUS Snapshot 17 47 63 Groupname 0x1d90 64 The field 'Reserved' in register 'GT Fatal Err Status Register' does not have a description in the BXML ERR_STAT_GT_FATAL Snapshot 1 0 0 Array BIST Error ERR_STAT_GT_FATAL Snapshot 1 1 1 The field 'Reserved HW Error1' in register 'GT Fatal Err Status Register' does not have a description in the BXML ERR_STAT_GT_FATAL Snapshot 1 2 2 The field 'FPU Uncorrectable Error' in register 'GT Fatal Err Status Register' does not have a description in the BXML ERR_STAT_GT_FATAL Snapshot 1 3 3 L3 double error ERR_STAT_GT_FATAL Snapshot 1 4 4 L3 ECC Checker Error ERR_STAT_GT_FATAL Snapshot 1 5 5 Uncorrectable GUC SRAM error ERR_STAT_GT_FATAL Snapshot 1 6 6 The field 'Reserved' in register 'GT Fatal Err Status Register' does not have a description in the BXML ERR_STAT_GT_FATAL Snapshot 1 7 7 IDI Parity Error ERR_STAT_GT_FATAL Snapshot 1 8 8 Poison detected in SQIDI ERR_STAT_GT_FATAL Snapshot 1 9 9 The field 'Reserved' in register 'GT Fatal Err Status Register' does not have a description in the BXML ERR_STAT_GT_FATAL Snapshot 2 10 11 On ATS, sampler does not generate this event - so this bit is reserved for future Sampler error use.Uncorrectable Sampler error detected ERR_STAT_GT_FATAL Snapshot 1 12 12 Uncorrectable SLM error detected ERR_STAT_GT_FATAL Snapshot 1 13 13 Uncorrectable EU Instruction Cache error detected ERR_STAT_GT_FATAL Snapshot 1 14 14 Uncorrectable GRF error detected ERR_STAT_GT_FATAL Snapshot 1 15 15 The field 'Reserved' in register 'GT Fatal Err Status Register' does not have a description in the BXML ERR_STAT_GT_FATAL Snapshot 16 16 31 Set to 1 when Poisoned data has been received from IOSF-Primary. This sticky bit must survive secondary bus reset/FLR. POISON_DATA_STATUS Snapshot 1 32 32 Logs status of the Viral Poison Condition: 0 : HW is not virally poisoning data sent to the Host system 1 : HW is virally poisoning data sent to the Host system Cleared by FLR. POISON_DATA_STATUS Snapshot 1 33 33 The field 'Reserved' in register 'POISON_DATA_STATUS' does not have a description in the BXML POISON_DATA_STATUS Snapshot 30 34 63 Groupname 0x1d98 64 0=No Primary SPI access error. 1=Primary SPI access error occurred. SPI_ERROR_SRC Snapshot 1 0 0 OPTIONROMBAR SPI access error opcode (00=Write, 01=Read, 10=Erase, 11=Reserved). SPI_ERROR_SRC Snapshot 2 1 2 Spare. SPI_ERROR_SRC Snapshot 1 3 3 0=No OptionROMBAR SPI access error. 1=OptionROMBAR SPI access error occurred. SPI_ERROR_SRC Snapshot 1 4 4 OPTIONROMBAR SPI access error opcode (00=Write, 01=Read, 10=Erase, 11=Reserved). SPI_ERROR_SRC Snapshot 2 5 6 Spare. SPI_ERROR_SRC Snapshot 1 7 7 0=No gSC SPI access error. 1=gSC SPI access error occurred. SPI_ERROR_SRC Snapshot 1 8 8 gSC SPI access error opcode (00=Write, 01=Read, 10=Erase, 11=Reserved). SPI_ERROR_SRC Snapshot 2 9 10 Spare. SPI_ERROR_SRC Snapshot 1 11 11 Spare. SPI_ERROR_SRC Snapshot 20 12 31 This register counts the same event as counter SPM0 however is not affected by context ID or other conditions that prevent SPM0 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted using this register. This 32-bit field returns bits 63:32 of the live performance counter value when read. Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO, so the value returned from this register may be different on back-to-back reads. OAG_OAPERF_SPM0_UPPER_FREE Counter 32 32 63 Groupname 0x1da0 64 This register counts the same event as counter SPM0 however is not affected by context ID or other conditions that prevent SPM0 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted used this register. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. OAG_OAPERF_SPM0_LOWER_FREE Counter 32 0 31 This register counts the same event as counter SPM1 however is not affected by context ID or other conditions that prevent SPM1 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.;Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted using this register. This 32-bit field returns bits 63:32 of the live performance counter value when read. Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO, so the value returned from this register may be different on back-to-back reads. OAG_OAPERF_SPM1_UPPER_FREE Counter 32 32 63 Groupname 0x1da8 64 This register counts the same event as counter SPM1 however is not affected by context ID or other conditions that prevent SPM1 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted used this register. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. OAG_OAPERF_SPM1_LOWER_FREE Counter 32 0 31 This register counts the same event as counter SPM2 however is not affected by context ID or other conditions that prevent SPM2 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.;Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted using this register. This 32-bit field returns bits 63:32 of the live performance counter value when read. Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO, so the value returned from this register may be different on back-to-back reads. OAG_OAPERF_SPM2_UPPER_FREE Counter 32 32 63 Groupname 0x1db0 64 This register counts the same event as counter SPM2 however is not affected by context ID or other conditions that prevent SPM2 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted used this register. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. OAG_OAPERF_SPM2_LOWER_FREE Counter 32 0 31 This register counts the same event as counter SPM3 however is not affected by context ID or other conditions that prevent SPM3 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.;Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted using this register. This 32-bit field returns bits 63:32 of the live performance counter value when read. Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO, so the value returned from this register may be different on back-to-back reads. OAG_OAPERF_SPM3_UPPER_FREE Counter 32 32 63 Groupname 0x1db8 64 This register counts the same event as counter SPM3 however is not affected by context ID or other conditions that prevent SPM3 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted used this register. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. OAG_OAPERF_SPM3_LOWER_FREE Counter 32 0 31 This register counts the same event as counter SPM4 however is not affected by context ID or other conditions that prevent SPM4 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted used this register. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. OAG_OAPERF_SPM4_LOWER_FREE Counter 32 32 63 Groupname 0x1dc0 64 Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted used this register.This counter is free running, always enabled and countsirrespective of OA enable configuration. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. OAG_OAPERF_SPM5_LOWER_FREE Counter 32 0 31 This register counts the time that any render engine is busy. This counter is free running, always enabled and counting irrespective of OA enabled or disabled. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. OAG_RENDER_BUSY_FREE Counter 32 32 63 Groupname 0x1dc8 64 This register counts the time that any media fixed function is busy. This counter is free running, always enabled and counts irrespective of OA being enabled or disabled. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. OAG_ANY_MEDIA_FF_BUSY_FREE Counter 32 0 31 This register counts the time thatBLT engine is busy. This counter is free running, always enabled and counting irrespective of OA enabled or disabled. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. OAG_BLT_BUSY_FREE Counter 32 32 63 Groupname 0x1dd0 64 This register counts the time that any engine is truly busy (not simply powered up). This counter is free running, always enabled and counting irrespective of OA enabled or disabled. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. Unit in GPMusec. Refer to Timestamp Bases for details. OAG_RC0_ANY_ENGINE_BUSY_FREE Counter 32 0 31 Reserved register Reserved field RESERVED_CONTAINER_ALIGN_2 Counter 32 32 63 Groupname 0x1dd8 64 Reserved field RESERVED_REG_RANGE_1 Snapshot 64 0 63 Groupname 0x1de0 64 Reserved field RESERVED_REG_RANGE_2 Snapshot 64 0 63 Groupname 0x1de8 64 Reserved field RESERVED_REG_RANGE_3 Snapshot 64 0 63 Groupname 0x1df0 64 Reserved field RESERVED_REG_RANGE_4 Snapshot 64 0 63 Groupname 0x1df8 64 Reserved field RESERVED_REG_RANGE_5 Snapshot 64 0 63 Groupname 0x1e00 64 Reserved field RESERVED_REG_RANGE_6 Snapshot 64 0 63 Groupname 0x1e08 64 Reserved field RESERVED_REG_RANGE_7 Snapshot 64 0 63 Groupname 0x1e10 64 Reserved field RESERVED_REG_RANGE_8 Snapshot 64 0 63 Groupname 0x1e18 64 Reserved field RESERVED_REG_RANGE_9 Snapshot 64 0 63 Groupname 0x1e20 64 Reserved field RESERVED_REG_RANGE_10 Snapshot 64 0 63 Groupname 0x1e28 64 Reserved field RESERVED_REG_RANGE_11 Snapshot 64 0 63 Groupname 0x1e30 64 Reserved field RESERVED_REG_RANGE_12 Snapshot 64 0 63 Groupname 0x1e38 64 Reserved field RESERVED_REG_RANGE_13 Snapshot 64 0 63 Groupname 0x1e40 64 Reserved field RESERVED_REG_RANGE_14 Snapshot 64 0 63 Groupname 0x1e48 64 Reserved field RESERVED_REG_RANGE_15 Snapshot 64 0 63 Groupname 0x1e50 64 Reserved field RESERVED_REG_RANGE_16 Snapshot 64 0 63 Groupname 0x1e58 64 Reserved field RESERVED_REG_RANGE_17 Snapshot 64 0 63 Groupname 0x1e60 64 Reserved field RESERVED_REG_RANGE_18 Snapshot 64 0 63 Groupname 0x1e68 64 Reserved field RESERVED_REG_RANGE_19 Snapshot 64 0 63 Groupname 0x1e70 64 Reserved field RESERVED_REG_RANGE_20 Snapshot 64 0 63 Groupname 0x1e78 64 Reserved field RESERVED_REG_RANGE_21 Snapshot 64 0 63 Groupname 0x1e80 64 Reserved field RESERVED_REG_RANGE_22 Snapshot 64 0 63 Groupname 0x1e88 64 Reserved field RESERVED_REG_RANGE_23 Snapshot 64 0 63 Groupname 0x1e90 64 Reserved field RESERVED_710 Snapshot 32 0 31 Reserved field RESERVED_711 Snapshot 32 32 63 Groupname 0x1e98 64 Reserved field RESERVED_712 Snapshot 32 0 31 IFWI VERSION OEM IFWIVERSION_OEM_UPPER Snapshot 32 32 63 Groupname 0x1ea0 64 IFWI VERSION OEM IFWIVERSION_OEM_LOWER Snapshot 32 0 31 IFWI VERSION FW CODE IFWIVERSION_FWCODE_UPPER Snapshot 32 32 63 Groupname 0x1ea8 64 IFWI VERSION FW CODE IFWIVERSION_FWCODE_LOWER Snapshot 32 0 31 IFWI VERSION FW DATA IFWVERSION_FWDATA Snapshot 32 32 63 Groupname 0x1eb0 64 Reserved field RESERVED_718 Snapshot 32 0 31 Reserved field RESERVED_719 Snapshot 32 32 63 Groupname 0x1eb8 64 SSVID SSDID SSVID_SSDID Snapshot 32 0 31 Reserved field RESERVED_721 Snapshot 32 32 63 Groupname 0x1ec0 64 Reserved field RESERVED_722 Snapshot 32 0 31 ECC STATE ECC_STATE Snapshot 32 32 63 Groupname 0x1ec8 64 AUDIO STATE AUDIO_STATE Snapshot 32 0 31 DISPLAY STATE DISPLAY_STATE Snapshot 32 32 63 Groupname 0x1ed0 64 SLICE COUNT SLICE_COUNT_1 Snapshot 32 0 31 SLICE COUNT SLICE_COUNT_2 Snapshot 32 32 63 Groupname 0x1ed8 64 SLICE COUNT SLICE_COUNT_3 Snapshot 32 0 31 NUM OF MEM CHANNEL NUM_OF_MEM_CHANNEL Snapshot 32 32 63 Groupname 0x1ee0 64 SRIOV STATE SRIOV_STATE Snapshot 32 0 31 MAX NUM VF MAX_NUM_VF Snapshot 32 32 63 Groupname 0x1ee8 64 NUM VD BOX ENABLED NUM_VD_BOX_ENABLED Snapshot 32 0 31 LMEM SIZE AVAILABLE LMEM_SIZE_AVAILABLE Snapshot 32 32 63 Groupname 0x1ef0 64 PAGE RETIREMENT ENABLED PAGE_RETIREMENT_ENABLED Snapshot 32 0 31 NUM OF RETIRED PAGES NUM_OF_RETIRED_PAGES Snapshot 32 32 63 Groupname 0x1ef8 64 MSU BITMASK MSU_BITMASK Snapshot 32 0 31 DISPLAY PIPE MASK DISPLAY_PIPE_MASK Snapshot 32 32 63 Groupname 0x1f00 64 PCIE error counter enabled PCIE_COUNTER Snapshot 32 0 31 Reserved field RESERVED_REG_RANGE_24 Snapshot 32 32 63