float parameter_0 $parameter_0 / 25e6 float parameter_0 $parameter_0 / 25e6 float parameter_0 $parameter_0 float parameter_0 $parameter_0 * 0.0025 float parameter_0 $parameter_0 float parameter_0 $parameter_0 float parameter_0 $parameter_0 * 16.67 float parameter_0 $parameter_0 float parameter_0 $parameter_0 / 8 float parameter_0 ( $parameter_0 * 1.28 ) / 1e6 float parameter_0 ( $parameter_0 * 1.28 ) / 1e6 float parameter_0 $parameter_0 * 32 / 1e6 float parameter_0 $parameter_0 * 64 / 1e6 float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x01 ) >> 0x0 ) * $parameter_0 ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x02 ) >> 0x1 ) * $parameter_0 ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x04 ) >> 0x2 ) * $parameter_0 ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x08 ) >> 0x3 ) * $parameter_0 ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x10 ) >> 0x4 ) * $parameter_0 ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x20 ) >> 0x5 ) * $parameter_0 ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x40 ) >> 0x6 ) * $parameter_0 ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x80 ) >> 0x7 ) * $parameter_0 ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x01 ) >> 0x0 ) * ( $parameter_0 * 32 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x02 ) >> 0x1 ) * ( $parameter_0 * 32 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x04 ) >> 0x2 ) * ( $parameter_0 * 32 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x08 ) >> 0x3 ) * ( $parameter_0 * 32 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x10 ) >> 0x4 ) * ( $parameter_0 * 32 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x20 ) >> 0x5 ) * ( $parameter_0 * 32 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x40 ) >> 0x6 ) * ( $parameter_0 * 32 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x80 ) >> 0x7 ) * ( $parameter_0 * 32 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x01 ) >> 0x0 ) * ( $parameter_0 * 64 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x02 ) >> 0x1 ) * ( $parameter_0 * 64 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x04 ) >> 0x2 ) * ( $parameter_0 * 64 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x08 ) >> 0x3 ) * ( $parameter_0 * 64 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x10 ) >> 0x4 ) * ( $parameter_0 * 64 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x20 ) >> 0x5 ) * ( $parameter_0 * 64 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x40 ) >> 0x6 ) * ( $parameter_0 * 64 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x80 ) >> 0x7 ) * ( $parameter_0 * 64 / 1e6 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x01 ) >> 0x0 ) * ( $parameter_0 / 256 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x02 ) >> 0x0 ) * ( $parameter_0 / 256 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x04 ) >> 0x0 ) * ( $parameter_0 / 256 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x08 ) >> 0x0 ) * ( $parameter_0 / 256 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x10 ) >> 0x0 ) * ( $parameter_0 / 256 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x20 ) >> 0x0 ) * ( $parameter_0 / 256 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x40 ) >> 0x0 ) * ( $parameter_0 / 256 ) ) float parameter_0 parameter_1 ( ( ( $parameter_1 & 0x80 ) >> 0x0 ) * ( $parameter_0 / 256 ) ) integer parameter_0 $parameter_0 BMG BMG OOBMSM PMT Telemetry aggregator samples definition and transformation rules 0x5E2F8211 Public 10 2025-01-07 This field indicates the maximum RP0 base frequency capability for the Integrated GFX Engine GT. Values are in units of 16.67 MHz bins. GT P0,P1,Pn Frequencies Snapshot Container_0 RP0_CAP freq_scaler This field indicates the maximum RPN base frequency capability for the Integrated GFX Engine GT. Values are in units of 16.67 MHz bins. GT P0,P1,Pn Frequencie Snapshot Container_0 RPN_CAP freq_scaler The efficient GT P-state in 16.67 MHz bins. Efficient frequency RPe for GT Snapshot Container_0 RPE freq_scaler RAPL Frequency constraint for GT. Snapshot Container_1 RPA generic_sample HW reflects CV voltage of GT slice0 DomainID = 1 to this field, in 2.5mV granularity. Snapshot Container_1 PERF_STATUS_SLICES_VOLTAGE_GT generic_sample Present GT frequency and VID. Snapshot Container_1 PERF_STATUS_UNSLICE_RATIO_GT generic_sample Present GT frequency and VID. Snapshot Container_1 PERF_STATUS_UNSLICE_RATIO_LSB_1MHZ_GT generic_sample Present GT frequency and VID. Snapshot Container_1 PERF_STATUS_SLICES_RATIO_GT generic_sample If Frequency is clipped because of Prochot Snapshot Container_2 PROCHOT generic_sample If Frequency is clipped because of Package thermals either SoC die or ADM die or GDDR device Snapshot Container_2 THERMAL generic_sample If frequency is clipped because VR is hitting FastVMode. Snapshot Container_2 PBM_DDR generic_sample PCS_LIMIT: Limited via PCS Snapshot Container_2 PCS_LIMIT generic_sample If frequency clipping is happening because of ICCMAX checks. Snapshot Container_2 RSR_LIMIT generic_sample Running average thermal limit Status, If Frequency is clipped because of RATL thermal algorithm Snapshot Container_2 RATL generic_sample Hot VR Status, RO, When set by PCODE indicates that Hot VR has cause GT frequency clipping. Snapshot Container_2 VR_THERMALERT generic_sample VR TDC Thermal design current Status, RO, When set by PCODE indicates that VR TDC . Thermal design current has cause MEDIA frequency clipping. Snapshot Container_2 VR_TDC generic_sample If frequency clipping is happening because of PL4 checks Snapshot Container_2 EDP generic_sample If frequency clipping is happening because of max. VID checks Snapshot Container_2 MAX_VID generic_sample If frequency clipping is happening because of Package/Psys PL1. Snapshot Container_2 PBM_PL1 generic_sample If frequency clipping is happening because of Package/Psys PL2/PL3. RO_V[/IntelRsvd] Snapshot Container_2 PBM_PL2 generic_sample If operating frequency is less than Rpe Snapshot Container_2 INEFFICIENT_OPERATION generic_sample MAX_TURBO_LIMIT: GT n-slice fused limit was hit, causing GT frequency clipping Snapshot Container_2 MAX_TURBO_LIMIT generic_sample Resolved Pkg PL1 power limit is less than advertised Minimum Value PACKAGE_POWER_SKU.PKG_MIN_PWR Snapshot Container_2 MSPE generic_sample If frequency clipping is happening because of psys_crit. Snapshot Container_2 PSYS_CRIT generic_sample PROCHOT# Log, RW, When set by PCODE indicates that PROCHOT# has cause GT frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_2 PROCHOT_LOG generic_sample Thermal Log, RW, When set by PCODE indicates that Package thermals either SoC die or ADM die or GDDR device non RATL/VR related thermal clipping have caused GT frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_2 THERMAL_LOG generic_sample PBM_DDR_LOG status Snapshot Container_2 PBM_DDR_LOG generic_sample PCS_LIMIT status Snapshot Container_2 PCS_LIMIT_LOG generic_sample Reserved Snapshot Container_2 RSR_LIMIT_LOG generic_sample Running average thermal limit Log, RW, When set by PCODE indicates that Running average thermal limit has cause GT frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_2 RATL_LOG generic_sample Hot VR Log, RW, When set by PCODE indicates that Hot VR has cause GT frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_2 VR_THERMALERT_LOG generic_sample VR TDC Log, RW, When set by PCODE indicates that VR TDC . Thermal design current has cause GT frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_2 VR_TDC_LOG generic_sample Other Status, RO, When set by PCODE, indicates that other checks IccMax, PL4 have caused GT frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_2 EDP_LOG generic_sample Max VID Status, RO, When set by PCODE, indicates that max VID checks have caused GT frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_2 MAX_VID_LOG generic_sample PBM PL1 Log, RW, When set by PCODE indicates that PBM PL1 package or platform PL1 has cause GT frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_2 PBM_PL1_LOG generic_sample PBM PL2, PL3 pkg, platform Log, RW, When set by PCODE indicates that PBM PL2 or PL3 package or platform PL2 or PL3 has cause GT frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_2 PBM_PL2_LOG generic_sample Inefficient operation Log, RW, The current GT Frequency lower than the DCC target Frequency. Software should write to this bit to clear the status in this bit Snapshot Container_2 INEFFICIENT_OPERATION_LOG generic_sample MAX_TURBO_LIMIT status Snapshot Container_2 MAX_TURBO_LIMIT_LOG generic_sample Resolved Pkg PL1 power limit is less than advertised Minimum Value PACKAGE_POWER_SKU.PKG_MIN_PWR. Software should write to this bit to clear the status in this bit Snapshot Container_2 MSPE_LOG generic_sample PSYS_CRIT, RO, When set by PCODE, indicates that PSYS_CRIT has caused GT frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_2 PSYS_CRIT_LOG generic_sample This register contains the total RC6 residency time that GT was in since boot. The counter will wrap around. The time is given in units of 1.28 uSec. GT RC6 residency Counter Container_2 GT_GFX_RC6 rc6_resi_time GT C0 residency. GT C0 residency. Counter Container_3 PKG_GT_C0_ANY generic_counter Sum the cycles if EU is active. Sum the cycles if EU is active. Counter Container_4 PKG_GT_C0_ANY_SLICE generic_counter Useful for determining GT Average Frequency when it is in C0. Useful for determining GT Average Frequency when it is in C0. Counter Container_5 PKG_GT_C0_ANY_RATIO generic_counter Useful for determining GT Average Frequency when EU is active. Useful for determining GT Average Frequency when EU is active. Counter Container_6 PKG_GT_C0_ANY_SLICE_RATIO generic_counter GT Temperature Snapshot Container_7 GT_TEMPERATURE temp_8 Media P0,P1,Pn Frequencies. Snapshot Container_7 MP0_CAP generic_sample Media P0,P1,Pn Frequencies. Snapshot Container_7 MPN_CAP generic_sample Efficient frequency RPe for Media Snapshot Container_8 MEDIA_RPE_FREQUENCY generic_sample RAPL Frequency constraint for Media. Snapshot Container_8 MPA_FREQUENCY generic_sample HW reflects CV voltage of Media to this field, in 2.5mV granularity. Snapshot Container_9 PERF_STATUS_SLICES_VOLTAGE_MEDIA generic_sample Present Media frequency and VID. Snapshot Container_9 PERF_STATUS_UNSLICE_RATIO_MEDIA generic_sample Present Media frequency and VID. Snapshot Container_9 PERF_STATUS_UNSLICE_RATIO_LSB_1MHZ_MEDIA generic_sample Present Media frequency and VID. Snapshot Container_9 PERF_STATUS_SLICES_RATIO_MEDIA generic_sample If Frequency is clipped because of Prochot Snapshot Container_9 PROCHOT_1 generic_sample If Frequency is clipped because of Package thermals either SoC die or ADM die or GDDR device Snapshot Container_9 THERMAL_1 generic_sample If frequency is clipped because VR is hitting FastVMode. Snapshot Container_9 PBM_DDR_1 generic_sample PCS_LIMIT: Limited via PCS Snapshot Container_9 PCS_LIMIT_1 generic_sample If frequency clipping is happening because of ICCMAX checks. Snapshot Container_9 RSR_LIMIT_1 generic_sample Running average thermal limit Status, If Frequency is clipped because of RATL thermal algorithm Snapshot Container_9 RATL_1 generic_sample Hot VR Status, RO, When set by PCODE indicates that Hot VR has cause GT frequency clipping. [IntelRsvd]Was RO_VFW changed in CNL to be RO_V[/IntelRsvd] Snapshot Container_9 VR_THERMALERT_1 generic_sample VR TDC Status, RO, When set by PCODE indicates that VR TDC. Thermal design current has cause MEDIA frequency clipping. Snapshot Container_9 VR_TDC_1 generic_sample If frequency clipping is happening because of PL4 checks Snapshot Container_9 EDP_1 generic_sample If frequency clipping is happening because of max. VID checks Snapshot Container_9 MAX_VID_1 generic_sample If frequency clipping is happening because of Package/Psys PL1. Snapshot Container_9 PBM_PL1_1 generic_sample If frequency clipping is happening because of Package/Psys PL2/PL3. RO_V[/IntelRsvd] Snapshot Container_9 PBM_PL2_1 generic_sample If operating frequency is less than Rpe Snapshot Container_9 INEFFICIENT_OPERATION_1 generic_sample MAX_TURBO_LIMIT: GT n-slice fused limit was hit, causing GT frequency clipping Snapshot Container_9 MAX_TURBO_LIMIT_1 generic_sample Resolved Pkg PL1 power limit is less than advertised Minimum Value PACKAGE_POWER_SKU.PKG_MIN_PWR Snapshot Container_9 MSPE_1 generic_sample If frequency clipping is happening because of psys_crit. Snapshot Container_9 PSYS_CRIT_1 generic_sample PROCHOT# Log, RW, When set by PCODE indicates that PROCHOT# has cause MEDIA frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_9 PROCHOT_LOG_1 generic_sample Thermal Log, RW, When set by PCODE indicates that Package thermals either SoC die or ADM die or GDDR device Snapshot Container_9 THERMAL_LOG_1 generic_sample PBM_DDR_LOG status Snapshot Container_9 PBM_DDR_LOG_1 generic_sample PCS_LIMIT status Snapshot Container_9 PCS_LIMIT_LOG_1 generic_sample Reserved Snapshot Container_9 RSR_LIMIT_LOG_1 generic_sample Running average thermal limit Log, RW, When set by PCODE indicates that Running average thermal limit has cause MEDIA frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_9 RATL_LOG_1 generic_sample Hot VR Log, RW, When set by PCODE indicates that Hot VR has cause MEDIA frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_9 VR_THERMALERT_LOG_1 generic_sample VR TDC Thermal design current Log, RW, When set by PCODE indicates that VR TDC .Thermal design current has cause MEDIA frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_9 VR_TDC_LOG_1 generic_sample Other IccMax, PL4, etc Status, RO, When set by PCODE, indicates that other checks have caused MEDIA frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_9 EDP_LOG_1 generic_sample Max VID Status, RO, When set by PCODE, indicates that max VID checks have caused MEDIA frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_9 MAX_VID_LOG_1 generic_sample PBM PL1 Log, RW, When set by PCODE indicates that PBM PL1 has cause MEDIA frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_9 PBM_PL1_LOG_1 generic_sample PBM PL2, PL3 Log, RW, When set by PCODE indicates that PBM PL2 or PL3, package or platform PL2 or PL3 has cause MEDIA frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_9 PBM_PL2_LOG_1 generic_sample Inefficient operation Log, RW, The current MEDIA Frequency lower than the DCC target Frequency. Software should write to this bit to clear the status in this bit Snapshot Container_9 INEFFICIENT_OPERATION_LOG_1 generic_sample MAX_TURBO_LIMIT status Snapshot Container_9 MAX_TURBO_LIMIT_LOG_1 generic_sample Resolved Pkg PL1 power limit is less than advertised Minimum Value PACKAGE_POWER_SKU.PKG_MIN_PWR. Software should write to this bit to clear the status in this bit Snapshot Container_9 MSPE_LOG_1 generic_sample PSYS_CRIT, RO, When set by PCODE, indicates that PSYS_CRIT has caused MEDIA frequency clipping. Software should write to this bit to clear the status in this bit Snapshot Container_9 PSYS_CRIT_LOG_1 generic_sample This register contains the total MC6 residency time that media was in since boot. The counter will wrap around. The time is given in units of 1.28 uSec. Media MC6 residency. Counter Container_10 MEDIA_MC6 mc6_resi_time Media Temperature Snapshot Container_10 MEDIA_TEMPERATURE temp_8 Media C0 residency Media C0 residency Counter Container_11 PKG_MEDIA_C0_ANY generic_counter Sum the cycles if any Media Engine is active. Sum the cycles if any Media Engine is active. Counter Container_12 PKG_MEDIA_C0_ANY_SLICE generic_counter Sum the cycles if any Media Engine is active with Media Count Sum the cycles if any Media Engine is active with Media Count Counter Container_13 PKG_MEDIA_C0_SLICES_SUM generic_counter Useful for determining Media Average Frequency when it is in C0 Useful for determining Media Average Frequency when it is in C0 Counter Container_14 PKG_MEDIA_C0_ANY_RATIO generic_counter Useful for determining Media Average Frequency when any Media Engine is active. Useful for determining Media Average Frequency when any Media Engine is active. Counter Container_15 PKG_MEDIA_C0_ANY_SLICE_RATIO generic_counter The TDP package power setting allowed for this part. The units for this value are defined in PACKAGE_POWER_SKU_MSR[PWR_UNIT]. Snapshot Container_16 PKG_TDP generic_sample The minimal package power setting allowed for this part. Lower values will be clamped to this value. The minimum setting is typical Snapshot Container_16 PKG_MIN_PWR generic_sample The maximal package power setting allowed for the SKU. Higher values will be clamped to this value. The maximum setting is typical not guaranteed. Snapshot Container_16 PKG_MAX_PWR generic_sample The maximal time window allowed for the SKU. Higher values will be clamped to this value. Snapshot Container_16 PKG_MAX_WIN generic_sample Package Energy Accumulator Snapshot Container_17 PACKAGE_ENERGY_STATUS_SKU generic_sample Psys GPU Energy Accumulator Snapshot Container_17 PLATFORM_ENERGY_STATUS generic_sample Number of Tachometer Pulses from PWM fan Number of Tachometer Pulses from PWM fan Counter Container_18 PWM_FAN_1_SPEED generic_counter Number of Tachometer Pulses from PWM fan Number of Tachometer Pulses from PWM fan Counter Container_18 PWM_FAN_2_SPEED generic_counter Worst Temperature across SoC Top die and ADM Snapshot Container_19 Package_Temperature temp_8 Worst case thermal margin available before thermal throttling can occur Snapshot Container_19 PACKAGE_THERM_MARGIN temp Worst Temperature across ADM Snapshot Container_20 SOC_TEMP0 temp_8 Worst Temperature across SoC TopDie. Snapshot Container_20 SOC_TEMP1 temp_8 Worst Temperature across all GDDR devices Snapshot Container_21 VRAM_TEMPERATURE temp_8 GDDR0 device temperature Snapshot Container_21 GDDR0_DEVICE_TEMPERATURE0 Container_461 MSU_BITMASK mem0_temp_counter GDDR0 device temperature Snapshot Container_22 GDDR0_DEVICE_TEMPERATURE1 Container_461 MSU_BITMASK mem0_temp_counter GDDR1 device temperature Snapshot Container_22 GDDR1_DEVICE_TEMPERATURE0 Container_461 MSU_BITMASK mem1_temp_counter GDDR1 device temperature Snapshot Container_23 GDDR1_DEVICE_TEMPERATURE1 Container_461 MSU_BITMASK mem1_temp_counter GDDR2 device temperature Snapshot Container_23 GDDR2_DEVICE_TEMPERATURE0 Container_461 MSU_BITMASK mem2_temp_counter GDDR2 device temperature Snapshot Container_24 GDDR2_DEVICE_TEMPERATURE1 Container_461 MSU_BITMASK mem2_temp_counter GDDR3 device temperature Snapshot Container_24 GDDR3_DEVICE_TEMPERATURE0 Container_461 MSU_BITMASK mem3_temp_counter GDDR3device temperature Snapshot Container_25 GDDR3_DEVICE_TEMPERATURE1 Container_461 MSU_BITMASK mem3_temp_counter GDDR4 device temperature Snapshot Container_25 GDDR4_DEVICE_TEMPERATURE0 Container_461 MSU_BITMASK mem4_temp_counter GDDR4 device temperature Snapshot Container_26 GDDR4_DEVICE_TEMPERATURE1 Container_461 MSU_BITMASK mem4_temp_counter GDDR5 device temperature Snapshot Container_26 GDDR5_DEVICE_TEMPERATURE0 Container_461 MSU_BITMASK mem5_temp_counter GDDR5 device temperature Snapshot Container_27 GDDR5_DEVICE_TEMPERATURE1 Container_461 MSU_BITMASK mem5_temp_counter Reserved field Snapshot Container_27 RESERVED_119 generic_sample Reserved field Snapshot Container_28 RESERVED_120 generic_sample Reserved field Snapshot Container_28 RESERVED_121 generic_sample Reserved field Snapshot Container_29 RESERVED_122 generic_sample Platform Ambient Temperature. Memory Thermal Sensor Calibrated Temperature written by pcode. Snapshot Container_29 PLATFORM_AMB_TEMPERATURE0 temp_8 Platform Ambient Temperature. Memory Thermal Sensor Calibrated Temperature written by pcode. Snapshot Container_30 PLATFORM_AMB_TEMPERATURE1 temp_8 MBVR Temperatures VCCGT. Memory Thermal Sensor Calibrated Temperature written by pcode. Snapshot Container_30 PLATFORM_VCCGT_VR_TEMPERATURE temp_8 MBVR Temperatures VCCADM_DIG. Memory Thermal Sensor Calibrated Temperature written by pcode. Snapshot Container_31 PLATFORM_VCCADM_DIG_VR_TEMPERATURE temp_8 MBVR Temperatures VCCDDR. Memory Thermal Sensor Calibrated Temperature written by pcode. Snapshot Container_31 PLATFORM_VCCDDR_VR_TEMPERATURE temp_8 MBVR Temperatures VCCSA. Memory Thermal Sensor Calibrated Temperature written by pcode. Snapshot Container_32 PLATFORM_VCCSA_VR_TEMPERATURE temp_8 Policy for slice/unslice GT ratios: Snapshot Container_32 SLICE_UNSLICE_POLICY_GT freq_scaler reserved bits Snapshot Container_32 RESEREVED freq_scaler Latest GT frequency Request Snapshot Container_32 MEDIA_RATIO_REQ_GT freq_scaler reserved bits Snapshot Container_32 SLICE_RATIO_GT freq_scaler This field indicates the maximum P-State request for GT Unslice in units of 16.666MHz frequency request before entering RC6. It is determined by GT Driver. Snapshot Container_32 UNSLICE_RATIO_GT freq_scaler Policy for slice/unslice GT ratios: Snapshot Container_33 SLICE_UNSLICE_POLICY_MEDIA freq_scaler reserved bits Snapshot Container_33 RESEREVED_1 freq_scaler Latest Media frequency Request Snapshot Container_33 MEDIA_RATIO_REQ_MEDIA freq_scaler reserved bits Snapshot Container_33 SLICE_RATIO_MEDIA freq_scaler This field indicates the maximum P-State request for GT Unslice in units of 16.666MHz frequency request before entering RC6. It is determined by GT Driver. Snapshot Container_33 UNSLICE_RATIO_MEDIA freq_scaler Current state of the LTSSM. Encoding is defined as follows: Snapshot Container_33 SMLH_LTSSM_STATE generic_counter PHY Link up/down indicator: Snapshot Container_33 SMLH_LINK_UP generic_counter Data link layer up/down indicator: This status from the flow control initialization state machine indicates that flow control has been initiated and the Data link layer is ready to transmit and receive packets. For multi-VC designs, this register indicates status for VC0 only. Snapshot Container_33 RDLH_LINK_UP generic_counter Reserved Snapshot Container_33 RSVDP_11 generic_counter Reserved Snapshot Container_33 RSVDP_12 generic_counter Reserved Snapshot Container_33 RSVDP_15 generic_counter RADM VC0 queue is not empty. Snapshot Container_33 VC0_Q_NOT_EMPTY generic_counter Reserved Snapshot Container_33 RSVDP_17 generic_counter Reserved Snapshot Container_33 RSVDP_18 generic_counter Reserved Snapshot Container_33 RSVDP_19 generic_counter Reserved Snapshot Container_33 RSVDP_20 generic_counter Reserved Snapshot Container_33 RSVDP_21 generic_counter Reserved Snapshot Container_33 RSVDP_22 generic_counter Reserved Snapshot Container_33 RSVDP_23 generic_counter Indicator that PCIe controller register block is under reset or to be reset. When this register is 1, programming to PCIe controller register block might be reset. Snapshot Container_33 CDM_IN_RESET generic_counter Link signaling rate. Snapshot Container_33 RATE generic_counter PHY power state. Snapshot Container_33 PHY_POWRDOWN generic_counter Active State Power Management ASPM Control. Snapshot Container_34 PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL generic_counter Reserved for future use. Snapshot Container_34 RSVDP_2 generic_counter Read Completion Boundary RCB. Snapshot Container_34 PCIE_CAP_RCB generic_counter Link Disable. Snapshot Container_34 PCIE_CAP_LINK_DISABLE generic_counter Retrain Link. Snapshot Container_34 PCIE_CAP_RETRAIN_LINK generic_counter Common Clock Configuration. When set, this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. Snapshot Container_34 PCIE_CAP_COMMON_CLK_CONFIG generic_counter Extended Synch. When set, this bit forces the transmission of additional Ordered Sets when exiting the L0s state and when in the Recovery state (see section 4.2.6.4.1 of PCI . This mode provides external devices monitoring the Link time to achieve bit and Symbol lock before the Link enters the L0 state and resumes communication. Snapshot Container_34 PCIE_CAP_EXTENDED_SYNCH generic_counter Enable Clock Power Management. Snapshot Container_34 PCIE_CAP_EN_CLK_POWER_MAN generic_counter Hardware Autonomous Width Disable. Snapshot Container_34 PCIE_CAP_HW_AUTO_WIDTH_DISABLE generic_counter Link Bandwidth Management Interrupt Enable. When set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Snapshot Container_34 PCIE_CAP_LINK_BW_MAN_INT_EN generic_counter Link Autonomous Bandwidth Management Interrupt Enable. Snapshot Container_34 PCIE_CAP_LINK_AUTO_BW_INT_EN generic_counter Reserved for future use. Snapshot Container_34 RSVDP_12_1 generic_counter DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: Snapshot Container_34 PCIE_CAP_DRS_SIGNALING_CONTROL generic_counter Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. Snapshot Container_34 PCIE_CAP_LINK_SPEED generic_counter Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Snapshot Container_34 PCIE_CAP_NEGO_LINK_WIDTH generic_counter Reserved for future use. Snapshot Container_34 RSVDP_26 generic_counter Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state, or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when the LTSSM exits the Configuration/Recovery state. Snapshot Container_34 PCIE_CAP_LINK_TRAINING generic_counter Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a reference clock on the connector, this bit must be clear. Snapshot Container_34 PCIE_CAP_SLOT_CLK_CONFIG generic_counter Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state, 0b otherwise. Snapshot Container_34 PCIE_CAP_DLL_ACTIVE generic_counter Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: Snapshot Container_34 PCIE_CAP_LINK_BW_MAN_STATUS generic_counter Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width, without the Port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable Link operation. Snapshot Container_34 PCIE_CAP_LINK_AUTO_BW_STATUS generic_counter Counter to detect PCIE link traning and downgrade Counter to detect PCIE link traning and downgrade Counter Container_34 PCIE_EVENT_COUNTER_DATA generic_counter 32 bits of received byte count in downstream path. For every n us time programmed in cfg_num_auxclks new value sampled into this register. 64 bits of rx byte counter Counter Container_35 PCIE_RECEIVE_BYTES generic_counter 32 bits of transmitted byte count in Upstream path. For every n us time programmed in cfg_num_auxclks new value sampled into this register. 64 bits of tx byte counter Counter Container_36 PCIE_TRANSMIT_BYTES generic_counter 32 bits of received packet count in downstream path 64 bits of rx packet counter Counter Container_37 PCIE_RECEIVE_PACKETS generic_counter 32 bits of transmitted packet count in upstream path 64 bits of tx packet counter Counter Container_38 PCIE_TRANSMIT_PACKETS generic_counter 32 bits of PCIe L0 state time counter. For every n us time programmed in cfg_num_auxclks new value sampled into this register. 64 bits of L0 residence counter Counter Container_39 PCIE_L0_RESIDENCY generic_counter 32 bits of PCIe L0s state time counter. For every n us time programmed in cfg_num_auxclks new value sampled into this register. 64 bits of L0s residence counter Counter Container_40 PCIE_L0s_RESIDENCY generic_counter 32 bits of PCIe L1 state time counter. For every n us time programmed in cfg_num_auxclks new value sampled into this register. 64 bits of L1 residence counter Counter Container_41 PCIE_L1_RESIDENCY generic_counter 32 bits of PCIe L1sub state time counter. For every n us time programmed in cfg_num_auxclks new value sampled into this register. 64 bits of L1sub residence counter Counter Container_42 PCIE_L1sub_RESIDENCY generic_counter 32 bits of PCIe L2 state time counter. For every n us time programmed in cfg_num_auxclks new value sampled into this register. 64 bits of L2 residence counter Counter Container_43 PCIE_L2_RESIDENCY generic_counter Lower 16 bit represents tlp error corresponds to radm_trgt1_tlp_abort and upper 16 bits represents dllp error count. DLLP error count Counter Container_44 PCIE_RX_TLP_DLLP_ERRORS generic_counter Lower 16 bit represents ECRCerror corresponds to radm_trgt1_ecrc_err and upper 16 bits Reserved PCIE RX CRC error Counter Container_44 PCIE_RX_ECRC_ERRORS generic_counter Lower 16 bit represents command parity error and upper 16 bits represents data parity error count. data packet error count Counter Container_45 PCIE_DNS_PARITY_ERRORS generic_counter Upstream command and data parity error count Data Parity Error count. Counter Container_45 PCIE_UPS_PARITY_ERRORS generic_counter TimeStamp units in milliseconds TIMESTAMP Counter Container_46 TIMESTAMP generic_counter read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_47 GDDR0_CH0_GT_32B_RD_REQ Container_461 MSU_BITMASK msu0_32bw_counter read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_48 GDDR0_CH0_GT_64B_RD_REQ Container_461 MSU_BITMASK msu0_32bw_counter write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_49 GDDR0_CH0_GT_32B_WR_REQ Container_461 MSU_BITMASK msu0_32bw_counter write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_50 GDDR0_CH0_GT_64B_WR_REQ Container_461 MSU_BITMASK msu0_32bw_counter Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_51 GDDR0_CH0_DISPLAYVC0_32B_RD_REQ Container_461 MSU_BITMASK msu0_32bw_counter Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_52 GDDR0_CH0_DISPLAYVC0_64B_RD_REQ Container_461 MSU_BITMASK msu0_32bw_counter read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_53 GDDR0_CH0_SOC_32B_RD_REQ Container_461 MSU_BITMASK msu0_32bw_counter read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_54 GDDR0_CH0_SOC_64B_RD_REQ Container_461 MSU_BITMASK msu0_32bw_counter write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_55 GDDR0_CH0_SOC_32B_WR_REQ Container_461 MSU_BITMASK msu0_32bw_counter write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_56 GDDR0_CH0_SOC_64B_WR_REQ Container_461 MSU_BITMASK msu0_32bw_counter read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_57 GDDR0_CH1_GT_32B_RD_REQ Container_461 MSU_BITMASK msu0_32bw_counter read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_58 GDDR0_CH1_GT_64B_RD_REQ Container_461 MSU_BITMASK msu0_32bw_counter write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_59 GDDR0_CH1_GT_32B_WR_REQ Container_461 MSU_BITMASK msu0_32bw_counter write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_60 GDDR0_CH1_GT_64B_WR_REQ Container_461 MSU_BITMASK msu0_32bw_counter Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_61 GDDR0_CH1_DISPLAYVC0_32B_RD_REQ Container_461 MSU_BITMASK msu0_32bw_counter Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_62 GDDR0_CH1_DISPLAYVC0_64B_RD_REQ Container_461 MSU_BITMASK msu0_32bw_counter read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_63 GDDR0_CH1_SOC_32B_RD_REQ Container_461 MSU_BITMASK msu0_32bw_counter read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_64 GDDR0_CH1_SOC_64B_RD_REQ Container_461 MSU_BITMASK msu0_32bw_counter write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_65 GDDR0_CH1_SOC_32B_WR_REQ Container_461 MSU_BITMASK msu0_32bw_counter write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x01 SHIFT 0x0) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_66 GDDR0_CH1_SOC_64B_WR_REQ Container_461 MSU_BITMASK msu0_32bw_counter read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_67 GDDR1_CH0_GT_32B_RD_REQ Container_461 MSU_BITMASK msu1_32bw_counter read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_68 GDDR1_CH0_GT_64B_RD_REQ Container_461 MSU_BITMASK msu1_32bw_counter write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_69 GDDR1_CH0_GT_32B_WR_REQ Container_461 MSU_BITMASK msu1_32bw_counter write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_70 GDDR1_CH0_GT_64B_WR_REQ Container_461 MSU_BITMASK msu1_32bw_counter Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_71 GDDR1_CH0_DISPLAYVC0_32B_RD_REQ Container_461 MSU_BITMASK msu1_32bw_counter Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_72 GDDR1_CH0_DISPLAYVC0_64B_RD_REQ Container_461 MSU_BITMASK msu1_32bw_counter read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_73 GDDR1_CH0_SOC_32B_RD_REQ Container_461 MSU_BITMASK msu1_32bw_counter read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_74 GDDR1_CH0_SOC_64B_RD_REQ Container_461 MSU_BITMASK msu1_32bw_counter write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_75 GDDR1_CH0_SOC_32B_WR_REQ Container_461 MSU_BITMASK msu1_32bw_counter write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_76 GDDR1_CH0_SOC_64B_WR_REQ Container_461 MSU_BITMASK msu1_32bw_counter read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_77 GDDR1_CH1_GT_32B_RD_REQ Container_461 MSU_BITMASK msu1_32bw_counter read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_78 GDDR1_CH1_GT_64B_RD_REQ Container_461 MSU_BITMASK msu1_32bw_counter write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_79 GDDR1_CH1_GT_32B_WR_REQ Container_461 MSU_BITMASK msu1_32bw_counter write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_80 GDDR1_CH1_GT_64B_WR_REQ Container_461 MSU_BITMASK msu1_32bw_counter Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_81 GDDR1_CH1_DISPLAYVC0_32B_RD_REQ Container_461 MSU_BITMASK msu1_32bw_counter Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_82 GDDR1_CH1_DISPLAYVC0_64B_RD_REQ Container_461 MSU_BITMASK msu1_32bw_counter read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_83 GDDR1_CH1_SOC_32B_RD_REQ Container_461 MSU_BITMASK msu1_32bw_counter read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_84 GDDR1_CH1_SOC_64B_RD_REQ Container_461 MSU_BITMASK msu1_32bw_counter write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_85 GDDR1_CH1_SOC_32B_WR_REQ Container_461 MSU_BITMASK msu1_32bw_counter write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x02 SHIFT 0x1) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_86 GDDR1_CH1_SOC_64B_WR_REQ Container_461 MSU_BITMASK msu1_32bw_counter read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_87 GDDR2_CH0_GT_32B_RD_REQ Container_461 MSU_BITMASK msu2_32bw_counter read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_88 GDDR2_CH0_GT_64B_RD_REQ Container_461 MSU_BITMASK msu2_32bw_counter write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_89 GDDR2_CH0_GT_32B_WR_REQ Container_461 MSU_BITMASK msu2_32bw_counter write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_90 GDDR2_CH0_GT_64B_WR_REQ Container_461 MSU_BITMASK msu2_32bw_counter Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_91 GDDR2_CH0_DISPLAYVC0_32B_RD_REQ Container_461 MSU_BITMASK msu2_32bw_counter Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_92 GDDR2_CH0_DISPLAYVC0_64B_RD_REQ Container_461 MSU_BITMASK msu2_32bw_counter read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_93 GDDR2_CH0_SOC_32B_RD_REQ Container_461 MSU_BITMASK msu2_32bw_counter read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_94 GDDR2_CH0_SOC_64B_RD_REQ Container_461 MSU_BITMASK msu2_32bw_counter write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_95 GDDR2_CH0_SOC_32B_WR_REQ Container_461 MSU_BITMASK msu2_32bw_counter write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_96 GDDR2_CH0_SOC_64B_WR_REQ Container_461 MSU_BITMASK msu2_32bw_counter read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_97 GDDR2_CH1_GT_32B_RD_REQ Container_461 MSU_BITMASK msu2_32bw_counter read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_98 GDDR2_CH1_GT_64B_RD_REQ Container_461 MSU_BITMASK msu2_32bw_counter write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_99 GDDR2_CH1_GT_32B_WR_REQ Container_461 MSU_BITMASK msu2_32bw_counter write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_100 GDDR2_CH1_GT_64B_WR_REQ Container_461 MSU_BITMASK msu2_32bw_counter Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_101 GDDR2_CH1_DISPLAYVC0_32B_RD_REQ Container_461 MSU_BITMASK msu2_32bw_counter Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_102 GDDR2_CH1_DISPLAYVC0_64B_RD_REQ Container_461 MSU_BITMASK msu2_32bw_counter read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_103 GDDR2_CH1_SOC_32B_RD_REQ Container_461 MSU_BITMASK msu2_32bw_counter read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_104 GDDR2_CH1_SOC_64B_RD_REQ Container_461 MSU_BITMASK msu2_32bw_counter write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_105 GDDR2_CH1_SOC_32B_WR_REQ Container_461 MSU_BITMASK msu2_32bw_counter write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x04 SHIFT 0x2) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_106 GDDR2_CH1_SOC_64B_WR_REQ Container_461 MSU_BITMASK msu2_32bw_counter read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_107 GDDR3_CH0_GT_32B_RD_REQ Container_461 MSU_BITMASK msu3_32bw_counter read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_108 GDDR3_CH0_GT_64B_RD_REQ Container_461 MSU_BITMASK msu3_32bw_counter write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_109 GDDR3_CH0_GT_32B_WR_REQ Container_461 MSU_BITMASK msu3_32bw_counter write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_110 GDDR3_CH0_GT_64B_WR_REQ Container_461 MSU_BITMASK msu3_32bw_counter Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_111 GDDR3_CH0_DISPLAYVC0_32B_RD_REQ Container_461 MSU_BITMASK msu3_32bw_counter Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_112 GDDR3_CH0_DISPLAYVC0_64B_RD_REQ Container_461 MSU_BITMASK msu3_32bw_counter read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_113 GDDR3_CH0_SOC_32B_RD_REQ Container_461 MSU_BITMASK msu3_32bw_counter read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_114 GDDR3_CH0_SOC_64B_RD_REQ Container_461 MSU_BITMASK msu3_32bw_counter write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_115 GDDR3_CH0_SOC_32B_WR_REQ Container_461 MSU_BITMASK msu3_32bw_counter write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_116 GDDR3_CH0_SOC_64B_WR_REQ Container_461 MSU_BITMASK msu3_32bw_counter read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_117 GDDR3_CH1_GT_32B_RD_REQ Container_461 MSU_BITMASK msu3_32bw_counter read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_118 GDDR3_CH1_GT_64B_RD_REQ Container_461 MSU_BITMASK msu3_32bw_counter write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_119 GDDR3_CH1_GT_32B_WR_REQ Container_461 MSU_BITMASK msu3_32bw_counter write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_120 GDDR3_CH1_GT_64B_WR_REQ Container_461 MSU_BITMASK msu3_32bw_counter Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_121 GDDR3_CH1_DISPLAYVC0_32B_RD_REQ Container_461 MSU_BITMASK msu3_32bw_counter Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_122 GDDR3_CH1_DISPLAYVC0_64B_RD_REQ Container_461 MSU_BITMASK msu3_32bw_counter read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_123 GDDR3_CH1_SOC_32B_RD_REQ Container_461 MSU_BITMASK msu3_32bw_counter read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_124 GDDR3_CH1_SOC_64B_RD_REQ Container_461 MSU_BITMASK msu3_32bw_counter write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_125 GDDR3_CH1_SOC_32B_WR_REQ Container_461 MSU_BITMASK msu3_32bw_counter write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x08 SHIFT 0x3) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_126 GDDR3_CH1_SOC_64B_WR_REQ Container_461 MSU_BITMASK msu3_32bw_counter read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_127 GDDR4_CH0_GT_32B_RD_REQ Container_461 MSU_BITMASK msu4_32bw_counter read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_128 GDDR4_CH0_GT_64B_RD_REQ Container_461 MSU_BITMASK msu4_32bw_counter write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_129 GDDR4_CH0_GT_32B_WR_REQ Container_461 MSU_BITMASK msu4_32bw_counter write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_130 GDDR4_CH0_GT_64B_WR_REQ Container_461 MSU_BITMASK msu4_32bw_counter Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_131 GDDR4_CH0_DISPLAYVC0_32B_RD_REQ Container_461 MSU_BITMASK msu4_32bw_counter Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_132 GDDR4_CH0_DISPLAYVC0_64B_RD_REQ Container_461 MSU_BITMASK msu4_32bw_counter read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_133 GDDR4_CH0_SOC_32B_RD_REQ Container_461 MSU_BITMASK msu4_32bw_counter read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_134 GDDR4_CH0_SOC_64B_RD_REQ Container_461 MSU_BITMASK msu4_32bw_counter write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_135 GDDR4_CH0_SOC_32B_WR_REQ Container_461 MSU_BITMASK msu4_32bw_counter write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_136 GDDR4_CH0_SOC_64B_WR_REQ Container_461 MSU_BITMASK msu4_32bw_counter read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_137 GDDR4_CH1_GT_32B_RD_REQ Container_461 MSU_BITMASK msu4_32bw_counter read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_138 GDDR4_CH1_GT_64B_RD_REQ Container_461 MSU_BITMASK msu4_32bw_counter write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_139 GDDR4_CH1_GT_32B_WR_REQ Container_461 MSU_BITMASK msu4_32bw_counter write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_140 GDDR4_CH1_GT_64B_WR_REQ Container_461 MSU_BITMASK msu4_32bw_counter Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_141 GDDR4_CH1_DISPLAYVC0_32B_RD_REQ Container_461 MSU_BITMASK msu4_32bw_counter Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_142 GDDR4_CH1_DISPLAYVC0_64B_RD_REQ Container_461 MSU_BITMASK msu4_32bw_counter read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_143 GDDR4_CH1_SOC_32B_RD_REQ Container_461 MSU_BITMASK msu4_32bw_counter read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_144 GDDR4_CH1_SOC_64B_RD_REQ Container_461 MSU_BITMASK msu4_32bw_counter write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_145 GDDR4_CH1_SOC_32B_WR_REQ Container_461 MSU_BITMASK msu4_32bw_counter write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x10 SHIFT 0x4) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_146 GDDR4_CH1_SOC_64B_WR_REQ Container_461 MSU_BITMASK msu4_32bw_counter read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_147 GDDR5_CH0_GT_32B_RD_REQ Container_461 MSU_BITMASK msu5_32bw_counter read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_148 GDDR5_CH0_GT_64B_RD_REQ Container_461 MSU_BITMASK msu5_32bw_counter write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_149 GDDR5_CH0_GT_32B_WR_REQ Container_461 MSU_BITMASK msu5_32bw_counter write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_150 GDDR5_CH0_GT_64B_WR_REQ Container_461 MSU_BITMASK msu5_32bw_counter Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_151 GDDR5_CH0_DISPLAYVC0_32B_RD_REQ Container_461 MSU_BITMASK msu5_32bw_counter Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_152 GDDR5_CH0_DISPLAYVC0_64B_RD_REQ Container_461 MSU_BITMASK msu5_32bw_counter read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_153 GDDR5_CH0_SOC_32B_RD_REQ Container_461 MSU_BITMASK msu5_32bw_counter read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_154 GDDR5_CH0_SOC_64B_RD_REQ Container_461 MSU_BITMASK msu5_32bw_counter write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_155 GDDR5_CH0_SOC_32B_WR_REQ Container_461 MSU_BITMASK msu5_32bw_counter write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH0. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_156 GDDR5_CH0_SOC_64B_WR_REQ Container_461 MSU_BITMASK msu5_32bw_counter read bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_157 GDDR5_CH1_GT_32B_RD_REQ Container_461 MSU_BITMASK msu5_32bw_counter read bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_158 GDDR5_CH1_GT_64B_RD_REQ Container_461 MSU_BITMASK msu5_32bw_counter write bandwidth of 32B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 32B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_159 GDDR5_CH1_GT_32B_WR_REQ Container_461 MSU_BITMASK msu5_32bw_counter write bandwidth of 64B requests from GT to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 64B requests from GT to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_160 GDDR5_CH1_GT_64B_WR_REQ Container_461 MSU_BITMASK msu5_32bw_counter Display iosch read bandwidth of 32B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "Display iosch read bandwidth of 32B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_161 GDDR5_CH1_DISPLAYVC0_32B_RD_REQ Container_461 MSU_BITMASK msu5_32bw_counter Display iosch read bandwidth of 64B requests to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "Display iosch read bandwidth of 64B requests to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_162 GDDR5_CH1_DISPLAYVC0_64B_RD_REQ Container_461 MSU_BITMASK msu5_32bw_counter read bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_163 GDDR5_CH1_SOC_32B_RD_REQ Container_461 MSU_BITMASK msu5_32bw_counter read bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "read bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_164 GDDR5_CH1_SOC_64B_RD_REQ Container_461 MSU_BITMASK msu5_32bw_counter write bandwidth of 32B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 32B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*32/1e6 (MB)" Counter Container_165 GDDR5_CH1_SOC_32B_WR_REQ Container_461 MSU_BITMASK msu5_32bw_counter write bandwidth of 64B requests from SOC memory port to GDDR CH. Total BW is sum of 32B and 64B requests. MSU_BITMASK AND 0x20 SHIFT 0x5) * field*32/1e6 "write bandwidth of 64B requests from SOC memory port to GDDR CH1. Total BW is sum of 32B and 64B requests field*64/1e6 (MB)" Counter Container_166 GDDR5_CH1_SOC_64B_WR_REQ Container_461 MSU_BITMASK msu5_32bw_counter Reserved field Counter Container_167 RESERVED_312 generic_counter Reserved field Counter Container_168 RESERVED_313 generic_counter Reserved field Counter Container_169 RESERVED_314 generic_counter Reserved field Counter Container_170 RESERVED_315 generic_counter Reserved field Counter Container_171 RESERVED_316 generic_counter Reserved field Counter Container_172 RESERVED_317 generic_counter Reserved field Counter Container_173 RESERVED_318 generic_counter Reserved field Counter Container_174 RESERVED_319 generic_counter Reserved field Counter Container_175 RESERVED_320 generic_counter Reserved field Counter Container_176 RESERVED_321 generic_counter Reserved field Counter Container_177 RESERVED_322 generic_counter Reserved field Counter Container_178 RESERVED_323 generic_counter Reserved field Counter Container_179 RESERVED_324 generic_counter Reserved field Counter Container_180 RESERVED_325 generic_counter Reserved field Counter Container_181 RESERVED_326 generic_counter Reserved field Counter Container_182 RESERVED_327 generic_counter Reserved field Counter Container_183 RESERVED_328 generic_counter Reserved field Counter Container_184 RESERVED_329 generic_counter Reserved field Counter Container_185 RESERVED_330 generic_counter Reserved field Counter Container_186 RESERVED_331 generic_counter Reserved field Counter Container_187 RESERVED_332 generic_counter Reserved field Counter Container_188 RESERVED_333 generic_counter Reserved field Counter Container_189 RESERVED_334 generic_counter Reserved field Counter Container_190 RESERVED_335 generic_counter Reserved field Counter Container_191 RESERVED_336 generic_counter Reserved field Counter Container_192 RESERVED_337 generic_counter Reserved field Counter Container_193 RESERVED_338 generic_counter Reserved field Counter Container_194 RESERVED_339 generic_counter Reserved field Counter Container_195 RESERVED_340 generic_counter Reserved field Counter Container_196 RESERVED_341 generic_counter Reserved field Counter Container_197 RESERVED_342 generic_counter Reserved field Counter Container_198 RESERVED_343 generic_counter Reserved field Counter Container_199 RESERVED_344 generic_counter Reserved field Counter Container_200 RESERVED_345 generic_counter Reserved field Counter Container_201 RESERVED_346 generic_counter Reserved field Counter Container_202 RESERVED_347 generic_counter Reserved field Counter Container_203 RESERVED_348 generic_counter Reserved field Counter Container_204 RESERVED_349 generic_counter Reserved field Counter Container_205 RESERVED_350 generic_counter Reserved field Counter Container_206 RESERVED_351 generic_counter Reserved field Counter Container_207 RESERVED_352 generic_counter Reserved field Counter Container_208 RESERVED_353 generic_counter Reserved field Counter Container_209 RESERVED_354 generic_counter Reserved field Counter Container_210 RESERVED_355 generic_counter Reserved field Counter Container_211 RESERVED_356 generic_counter Reserved field Counter Container_212 RESERVED_357 generic_counter Reserved field Counter Container_213 RESERVED_358 generic_counter Reserved field Counter Container_214 RESERVED_359 generic_counter Reserved field Counter Container_215 RESERVED_360 generic_counter Reserved field Counter Container_216 RESERVED_361 generic_counter Reserved field Counter Container_217 RESERVED_362 generic_counter Reserved field Counter Container_218 RESERVED_363 generic_counter Reserved field Counter Container_219 RESERVED_364 generic_counter Reserved field Counter Container_220 RESERVED_365 generic_counter Reserved field Counter Container_221 RESERVED_366 generic_counter Reserved field Counter Container_222 RESERVED_367 generic_counter Reserved field Counter Container_223 RESERVED_368 generic_counter Reserved field Counter Container_224 RESERVED_369 generic_counter Reserved field Counter Container_225 RESERVED_370 generic_counter Reserved field Counter Container_226 RESERVED_371 generic_counter Reserved field Counter Container_227 RESERVED_372 generic_counter Reserved field Counter Container_228 RESERVED_373 generic_counter Reserved field Counter Container_229 RESERVED_374 generic_counter Reserved field Counter Container_230 RESERVED_375 generic_counter Reserved field Counter Container_231 RESERVED_376 generic_counter Reserved field Counter Container_232 RESERVED_377 generic_counter Reserved field Counter Container_233 RESERVED_378 generic_counter Reserved field Counter Container_234 RESERVED_379 generic_counter Reserved field Counter Container_235 RESERVED_380 generic_counter Reserved field Counter Container_236 RESERVED_381 generic_counter Reserved field Counter Container_237 RESERVED_382 generic_counter Reserved field Counter Container_238 RESERVED_383 generic_counter Reserved field Counter Container_239 RESERVED_384 generic_counter Reserved field Counter Container_240 RESERVED_385 generic_counter Reserved field Counter Container_241 RESERVED_386 generic_counter Reserved field Counter Container_242 RESERVED_387 generic_counter Reserved field Counter Container_243 RESERVED_388 generic_counter Reserved field Counter Container_244 RESERVED_389 generic_counter Reserved field Counter Container_245 RESERVED_390 generic_counter Reserved field Counter Container_246 RESERVED_391 generic_counter Reserved field Counter Container_247 RESERVED_392 generic_counter Reserved field Counter Container_248 RESERVED_393 generic_counter Reserved field Counter Container_249 RESERVED_394 generic_counter Reserved field Counter Container_250 RESERVED_395 generic_counter Reserved field Counter Container_251 RESERVED_396 generic_counter Reserved field Counter Container_252 RESERVED_397 generic_counter Reserved field Counter Container_253 RESERVED_398 generic_counter Reserved field Counter Container_254 RESERVED_399 generic_counter Reserved field Counter Container_255 RESERVED_400 generic_counter Reserved field Counter Container_256 RESERVED_401 generic_counter Reserved field Counter Container_257 RESERVED_402 generic_counter Reserved field Counter Container_258 RESERVED_403 generic_counter Reserved field Counter Container_259 RESERVED_404 generic_counter Reserved field Counter Container_260 RESERVED_405 generic_counter Reserved field Counter Container_261 RESERVED_406 generic_counter Reserved field Counter Container_262 RESERVED_407 generic_counter Reserved field Counter Container_263 RESERVED_408 generic_counter Reserved field Counter Container_264 RESERVED_409 generic_counter Reserved field Counter Container_265 RESERVED_410 generic_counter Reserved field Counter Container_266 RESERVED_411 generic_counter Reserved field Counter Container_267 RESERVED_412 generic_counter Reserved field Counter Container_268 RESERVED_413 generic_counter Reserved field Counter Container_269 RESERVED_414 generic_counter Reserved field Counter Container_270 RESERVED_415 generic_counter Reserved field Counter Container_271 RESERVED_416 generic_counter Reserved field Counter Container_272 RESERVED_417 generic_counter Reserved field Counter Container_273 RESERVED_418 generic_counter Reserved field Counter Container_274 RESERVED_419 generic_counter Reserved field Counter Container_275 RESERVED_420 generic_counter Reserved field Counter Container_276 RESERVED_421 generic_counter Reserved field Counter Container_277 RESERVED_422 generic_counter Reserved field Counter Container_278 RESERVED_423 generic_counter Reserved field Counter Container_279 RESERVED_424 generic_counter Reserved field Counter Container_280 RESERVED_425 generic_counter Reserved field Counter Container_281 RESERVED_426 generic_counter Reserved field Counter Container_282 RESERVED_427 generic_counter Reserved field Counter Container_283 RESERVED_428 generic_counter Reserved field Counter Container_284 RESERVED_429 generic_counter Reserved field Counter Container_285 RESERVED_430 generic_counter Reserved field Counter Container_286 RESERVED_431 generic_counter Reserved field Counter Container_287 RESERVED_432 generic_counter Reserved field Counter Container_288 RESERVED_433 generic_counter Reserved field Counter Container_289 RESERVED_434 generic_counter Reserved field Counter Container_290 RESERVED_435 generic_counter Reserved field Counter Container_291 RESERVED_436 generic_counter Reserved field Counter Container_292 RESERVED_437 generic_counter Reserved field Counter Container_293 RESERVED_438 generic_counter Reserved field Counter Container_294 RESERVED_439 generic_counter Reserved field Counter Container_295 RESERVED_440 generic_counter Reserved field Counter Container_296 RESERVED_441 generic_counter Reserved field Counter Container_297 RESERVED_442 generic_counter Reserved field Counter Container_298 RESERVED_443 generic_counter Reserved field Counter Container_299 RESERVED_444 generic_counter Reserved field Counter Container_300 RESERVED_445 generic_counter Reserved field Counter Container_301 RESERVED_446 generic_counter Reserved field Counter Container_302 RESERVED_447 generic_counter Reserved field Counter Container_303 RESERVED_448 generic_counter Reserved field Counter Container_304 RESERVED_449 generic_counter Reserved field Counter Container_305 RESERVED_450 generic_counter Reserved field Counter Container_306 RESERVED_451 generic_counter Reserved field Counter Container_307 RESERVED_452 generic_counter Reserved field Counter Container_308 RESERVED_453 generic_counter Reserved field Counter Container_309 RESERVED_454 generic_counter Reserved field Counter Container_310 RESERVED_455 generic_counter Reserved field Counter Container_311 RESERVED_456 generic_counter Reserved field Counter Container_312 RESERVED_457 generic_counter Reserved field Counter Container_313 RESERVED_458 generic_counter Reserved field Counter Container_314 RESERVED_459 generic_counter Reserved field Counter Container_315 RESERVED_460 generic_counter Reserved field Counter Container_316 RESERVED_461 generic_counter Reserved field Counter Container_317 RESERVED_462 generic_counter Reserved field Counter Container_318 RESERVED_463 generic_counter Reserved field Counter Container_319 RESERVED_464 generic_counter Reserved field Counter Container_320 RESERVED_465 generic_counter Reserved field Counter Container_321 RESERVED_466 generic_counter Reserved field Counter Container_322 RESERVED_467 generic_counter Reserved field Counter Container_323 RESERVED_468 generic_counter Reserved field Counter Container_324 RESERVED_469 generic_counter Reserved field Counter Container_325 RESERVED_470 generic_counter Reserved field Counter Container_326 RESERVED_471 generic_counter Reserved field Counter Container_327 RESERVED_472 generic_counter Reserved field Counter Container_328 RESERVED_473 generic_counter Reserved field Counter Container_329 RESERVED_474 generic_counter Reserved field Counter Container_330 RESERVED_475 generic_counter Reserved field Counter Container_331 RESERVED_476 generic_counter Reserved field Counter Container_332 RESERVED_477 generic_counter Reserved field Counter Container_333 RESERVED_478 generic_counter Reserved field Counter Container_334 RESERVED_479 generic_counter Reserved field Counter Container_335 RESERVED_480 generic_counter Reserved field Counter Container_336 RESERVED_481 generic_counter Reserved field Counter Container_337 RESERVED_482 generic_counter Reserved field Counter Container_338 RESERVED_483 generic_counter Reserved field Counter Container_339 RESERVED_484 generic_counter Reserved field Counter Container_340 RESERVED_485 generic_counter Reserved field Counter Container_341 RESERVED_486 generic_counter Reserved field Counter Container_342 RESERVED_487 generic_counter Reserved field Counter Container_343 RESERVED_488 generic_counter Reserved field Counter Container_344 RESERVED_489 generic_counter Reserved field Counter Container_345 RESERVED_490 generic_counter Reserved field Counter Container_346 RESERVED_491 generic_counter Reserved field Counter Container_347 RESERVED_492 generic_counter Reserved field Counter Container_348 RESERVED_493 generic_counter Reserved field Counter Container_349 RESERVED_494 generic_counter Reserved field Counter Container_350 RESERVED_495 generic_counter Reserved field Counter Container_351 RESERVED_496 generic_counter Reserved field Counter Container_352 RESERVED_497 generic_counter Reserved field Counter Container_353 RESERVED_498 generic_counter Reserved field Counter Container_354 RESERVED_499 generic_counter Reserved field Counter Container_355 RESERVED_500 generic_counter Reserved field Counter Container_356 RESERVED_501 generic_counter Reserved field Counter Container_357 RESERVED_502 generic_counter Reserved field Counter Container_358 RESERVED_503 generic_counter Reserved field Counter Container_359 RESERVED_504 generic_counter Reserved field Counter Container_360 RESERVED_505 generic_counter Reserved field Counter Container_361 RESERVED_506 generic_counter Reserved field Counter Container_362 RESERVED_507 generic_counter Reserved field Counter Container_363 RESERVED_508 generic_counter Reserved field Counter Container_364 RESERVED_509 generic_counter Reserved field Counter Container_365 RESERVED_510 generic_counter Reserved field Counter Container_366 RESERVED_511 generic_counter GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC0. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_367 ACT_MON_AM_WR_CMD_am_wr_cmd Container_461 MSU_BITMASK msu0_counter GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_367 ACT_MON_AM_WR_AP_CMD_am_wr_ap_cmd Container_461 MSU_BITMASK msu0_counter GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC0. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge).Use MSU_BITMASK with MSU# to intrepret this register Counter Container_368 ACT_MON_AM_RD_CMD_am_rd_cmd Container_461 MSU_BITMASK msu0_counter GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_368 ACT_MON_AM_RD_AP_CMD_am_rd_ap_cmd Container_461 MSU_BITMASK msu0_counter The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit error. Use MSU_BITMASK with MSU# to intrepret this registercorrection counts. Counter Container_369 ECC_CONFIG_CFG_ECC_1BIT_INT_THRESH_cfg_ecc_1bit_int_thresh Container_461 MSU_BITMASK msu0_counter Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_369 ECC_STAT_ERR_STAT_ECC_SCRUB_ERROR_1BIT_CNT_stat_ecc_scrub_error_1bit_cnt Container_461 MSU_BITMASK msu0_counter GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC1. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_370 ACT_MON_AM_WR_CMD_am_wr_cmd_1 Container_461 MSU_BITMASK msu0_counter GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_370 ACT_MON_AM_WR_AP_CMD_am_wr_ap_cmd_1 Container_461 MSU_BITMASK msu0_counter GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC1. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_371 ACT_MON_AM_RD_CMD_am_rd_cmd_1 Container_461 MSU_BITMASK msu0_counter GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_371 ACT_MON_AM_RD_AP_CMD_am_rd_ap_cmd_1 Container_461 MSU_BITMASK msu0_counter The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit errorcorrection counts. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_372 ECC_CONFIG_CFG_ECC_1BIT_INT_THRESH_cfg_ecc_1bit_int_thresh_1 Container_461 MSU_BITMASK msu0_counter Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached Counter Container_372 ECC_STAT_ERR_STAT_ECC_SCRUB_ERROR_1BIT_CNT_stat_ecc_scrub_error_1bit_cnt_1 Container_461 MSU_BITMASK msu0_counter GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC0. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_373 ACT_MON_AM_WR_CMD_am_wr_cmd_2 Container_461 MSU_BITMASK msu1_counter GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_373 ACT_MON_AM_WR_AP_CMD_am_wr_ap_cmd_2 Container_461 MSU_BITMASK msu1_counter GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC0. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge).Use MSU_BITMASK with MSU# to intrepret this register Counter Container_374 ACT_MON_AM_RD_CMD_am_rd_cmd_2 Container_461 MSU_BITMASK msu1_counter GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_374 ACT_MON_AM_RD_AP_CMD_am_rd_ap_cmd_2 Container_461 MSU_BITMASK msu1_counter The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit error. Use MSU_BITMASK with MSU# to intrepret this registercorrection counts. Counter Container_375 ECC_CONFIG_CFG_ECC_1BIT_INT_THRESH_cfg_ecc_1bit_int_thresh_2 Container_461 MSU_BITMASK msu1_counter Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_375 ECC_STAT_ERR_STAT_ECC_SCRUB_ERROR_1BIT_CNT_stat_ecc_scrub_error_1bit_cnt_2 Container_461 MSU_BITMASK msu1_counter GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC1. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_376 ACT_MON_AM_WR_CMD_am_wr_cmd_3 Container_461 MSU_BITMASK msu1_counter GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_376 ACT_MON_AM_WR_AP_CMD_am_wr_ap_cmd_3 Container_461 MSU_BITMASK msu1_counter GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC1. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_377 ACT_MON_AM_RD_CMD_am_rd_cmd_3 Container_461 MSU_BITMASK msu1_counter GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_377 ACT_MON_AM_RD_AP_CMD_am_rd_ap_cmd_3 Container_461 MSU_BITMASK msu1_counter The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit errorcorrection counts. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_378 ECC_CONFIG_CFG_ECC_1BIT_INT_THRESH_cfg_ecc_1bit_int_thresh_3 Container_461 MSU_BITMASK msu1_counter Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached Counter Container_378 ECC_STAT_ERR_STAT_ECC_SCRUB_ERROR_1BIT_CNT_stat_ecc_scrub_error_1bit_cnt_3 Container_461 MSU_BITMASK msu1_counter GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC0. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_379 ACT_MON_AM_WR_CMD_am_wr_cmd_4 Container_461 MSU_BITMASK msu2_counter GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_379 ACT_MON_AM_WR_AP_CMD_am_wr_ap_cmd_4 Container_461 MSU_BITMASK msu2_counter GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC0. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge).Use MSU_BITMASK with MSU# to intrepret this register Counter Container_380 ACT_MON_AM_RD_CMD_am_rd_cmd_4 Container_461 MSU_BITMASK msu2_counter GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_380 ACT_MON_AM_RD_AP_CMD_am_rd_ap_cmd_4 Container_461 MSU_BITMASK msu2_counter The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit error. Use MSU_BITMASK with MSU# to intrepret this registercorrection counts. Counter Container_381 ECC_CONFIG_CFG_ECC_1BIT_INT_THRESH_cfg_ecc_1bit_int_thresh_4 Container_461 MSU_BITMASK msu2_counter Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_381 ECC_STAT_ERR_STAT_ECC_SCRUB_ERROR_1BIT_CNT_stat_ecc_scrub_error_1bit_cnt_4 Container_461 MSU_BITMASK msu2_counter GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC1. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_382 ACT_MON_AM_WR_CMD_am_wr_cmd_5 Container_461 MSU_BITMASK msu2_counter GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_382 ACT_MON_AM_WR_AP_CMD_am_wr_ap_cmd_5 Container_461 MSU_BITMASK msu2_counter GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC1. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_383 ACT_MON_AM_RD_CMD_am_rd_cmd_5 Container_461 MSU_BITMASK msu2_counter GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_383 ACT_MON_AM_RD_AP_CMD_am_rd_ap_cmd_5 Container_461 MSU_BITMASK msu2_counter The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit errorcorrection counts. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_384 ECC_CONFIG_CFG_ECC_1BIT_INT_THRESH_cfg_ecc_1bit_int_thresh_5 Container_461 MSU_BITMASK msu2_counter Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached Counter Container_384 ECC_STAT_ERR_STAT_ECC_SCRUB_ERROR_1BIT_CNT_stat_ecc_scrub_error_1bit_cnt_5 Container_461 MSU_BITMASK msu2_counter GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC0. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_385 ACT_MON_AM_WR_CMD_am_wr_cmd_6 Container_461 MSU_BITMASK msu3_counter GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_385 ACT_MON_AM_WR_AP_CMD_am_wr_ap_cmd_6 Container_461 MSU_BITMASK msu3_counter GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC0. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge).Use MSU_BITMASK with MSU# to intrepret this register Counter Container_386 ACT_MON_AM_RD_CMD_am_rd_cmd_6 Container_461 MSU_BITMASK msu3_counter GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_386 ACT_MON_AM_RD_AP_CMD_am_rd_ap_cmd_6 Container_461 MSU_BITMASK msu3_counter The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit error. Use MSU_BITMASK with MSU# to intrepret this registercorrection counts. Counter Container_387 ECC_CONFIG_CFG_ECC_1BIT_INT_THRESH_cfg_ecc_1bit_int_thresh_6 Container_461 MSU_BITMASK msu3_counter Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_387 ECC_STAT_ERR_STAT_ECC_SCRUB_ERROR_1BIT_CNT_stat_ecc_scrub_error_1bit_cnt_6 Container_461 MSU_BITMASK msu3_counter GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC1. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_388 ACT_MON_AM_WR_CMD_am_wr_cmd_7 Container_461 MSU_BITMASK msu3_counter GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_388 ACT_MON_AM_WR_AP_CMD_am_wr_ap_cmd_7 Container_461 MSU_BITMASK msu3_counter GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC1. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_389 ACT_MON_AM_RD_CMD_am_rd_cmd_7 Container_461 MSU_BITMASK msu3_counter GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_389 ACT_MON_AM_RD_AP_CMD_am_rd_ap_cmd_7 Container_461 MSU_BITMASK msu3_counter The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit errorcorrection counts. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_390 ECC_CONFIG_CFG_ECC_1BIT_INT_THRESH_cfg_ecc_1bit_int_thresh_7 Container_461 MSU_BITMASK msu3_counter Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached Counter Container_390 ECC_STAT_ERR_STAT_ECC_SCRUB_ERROR_1BIT_CNT_stat_ecc_scrub_error_1bit_cnt_7 Container_461 MSU_BITMASK msu3_counter GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC0. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_391 ACT_MON_AM_WR_CMD_am_wr_cmd_8 Container_461 MSU_BITMASK msu4_counter GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_391 ACT_MON_AM_WR_AP_CMD_am_wr_ap_cmd_8 Container_461 MSU_BITMASK msu4_counter GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC0. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge).Use MSU_BITMASK with MSU# to intrepret this register Counter Container_392 ACT_MON_AM_RD_CMD_am_rd_cmd_8 Container_461 MSU_BITMASK msu4_counter GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_392 ACT_MON_AM_RD_AP_CMD_am_rd_ap_cmd_8 Container_461 MSU_BITMASK msu4_counter The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit error. Use MSU_BITMASK with MSU# to intrepret this registercorrection counts. Counter Container_393 ECC_CONFIG_CFG_ECC_1BIT_INT_THRESH_cfg_ecc_1bit_int_thresh_8 Container_461 MSU_BITMASK msu4_counter Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_393 ECC_STAT_ERR_STAT_ECC_SCRUB_ERROR_1BIT_CNT_stat_ecc_scrub_error_1bit_cnt_8 Container_461 MSU_BITMASK msu4_counter GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC1. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_394 ACT_MON_AM_WR_CMD_am_wr_cmd_9 Container_461 MSU_BITMASK msu4_counter GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_394 ACT_MON_AM_WR_AP_CMD_am_wr_ap_cmd_9 Container_461 MSU_BITMASK msu4_counter GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC1. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_395 ACT_MON_AM_RD_CMD_am_rd_cmd_9 Container_461 MSU_BITMASK msu4_counter GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_395 ACT_MON_AM_RD_AP_CMD_am_rd_ap_cmd_9 Container_461 MSU_BITMASK msu4_counter The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit errorcorrection counts. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_396 ECC_CONFIG_CFG_ECC_1BIT_INT_THRESH_cfg_ecc_1bit_int_thresh_9 Container_461 MSU_BITMASK msu4_counter Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached Counter Container_396 ECC_STAT_ERR_STAT_ECC_SCRUB_ERROR_1BIT_CNT_stat_ecc_scrub_error_1bit_cnt_9 Container_461 MSU_BITMASK msu4_counter GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC0. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_397 ACT_MON_AM_WR_CMD_am_wr_cmd_10 Container_461 MSU_BITMASK msu5_counter GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_397 ACT_MON_AM_WR_AP_CMD_am_wr_ap_cmd_10 Container_461 MSU_BITMASK msu5_counter GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC0. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge).Use MSU_BITMASK with MSU# to intrepret this register Counter Container_398 ACT_MON_AM_RD_CMD_am_rd_cmd_10 Container_461 MSU_BITMASK msu5_counter GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC0. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_398 ACT_MON_AM_RD_AP_CMD_am_rd_ap_cmd_10 Container_461 MSU_BITMASK msu5_counter The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit error. Use MSU_BITMASK with MSU# to intrepret this registercorrection counts. Counter Container_399 ECC_CONFIG_CFG_ECC_1BIT_INT_THRESH_cfg_ecc_1bit_int_thresh_10 Container_461 MSU_BITMASK msu5_counter Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_399 ECC_STAT_ERR_STAT_ECC_SCRUB_ERROR_1BIT_CNT_stat_ecc_scrub_error_1bit_cnt_10 Container_461 MSU_BITMASK msu5_counter GDDR Memory Controller Write Command Count without auto-precharge addressed to MSU0 MC1. For getting total write command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_400 ACT_MON_AM_WR_CMD_am_wr_cmd_11 Container_461 MSU_BITMASK msu5_counter GDDR Memory Controller Write Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_400 ACT_MON_AM_WR_AP_CMD_am_wr_ap_cmd_11 Container_461 MSU_BITMASK msu5_counter GDDR Memory Controller Read Command Count without auto-precharge addressed to MSU0 MC1. For getting total read command count, add both the count values (without auto-precharge and with auto-precharge). Use MSU_BITMASK with MSU# to intrepret this register Counter Container_401 ACT_MON_AM_RD_CMD_am_rd_cmd_11 Container_461 MSU_BITMASK msu5_counter GDDR Memory Controller Read Command Count with auto-precharge addressed to MSU0 MC1. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_401 ACT_MON_AM_RD_AP_CMD_am_rd_ap_cmd_11 Container_461 MSU_BITMASK msu5_counter The number of ECC 1-bit error corrections that must be exceeded before the 'stat_int_ecc_1bit_thresh' status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit errorcorrection counts. Use MSU_BITMASK with MSU# to intrepret this register Counter Container_402 ECC_CONFIG_CFG_ECC_1BIT_INT_THRESH_cfg_ecc_1bit_int_thresh_11 Container_461 MSU_BITMASK msu5_counter Count of 1-bit read ECC errors detected by the ECC scrub reads since the last time the counter was reset by assertion of 'init_ecc_scrub_error_clr'. Holds when maximum value (255) is reached Counter Container_402 ECC_STAT_ERR_STAT_ECC_SCRUB_ERROR_1BIT_CNT_stat_ecc_scrub_error_1bit_cnt_11 Container_461 MSU_BITMASK msu5_counter Reserved field Counter Container_403 RESERVED_584 generic_counter Reserved field Counter Container_403 RESERVED_585 generic_counter Reserved field Counter Container_404 RESERVED_586 generic_counter Reserved field Counter Container_404 RESERVED_587 generic_counter Reserved field Counter Container_405 RESERVED_588 generic_counter Reserved field Counter Container_405 RESERVED_589 generic_counter Reserved field Counter Container_406 RESERVED_590 generic_counter Reserved field Counter Container_406 RESERVED_591 generic_counter Reserved field Counter Container_407 RESERVED_592 generic_counter Reserved field Counter Container_407 RESERVED_593 generic_counter Reserved field Counter Container_408 RESERVED_594 generic_counter Reserved field Counter Container_408 RESERVED_595 generic_counter Reserved field Counter Container_409 RESERVED_596 generic_counter Reserved field Counter Container_409 RESERVED_597 generic_counter Reserved field Counter Container_410 RESERVED_598 generic_counter Reserved field Counter Container_410 RESERVED_599 generic_counter Reserved field Counter Container_411 RESERVED_600 generic_counter Reserved field Counter Container_411 RESERVED_601 generic_counter Reserved field Counter Container_412 RESERVED_602 generic_counter Reserved field Counter Container_412 RESERVED_603 generic_counter Reserved field Counter Container_413 RESERVED_604 generic_counter Reserved field Counter Container_413 RESERVED_605 generic_counter Reserved field Counter Container_414 RESERVED_606 generic_counter Reserved field Counter Container_414 RESERVED_607 generic_counter GT Error was detected Snapshot Container_415 GT_ERR generic_sample Command Parity Error detected in the MERT->SG IOSF interface Snapshot Container_415 SGGI_CP_ERR generic_sample The field 'Reserved' in register 'Device Error Source Fatal' does not have a description in the BXML Snapshot Container_415 Reserved_6 generic_sample Display Error was detected Snapshot Container_415 DISP_ERR generic_sample Command Parity Error detected in the DE->SG IOSF interface Snapshot Container_415 SGDI_CP_ERR generic_sample The field 'Reserved' in register 'Device Error Source Fatal' does not have a description in the BXML Snapshot Container_415 Reserved_5 generic_sample GSC Error was detected Snapshot Container_415 GSC_ERR generic_sample Command Parity Error detected in gSC -> SG IOSF interface Snapshot Container_415 SGLI_CP_ERR generic_sample The field 'Reserved' in register 'Device Error Source Fatal' does not have a description in the BXML Snapshot Container_415 Reserved_4 generic_sample SG unit Error was detected Snapshot Container_415 SGUNIT_ERR generic_sample Command Parity Error detected in C-die -> SG interface Snapshot Container_415 SGCI_CP_ERR generic_sample The field 'Reserved' in register 'Device Error Source Fatal' does not have a description in the BXML Snapshot Container_415 Reserved_3 generic_sample SoC Error was detected Snapshot Container_415 SOC_ERR generic_sample CSC saw a fatal error Snapshot Container_415 CSC_FATAL_ERROR generic_sample The field 'Reserved' in register 'Device Error Source Fatal' does not have a description in the BXML Snapshot Container_415 Reserved_2 generic_sample MERT writes to this bit using the message offset on detecting command or data parity error in the SG->MERT interface, or completion parity errors on completions from MERT-> SG. Snapshot Container_415 MERT_CP_ERR generic_sample The field 'Reserved' in register 'Device Error Source Fatal' does not have a description in the BXML Snapshot Container_415 Reserved_1 generic_sample Command Parity Error detected in SGMI IOSF interface Snapshot Container_415 SGMI_CP_ERR generic_sample The field 'Reserved' in register 'Device Error Source Fatal' does not have a description in the BXML Snapshot Container_415 Reserved_0 generic_sample 1: Error occurred Snapshot Container_415 T0_CORR_ERR_ROUTING generic_sample 1: Error occurred Snapshot Container_415 T0_NONFATAL_ERR_ROUTING generic_sample 1: Error occurred Snapshot Container_415 T0_FATAL_ERR_ROUTING generic_sample The field 'Reserved' in register 'Device PCIe Error Status' does not have a description in the BXML Snapshot Container_415 Reserved_3_1 generic_sample 1: Error occurred Snapshot Container_415 T1_CORR_ERR_ROUTING generic_sample 1: Error occurred Snapshot Container_415 T1_NONFATAL_ERR_ROUTING generic_sample 1: Error occurred Snapshot Container_415 T1_FATAL_ERR_ROUTING generic_sample The field 'Reserved' in register 'Device PCIe Error Status' does not have a description in the BXML Snapshot Container_415 Reserved_2_1 generic_sample 1: Error occurred Snapshot Container_415 T2_CORR_ERR_ROUTING generic_sample 1: Error occurred Snapshot Container_415 T2_NONFATAL_ERR_ROUTING generic_sample 1: Error occurred Snapshot Container_415 T2_FATAL_ERR_ROUTING generic_sample The field 'Reserved' in register 'Device PCIe Error Status' does not have a description in the BXML Snapshot Container_415 Reserved_1_1 generic_sample 1: Error occurred Snapshot Container_415 T3_CORR_ERR_ROUTING generic_sample 1: Error occurred Snapshot Container_415 T3_NONFATAL_ERR_ROUTING generic_sample 1: Error occurred Snapshot Container_415 T3_FATAL_ERR_ROUTING generic_sample The field 'Reserved' in register 'Device PCIe Error Status' does not have a description in the BXML Snapshot Container_415 Reserved_0_1 generic_sample The field 'Reserved' in register 'GT Fatal Err Status Register' does not have a description in the BXML Snapshot Container_416 Reserved_3_2 generic_sample Array BIST Error Snapshot Container_416 ARRAY_BIST_ERROR generic_sample The field 'Reserved HW Error1' in register 'GT Fatal Err Status Register' does not have a description in the BXML Snapshot Container_416 Reserved_HW_Error1 generic_sample The field 'FPU Uncorrectable Error' in register 'GT Fatal Err Status Register' does not have a description in the BXML Snapshot Container_416 FPU_UNCORR_ERR generic_sample L3 double error Snapshot Container_416 L3_DOUBLE_ERROR generic_sample L3 ECC Checker Error Snapshot Container_416 L3_ECC_CHECKER_ERR generic_sample Uncorrectable GUC SRAM error Snapshot Container_416 GUC_UNCORR_ERR generic_sample The field 'Reserved' in register 'GT Fatal Err Status Register' does not have a description in the BXML Snapshot Container_416 Reserved_2_2 generic_sample IDI Parity Error Snapshot Container_416 IDI_PARITY_ERR generic_sample Poison detected in SQIDI Snapshot Container_416 SQIDI_UNCORR_ERR generic_sample The field 'Reserved' in register 'GT Fatal Err Status Register' does not have a description in the BXML Snapshot Container_416 Reserved_1_2 generic_sample On ATS, sampler does not generate this event - so this bit is reserved for future Sampler error use.Uncorrectable Sampler error detected Snapshot Container_416 SAMPLER_UNCORR_ERR generic_sample Uncorrectable SLM error detected Snapshot Container_416 SLM_UNCORR_ERR generic_sample Uncorrectable EU Instruction Cache error detected Snapshot Container_416 EU_IC_UNCORR_ERR generic_sample Uncorrectable GRF error detected Snapshot Container_416 EU_GRF_UNCORR_ERR generic_sample The field 'Reserved' in register 'GT Fatal Err Status Register' does not have a description in the BXML Snapshot Container_416 Reserved_0_2 generic_sample Set to 1 when Poisoned data has been received from IOSF-Primary. This sticky bit must survive secondary bus reset/FLR. Snapshot Container_416 ERROR_STATUS generic_sample Logs status of the Viral Poison Condition: 0 : HW is not virally poisoning data sent to the Host system 1 : HW is virally poisoning data sent to the Host system Cleared by FLR. Snapshot Container_416 VIRAL_POISON_CONDITION generic_sample The field 'Reserved' in register 'POISON_DATA_STATUS' does not have a description in the BXML Snapshot Container_416 Reserved_0_3 generic_sample 0=No Primary SPI access error. 1=Primary SPI access error occurred. Snapshot Container_417 PRIMARY_SPI_ERROR generic_sample OPTIONROMBAR SPI access error opcode (00=Write, 01=Read, 10=Erase, 11=Reserved). Snapshot Container_417 PRIMARY_SPI_ERROR_OPCODE generic_sample Spare. Snapshot Container_417 SPARE1 generic_sample 0=No OptionROMBAR SPI access error. 1=OptionROMBAR SPI access error occurred. Snapshot Container_417 OPTIONROMBAR_SPI_ERROR generic_sample OPTIONROMBAR SPI access error opcode (00=Write, 01=Read, 10=Erase, 11=Reserved). Snapshot Container_417 OPTIONROMBAR_SPI_ERROR_OPCODE generic_sample Spare. Snapshot Container_417 SPARE2 generic_sample 0=No gSC SPI access error. 1=gSC SPI access error occurred. Snapshot Container_417 GSC_SPI_ERROR generic_sample gSC SPI access error opcode (00=Write, 01=Read, 10=Erase, 11=Reserved). Snapshot Container_417 GSC_SPI_ERROR_OPCODE generic_sample Spare. Snapshot Container_417 SPARE3 generic_sample Spare. Snapshot Container_417 SPARE generic_sample This register counts the same event as counter SPM0 however is not affected by context ID or other conditions that prevent SPM0 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted using this register. This 32-bit field returns bits 63:32 of the live performance counter value when read. Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO, so the value returned from this register may be different on back-to-back reads. Counter Container_417 OAG_OAPERF_SPM0_UPPER_FREE generic_counter This register counts the same event as counter SPM0 however is not affected by context ID or other conditions that prevent SPM0 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted used this register. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. Counter Container_418 OAG_OAPERF_SPM0_LOWER_FREE generic_counter This register counts the same event as counter SPM1 however is not affected by context ID or other conditions that prevent SPM1 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.;Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted using this register. This 32-bit field returns bits 63:32 of the live performance counter value when read. Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO, so the value returned from this register may be different on back-to-back reads. Counter Container_418 OAG_OAPERF_SPM1_UPPER_FREE generic_counter This register counts the same event as counter SPM1 however is not affected by context ID or other conditions that prevent SPM1 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted used this register. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. Counter Container_419 OAG_OAPERF_SPM1_LOWER_FREE generic_counter This register counts the same event as counter SPM2 however is not affected by context ID or other conditions that prevent SPM2 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.;Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted using this register. This 32-bit field returns bits 63:32 of the live performance counter value when read. Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO, so the value returned from this register may be different on back-to-back reads. Counter Container_419 OAG_OAPERF_SPM2_UPPER_FREE generic_counter This register counts the same event as counter SPM2 however is not affected by context ID or other conditions that prevent SPM2 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted used this register. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. Counter Container_420 OAG_OAPERF_SPM2_LOWER_FREE generic_counter This register counts the same event as counter SPM3 however is not affected by context ID or other conditions that prevent SPM3 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.;Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted using this register. This 32-bit field returns bits 63:32 of the live performance counter value when read. Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO, so the value returned from this register may be different on back-to-back reads. Counter Container_420 OAG_OAPERF_SPM3_UPPER_FREE generic_counter This register counts the same event as counter SPM3 however is not affected by context ID or other conditions that prevent SPM3 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted used this register. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. Counter Container_421 OAG_OAPERF_SPM3_LOWER_FREE generic_counter This register counts the same event as counter SPM4 however is not affected by context ID or other conditions that prevent SPM4 from incrementing. This counter is free running, always enabled and counting irrespective of OA enabled or disabled.Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted used this register. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. Counter Container_421 OAG_OAPERF_SPM4_LOWER_FREE generic_counter Please refer to the detailed description of the aggregating performance counters in the Aggregating Counters section for more details on what event is counted used this register.This counter is free running, always enabled and countsirrespective of OA enable configuration. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. Counter Container_422 OAG_OAPERF_SPM5_LOWER_FREE generic_counter This register counts the time that any render engine is busy. This counter is free running, always enabled and counting irrespective of OA enabled or disabled. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. Counter Container_422 OAG_RENDER_BUSY_FREE generic_counter This register counts the time that any media fixed function is busy. This counter is free running, always enabled and counts irrespective of OA being enabled or disabled. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. Counter Container_423 OAG_ANY_MEDIA_FF_BUSY_FREE generic_counter This register counts the time thatBLT engine is busy. This counter is free running, always enabled and counting irrespective of OA enabled or disabled. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. Counter Container_423 OAG_BLT_BUSY_FREE generic_counter This register counts the time that any engine is truly busy (not simply powered up). This counter is free running, always enabled and counting irrespective of OA enabled or disabled. This 32-bit field returns bits 31:0 of the live performance counter value when read.Note that there is no 'latch and hold' mechanism for performance counters when they are accessed through MMIO,so the value returned from this register may be different on back-to-back reads. Unit in GPMusec. Refer to Timestamp Bases for details. Counter Container_424 OAG_RC0_ANY_ENGINE_BUSY_FREE generic_counter Reserved register Reserved field Counter Container_424 RESERVED_CONTAINER_ALIGN_2 generic_counter Reserved field Snapshot Container_425 RESERVED_REG_FIELD_1 generic_sample Reserved field Snapshot Container_426 RESERVED_REG_FIELD_2 generic_sample Reserved field Snapshot Container_427 RESERVED_REG_FIELD_3 generic_sample Reserved field Snapshot Container_428 RESERVED_REG_FIELD_4 generic_sample Reserved field Snapshot Container_429 RESERVED_REG_FIELD_5 generic_sample Reserved field Snapshot Container_430 RESERVED_REG_FIELD_6 generic_sample Reserved field Snapshot Container_431 RESERVED_REG_FIELD_7 generic_sample Reserved field Snapshot Container_432 RESERVED_REG_FIELD_8 generic_sample Reserved field Snapshot Container_433 RESERVED_REG_FIELD_9 generic_sample Reserved field Snapshot Container_434 RESERVED_REG_FIELD_10 generic_sample Reserved field Snapshot Container_435 RESERVED_REG_FIELD_11 generic_sample Reserved field Snapshot Container_436 RESERVED_REG_FIELD_12 generic_sample Reserved field Snapshot Container_437 RESERVED_REG_FIELD_13 generic_sample Reserved field Snapshot Container_438 RESERVED_REG_FIELD_14 generic_sample Reserved field Snapshot Container_439 RESERVED_REG_FIELD_15 generic_sample Reserved field Snapshot Container_440 RESERVED_REG_FIELD_16 generic_sample Reserved field Snapshot Container_441 RESERVED_REG_FIELD_17 generic_sample Reserved field Snapshot Container_442 RESERVED_REG_FIELD_18 generic_sample Reserved field Snapshot Container_443 RESERVED_REG_FIELD_19 generic_sample Reserved field Snapshot Container_444 RESERVED_REG_FIELD_20 generic_sample Reserved field Snapshot Container_445 RESERVED_REG_FIELD_21 generic_sample Reserved field Snapshot Container_446 RESERVED_REG_FIELD_22 generic_sample Reserved field Snapshot Container_447 RESERVED_REG_FIELD_23 generic_sample Reserved field Snapshot Container_448 RESERVED_710 generic_sample Reserved field Snapshot Container_448 RESERVED_711 generic_sample Reserved field Snapshot Container_449 RESERVED_712 generic_sample IFWI VERSION OEM Snapshot Container_449 IFWIVERSION_OEM_UPPER generic_sample IFWI VERSION OEM Snapshot Container_450 IFWIVERSION_OEM_LOWER generic_sample IFWI VERSION FW CODE Snapshot Container_450 IFWIVERSION_FWCODE_UPPER generic_sample IFWI VERSION FW CODE Snapshot Container_451 IFWIVERSION_FWCODE_LOWER generic_sample IFWI VERSION FW DATA Snapshot Container_451 IFWVERSION_FWDATA generic_sample Reserved field Snapshot Container_452 RESERVED_718 generic_sample Reserved field Snapshot Container_452 RESERVED_719 generic_sample SSVID SSDID Snapshot Container_453 SSVID_SSDID generic_sample Reserved field Snapshot Container_453 RESERVED_721 generic_sample Reserved field Snapshot Container_454 RESERVED_722 generic_sample ECC STATE Snapshot Container_454 ECC_STATE generic_sample AUDIO STATE Snapshot Container_455 AUDIO_STATE generic_sample DISPLAY STATE Snapshot Container_455 DISPLAY_STATE generic_sample SLICE COUNT Snapshot Container_456 SLICE_COUNT_1 generic_sample SLICE COUNT Snapshot Container_456 SLICE_COUNT_2 generic_sample SLICE COUNT Snapshot Container_457 SLICE_COUNT_3 generic_sample NUM OF MEM CHANNEL Snapshot Container_457 NUM_OF_MEM_CHANNEL generic_sample SRIOV STATE Snapshot Container_458 SRIOV_STATE generic_sample MAX NUM VF Snapshot Container_458 MAX_NUM_VF generic_sample NUM VD BOX ENABLED Snapshot Container_459 NUM_VD_BOX_ENABLED generic_sample LMEM SIZE AVAILABLE Snapshot Container_459 LMEM_SIZE_AVAILABLE generic_sample PAGE RETIREMENT ENABLED Snapshot Container_460 PAGE_RETIREMENT_ENABLED generic_sample NUM OF RETIRED PAGES Snapshot Container_460 NUM_OF_RETIRED_PAGES generic_sample MSU BITMASK Snapshot Container_461 MSU_BITMASK generic_sample DISPLAY PIPE MASK Snapshot Container_461 DISPLAY_PIPE_MASK generic_sample PCIE error counter enabled Snapshot Container_462 PCIE_COUNTER_ENABLED generic_sample Reserved field Snapshot Container_462 RESERVED_REG_FIELD_24 generic_sample