float parameter_0 $parameter_0 / 38.4e6 float parameter_0 $parameter_0 * 0.005 float parameter_0 $parameter_0 * 64 / 1e6 float parameter_0 $parameter_0 / 1e6 float parameter_0 $parameter_0 * 32 / 1e6 float parameter_0 $parameter_0 float parameter_0 $parameter_0 float parameter_0 $parameter_0 / 1048576 float parameter_0 ( 49 + $parameter_0 ) * 0.005 float parameter_0 $parameter_0 float parameter_0 $parameter_0 float parameter_0 $parameter_0 float parameter_0 $parameter_0 float parameter_0 $parameter_0 * 0.1 float parameter_0 $parameter_0 * 0.01667 float parameter_0 $parameter_0 * 0.025 float parameter_0 $parameter_0 * 0.033 float parameter_0 $parameter_0 float parameter_0 $parameter_0 float parameter_0 $parameter_0 * 100 / 16 float parameter_0 $parameter_0 float parameter_0 $parameter_0 * 0.002 float parameter_0 $parameter_0 float parameter_0 $parameter_0 float parameter_0 $parameter_0 / 16384 float parameter_0 $parameter_0 * 64 float parameter_0 $parameter_0 float parameter_0 $parameter_0 * 0.025 * 33.33 float parameter_0 $parameter_0 * 0.025 / 1e6 float parameter_0 $parameter_0 float parameter_0 $parameter_0 float parameter_0 $parameter_0 * 0.025 float parameter_0 $parameter_0 / 960 float parameter_0 $parameter_0 float parameter_0 $parameter_0 * 40 float parameter_0 $parameter_0 * 0.001 float parameter_0 $parameter_0 float parameter_0 $parameter_0 * 0.005 float parameter_0 $parameter_0 * 100 integer parameter_0 $parameter_0 BMG BMG PUNIT PMT Telemetry aggregator samples definition and transformation rules 1e2f8200 Public 10 2025-01-07 LOCAL_VERSION Snapshot Container_0 LOCAL_VERSION generic_sample reserved Snapshot Container_0 reserved_0 generic_sample PRODUCT_ID Snapshot Container_0 PRODUCT_ID generic_sample SOURCEID Snapshot Container_0 SOURCEID generic_sample reserved Snapshot Container_0 reserved_1 generic_sample Represents the clock rate of the XTAL on this silicon. 1: 19.2MHz - 19.2e6(Reserved) 0: 24MHz - 24e6(Reserved)3: 25MHz - 25e6 2: 38.4MHz - 38.4e6 (Reserved) Snapshot Container_0 XTAL_CLK_FREQUENCY generic_sample reserved Snapshot Container_0 reserved_2 generic_sample GT Frequency in 1MHz granularity Snapshot Container_1 GT_FREQUENCY wp_clk_freq Voltage required for GT based on VF Curve (In U1.8 format) Snapshot Container_1 GT_V_FROM_VF_CURVE V_from_VF Final VID applied at VCCGT VR (in 1.8 format) Snapshot Container_1 GT_VID vid Present GT C-state Snapshot Container_1 GT_CSTATE generic_sample reserved Snapshot Container_1 reserved_3 generic_sample Worst case GT License Grant Latency in 40ns granularity Snapshot Container_2 GT_CONFIG_CHANGE wake_latency_ns_40 reserved Snapshot Container_2 reserved_4 generic_sample reserved Snapshot Container_2 reserved_5 generic_sample Worst case GT RC6 Exit Latency in 40ns granularity Snapshot Container_2 GT_UNSLICE wake_latency_ns_40 MEDIA Frequency in 1MHz granularity Snapshot Container_3 MEDIA_FREQUENCY wp_clk_freq Voltage required for MEDIA based on VF Curve (In U1.8 format) Snapshot Container_3 MEDIA_V_FROM_VF_CURVE V_from_VF Final VID applied at VCCGT VR (in 1.8 format) Snapshot Container_3 MEDIA_VID vid Present MEDIA C-state Snapshot Container_3 MEDIA_CSTATE generic_sample reserved Snapshot Container_3 reserved_6 generic_sample reserved Snapshot Container_4 MEDIA_SAMPLER_GT generic_sample reserved Snapshot Container_4 SYSTOLIC_GT generic_sample reserved Snapshot Container_4 GSC_GT generic_sample reserved Snapshot Container_4 reserved_7 generic_sample EU_COUNT Snapshot Container_4 EU_COUNT_GT generic_sample reserved Snapshot Container_4 MEDIA_ENGINE_COUNT_GT generic_sample reserved Snapshot Container_4 SUBSLICE_COUNT_GT generic_sample reserved Snapshot Container_4 RENDER_SLICE_COUNT_GT generic_sample reserved Snapshot Container_4 reserved_8 generic_sample Worst case MEDIA License Grant Latency in 40ns granularity Snapshot Container_4 MEDIA_CONFIG_CHANGE wake_latency_ns_40 reserved Snapshot Container_4 reserved_9 generic_sample AFM Frequency in 1MHz granularity Snapshot Container_5 AFM_FREQUENCY wp_clk_freq Voltage required for AFM based on VF Curve (In U1.8 format) Snapshot Container_5 AFM_V_FROM_VF_CURVE V_from_VF Final VID applied at VCCGT VR (in 1.8 format) Snapshot Container_5 AFM_VID vid Present AFM C-state Snapshot Container_5 AFM_CSTATE generic_sample reserved Snapshot Container_5 reserved_10 generic_sample ADM Frequency in 1MHz granularity Snapshot Container_6 ADM_FREQUENCY adm_wp_clk_freq Voltage required for ADM based on VF Curve (In U1.8 format) Snapshot Container_6 ADM_V_FROM_VF_CURVE V_from_VF Final VID applied at VCCADMDIG VR (in 1.8 format) Snapshot Container_6 ADM_VID vid Present ADM C-state Snapshot Container_6 ADM_CSTATE generic_sample reserved Snapshot Container_6 reserved_11 generic_sample VRAM (Memory) Frequency in 1MHz granularity Snapshot Container_7 VRAM_FREQUENCY ratio_1000 Maximum memory bandwidth in units of Mbps at this memory frequency. Snapshot Container_7 VRAM_BANDWIDTH generic_sample VRAM (Memory) VID in 1.8 format (i.e. VCCDDR VR) Snapshot Container_7 VRAM_VID vid Final VID applied at VCCSA VR (in 1.8 format) Snapshot Container_7 VCCSA_VID vid reserved Snapshot Container_7 reserved_12 generic_sample reserved Snapshot Container_8 reserved_13 generic_sample Worst case MEDIA RC6 Exit Latency in 40ns granularity Snapshot Container_8 MEDIA_UNSLICE wake_latency_ns_40 reserved Snapshot Container_8 MEDIA_SAMPLER generic_sample reserved Snapshot Container_8 SYSTOLIC_MEDIA generic_sample reserved Snapshot Container_8 GSC_MEDIA_MEDIA generic_sample reserved Snapshot Container_8 reserved_14 generic_sample reserved Snapshot Container_8 EU_COUNT_MEDIA generic_sample MEDIA_ENGINE_COUNT Snapshot Container_8 MEDIA_ENGINE_COUNT_MEDIA generic_sample reserved Snapshot Container_8 SUBSLICE_COUNT_MEDIA generic_sample reserved Snapshot Container_8 RENDER_SLICE_COUNT_MEDIA generic_sample reserved Snapshot Container_8 reserved_15 generic_sample This field indicates total number of active display PLLs in this die Snapshot Container_9 ACTIVE_PHYS generic_sample reserved Snapshot Container_9 reserved_16 generic_counter This field indicates total number of active DBUFs Snapshot Container_9 ACTIVE_DBUFS generic_sample This field indicates total number of active pipes Snapshot Container_9 ACTIVE_PIPES generic_sample DE request to Mask QCLK GV point. Value of 1 in the mask restricting the associated GV point Snapshot Container_9 QCLK_GV_INDEX generic_sample DE request to set Vdcore Voltage level and perform voltage transition. Punit sends Ack after DVFS Snapshot Container_9 VOLTAGE_INDEX generic_sample reserved Snapshot Container_9 reserved_17 generic_sample Bandwidth Value in multiple of 100MB/S. DE request BW value calculated from different QCLK GV points. Display will program this to all 1s for KVMR or SAGV disable case. Punit must not perform SAGV after this Snapshot Container_9 BANDWIDTH_FOR_QCLK_GV bw_100 This field indicates total number of active display PLLs in this die Snapshot Container_9 ACTIVE_PLLS generic_sample reserved Snapshot Container_9 reserved_18 generic_sample This field indicates total number of active Scalars Snapshot Container_9 ACTIVE_SCALARS generic_sample reserved Snapshot Container_9 reserved_19 generic_sample This field indicates highest enabled DDI PLL Freq in multiple of 1 MHZ Snapshot Container_9 DDICLK_FREQ ratio_1000 reserved Snapshot Container_9 reserved_20 generic_sample This field indicates DE PLL Freq in multiple of 1 MHZ Snapshot Container_9 CDCLK_FREQ ratio_1000 reserved Snapshot Container_9 reserved_21 generic_sample RPM calculated by pcode for FAN1 in last iteration Snapshot Container_10 FAN1_RPM generic_sample RPM calculated by pcode for FAN2 in last iteration Snapshot Container_10 FAN2_RPM generic_sample RPM calculated by pcode for FAN3 in last iteration Snapshot Container_10 FAN3_RPM generic_sample reserved Snapshot Container_10 reserved_22 generic_sample PWM calculated by pcode for FAN1 in last iteration Snapshot Container_11 FAN1_PWM passthru PWM calculated by pcode for FAN2 in last iteration Snapshot Container_11 FAN2_PWM passthru PWM calculated by pcode for FAN3 in last iteration Snapshot Container_11 FAN3_PWM passthru reserved Snapshot Container_11 reserved_23 generic_sample Worst Case G6 exit latency observed (in us) Snapshot Container_12 G6_EXIT_LATENCY generic_sample Worst Case G8 exit latency observed (in us) Snapshot Container_12 G8_EXIT_LATENCY generic_sample Worst Case G10 exit latency observed (in us) Snapshot Container_12 G10_EXIT_LATENCY generic_sample Worst Case Modern Standby exit latency observed (in us) Snapshot Container_12 ModS_EXIT_LATENCY generic_sample snoop latency. Units are defined by the scale parameter Snapshot Container_13 SNOOP_VALUE generic_sample SNOOP scale: 000=1ns (shift -10), 001=32nS (shift -5), 010=1uS, 011=32uS (shift 5), 100=1024uS (shift 10), 101=32ms (shift 15), 11x=reserved Snapshot Container_13 SNOOP_SCALE generic_sample SNOOP reserved Snapshot Container_13 SNOOP_RESERVED generic_sample SNOOP valid bit Snapshot Container_13 SNOOP_VALID generic_sample nonsnoop latency. Units are defined by the scale parameter Snapshot Container_13 NONSNOOP_VALUE generic_sample NonSNOOP scale: 000=1ns (shift -10), 001=32nS (shift -5), 010=1uS, 011=32uS (shift 5), 100=1024uS (shift 10), 101=32ms (shift 15), 11x=reserved Snapshot Container_13 NONSNOOP_SCALE generic_sample Non-SNOOP reserved Snapshot Container_13 NONSNOOP_RESERVED generic_sample NonSNOOP valid bit Snapshot Container_13 NONSNOOP_VALID generic_sample Time, in us, until the next fill.A value of all 1's means there is no next fill scheduled Snapshot Container_13 TIME_TO_NEXT_FILL generic_sample reserved Snapshot Container_13 reserved_24 generic_sample LTR Threshold for G6 entry in us Snapshot Container_14 G6_LTR_THRESHOLD ltr LTR Threshold for G8 entry in us Snapshot Container_14 G8_LTR_THRESHOLD ltr LTR Threshold for G10 entry in us Snapshot Container_14 G10_LTR_THRESHOLD ltr reserved Snapshot Container_14 reserved_25 generic_sample Average Current consumed from VCCGT VR in last slowloop for RAPL PID loop computation (U10.6 format) Snapshot Container_15 VCCGT_CURRENT generic_sample Average Current consumed from VCCGT VR in last slowloop for RAPL PID loop computation (U10.6 format) Snapshot Container_15 VCCADMDIG_CURRENT generic_sample Average Current consumed from VCCGT VR in last slowloop for RAPL PID loop computation (U10.6 format) Snapshot Container_15 VCCSA_CURRENT generic_sample Average Current consumed from VCCGT VR in last slowloop for RAPL PID loop computation (U10.6 format) Snapshot Container_15 VCCDDR_CURRENT generic_sample Average Power consumed by package in last slowloop for RAPL PID loop computation (U13.3 format) Snapshot Container_16 PACKAGE_POWER generic_sample Average Power consumed by VRAM in last slowloop (U13.3 format) Snapshot Container_16 VRAM_POWER generic_sample Average Power consumed by Card (PsysGPU) in last slowloop for RAPL PID loop computation (U13.3 format) Snapshot Container_16 PSYSGPU_POWER generic_sample reserved Snapshot Container_16 reserved_26 generic_sample Moving average powered computed by Package PL1 RAPL algorithm Snapshot Container_17 SUSTAINED_PACKAGE_POWER generic_sample Moving average powered computed by Package PL2 RAPL algorithm Snapshot Container_17 BURST_PACKAGE_POWER generic_sample Moving average powered computed by Card (PsysGPU) PL1 RAPL algorithm Snapshot Container_17 SUSTAINED_CARD_POWER generic_sample Moving average powered computed by Card (PsysGPU) PL2 RAPL algorithm Snapshot Container_17 BURST_CARD_POWER generic_sample Thermal margin available before throttling GT in S7.8 format Snapshot Container_18 DISTANCE_TO_THROTTLE_GT generic_sample Thermal margin available before throttling MEDIA in S7.8 format Snapshot Container_18 DISTANCE_TO_THROTTLE_MEDIA generic_sample Thermal margin available before throttling ADM in S7.8 format Snapshot Container_18 DISTANCE_TO_THROTTLE_ADM generic_sample Thermal margin available before throttling VRAM in S7.8 format Snapshot Container_18 DISTANCE_TO_THROTTLE_VRAM generic_sample Display request to enable Vdcore rail Snapshot Container_19 VDCORE_REQ generic_sample Display request to enable Always ON rail. The actual power rail transitions can only be initiated with set block ack bit. This bit can be ignored for no block scenario but it is still an accurate representation of current intent. Snapshot Container_19 VDTG_REQ generic_sample Display request to enable Always ON rail. The actual power rail transitions can only be initiated with set block ack bit. This bit can be ignored for no block scenario but it is still an accurate representation of current intent. Snapshot Container_19 VDRET_REQ generic_sample Display request to enable Always ON rail. The actual power rail transitions can only be initiated with set block ack bit. This bit can be ignored for no block scenario but it is still an accurate representation of current intent. Snapshot Container_19 VDAON_REQ generic_sample reserved Snapshot Container_19 RSVD_4 generic_sample reserved Snapshot Container_19 RSVD_5 generic_sample This field indicates that display has reached the QCLK GV WM Snapshot Container_19 QCLK_GV_STATUS generic_sample reserved Snapshot Container_19 RSVD_7 generic_sample Block acknoweledge (following pmreq with block req, if with force_block, must be acked) Snapshot Container_19 BLOCK_ACK generic_sample reserved Snapshot Container_19 RSVD_9 generic_sample reserved Snapshot Container_19 RSVD_10 generic_sample reserved Snapshot Container_19 RSVD_11 generic_sample Display request to keep crystal running Snapshot Container_19 XTAL_REQ generic_sample reserved Snapshot Container_19 RSVD_13 generic_sample reserved Snapshot Container_19 RSVD_14 generic_sample reserved Snapshot Container_19 RSVD_15 generic_sample LTR in microseconds. Display expects path to memory available in LTR us after DE_wake assertion Snapshot Container_19 LTR ltr reserved Snapshot Container_19 RSVD_29 generic_sample reserved Snapshot Container_19 RSVD_30 generic_sample reserved Snapshot Container_19 RSVD_31 generic_sample Throttle Temperature Limit for SoC Top Die in U8.0 format Snapshot Container_19 THROTTLE_TEMPERATURE_LIMIT_SOC_DIE temperature Throttle Temperature Limit for ADM Base Die in U8.0 format Snapshot Container_19 THROTTLE_TEMPERATURE_LIMIT_ADM_DIE temperature Throttle Temperature Limit for VRAM Device in U8.0 format Snapshot Container_19 THROTTLE_TEMPERATURE_LIMIT_VRAM_DEVICE temperature Throttle Temperature Limit for Voltage Regulator in U8.0 format Snapshot Container_19 THROTTLE_TEMPERATURE_LIMIT_MBVR temperature Release version starting from 0x1 (0x0 indicates unreleased, in addition to platform version, for compatibility) per major version. Does NOT re-start for stepping. 0x0 - Silicon others TBD (>=0x8 expected to be pre-Si such as VP or (H)SLE if format or compile flags are different) 0xB - Release pre-Si version (e.g. ifwi load testing). 0xC - Unreleased CI/CD (i.e. gatekeeper) SOC compile. 0xD - Unreleased CI/CD (i.e. gatekeeper) PUNIT compile. 0xE - Unrelease CI/CD (i.e. gatekeeper) PCODE compile.0xF - Unreleased user build Snapshot Container_20 MINOR_VERSION generic_sample Platform target of compile 0x0 - Silicon others TBD (>=0x8 expected to be pre-Si such as VP or (H)SLE if format or compile flags are different) 0xB - Release pre-Si version (e.g. ifwi load testing) 0xC - Unreleased CI/CD (i.e. gatekeeper) SOC compile 0xD - Unreleased CI/CD (i.e. gatekeeper) PUNIT compile 0xE - Unrelease CI/CD (i.e. gatekeeper) PCODE compile 0xF - Unreleased user build Snapshot Container_20 PLATFORM_VERSION generic_sample Silicon stepping group (grouped by compatible hardware, i.e. if the same PCODE compile can run on A1 or B0 they will have the same STEPPING_VERSION) Snapshot Container_20 STEPPING_VERSION generic_sample New version for each product (Elasti X2, X3, compute, etc.) starting with 1 (0 is invalid indication) Snapshot Container_20 MAJOR_VERSION generic_sample Must be 0 for productionn-releasedd builds For debug, hotfix, release candidate etc. builds (which have a MINOR_VERSION) - First 28 bits are last 6 digits of owner's WWID without conversion from decimal to hex (e.g. 11305524->0x305524) - Lowest nibble (4 bits) is a user increment within the respective major/minor version For unreleased CI/CD builds (platform 0xC ~ 0xE): - All 32 bits will be the first 8 bits of the most recent commit SHA (sufficient to find a git commit in the history) in the repo of the subsystem where it was compiled For user unreleased builds (Platform 0xF): - First 28 bits are last 6 digits of owner's WWID without conversion from decimal to hex (e.g. 11305524->0x305524) - Lowest nibble (4 bits) is 0 if there are uncommitted changes in the repo or the first two MSB of the most recent commits SHA in the repo (this is NOT sufficient to find the commit in the history, but enough to identify recent commits through reflog etc.). Snapshot Container_20 ENGINEERING_VERSION generic_sample Rsvd Snapshot Container_21 Rsvd_0 generic_sample Rsvd Snapshot Container_22 Rsvd_1 generic_sample Rsvd Snapshot Container_23 Rsvd_2 generic_sample Rsvd Snapshot Container_24 Rsvd_3 generic_sample Rsvd Snapshot Container_25 Rsvd_4 generic_sample Rsvd Snapshot Container_26 Rsvd_5 generic_sample Rsvd Snapshot Container_27 Rsvd_6 generic_sample Rsvd Snapshot Container_28 Rsvd_7 generic_sample Rsvd Snapshot Container_29 Rsvd_8 generic_sample Rsvd Snapshot Container_30 Rsvd_9 generic_sample Rsvd Snapshot Container_31 Rsvd_10 generic_sample Rsvd Snapshot Container_32 Rsvd_11 generic_sample Rsvd Snapshot Container_33 Rsvd_12 generic_sample Rsvd Snapshot Container_34 Rsvd_13 generic_sample Rsvd Snapshot Container_35 Rsvd_14 generic_sample Rsvd Snapshot Container_36 Rsvd_15 generic_sample Rsvd Snapshot Container_37 Rsvd_16 generic_sample Rsvd Snapshot Container_38 Rsvd_17 generic_sample Rsvd Snapshot Container_39 Rsvd_18 generic_sample Rsvd Snapshot Container_40 Rsvd_19 generic_sample Rsvd Snapshot Container_41 Rsvd_20 generic_sample Rsvd Snapshot Container_42 Rsvd_21 generic_sample Rsvd Snapshot Container_43 Rsvd_22 generic_sample Rsvd Snapshot Container_44 Rsvd_23 generic_sample Rsvd Snapshot Container_45 Rsvd_24 generic_sample Rsvd Snapshot Container_46 Rsvd_25 generic_sample Rsvd Snapshot Container_47 Rsvd_26 generic_sample Rsvd Snapshot Container_48 Rsvd_27 generic_sample Rsvd Snapshot Container_49 Rsvd_28 generic_sample Rsvd Snapshot Container_50 Rsvd_29 generic_sample Rsvd Snapshot Container_51 Rsvd_30 generic_sample Rsvd Snapshot Container_52 Rsvd_31 generic_sample Rsvd Snapshot Container_53 Rsvd_32 generic_sample Rsvd Snapshot Container_54 Rsvd_33 generic_sample Rsvd Snapshot Container_55 Rsvd_34 generic_sample Rsvd Snapshot Container_56 Rsvd_35 generic_sample Rsvd Snapshot Container_57 Rsvd_36 generic_sample Rsvd Snapshot Container_58 Rsvd_37 generic_sample Rsvd Snapshot Container_59 Rsvd_38 generic_sample Rsvd Snapshot Container_60 Rsvd_39 generic_sample Rsvd Snapshot Container_61 Rsvd_40 generic_sample Rsvd Snapshot Container_62 Rsvd_41 generic_sample Rsvd Snapshot Container_63 Rsvd_42 generic_sample Rsvd Snapshot Container_64 Rsvd_43 generic_sample Rsvd Snapshot Container_65 Rsvd_44 generic_sample Rsvd Snapshot Container_66 Rsvd_45 generic_sample Rsvd Snapshot Container_67 Rsvd_46 generic_sample Rsvd Snapshot Container_68 Rsvd_47 generic_sample Rsvd Snapshot Container_69 Rsvd_48 generic_sample Rsvd Snapshot Container_70 Rsvd_49 generic_sample Rsvd Snapshot Container_71 Rsvd_50 generic_sample Rsvd Snapshot Container_72 Rsvd_51 generic_sample Rsvd Snapshot Container_73 Rsvd_52 generic_sample Rsvd Snapshot Container_74 Rsvd_53 generic_sample Rsvd Snapshot Container_75 Rsvd_54 generic_sample Rsvd Snapshot Container_76 Rsvd_55 generic_sample Rsvd Snapshot Container_77 Rsvd_56 generic_sample Rsvd Snapshot Container_78 Rsvd_57 generic_sample Rsvd Snapshot Container_79 Rsvd_58 generic_sample Rsvd Snapshot Container_80 Rsvd_59 generic_sample Rsvd Snapshot Container_81 Rsvd_60 generic_sample Rsvd Snapshot Container_82 Rsvd_61 generic_sample Rsvd Snapshot Container_83 Rsvd_62 generic_sample Rsvd Snapshot Container_84 Rsvd_63 generic_sample Rsvd Snapshot Container_85 Rsvd_64 generic_sample Rsvd Snapshot Container_86 Rsvd_65 generic_sample Rsvd Snapshot Container_87 Rsvd_66 generic_sample Rsvd Snapshot Container_88 Rsvd_67 generic_sample Rsvd Snapshot Container_89 Rsvd_68 generic_sample Rsvd Snapshot Container_90 Rsvd_69 generic_sample Rsvd Snapshot Container_91 Rsvd_70 generic_sample Rsvd Snapshot Container_92 Rsvd_71 generic_sample Rsvd Snapshot Container_93 Rsvd_72 generic_sample Rsvd Snapshot Container_94 Rsvd_73 generic_sample Rsvd Snapshot Container_95 Rsvd_74 generic_sample Rsvd Snapshot Container_96 Rsvd_75 generic_sample Rsvd Snapshot Container_97 Rsvd_76 generic_sample Rsvd Snapshot Container_98 Rsvd_77 generic_sample Rsvd Snapshot Container_99 Rsvd_78 generic_sample Rsvd Snapshot Container_100 Rsvd_79 generic_sample Rsvd Snapshot Container_101 Rsvd_80 generic_sample Rsvd Snapshot Container_102 Rsvd_81 generic_sample Rsvd Snapshot Container_103 Rsvd_82 generic_sample Rsvd Snapshot Container_104 Rsvd_83 generic_sample Rsvd Snapshot Container_105 Rsvd_84 generic_sample Rsvd Snapshot Container_106 Rsvd_85 generic_sample Rsvd Snapshot Container_107 Rsvd_86 generic_sample Rsvd Snapshot Container_108 Rsvd_87 generic_sample Rsvd Snapshot Container_109 Rsvd_88 generic_sample Rsvd Snapshot Container_110 Rsvd_89 generic_sample Rsvd Snapshot Container_111 Rsvd_90 generic_sample Rsvd Snapshot Container_112 Rsvd_91 generic_sample Rsvd Snapshot Container_113 Rsvd_92 generic_sample Rsvd Snapshot Container_114 Rsvd_93 generic_sample Rsvd Snapshot Container_115 Rsvd_94 generic_sample Rsvd Snapshot Container_116 Rsvd_95 generic_sample Rsvd Snapshot Container_117 Rsvd_96 generic_sample Rsvd Snapshot Container_118 Rsvd_97 generic_sample Rsvd Snapshot Container_119 Rsvd_98 generic_sample Rsvd Snapshot Container_120 Rsvd_99 generic_sample Rsvd Snapshot Container_121 Rsvd_100 generic_sample Rsvd Snapshot Container_122 Rsvd_101 generic_sample Rsvd Snapshot Container_123 Rsvd_102 generic_sample Rsvd Snapshot Container_124 Rsvd_103 generic_sample Rsvd Snapshot Container_125 Rsvd_104 generic_sample Rsvd Snapshot Container_126 Rsvd_105 generic_sample Rsvd Snapshot Container_127 Rsvd_106 generic_sample Accumulator count for Xtal Clock Counter Container_128 XTAL_COUNT xtal_time Power Limited Residency for GT - PL1 : Counter for time while GT is power limited (frequency is being throttled due to power limitations - either because of Package PL1 or Psys GPU PL1) Counter Container_129 PERF_LIMIT_GT_PL1_RESIDENCY xtal_time Power Limited Residency for GT - PL1 : Counter for time while GT is power limited (frequency is being throttled due to power limitations - either because of Package PL2 or Psys GPU PL2) Counter Container_130 PERF_LIMIT_GT_PL2_RESIDENCY xtal_time Power Limited Residency for GT - PL4 : Counter for time while GT is power limited (frequency is being throttled due to power limitations - because of Package PL4 Limit) Counter Container_131 PERF_LIMIT_GT_PL4_RESIDENCY xtal_time Thermal Limited Residency for GT : Counter for time while temperature limited (GT frequency is being throttled to meet temperature limits for any of the dies i.e. SoC top die, ADM die, GDDR device or VR) Counter Container_132 PERF_LIMIT_GT_THERMAL_RESIDENCY xtal_time ICCMAX Limited Residency for GT : Counter for time while current limited (frequency is being throttled because the requested GT frequency would result in exceeding VR Max. current ) Counter Container_133 PERF_LIMIT_GT_ICCMAX_RESIDENCY xtal_time VID Limited Residency for GT : Counter for time while VID limited (frequency is being throttled because the requested GT frequency would result in exceeding MAX VID limit) Counter Container_134 PERF_LIMIT_GT_MAXVID_RESIDENCY xtal_time Utilization Limited Residency for GT : Counter for time while utilization limited (GT frequency request < RPa - driver is requesting a lower frequency than it could if it wanted more performance) Counter Container_135 PERF_LIMIT_GT_UTILIZATION_RESIDENCY xtal_time Prochot Limited Residency for GT : Counter for time while limited due to Prochot (frequency requested for GT is not granted because of Prochot) Counter Container_136 PERF_LIMIT_GT_PROCHOT_RESIDENCY xtal_time Psys_crit Limited Residency for GT : Counter for time while limited due to Prochot (frequency requested for GT is not granted because of Psys_crit) Counter Container_137 PERF_LIMIT_GT_PSYS_CRIT_RESIDENCY xtal_time Power Limited Residency for MEDIA - PL1 : Counter for time while MEDIA is power limited (frequency is being throttled due to power limitations - either because of Package PL1 or Psys GPU PL1) Counter Container_138 PERF_LIMIT_MEDIA_PL1_RESIDENCY xtal_time Power Limited Residency for MEDIA - PL1 : Counter for time while MEDIA is power limited (frequency is being throttled due to power limitations - either because of Package PL2 or Psys GPU PL2) Counter Container_139 PERF_LIMIT_MEDIA_PL2_RESIDENCY xtal_time Power Limited Residency for MEDIA - PL4 : Counter for time while MEDIA is power limited (frequency is being throttled due to power limitations - because of Package PL4 Limit) Counter Container_140 PERF_LIMIT_MEDIA_PL4_RESIDENCY xtal_time Thermal Limited Residency for MEDIA : Counter for time while temperature limited (MEDIA frequency is being throttled to meet temperature limits for any of the dies i.e. SoC top die, ADM die, GDDR device or VR) Counter Container_141 PERF_LIMIT_MEDIA_THERMAL_RESIDENCY xtal_time ICCMAX Limited Residency for MEDIA : Counter for time while current limited (frequency is being throttled because the requested MEDIA frequency would result in exceeding VR Max. current ) Counter Container_142 PERF_LIMIT_MEDIA_ICCMAX_RESIDENCY xtal_time VID Limited Residency for MEDIA : Counter for time while VID limited (frequency is being throttled because the requested MEDIA frequency would result in exceeding MAX VID limit) Counter Container_143 PERF_LIMIT_MEDIA_MAXVID_RESIDENCY xtal_time Utilization Limited Residency for MEDIA : Counter for time while utilization limited (MEDIA frequency request < MPa - driver is requesting a lower frequency than it could if it wanted more performance) Counter Container_144 PERF_LIMIT_MEDIA_UTILIZATION_RESIDENCY xtal_time Prochot Limited Residency for MEDIA : Counter for time while limited due to Prochot (frequency requested for MEDIA is not granted because of Prochot) Counter Container_145 PERF_LIMIT_MEDIA_PROCHOT_RESIDENCY xtal_time Psys_crit Limited Residency for MEDIA : Counter for time while limited due to Prochot (frequency requested for MEDIA is not granted because of Psys_crit) Counter Container_146 PERF_LIMIT_MEDIA_PSYS_CRIT_RESIDENCY xtal_time AFM C3 residency Counter Container_147 AFM_C3_RESIDENCY xtal_time AFM C6 residency Counter Container_148 AFM_C6_RESIDENCY xtal_time ADM C3 residency Counter Container_149 ADM_C3_RESIDENCY xtal_time ADM C6 residency Counter Container_150 ADM_C6_RESIDENCY xtal_time Thermal Limited Residency for ADM : Counter for time while temperature limited (ADM frequency is being throttled to meet temperature limits for any of the dies i.e. SoC top die, ADM die, GDDR device or VR) or ADM temperature is less and hence it has to operate at mid-point Counter Container_151 PERF_LIMIT_ADM_THERMAL_RESIDENCY xtal_time Duration for Memory Frequency Limited because of DC mode of operation Counter Container_152 PERF_LIMIT_VRAM_DC_RESIDENCY xtal_time VRAM Self-Refresh Residency (i.e. G8 + G10 + ModS Residency) Counter Container_153 VRAM_SELF_REFRESH_RESIDENCY xtal_time Modern Standby Residency Counter Container_154 ModS_RESIDENCY xtal_time D0 residency for SGUNIT Counter Container_155 D0_RESIDENCY_SGUNIT xtal_time D0 residency for Audio Counter Container_156 D0_RESIDENCY_AUDIO xtal_time D0 residency for pcie usp controller Counter Container_157 D0_RESIDENCY_PCIE_USP_CONTROLLER xtal_time D3 residency for SGUNIT Counter Container_158 D3_RESIDENCY_SGUNIT xtal_time D3 residency for Audio Counter Container_159 D3_RESIDENCY_AUDIO xtal_time D3 residency for pcie usp controller Counter Container_160 D3_RESIDENCY_PCIE_USP_CONTROLLER xtal_time Duration VCCGT MBVR is hot (i.e. VR reported ThermALERT or VRHOT) Counter Container_161 VCCGT_VRHOT_RESIDENCY xtal_time Duration VCCADMDIG MBVR is hot (i.e. VR reported ThermALERT or VRHOT) Counter Container_162 VCCADMDIG_VRHOT_RESIDENCY xtal_time Duration VCCSA MBVR is hot (i.e. VR reported ThermALERT or VRHOT) Counter Container_163 VCCSA_VRHOT_RESIDENCY xtal_time Duration VCCDDR MBVR is hot (i.e. VR reported ThermALERT or VRHOT) Counter Container_164 VCCDDR_VRHOT_RESIDENCY xtal_time G0 Residency Counter Container_165 G0_RESIDENCY xtal_time G2 Residency Counter Container_166 G2_RESIDENCY xtal_time G6 Residency Counter Container_167 G6_RESIDENCY xtal_time G8 Residency Counter Container_168 G8_RESIDENCY xtal_time G10 Residency Counter Container_169 G10_RESIDENCY xtal_time Time duration for AC mode of operation Counter Container_170 AC_MODE_DURATION_RESIDENCY generic_counter Time duration for DC mode of operation Counter Container_171 DC_MODE_DURATION_RESIDENCY generic_counter Duration for Prochot Counter Container_172 PROCHOT_DURATION_RESIDENCY generic_counter Duration for Psys_crit Counter Container_173 PSYS_CRIT_DURATION_RESIDENCY generic_counter Pcie Link L0 residency Counter Container_174 PCIE_LINK_L0_RESIDENCY xtal_time Pcie Link L1 residency Counter Container_175 PCIE_LINK_L1_RESIDENCY xtal_time Pcie Link L1.2 residency Counter Container_176 PCIE_LINK_L1_2_RESIDENCY xtal_time Pcie Link L2 residency Counter Container_177 PCIE_LINK_L2_RESIDENCY xtal_time GT RC6 entry counter (Accumulator) Counter Container_178 GT_RC6_ENTRY_COUNTER event_counter GT Render Off entry counter (Accumulator) Counter Container_179 GT_RENDER_OFF_ENTRY_COUNTER event_counter MEDIA RC6 entry counter (Accumulator) Counter Container_180 MEDIA_MC6_ENTRY_COUNTER event_counter MEDIA Render Off entry counter (Accumulator) : Both Media Engines should be off.. Counter Container_181 MEDIA_MEDIA_ENGINE_OFF_ENTRY_COUNTER event_counter G0 Entry Count Counter Container_182 G0_ENTRY_COUNT event_counter G2 Entry Count Counter Container_183 G2_ENTRY_COUNT event_counter G6 Entry Count Counter Container_184 G6_ENTRY_COUNT event_counter G8 Entry Count Counter Container_185 G8_ENTRY_COUNT event_counter G10 Entry Count Counter Container_186 G10_ENTRY_COUNT event_counter Modern Standby Entry Count Counter Container_187 ModS_ENTRY_COUNT event_counter GT ACM- PERF_PLL_CNT (64 bit accumulator counter) : IP provides only 16 bit accumulator counter. Pcode should make it 64 bit accumulator. Counter Container_188 GT_ACM_PERF_PLL_CNT event_counter GT ACM- PERF_ACM_CNT (64 bit accumulator counter) : IP provides only 16 bit accumulator counter. Pcode should make it 64 bit accumulator. Counter Container_189 GT_ACM_PERF_ACM_CNT event_counter Transistion count when VCCSA MBVR is hot (i.e. VR reported ThermALERT or VRHOT) Counter Container_190 VCCSA_VRHOT_TRANSITION_COUNT event_counter Transistion count when VCCDDR MBVR is hot (i.e. VR reported ThermALERT or VRHOT) Counter Container_191 VCCDDR_VRHOT_TRANSITION_COUNT event_counter Transition counter for GT Power Limited - PL1 : Transition Count when GT entered power limited state (frequency is being throttled due to power limitations - either because of Package PL1 or Psys GPU PL1) Counter Container_192 PERF_LIMIT_GT_PL1_TRANSITION_COUNT event_counter Transition counter for GT Power Limited - PL2 : Transition Count when GT entered power limited state (frequency is being throttled due to power limitations - either because of Package PL2 or Psys GPU PL2) Counter Container_192 PERF_LIMIT_GT_PL2_TRANSITION_COUNT event_counter Transition counter for GT Power Limited - PL2 : Transition Count when GT entered power limited state (frequency is being throttled due to power limitations - because of Package PL4 limit) Counter Container_193 PERF_LIMIT_GT_PL4_TRANSITION_COUNT event_counter Transition counter for GT Limited - Thermal : Transition count when GT entered thermal limited state(GT frequency is being throttled to meet temperature limits for any of the dies i.e. SoC top die, ADM die, GDDR device or VR) Counter Container_193 PERF_LIMIT_GT_THERMAL_TRANSITION_COUNT event_counter Transition counter for GT Limited - ICCMAX Limit : Transition count when GT entered Current Limited state (frequency is being throttled because the requested GT frequency would result in exceeding VR Max. current ) Counter Container_194 PERF_LIMIT_GT_ICCMAX_TRANSITION_COUNT event_counter Transition counter for GT Limited - VID Limit : Transition count when GT entered VID limited state (frequency is being throttled because the requested GT frequency would result in exceeding MAX VID limit) Counter Container_194 PERF_LIMIT_GT_MAXVID_TRANSITION_COUNT event_counter Transition counter for GT Limited - Prochot : Transition count when GT entered frequency limited state due to Prochot (frequency requested for GT is not granted because of Prochot) Counter Container_195 PERF_LIMIT_GT_PROCHOT_TRANSITION_COUNT event_counter Transition counter for GT Limited - Prochot : Transition count when GT entered frequency limited state due to Psys_crit (frequency requested for GT is not granted because of Psys_crit) Counter Container_195 PERF_LIMIT_GT_PSYS_CRIT_TRANSITION_COUNT event_counter Transition counter for MEDIA Power Limited - PL1 : Transition Count when MEDIA entered power limited state (frequency is being throttled due to power limitations - either because of Package PL1 or Psys GPU PL1) Counter Container_196 PERF_LIMIT_MEDIA_PL1_TRANSITION_COUNT event_counter Transition counter for MEDIA Power Limited - PL2 : Transition Count when MEDIA entered power limited state (frequency is being throttled due to power limitations - either because of Package PL2 or Psys GPU PL2) Counter Container_196 PERF_LIMIT_MEDIA_PL2_TRANSITION_COUNT event_counter Transition counter for MEDIA Power Limited - PL2 : Transition Count when MEDIA entered power limited state (frequency is being throttled due to power limitations - because of Package PL4 limit) Counter Container_197 PERF_LIMIT_MEDIA_PL4_TRANSITION_COUNT event_counter Transition counter for MEDIA Limited - Thermal : Transition count when MEDIA entered thermal limited state(MEDIA frequency is being throttled to meet temperature limits for any of the dies i.e. SoC top die, ADM die, GDDR device or VR) Counter Container_197 PERF_LIMIT_MEDIA_THERMAL_TRANSITION_COUNT event_counter Transition counter for MEDIA Limited - ICCMAX Limit : Transition count when MEDIA entered Current Limited state (frequency is being throttled because the requested MEDIA frequency would result in exceeding VR Max. current ) Counter Container_198 PERF_LIMIT_MEDIA_ICCMAX_TRANSITION_COUNT event_counter Transition counter for MEDIA Limited - VID Limit : Transition count when MEDIA entered VID limited state (frequency is being throttled because the requested MEDIA frequency would result in exceeding MAX VID limit) Counter Container_198 PERF_LIMIT_MEDIA_MAXVID_TRANSITION_COUNT event_counter Transition counter for MEDIA Limited - Prochot : Transition count when MEDIA entered frequency limited state due to Prochot (frequency requested for MEDIA is not granted because of Prochot) Counter Container_199 PERF_LIMIT_MEDIA_PROCHOT_TRANSITION_COUNT event_counter Transition counter for MEDIA Limited - Prochot : Transition count when MEDIA entered frequency limited state due to Psys_crit (frequency requested for MEDIA is not granted because of Psys_crit) Counter Container_199 PERF_LIMIT_MEDIA_PSYS_CRIT_TRANSITION_COUNT event_counter Transition counter for ADM Limited - Thermal : Transition count when ADM entered thermal limited state Counter Container_200 PERF_LIMIT_ADM_THERMAL_TRANSITION_COUNT event_counter Transition counter for Memory Frequency Limited - DC Mode Counter Container_200 PERF_LIMIT_VRAM_DC_TRANSITION_COUNT event_counter AC -> DC transition Count Counter Container_201 AC_TO_DC_TRANSITION_COUNT event_counter Transistion count when VCCGT MBVR entered hot state (i.e. VR reported ThermALERT or VRHOT) Counter Container_201 VCCGT_VRHOT_TRANSITION_COUNT event_counter Transistion count when VCCADMDIG MBVR is hot (i.e. VR reported ThermALERT or VRHOT) Counter Container_202 VCCADMDIG_VRHOT_TRANSITION_COUNT event_counter Prochot Assertion Count Counter Container_202 PROCHOT_ASSERTION_COUNT event_counter Psys_crit Assertion Count Counter Container_203 PSYS_CRIT_ASSERTION_COUNT event_counter VCCGT Energy Accumulator (U18.14 format) Counter Container_203 VCCGT_ENERGY_ACCUMULATOR energy VCCADMDIG Energy Accumulator (U18.14 format) Counter Container_204 VCCADMDIG_ENERGY_ACCUMULATOR energy VCCSA Energy Accumulator (U18.14 format) Counter Container_204 VCCSA_ENERGY_ACCUMULATOR energy VCCDDR Energy Accumulator (U18.14 format) Counter Container_205 VCCDDR_ENERGY_ACCUMULATOR energy SoC G-state wakeup counter due to wake up Counter Container_205 SoC_LOW_POWER_STATE_WAKEUP_REASON event_counter SoC G-state wakeup counter due to wake up from Display (De_poke) Counter Container_206 SoC_LOW_POWER_STATE_WAKEUP_REASON_DEPOKE passthru SoC G-state wakeup counter due to wake up from Display (De_Wake) Counter Container_206 SoC_LOW_POWER_STATE_WAKEUP_REASON_DEWAKE passthru SoC G-state wakeup counter due to wake up from Display (TTNF) Counter Container_207 SoC_LOW_POWER_STATE_WAKEUP_REASON_DISPLAY_TTNF passthru SoC G-state wakeup counter due to wake up from Display Hotplug Counter Container_207 SoC_LOW_POWER_STATE_WAKEUP_REASON_DISPLAY_HOTPLUG passthru SoC G-state wakeup counter due to wake up from Audio Vnn_req (or) clk_req Counter Container_208 SoC_LOW_POWER_STATE_WAKEUP_REASON_AUDIO passthru SoC G-state wakeup counter due to wake up from CSC Timer Counter Container_208 SoC_LOW_POWER_STATE_WAKEUP_REASON_CSC_TIMER passthru SoC G-state wakeup counter due to wake up from GT ARAT Timer Counter Container_209 SoC_LOW_POWER_STATE_WAKEUP_REASON_GT_ARAT passthru SoC G-state wakeup counter due to wake up from Media Arat Timer Counter Container_209 SoC_LOW_POWER_STATE_WAKEUP_REASON_MEDIA_ARAT passthru SoC G-state wakeup counter due to wake up from Pcie Link Counter Container_210 SoC_LOW_POWER_STATE_WAKEUP_REASON_PCIE_LINK passthru SoC G-state wakeup counter due to wake up from OOB IPs Counter Container_210 SoC_LOW_POWER_STATE_WAKEUP_REASON_OOB passthru SoC G-state wakeup counter due to wake up from Serial Peci Counter Container_211 SoC_LOW_POWER_STATE_WAKEUP_REASON_SERIAL_PECI passthru SoC G-state wakeup counter due to wake up from Surprise PERST_N (warm reset) Counter Container_211 SoC_LOW_POWER_STATE_WAKEUP_REASON_WARM_RESET passthru SoC G-state wakeup counter due to wake up from PERST_N (modern standby exit) Counter Container_212 SoC_LOW_POWER_STATE_WAKEUP_REASON_PERST_N passthru SoC G-state wakeup counter due to wake up from TAP Counter Container_212 SoC_LOW_POWER_STATE_WAKEUP_REASON_TAP passthru SoC G-state wakeup counter due to wake up from I2C Alert Counter Container_213 SoC_LOW_POWER_STATE_WAKEUP_REASON_I2C_ALERT passthru SoC G-state wakeup counter due to wake up from SPI VNN_REQ Counter Container_213 SoC_LOW_POWER_STATE_WAKEUP_REASON_SPI passthru SoC G-state wakeup counter due to wake up from SGUNIT CLK_REQ Counter Container_214 SoC_LOW_POWER_STATE_WAKEUP_REASON_SGUNIT passthru Counts the number of 1ms intervals during which SoC G-state entry was blocked for any reason Counter Container_214 SoC_LOW_POWER_ENTRY_BLOCK_RESIDENCY event_counter Counts the number of 1ms intervals during which SoC G-state entry was blocked at least once by pcie link state Counter Container_215 SoC_LOW_POWER_ENTRY_BLOCK_RESIDENCY_PCIE_LINK_STATE soc_lp_block_cause Counts the number of 1ms intervals during which SoC G-state entry was blocked at least once by display Counter Container_215 SoC_LOW_POWER_ENTRY_BLOCK_RESIDENCY_DISPLAY soc_lp_block_cause Counts the number of 1ms intervals during which SoC G-state entry was blocked at least once by audio Counter Container_216 SoC_LOW_POWER_ENTRY_BLOCK_RESIDENCY_AUDIO soc_lp_block_cause Counts the number of 1ms intervals during which SoC G-state entry was blocked at least once by csc Counter Container_216 SoC_LOW_POWER_ENTRY_BLOCK_RESIDENCY_CSC soc_lp_block_cause Counts the number of 1ms intervals during which SoC G-state entry was blocked at least once by spi controller Counter Container_217 SoC_LOW_POWER_ENTRY_BLOCK_RESIDENCY_SPI soc_lp_block_cause Counts the number of 1ms intervals during which SoC G-state entry was blocked at least once by OOB IPs Counter Container_217 SoC_LOW_POWER_ENTRY_BLOCK_RESIDENCY_OOB soc_lp_block_cause Counts the number of 1ms intervals during which SoC G-state entry was blocked at least once by I2c Host Controller Counter Container_218 SoC_LOW_POWER_ENTRY_BLOCK_RESIDENCY_I2CHOST soc_lp_block_cause Counts the number of 1ms intervals during which SoC G-state entry was blocked at least once by Northpeak Counter Container_218 SoC_LOW_POWER_ENTRY_BLOCK_RESIDENCY_NPK soc_lp_block_cause Reserved for future expansion Counter Container_219 CNTR_RESERVED_0 generic_counter Reserved for future expansion Counter Container_220 CNTR_RESERVED_1 generic_counter Reserved for future expansion Counter Container_221 CNTR_RESERVED_2 generic_counter Reserved for future expansion Counter Container_222 CNTR_RESERVED_3 generic_counter Reserved for future expansion Counter Container_223 CNTR_RESERVED_4 generic_counter Reserved for future expansion Counter Container_224 CNTR_RESERVED_5 generic_counter Reserved for future expansion Counter Container_225 CNTR_RESERVED_6 generic_counter Reserved for future expansion Counter Container_226 CNTR_RESERVED_7 generic_counter Reserved for future expansion Counter Container_227 CNTR_RESERVED_8 generic_counter Reserved for future expansion Counter Container_228 CNTR_RESERVED_9 generic_counter Reserved for future expansion Counter Container_229 CNTR_RESERVED_10 generic_counter Reserved for future expansion Counter Container_230 CNTR_RESERVED_11 generic_counter Reserved for future expansion Counter Container_231 CNTR_RESERVED_12 generic_counter Reserved for future expansion Counter Container_232 CNTR_RESERVED_13 generic_counter Reserved for future expansion Counter Container_233 CNTR_RESERVED_14 generic_counter Reserved for future expansion Counter Container_234 CNTR_RESERVED_15 generic_counter Reserved for future expansion Counter Container_235 CNTR_RESERVED_16 generic_counter Reserved for future expansion Counter Container_236 CNTR_RESERVED_17 generic_counter Reserved for future expansion Counter Container_237 CNTR_RESERVED_18 generic_counter Reserved for future expansion Counter Container_238 CNTR_RESERVED_19 generic_counter Reserved for future expansion Counter Container_239 CNTR_RESERVED_20 generic_counter Reserved for future expansion Counter Container_240 CNTR_RESERVED_21 generic_counter Reserved for future expansion Counter Container_241 CNTR_RESERVED_22 generic_counter Reserved for future expansion Counter Container_242 CNTR_RESERVED_23 generic_counter Reserved for future expansion Counter Container_243 CNTR_RESERVED_24 generic_counter Reserved for future expansion Counter Container_244 CNTR_RESERVED_25 generic_counter Reserved for future expansion Counter Container_245 CNTR_RESERVED_26 generic_counter Reserved for future expansion Counter Container_246 CNTR_RESERVED_27 generic_counter Reserved for future expansion Counter Container_247 CNTR_RESERVED_28 generic_counter Reserved for future expansion Counter Container_248 CNTR_RESERVED_29 generic_counter Reserved for future expansion Counter Container_249 CNTR_RESERVED_30 generic_counter Reserved for future expansion Counter Container_250 CNTR_RESERVED_31 generic_counter Reserved for future expansion Counter Container_251 CNTR_RESERVED_32 generic_counter Reserved for future expansion Counter Container_252 CNTR_RESERVED_33 generic_counter Reserved for future expansion Counter Container_253 CNTR_RESERVED_34 generic_counter Reserved for future expansion Counter Container_254 CNTR_RESERVED_35 generic_counter Reserved for future expansion Counter Container_255 CNTR_RESERVED_36 generic_counter Reserved for future expansion Counter Container_256 CNTR_RESERVED_37 generic_counter Reserved for future expansion Counter Container_257 CNTR_RESERVED_38 generic_counter Reserved for future expansion Counter Container_258 CNTR_RESERVED_39 generic_counter Reserved for future expansion Counter Container_259 CNTR_RESERVED_40 generic_counter Reserved for future expansion Counter Container_260 CNTR_RESERVED_41 generic_counter Reserved for future expansion Counter Container_261 CNTR_RESERVED_42 generic_counter Reserved for future expansion Counter Container_262 CNTR_RESERVED_43 generic_counter Reserved for future expansion Counter Container_263 CNTR_RESERVED_44 generic_counter Reserved for future expansion Counter Container_264 CNTR_RESERVED_45 generic_counter Reserved for future expansion Counter Container_265 CNTR_RESERVED_46 generic_counter Reserved for future expansion Counter Container_266 CNTR_RESERVED_47 generic_counter Reserved for future expansion Counter Container_267 CNTR_RESERVED_48 generic_counter Reserved for future expansion Counter Container_268 CNTR_RESERVED_49 generic_counter Reserved for future expansion Counter Container_269 CNTR_RESERVED_50 generic_counter Reserved for future expansion Counter Container_270 CNTR_RESERVED_51 generic_counter Reserved for future expansion Counter Container_271 CNTR_RESERVED_52 generic_counter Reserved for future expansion Counter Container_272 CNTR_RESERVED_53 generic_counter Reserved for future expansion Counter Container_273 CNTR_RESERVED_54 generic_counter Reserved for future expansion Counter Container_274 CNTR_RESERVED_55 generic_counter Reserved for future expansion Counter Container_275 CNTR_RESERVED_56 generic_counter Reserved for future expansion Counter Container_276 CNTR_RESERVED_57 generic_counter Reserved for future expansion Counter Container_277 CNTR_RESERVED_58 generic_counter Reserved for future expansion Counter Container_278 CNTR_RESERVED_59 generic_counter Reserved for future expansion Counter Container_279 CNTR_RESERVED_60 generic_counter Reserved for future expansion Counter Container_280 CNTR_RESERVED_61 generic_counter Reserved for future expansion Counter Container_281 CNTR_RESERVED_62 generic_counter Reserved for future expansion Counter Container_282 CNTR_RESERVED_63 generic_counter Reserved for future expansion Counter Container_283 CNTR_RESERVED_64 generic_counter Reserved for future expansion Counter Container_284 CNTR_RESERVED_65 generic_counter Reserved for future expansion Counter Container_285 CNTR_RESERVED_66 generic_counter Reserved for future expansion Counter Container_286 CNTR_RESERVED_67 generic_counter Reserved for future expansion Counter Container_287 CNTR_RESERVED_68 generic_counter Reserved for future expansion Counter Container_288 CNTR_RESERVED_69 generic_counter Reserved for future expansion Counter Container_289 CNTR_RESERVED_70 generic_counter Reserved for future expansion Counter Container_290 CNTR_RESERVED_71 generic_counter Reserved for future expansion Counter Container_291 CNTR_RESERVED_72 generic_counter Reserved for future expansion Counter Container_292 CNTR_RESERVED_73 generic_counter Reserved for future expansion Counter Container_293 CNTR_RESERVED_74 generic_counter Reserved for future expansion Counter Container_294 CNTR_RESERVED_75 generic_counter Reserved for future expansion Counter Container_295 CNTR_RESERVED_76 generic_counter Reserved for future expansion Counter Container_296 CNTR_RESERVED_77 generic_counter Reserved for future expansion Counter Container_297 CNTR_RESERVED_78 generic_counter Reserved for future expansion Counter Container_298 CNTR_RESERVED_79 generic_counter Reserved for future expansion Counter Container_299 CNTR_RESERVED_80 generic_counter Reserved for future expansion Counter Container_300 CNTR_RESERVED_81 generic_counter Reserved for future expansion Counter Container_301 CNTR_RESERVED_82 generic_counter Reserved for future expansion Counter Container_302 CNTR_RESERVED_83 generic_counter Reserved for future expansion Counter Container_303 CNTR_RESERVED_84 generic_counter Reserved for future expansion Counter Container_304 CNTR_RESERVED_85 generic_counter Reserved for future expansion Counter Container_305 CNTR_RESERVED_86 generic_counter Reserved for future expansion Counter Container_306 CNTR_RESERVED_87 generic_counter Reserved for future expansion Counter Container_307 CNTR_RESERVED_88 generic_counter Reserved for future expansion Counter Container_308 CNTR_RESERVED_89 generic_counter Reserved for future expansion Counter Container_309 CNTR_RESERVED_90 generic_counter Reserved for future expansion Counter Container_310 CNTR_RESERVED_91 generic_counter Reserved for future expansion Counter Container_311 CNTR_RESERVED_92 generic_counter Reserved for future expansion Counter Container_312 CNTR_RESERVED_93 generic_counter Reserved for future expansion Counter Container_313 CNTR_RESERVED_94 generic_counter Reserved for future expansion Counter Container_314 CNTR_RESERVED_95 generic_counter Reserved for future expansion Counter Container_315 CNTR_RESERVED_96 generic_counter Reserved for future expansion Counter Container_316 CNTR_RESERVED_97 generic_counter Reserved for future expansion Counter Container_317 CNTR_RESERVED_98 generic_counter Reserved for future expansion Counter Container_318 CNTR_RESERVED_99 generic_counter Reserved for future expansion Counter Container_319 CNTR_RESERVED_100 generic_counter Reserved for future expansion Counter Container_320 CNTR_RESERVED_101 generic_counter Reserved for future expansion Counter Container_321 CNTR_RESERVED_102 generic_counter Reserved for future expansion Counter Container_322 CNTR_RESERVED_103 generic_counter Reserved for future expansion Counter Container_323 CNTR_RESERVED_104 generic_counter Reserved for future expansion Counter Container_324 CNTR_RESERVED_105 generic_counter Reserved for future expansion Counter Container_325 CNTR_RESERVED_106 generic_counter Reserved for future expansion Counter Container_326 CNTR_RESERVED_107 generic_counter Reserved for future expansion Counter Container_327 CNTR_RESERVED_108 generic_counter Reserved for future expansion Counter Container_328 CNTR_RESERVED_109 generic_counter Reserved for future expansion Counter Container_329 CNTR_RESERVED_110 generic_counter Reserved for future expansion Counter Container_330 CNTR_RESERVED_111 generic_counter Reserved for future expansion Counter Container_331 CNTR_RESERVED_112 generic_counter Reserved for future expansion Counter Container_332 CNTR_RESERVED_113 generic_counter Reserved for future expansion Counter Container_333 CNTR_RESERVED_114 generic_counter Reserved for future expansion Counter Container_334 CNTR_RESERVED_115 generic_counter Reserved for future expansion Counter Container_335 CNTR_RESERVED_116 generic_counter Reserved for future expansion Counter Container_336 CNTR_RESERVED_117 generic_counter Reserved for future expansion Counter Container_337 CNTR_RESERVED_118 generic_counter Reserved for future expansion Counter Container_338 CNTR_RESERVED_119 generic_counter Reserved for future expansion Counter Container_339 CNTR_RESERVED_120 generic_counter Reserved for future expansion Counter Container_340 CNTR_RESERVED_121 generic_counter Reserved for future expansion Counter Container_341 CNTR_RESERVED_122 generic_counter Reserved for future expansion Counter Container_342 CNTR_RESERVED_123 generic_counter Reserved for future expansion Counter Container_343 CNTR_RESERVED_124 generic_counter Reserved for future expansion Counter Container_344 CNTR_RESERVED_125 generic_counter Reserved for future expansion Counter Container_345 CNTR_RESERVED_126 generic_counter Reserved for future expansion Counter Container_346 CNTR_RESERVED_127 generic_counter Reserved for future expansion Counter Container_347 CNTR_RESERVED_128 generic_counter Reserved for future expansion Counter Container_348 CNTR_RESERVED_129 generic_counter Reserved for future expansion Counter Container_349 CNTR_RESERVED_130 generic_counter Reserved for future expansion Counter Container_350 CNTR_RESERVED_131 generic_counter Reserved for future expansion Counter Container_351 CNTR_RESERVED_132 generic_counter Reserved for future expansion Counter Container_352 CNTR_RESERVED_133 generic_counter Reserved for future expansion Counter Container_353 CNTR_RESERVED_134 generic_counter Reserved for future expansion Counter Container_354 CNTR_RESERVED_135 generic_counter Reserved for future expansion Counter Container_355 CNTR_RESERVED_136 generic_counter Reserved for future expansion Counter Container_356 CNTR_RESERVED_137 generic_counter Reserved for future expansion Counter Container_357 CNTR_RESERVED_138 generic_counter Reserved for future expansion Counter Container_358 CNTR_RESERVED_139 generic_counter Reserved for future expansion Counter Container_359 CNTR_RESERVED_140 generic_counter Reserved for future expansion Counter Container_360 CNTR_RESERVED_141 generic_counter Reserved for future expansion Counter Container_361 CNTR_RESERVED_142 generic_counter Reserved for future expansion Counter Container_362 CNTR_RESERVED_143 generic_counter Reserved for future expansion Counter Container_363 CNTR_RESERVED_144 generic_counter Reserved for future expansion Counter Container_364 CNTR_RESERVED_145 generic_counter Reserved for future expansion Counter Container_365 CNTR_RESERVED_146 generic_counter Reserved for future expansion Counter Container_366 CNTR_RESERVED_147 generic_counter Reserved for future expansion Counter Container_367 CNTR_RESERVED_148 generic_counter Reserved for future expansion Counter Container_368 CNTR_RESERVED_149 generic_counter Reserved for future expansion Counter Container_369 CNTR_RESERVED_150 generic_counter Reserved for future expansion Counter Container_370 CNTR_RESERVED_151 generic_counter Reserved for future expansion Counter Container_371 CNTR_RESERVED_152 generic_counter Reserved for future expansion Counter Container_372 CNTR_RESERVED_153 generic_counter Reserved for future expansion Counter Container_373 CNTR_RESERVED_154 generic_counter Reserved for future expansion Counter Container_374 CNTR_RESERVED_155 generic_counter Reserved for future expansion Counter Container_375 CNTR_RESERVED_156 generic_counter Reserved for future expansion Counter Container_376 CNTR_RESERVED_157 generic_counter Reserved for future expansion Counter Container_377 CNTR_RESERVED_158 generic_counter Reserved for future expansion Counter Container_378 CNTR_RESERVED_159 generic_counter Reserved for future expansion Counter Container_379 CNTR_RESERVED_160 generic_counter Reserved for future expansion Counter Container_380 CNTR_RESERVED_161 generic_counter Reserved for future expansion Counter Container_381 CNTR_RESERVED_162 generic_counter Reserved for future expansion Counter Container_382 CNTR_RESERVED_163 generic_counter Reserved for future expansion Counter Container_383 CNTR_RESERVED_164 generic_counter Reserved for future expansion Counter Container_384 CNTR_RESERVED_165 generic_counter Reserved for future expansion Counter Container_385 CNTR_RESERVED_166 generic_counter Reserved for future expansion Counter Container_386 CNTR_RESERVED_167 generic_counter Reserved for future expansion Counter Container_387 CNTR_RESERVED_168 generic_counter Reserved for future expansion Counter Container_388 CNTR_RESERVED_169 generic_counter Reserved for future expansion Counter Container_389 CNTR_RESERVED_170 generic_counter Reserved for future expansion Counter Container_390 CNTR_RESERVED_171 generic_counter Reserved for future expansion Counter Container_391 CNTR_RESERVED_172 generic_counter Reserved for future expansion Counter Container_392 CNTR_RESERVED_173 generic_counter Reserved for future expansion Counter Container_393 CNTR_RESERVED_174 generic_counter Reserved for future expansion Counter Container_394 CNTR_RESERVED_175 generic_counter Reserved for future expansion Counter Container_395 CNTR_RESERVED_176 generic_counter Reserved for future expansion Counter Container_396 CNTR_RESERVED_177 generic_counter Reserved for future expansion Counter Container_397 CNTR_RESERVED_178 generic_counter Reserved for future expansion Counter Container_398 CNTR_RESERVED_179 generic_counter Reserved for future expansion Counter Container_399 CNTR_RESERVED_180 generic_counter Reserved for future expansion Counter Container_400 CNTR_RESERVED_181 generic_counter Reserved for future expansion Counter Container_401 CNTR_RESERVED_182 generic_counter Reserved for future expansion Counter Container_402 CNTR_RESERVED_183 generic_counter Reserved for future expansion Counter Container_403 CNTR_RESERVED_184 generic_counter Reserved for future expansion Counter Container_404 CNTR_RESERVED_185 generic_counter Reserved for future expansion Counter Container_405 CNTR_RESERVED_186 generic_counter Reserved for future expansion Counter Container_406 CNTR_RESERVED_187 generic_counter Reserved for future expansion Counter Container_407 CNTR_RESERVED_188 generic_counter Reserved for future expansion Counter Container_408 CNTR_RESERVED_189 generic_counter Reserved for future expansion Counter Container_409 CNTR_RESERVED_190 generic_counter Reserved for future expansion Counter Container_410 CNTR_RESERVED_191 generic_counter Reserved for future expansion Counter Container_411 CNTR_RESERVED_192 generic_counter Reserved for future expansion Counter Container_412 CNTR_RESERVED_193 generic_counter Reserved for future expansion Counter Container_413 CNTR_RESERVED_194 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Reserved for future expansion Counter Container_495 CNTR_RESERVED_276 generic_counter Reserved for future expansion Counter Container_496 CNTR_RESERVED_277 generic_counter Reserved for future expansion Counter Container_497 CNTR_RESERVED_278 generic_counter Reserved for future expansion Counter Container_498 CNTR_RESERVED_279 generic_counter Reserved for future expansion Counter Container_499 CNTR_RESERVED_280 generic_counter Reserved for future expansion Counter Container_500 CNTR_RESERVED_281 generic_counter Reserved for future expansion Counter Container_501 CNTR_RESERVED_282 generic_counter Reserved for future expansion Counter Container_502 CNTR_RESERVED_283 generic_counter Reserved for future expansion Counter Container_503 CNTR_RESERVED_284 generic_counter Reserved for future expansion Counter Container_504 CNTR_RESERVED_285 generic_counter Reserved for future expansion Counter Container_505 CNTR_RESERVED_286 generic_counter Reserved for future expansion Counter Container_506 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