]> &otherfile; LNL LNL M/P PMT Telemetry aggregator 0 samples definition and transformation rules 0x03072005 LNL 0 Groupname 0x82e8 64 Local Revision ID for this product (revision of the xml) GLOBAL_ID Snapshot 8 0 7 1' for Fixed block telemetry ID, '0' for rest. Default is '0' GLOBAL_ID Snapshot 1 8 8 Product ID= 22 | TGLUY= 23 | TGLH= 24 | TGLS= 79 | ADL-P= 80 | ADL-S= 90 | RPL= 91 | RPL-P= 92 | RPL-S= 103 | MTL-M= 104 | MTL-P= 105 | MTL-S= 106 | ARL= 114 | LNL-M= 134 | PTL-P= 135 | PTL-H GLOBAL_ID Snapshot 12 12 23 source id for data provider GLOBAL_ID Snapshot 6 24 29 reserved GLOBAL_ID Snapshot 2 30 31 Represents the clock rate of the XTAL on this silicon.= 0 | 24MHz= 1 | 19.2MHz= 2 | 38.4MHz= 3 | 25MHz STRAPS Snapshot 2 32 33 reserved STRAPS Snapshot 30 34 63 Groupname 0x82f0 64 ICCMAX level for the IPU's IS system IPU_WORKPOINT Snapshot 8 0 7 ICCMAX level for the IPU's PS system IPU_WORKPOINT Snapshot 8 8 15 Processing system frequency. Frequency is ratio*25MHz. Zero means power down. IPU_WORKPOINT Snapshot 8 16 23 IS system frequency. Frequency is ratio*16MHz. Zero means power down. IPU_WORKPOINT Snapshot 8 24 31 IS voltage requirement IPU_WORKPOINT Snapshot 8 32 39 PS voltage requirement IPU_WORKPOINT Snapshot 8 40 47 reserved IPU_WORKPOINT Snapshot 16 48 63 Groupname 0x82f8 64 Qclk frequency for Mem SS in units of 33MHz SA_OTHERS_WORKPOINT0 Snapshot 8 0 7 Mem SS voltage requirement SA_OTHERS_WORKPOINT0 Snapshot 8 8 15 CDCLK frequency for display SA_OTHERS_WORKPOINT0 Snapshot 10 16 25 Display voltage requirement SA_OTHERS_WORKPOINT0 Snapshot 8 26 33 NCLK frequency SA_OTHERS_WORKPOINT0 Snapshot 8 34 41 NCLK voltage requirement SA_OTHERS_WORKPOINT0 Snapshot 8 42 49 D2D frequency in units of 50MHz SA_OTHERS_WORKPOINT0 Snapshot 8 50 57 reserved SA_OTHERS_WORKPOINT0 Snapshot 6 58 63 Groupname 0x8300 64 VPU frequency in units of 50MHz VPU_WORKPOINT Snapshot 8 0 7 VPU voltage requirement VPU_WORKPOINT Snapshot 8 8 15 Indicates the tile configuration internal to VPU VPU_WORKPOINT Snapshot 8 16 23 reserved VPU_WORKPOINT Snapshot 8 24 31 Media voltage requirement MEDIA_WORKPOINT Snapshot 8 32 39 Media ratio in units of 50MHz MEDIA_WORKPOINT Snapshot 8 48 55 Reserved MEDIA_WORKPOINT Snapshot 8 56 63 Groupname 0x8308 64 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. LLC_WORKPOINT Snapshot 11 0 10 Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. LLC_WORKPOINT Snapshot 10 11 20 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. LLC_WORKPOINT Snapshot 3 21 23 IA Module clock ratio, in units of 100MHz. LLC_WORKPOINT Snapshot 8 24 31 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. CCP_WORKPOINT0 Snapshot 11 32 42 Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. CCP_WORKPOINT0 Snapshot 10 43 52 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. CCP_WORKPOINT0 Snapshot 3 53 55 IA Module clock ratio, in units of 100MHz. CCP_WORKPOINT0 Snapshot 8 56 63 Groupname 0x8310 64 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. CCP_WORKPOINT1 Snapshot 11 0 10 Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. CCP_WORKPOINT1 Snapshot 10 11 20 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. CCP_WORKPOINT1 Snapshot 3 21 23 IA Module clock ratio, in units of 100MHz. CCP_WORKPOINT1 Snapshot 8 24 31 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. CCP_WORKPOINT2 Snapshot 11 32 42 Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. CCP_WORKPOINT2 Snapshot 10 43 52 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. CCP_WORKPOINT2 Snapshot 3 53 55 IA Module clock ratio, in units of 100MHz. CCP_WORKPOINT2 Snapshot 8 56 63 Groupname 0x8318 64 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. CCP_WORKPOINT3 Snapshot 11 0 10 Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. CCP_WORKPOINT3 Snapshot 10 11 20 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. CCP_WORKPOINT3 Snapshot 3 21 23 IA Module clock ratio, in units of 100MHz. CCP_WORKPOINT3 Snapshot 8 24 31 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. CCP_WORKPOINT4 Snapshot 11 32 42 Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. CCP_WORKPOINT4 Snapshot 10 43 52 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. CCP_WORKPOINT4 Snapshot 3 53 55 IA Module clock ratio, in units of 100MHz. CCP_WORKPOINT4 Snapshot 8 56 63 Groupname 0x8320 64 reserved RSVD_8320 Snapshot 32 0 31 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if GT modules are supplied by internal VR, otherwise value should be ignored. GT_WORKPOINT Snapshot 11 32 42 Reserved GT_WORKPOINT Snapshot 10 43 52 Internal VR power state (PS). valid only if GT modules are supplied by internal VR, otherwise value should be ignored. GT_WORKPOINT Snapshot 3 53 55 GT clock ratio, in units of 50MHz GT_WORKPOINT Snapshot 8 56 63 Groupname 0x8328 64 Indicates systolic config GT_CONFIG_REQ Snapshot 1 1 1 EUs active GT_CONFIG_REQ Snapshot 8 2 9 unused in LNL GT_CONFIG_REQ Snapshot 3 10 12 subslice count GT_CONFIG_REQ Snapshot 5 13 17 active slices in GT GT_CONFIG_REQ Snapshot 4 18 21 reserved GT_CONFIG_REQ Snapshot 10 22 31 Graphics Security Controller (GSC). 0 - GSC is power-gated. 1 - GSC is not power-gated. MEDIA_CONFIG_REQ Snapshot 1 32 32 Total number of active media engines in Media. Inactive means power-gated, that is, no leakage. The range in LNL is 0-1, since LNL Media has only 1 slice. MEDIA_CONFIG_REQ Snapshot 3 33 35 Reserved MEDIA_CONFIG_REQ Snapshot 28 36 63 Groupname 0x8330 64 VID Code. Encoding is based on SVID spec. SVID_WORKPOINT_0_1 Snapshot 8 0 7 VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 SVID_WORKPOINT_0_1 Snapshot 3 8 10 Issue FAST ramp, instead of SLOW ramp. SVID_WORKPOINT_0_1 Snapshot 1 11 11 Issue DECAY ramp, instead of SLOW ramp. Only going down. SVID_WORKPOINT_0_1 Snapshot 1 12 12 VID Code. Encoding is based on SVID spec. SVID_WORKPOINT_0_1 Snapshot 8 16 23 VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 SVID_WORKPOINT_0_1 Snapshot 3 24 26 Issue FAST ramp, instead of SLOW ramp. SVID_WORKPOINT_0_1 Snapshot 1 27 27 Issue DECAY ramp, instead of SLOW ramp. Only going down. SVID_WORKPOINT_0_1 Snapshot 1 28 28 reserved SVID_WORKPOINT_0_1 Snapshot 3 29 31 VID Code. Encoding is based on SVID spec. SVID_WORKPOINT_2_3 Snapshot 8 32 39 VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 SVID_WORKPOINT_2_3 Snapshot 3 40 42 Issue FAST ramp, instead of SLOW ramp. SVID_WORKPOINT_2_3 Snapshot 1 43 43 Issue DECAY ramp, instead of SLOW ramp. Only going down. SVID_WORKPOINT_2_3 Snapshot 1 44 44 VID Code. Encoding is based on SVID spec. SVID_WORKPOINT_2_3 Snapshot 8 48 55 VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 SVID_WORKPOINT_2_3 Snapshot 3 56 58 Issue FAST ramp, instead of SLOW ramp. SVID_WORKPOINT_2_3 Snapshot 1 59 59 Issue DECAY ramp, instead of SLOW ramp. Only going down. SVID_WORKPOINT_2_3 Snapshot 1 60 60 reserved SVID_WORKPOINT_2_3 Snapshot 3 61 63 Groupname 0x8338 64 VID Code. Encoding is based on SVID spec. SVID_WORKPOINT_4_5 Snapshot 8 0 7 VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 SVID_WORKPOINT_4_5 Snapshot 3 8 10 Issue FAST ramp, instead of SLOW ramp. SVID_WORKPOINT_4_5 Snapshot 1 11 11 Issue DECAY ramp, instead of SLOW ramp. Only going down. SVID_WORKPOINT_4_5 Snapshot 1 12 12 VID Code. Encoding is based on SVID spec. SVID_WORKPOINT_4_5 Snapshot 8 16 23 VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 SVID_WORKPOINT_4_5 Snapshot 3 24 26 Issue FAST ramp, instead of SLOW ramp. SVID_WORKPOINT_4_5 Snapshot 1 27 27 Issue DECAY ramp, instead of SLOW ramp. Only going down. SVID_WORKPOINT_4_5 Snapshot 1 28 28 reserved SVID_WORKPOINT_4_5 Snapshot 3 29 31 last SVID0 VR current reading - translated IMON version for VCCIA, in amps. U16.8.8 SVID_ICC_0_1 Snapshot 16 32 47 last SVID1 VR current reading - translated IMON version for VCCGT, in amps. U16.8.8 SVID_ICC_0_1 Snapshot 16 48 63 Groupname 0x8340 64 last SVID2 VR current reading - translated IMON version for VCCSA, in amps. U16.8.8 SVID_ICC_2_3 Snapshot 16 0 15 last SVID3 VR current reading - translated IMON version for VCCATOM, in amps. U16.8.8 SVID_ICC_2_3 Snapshot 16 16 31 last SVID4 VR current reading - translated IMON version for VCCL2, in amps. U16.8.8 SVID_ICC_4_5 Snapshot 16 32 47 last SVID5 VR current reading - translated IMON version for VCCL2, in amps. U16.8.8 SVID_ICC_4_5 Snapshot 16 48 63 Groupname 0x8348 64 IA Core C-state of BigCore0: C01: C13: C67: CRST IA_CLUSTER_CSTATES Snapshot 3 0 2 IA Core C-state of BigCore0: C01: C13: C67: CRST IA_CLUSTER_CSTATES Snapshot 3 3 5 IA Core C-state of BigCore0: C01: C13: C67: CRST IA_CLUSTER_CSTATES Snapshot 3 6 8 IA Core C-state of BigCore0: C01: C13: C67: CRST IA_CLUSTER_CSTATES Snapshot 3 9 11 IA Core C-state of Atom core0: C01: C13: C67: CRST IA_CLUSTER_CSTATES Snapshot 3 12 14 LLC/Ring C-state0: C0 - 01: C2 - 12: C3 - 23: C6 - 37: RST - 7 IA_CLUSTER_CSTATES Snapshot 3 24 26 Iceland cluster C-state0: C0 - 01: C2 - 12: C3 - 23: C6 - 37: RST - 7 IA_CLUSTER_CSTATES Snapshot 3 27 29 GT RC-state0: C01: C13: C67: CRST IA_CLUSTER_CSTATES Snapshot 3 30 32 reserved IA_CLUSTER_CSTATES Snapshot 31 33 63 Groupname 0x8350 64 CDYN level granted that CORE0 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX CDYN_LEVEL Snapshot 4 0 3 CDYN level granted that CORE1 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX CDYN_LEVEL Snapshot 4 4 7 CDYN level granted that CORE2 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX CDYN_LEVEL Snapshot 4 8 11 CDYN level granted that CORE3 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX CDYN_LEVEL Snapshot 4 12 15 CDYN level granted that Atom module0 can use.Grant long period protected CDYN index (factor index over the CDYN_INDEX) Long period is up to 100-200ns in Atom Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.LONG_CDYN_INDEX CDYN_LEVEL Snapshot 6 16 21 reserved CDYN_LEVEL Snapshot 42 22 63 Groupname 0x8358 64 Current PCH temperature SOC_TEMPERATURES Snapshot 8 0 7 Current reading from System Agent "always on" temperature sensor SOC_TEMPERATURES Snapshot 8 16 23 Current reading from IPU subsystem temperature sensor SOC_TEMPERATURES Snapshot 8 24 31 Current reading from Display subsystem temperature sensor SOC_TEMPERATURES Snapshot 8 32 39 Current reading from VPU subsystem temperature sensor SOC_TEMPERATURES Snapshot 8 40 47 Current reading from Media subsystem temperature sensor SOC_TEMPERATURES Snapshot 8 48 55 reserved SOC_TEMPERATURES Snapshot 8 56 63 Groupname 0x8360 64 Min temp across the core BIG_CORE_TEMPERATURE Snapshot 8 0 7 Max temp across the core BIG_CORE_TEMPERATURE Snapshot 8 8 15 Min temp across the core BIG_CORE_TEMPERATURE Snapshot 8 16 23 Max temp across the core BIG_CORE_TEMPERATURE Snapshot 8 24 31 Min temp across the core BIG_CORE_TEMPERATURE Snapshot 8 32 39 Max temp across the core BIG_CORE_TEMPERATURE Snapshot 8 40 47 Min temp across the core BIG_CORE_TEMPERATURE Snapshot 8 48 55 Max temp across the core BIG_CORE_TEMPERATURE Snapshot 8 56 63 Groupname 0x8368 64 Min temp across the atom module COMPUTE_TEMPERATURE Snapshot 8 0 7 Max temp across the atom module COMPUTE_TEMPERATURE Snapshot 8 8 15 reserved COMPUTE_TEMPERATURE Snapshot 8 24 31 LLC Min temp COMPUTE_TEMPERATURE Snapshot 8 32 39 LLC Max temp COMPUTE_TEMPERATURE Snapshot 8 40 47 Graphics Min temp COMPUTE_TEMPERATURE Snapshot 8 48 55 Graphics Max temp COMPUTE_TEMPERATURE Snapshot 8 56 63 Groupname 0x8370 64 Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. IA_SCALABILITY_CORE0_3 Snapshot 16 0 15 Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. IA_SCALABILITY_CORE0_3 Snapshot 16 16 31 Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. IA_SCALABILITY_CORE0_3 Snapshot 16 32 47 Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. IA_SCALABILITY_CORE0_3 Snapshot 16 48 63 Groupname 0x8378 64 Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. IA_SCALABILITY_CORE4_7 Snapshot 16 0 15 Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. IA_SCALABILITY_CORE4_7 Snapshot 16 16 31 Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. IA_SCALABILITY_CORE4_7 Snapshot 16 32 47 Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. IA_SCALABILITY_CORE4_7 Snapshot 16 48 63 Groupname 0x8380 64 P_alpha calculation. This represents the maximum allowed clock frequency on that core. IA_P_ALPHA_TARGET_CORE0_3 Snapshot 8 0 7 P_alpha calculation. This represents the maximum allowed clock frequency on that core. IA_P_ALPHA_TARGET_CORE0_3 Snapshot 8 8 15 P_alpha calculation. This represents the maximum allowed clock frequency on that core. IA_P_ALPHA_TARGET_CORE0_3 Snapshot 8 16 23 P_alpha calculation. This represents the maximum allowed clock frequency on that core. IA_P_ALPHA_TARGET_CORE0_3 Snapshot 8 24 31 P_alpha calculation. This represents the maximum allowed clock frequency on that core. IA_P_ALPHA_TARGET_CORE4_7 Snapshot 8 32 39 P_alpha calculation. This represents the maximum allowed clock frequency on that core. IA_P_ALPHA_TARGET_CORE4_7 Snapshot 8 40 47 P_alpha calculation. This represents the maximum allowed clock frequency on that core. IA_P_ALPHA_TARGET_CORE4_7 Snapshot 8 48 55 P_alpha calculation. This represents the maximum allowed clock frequency on that core. IA_P_ALPHA_TARGET_CORE4_7 Snapshot 8 56 63 Groupname 0x8388 64 Current autonomous frequency target for that IA Core IA_AUTONOMOUS_TARGET_CORE0_3 Snapshot 8 0 7 Current autonomous frequency target for that IA Core IA_AUTONOMOUS_TARGET_CORE0_3 Snapshot 8 8 15 Current autonomous frequency target for that IA Core IA_AUTONOMOUS_TARGET_CORE0_3 Snapshot 8 16 23 Current autonomous frequency target for that IA Core IA_AUTONOMOUS_TARGET_CORE0_3 Snapshot 8 24 31 Current autonomous frequency target for that IA Core IA_AUTONOMOUS_TARGET_CORE4_7 Snapshot 8 32 39 Current autonomous frequency target for that IA Core IA_AUTONOMOUS_TARGET_CORE4_7 Snapshot 8 40 47 Current autonomous frequency target for that IA Core IA_AUTONOMOUS_TARGET_CORE4_7 Snapshot 8 48 55 Current autonomous frequency target for that IA Core IA_AUTONOMOUS_TARGET_CORE4_7 Snapshot 8 56 63 Groupname 0x8390 64 Current efficient frequency target for that IA Core IA_EFFICIENT_FREQUENCY_CORE0_3 Snapshot 8 0 7 Current efficient frequency target for that IA Core IA_EFFICIENT_FREQUENCY_CORE0_3 Snapshot 8 8 15 Current efficient frequency target for that IA Core IA_EFFICIENT_FREQUENCY_CORE0_3 Snapshot 8 16 23 Current efficient frequency target for that IA Core IA_EFFICIENT_FREQUENCY_CORE0_3 Snapshot 8 24 31 Current efficient frequency target for that IA Core IA_EFFICIENT_FREQUENCY_CORE4_7 Snapshot 8 32 39 Current efficient frequency target for that IA Core IA_EFFICIENT_FREQUENCY_CORE4_7 Snapshot 8 40 47 Current efficient frequency target for that IA Core IA_EFFICIENT_FREQUENCY_CORE4_7 Snapshot 8 48 55 Current efficient frequency target for that IA Core IA_EFFICIENT_FREQUENCY_CORE4_7 Snapshot 8 56 63 Groupname 0x8398 64 Current GT Efficient P-state (used as the floor for autonomous control) GT_EFFICIENT_FREQUENCY Snapshot 8 0 7 reserved GT_EFFICIENT_FREQUENCY Snapshot 56 8 63 Groupname 0x83a0 64 Temperature of PECI sensor in 1/32 DegC PLATFORM_TEMPERATURE_EC Snapshot 16 0 15 Temperature of PECI sensor in 1/32 DegC PLATFORM_TEMPERATURE_EC Snapshot 16 16 31 Temperature of PECI sensor in 1/32 DegC PLATFORM_TEMPERATURE_EC Snapshot 16 32 47 reserved PLATFORM_TEMPERATURE_EC Snapshot 16 48 63 Groupname 0x83a8 64 Contains EC settings for sensor 0. PLATFORM_TEMPERATURE_EC_SETTINGS_0 Snapshot 32 0 31 Contains EC settings for sensor 1. PLATFORM_TEMPERATURE_EC_SETTINGS_0 Snapshot 32 32 63 Groupname 0x83b0 64 Contains EC settings for sensor 2. PLATFORM_TEMPERATURE_EC_SETTINGS_1 Snapshot 32 0 31 reserved PLATFORM_TEMPERATURE_EC_SETTINGS_1 Snapshot 32 32 63 Groupname 0x83b8 64 Contains MMIO settings for sensor 0. PLATFORM_TEMPERATURE_MMIO_SETTINGS_0 Snapshot 32 0 31 Contains MMIO settings for sensor 1. PLATFORM_TEMPERATURE_MMIO_SETTINGS_0 Snapshot 32 32 63 Groupname 0x83c0 64 Contains MMIO settings for sensor 2. PLATFORM_TEMPERATURE_MMIO_SETTINGS_1 Snapshot 32 0 31 reserved PLATFORM_TEMPERATURE_MMIO_SETTINGS_1 Snapshot 32 32 63 Groupname 0x83c8 64 Big core clock ratio, in units of 100MHz. AVG_FREQ_CORE0_3_RESERVED_83C8 Snapshot 8 0 7 Big core clock ratio, in units of 100MHz. AVG_FREQ_CORE0_3_RESERVED_83C8 Snapshot 8 8 15 Big core clock ratio, in units of 100MHz. AVG_FREQ_CORE0_3_RESERVED_83C8 Snapshot 8 16 23 Big core clock ratio, in units of 100MHz. AVG_FREQ_CORE0_3_RESERVED_83C8 Snapshot 8 24 31 Atom core clock ratio, in units of 100MHz. AVG_FREQ_CORE4_7_RESERVED_83CC Snapshot 8 32 39 Atom core clock ratio, in units of 100MHz. AVG_FREQ_CORE4_7_RESERVED_83CC Snapshot 8 40 47 Atom core clock ratio, in units of 100MHz. AVG_FREQ_CORE4_7_RESERVED_83CC Snapshot 8 48 55 Atom core clock ratio, in units of 100MHz. AVG_FREQ_CORE4_7_RESERVED_83CC Snapshot 8 56 63 Groupname 0x83d0 64 reserved SMPL_RESERVED_0_83D0 Snapshot 64 0 63 Groupname 0x83d8 64 reserved SMPL_RESERVED_1_to_69[0] Snapshot 64 0 63 Groupname 0x83e0 64 reserved SMPL_RESERVED_1_to_69[1] Snapshot 64 0 63 Groupname 0x83e8 64 reserved SMPL_RESERVED_1_to_69[2] Snapshot 64 0 63 Groupname 0x83f0 64 reserved SMPL_RESERVED_1_to_69[3] Snapshot 64 0 63 Groupname 0x83f8 64 reserved SMPL_RESERVED_1_to_69[4] Snapshot 64 0 63 Groupname 0x8400 64 reserved SMPL_RESERVED_1_to_69[5] Snapshot 64 0 63 Groupname 0x8408 64 reserved SMPL_RESERVED_1_to_69[6] Snapshot 64 0 63 Groupname 0x8410 64 reserved SMPL_RESERVED_1_to_69[7] Snapshot 64 0 63 Groupname 0x8418 64 reserved SMPL_RESERVED_1_to_69[8] Snapshot 64 0 63 Groupname 0x8420 64 reserved SMPL_RESERVED_1_to_69[9] Snapshot 64 0 63 Groupname 0x8428 64 reserved SMPL_RESERVED_1_to_69[10] Snapshot 64 0 63 Groupname 0x8430 64 reserved SMPL_RESERVED_1_to_69[11] Snapshot 64 0 63 Groupname 0x8438 64 reserved SMPL_RESERVED_1_to_69[12] Snapshot 64 0 63 Groupname 0x8440 64 reserved SMPL_RESERVED_1_to_69[13] Snapshot 64 0 63 Groupname 0x8448 64 reserved SMPL_RESERVED_1_to_69[14] Snapshot 64 0 63 Groupname 0x8450 64 reserved SMPL_RESERVED_1_to_69[15] Snapshot 64 0 63 Groupname 0x8458 64 reserved SMPL_RESERVED_1_to_69[16] Snapshot 64 0 63 Groupname 0x8460 64 reserved SMPL_RESERVED_1_to_69[17] Snapshot 64 0 63 Groupname 0x8468 64 reserved SMPL_RESERVED_1_to_69[18] Snapshot 64 0 63 Groupname 0x8470 64 reserved SMPL_RESERVED_1_to_69[19] Snapshot 64 0 63 Groupname 0x8478 64 reserved SMPL_RESERVED_1_to_69[20] Snapshot 64 0 63 Groupname 0x8480 64 reserved SMPL_RESERVED_1_to_69[21] Snapshot 64 0 63 Groupname 0x8488 64 reserved SMPL_RESERVED_1_to_69[22] Snapshot 64 0 63 Groupname 0x8490 64 reserved SMPL_RESERVED_1_to_69[23] Snapshot 64 0 63 Groupname 0x8498 64 reserved SMPL_RESERVED_1_to_69[24] Snapshot 64 0 63 Groupname 0x84a0 64 reserved SMPL_RESERVED_1_to_69[25] Snapshot 64 0 63 Groupname 0x84a8 64 reserved SMPL_RESERVED_1_to_69[26] Snapshot 64 0 63 Groupname 0x84b0 64 reserved SMPL_RESERVED_1_to_69[27] Snapshot 64 0 63 Groupname 0x84b8 64 reserved SMPL_RESERVED_1_to_69[28] Snapshot 64 0 63 Groupname 0x84c0 64 reserved SMPL_RESERVED_1_to_69[29] Snapshot 64 0 63 Groupname 0x84c8 64 reserved SMPL_RESERVED_1_to_69[30] Snapshot 64 0 63 Groupname 0x84d0 64 reserved SMPL_RESERVED_1_to_69[31] Snapshot 64 0 63 Groupname 0x84d8 64 reserved SMPL_RESERVED_1_to_69[32] Snapshot 64 0 63 Groupname 0x84e0 64 reserved SMPL_RESERVED_1_to_69[33] Snapshot 64 0 63 Groupname 0x84e8 64 reserved SMPL_RESERVED_1_to_69[34] Snapshot 64 0 63 Groupname 0x84f0 64 reserved SMPL_RESERVED_1_to_69[35] Snapshot 64 0 63 Groupname 0x84f8 64 reserved SMPL_RESERVED_1_to_69[36] Snapshot 64 0 63 Groupname 0x8500 64 reserved SMPL_RESERVED_1_to_69[37] Snapshot 64 0 63 Groupname 0x8508 64 reserved SMPL_RESERVED_1_to_69[38] Snapshot 64 0 63 Groupname 0x8510 64 reserved SMPL_RESERVED_1_to_69[39] Snapshot 64 0 63 Groupname 0x8518 64 reserved SMPL_RESERVED_1_to_69[40] Snapshot 64 0 63 Groupname 0x8520 64 reserved SMPL_RESERVED_1_to_69[41] Snapshot 64 0 63 Groupname 0x8528 64 reserved SMPL_RESERVED_1_to_69[42] Snapshot 64 0 63 Groupname 0x8530 64 reserved SMPL_RESERVED_1_to_69[43] Snapshot 64 0 63 Groupname 0x8538 64 reserved SMPL_RESERVED_1_to_69[44] Snapshot 64 0 63 Groupname 0x8540 64 reserved SMPL_RESERVED_1_to_69[45] Snapshot 64 0 63 Groupname 0x8548 64 reserved SMPL_RESERVED_1_to_69[46] Snapshot 64 0 63 Groupname 0x8550 64 reserved SMPL_RESERVED_1_to_69[47] Snapshot 64 0 63 Groupname 0x8558 64 reserved SMPL_RESERVED_1_to_69[48] Snapshot 64 0 63 Groupname 0x8560 64 reserved SMPL_RESERVED_1_to_69[49] Snapshot 64 0 63 Groupname 0x8568 64 reserved SMPL_RESERVED_1_to_69[50] Snapshot 64 0 63 Groupname 0x8570 64 reserved SMPL_RESERVED_1_to_69[51] Snapshot 64 0 63 Groupname 0x8578 64 reserved SMPL_RESERVED_1_to_69[52] Snapshot 64 0 63 Groupname 0x8580 64 reserved SMPL_RESERVED_1_to_69[53] Snapshot 64 0 63 Groupname 0x8588 64 reserved SMPL_RESERVED_1_to_69[54] Snapshot 64 0 63 Groupname 0x8590 64 reserved SMPL_RESERVED_1_to_69[55] Snapshot 64 0 63 Groupname 0x8598 64 reserved SMPL_RESERVED_1_to_69[56] Snapshot 64 0 63 Groupname 0x85a0 64 reserved SMPL_RESERVED_1_to_69[57] Snapshot 64 0 63 Groupname 0x85a8 64 reserved SMPL_RESERVED_1_to_69[58] Snapshot 64 0 63 Groupname 0x85b0 64 reserved SMPL_RESERVED_1_to_69[59] Snapshot 64 0 63 Groupname 0x85b8 64 reserved SMPL_RESERVED_1_to_69[60] Snapshot 64 0 63 Groupname 0x85c0 64 reserved SMPL_RESERVED_1_to_69[61] Snapshot 64 0 63 Groupname 0x85c8 64 reserved SMPL_RESERVED_1_to_69[62] Snapshot 64 0 63 Groupname 0x85d0 64 reserved SMPL_RESERVED_1_to_69[63] Snapshot 64 0 63 Groupname 0x85d8 64 reserved SMPL_RESERVED_1_to_69[64] Snapshot 64 0 63 Groupname 0x85e0 64 reserved SMPL_RESERVED_1_to_69[65] Snapshot 64 0 63 Groupname 0x85e8 64 reserved SMPL_RESERVED_1_to_69[66] Snapshot 64 0 63 Groupname 0x85f0 64 reserved SMPL_RESERVED_1_to_69[67] Snapshot 64 0 63 Groupname 0x85f8 64 reserved SMPL_RESERVED_1_to_69[68] Snapshot 64 0 63 Groupname 0x8600 64 slow limit THERM has limited performance for CCP0 PERF_LIMIT_THERM_CCP_RESIDENCY_0 Counter 64 0 63 Groupname 0x8608 64 slow limit THERM has limited performance for CCP1 PERF_LIMIT_THERM_CCP_RESIDENCY_1 Counter 64 0 63 Groupname 0x8610 64 slow limit THERM has limited performance for CCP2 PERF_LIMIT_THERM_CCP_RESIDENCY_2 Counter 64 0 63 Groupname 0x8618 64 slow limit THERM has limited performance for CCP3 PERF_LIMIT_THERM_CCP_RESIDENCY_3 Counter 64 0 63 Groupname 0x8620 64 slow limit THERM has limited performance for CCP4 PERF_LIMIT_THERM_CCP_RESIDENCY_4 Counter 64 0 63 Groupname 0x8628 64 slow limit THERM has limited performance for CLR PERF_LIMIT_THERM_CLR_RESIDENCY Counter 64 0 63 Groupname 0x8630 64 slow limit THERM has limited performance for GT. PERF_LIMIT_THERM_GT_RESIDENCY Counter 64 0 63 Groupname 0x8638 64 slow limit THERM has limited performance for IPU. PERF_LIMIT_THERM_IPU_RESIDENCY Counter 64 0 63 Groupname 0x8640 64 slow limit THERM has limited performance for VPU. PERF_LIMIT_THERM_VPU_RESIDENCY Counter 64 0 63 Groupname 0x8648 64 slow limit THERM has limited performance for Media. PERF_LIMIT_THERM_MEDIA_RESIDENCY Counter 64 0 63 Groupname 0x8650 64 slow limit POWER has limited performance for CCP0 PERF_LIMIT_POWER_CCP_RESIDENCY_0 Counter 64 0 63 Groupname 0x8658 64 slow limit POWER has limited performance for CCP1 PERF_LIMIT_POWER_CCP_RESIDENCY_1 Counter 64 0 63 Groupname 0x8660 64 slow limit POWER has limited performance for CCP2 PERF_LIMIT_POWER_CCP_RESIDENCY_2 Counter 64 0 63 Groupname 0x8668 64 slow limit POWER has limited performance for CCP3 PERF_LIMIT_POWER_CCP_RESIDENCY_3 Counter 64 0 63 Groupname 0x8670 64 slow limit POWER has limited performance for CCP4 PERF_LIMIT_POWER_CCP_RESIDENCY_4 Counter 64 0 63 Groupname 0x8678 64 slow limit POWER has limited performance for CLR PERF_LIMIT_POWER_CLR_RESIDENCY Counter 64 0 63 Groupname 0x8680 64 slow limit POWER has limited performance for GT PERF_LIMIT_POWER_GT_RESIDENCY Counter 64 0 63 Groupname 0x8688 64 slow limit POWER has limited performance for Media PERF_LIMIT_POWER_MEDIA_RESIDENCY Counter 64 0 63 Groupname 0x8690 64 slow limit POWER has limited performance for VPU PERF_LIMIT_POWER_VPU_RESIDENCY Counter 64 0 63 Groupname 0x8698 64 slow limit EDP has limited performance for CCP0 PERF_LIMIT_EDP_CCP_RESIDENCY_0 Counter 64 0 63 Groupname 0x86a0 64 slow limit EDP has limited performance for CCP1 PERF_LIMIT_EDP_CCP_RESIDENCY_1 Counter 64 0 63 Groupname 0x86a8 64 slow limit EDP has limited performance for CCP2 PERF_LIMIT_EDP_CCP_RESIDENCY_2 Counter 64 0 63 Groupname 0x86b0 64 slow limit EDP has limited performance for CCP3 PERF_LIMIT_EDP_CCP_RESIDENCY_3 Counter 64 0 63 Groupname 0x86b8 64 slow limit EDP has limited performance for CCP4 PERF_LIMIT_EDP_CCP_RESIDENCY_4 Counter 64 0 63 Groupname 0x86c0 64 slow limit EDP has limited performance for CLR PERF_LIMIT_EDP_CLR_RESIDENCY Counter 64 0 63 Groupname 0x86c8 64 slow limit EDP has limited performance for GT PERF_LIMIT_EDP_GT_RESIDENCY Counter 64 0 63 Groupname 0x86d0 64 slow limit EDP has limited performance for Media PERF_LIMIT_EDP_MEDIA_RESIDENCY Counter 64 0 63 Groupname 0x86d8 64 slow limit EDP has limited performance for VPU PERF_LIMIT_EDP_VPU_RESIDENCY Counter 64 0 63 Groupname 0x86e0 64 slow limit OTHER has limited performance for CCP0 PERF_LIMIT_OTHER_CCP_RESIDENCY_0 Counter 64 0 63 Groupname 0x86e8 64 slow limit OTHER has limited performance for CCP1 PERF_LIMIT_OTHER_CCP_RESIDENCY_1 Counter 64 0 63 Groupname 0x86f0 64 slow limit OTHER has limited performance for CCP2 PERF_LIMIT_OTHER_CCP_RESIDENCY_2 Counter 64 0 63 Groupname 0x86f8 64 slow limit OTHER has limited performance for CCP3 PERF_LIMIT_OTHER_CCP_RESIDENCY_3 Counter 64 0 63 Groupname 0x8700 64 slow limit OTHER has limited performance for CCP4 PERF_LIMIT_OTHER_CCP_RESIDENCY_4 Counter 64 0 63 Groupname 0x8708 64 slow limit OTHER has limited performance for CLR PERF_LIMIT_OTHER_CLR_RESIDENCY Counter 64 0 63 Groupname 0x8710 64 slow limit OTHER has limited performance for GT PERF_LIMIT_OTHER_GT_RESIDENCY Counter 64 0 63 Groupname 0x8718 64 slow limit OTHER has limited performance for Media PERF_LIMIT_OTHER_MEDIA_RESIDENCY Counter 64 0 63 Groupname 0x8720 64 slow limit OTHER has limited performance for VPU PERF_LIMIT_OTHER_VPU_RESIDENCY Counter 64 0 63 Groupname 0x8728 64 prochot assertions. PROCHOT_RESIDENCY Counter 64 0 63 Groupname 0x8730 64 VCCGT VR asserted VRHOT. VCCIA_VRHOT_RESIDENCY Counter 64 0 63 Groupname 0x8738 64 VCCGT VR asserted VRHOT. VCCGT_VRHOT_RESIDENCY Counter 64 0 63 Groupname 0x8740 64 VCCAUX VR asserted VRHOT. VCCSA_VRHOT_RESIDENCY Counter 64 0 63 Groupname 0x8748 64 SOC was PL3 limited PL3_LIMITED_RESIDENCY Counter 64 0 63 Groupname 0x8750 64 SOC was PL2 limited PL2_LIMITED_RESIDENCY Counter 64 0 63 Groupname 0x8758 64 SOC was PL1 limited PL1_LIMITED_RESIDENCY Counter 64 0 63 Groupname 0x8760 64 SOC was Psys PL3 limited PSYS_PL3_LIMITED_RESIDENCY Counter 64 0 63 Groupname 0x8768 64 SOC was Psys PL2 limited PSYS_PL2_LIMITED_RESIDENCY Counter 64 0 63 Groupname 0x8770 64 SOC was Psys PL1 limited PSYS_PL1_LIMITED_RESIDENCY Counter 64 0 63 Groupname 0x8778 64 GT RC6 GT_RC6_RESIDENCY Counter 64 0 63 Groupname 0x8780 64 Media C6 residency MEDIA_C6_RESIDENCY Counter 64 0 63 Groupname 0x8788 64 IPU IS C6// IPU Powerdown Telemetry (IS/PS Residency Counters)// --------------------------------------------------// - If the above WP issue caused a IS or PS powerdown, we want to detect that transition// and trigger the IS/PS C6 Residency Counters to resume counting//// - Note that the above WP is the only one that can cause a powerdown since both IS and PS poweroff// are represented by ratio (or divisor) equal to 0, which will get captured by the Min WP above.// ------------------------------------------------------------------------------------------------- IPU_IS_C6_RESIDENCY Counter 64 0 63 Groupname 0x8790 64 IPU PS C6// IPU Powerdown Telemetry (IS/PS Residency Counters)// --------------------------------------------------// - If the above WP issue caused a IS or PS powerdown, we want to detect that transition// and trigger the IS/PS C6 Residency Counters to resume counting//// - Note that the above WP is the only one that can cause a powerdown since both IS and PS poweroff// are represented by ratio (or divisor) equal to 0, which will get captured by the Min WP above.// ------------------------------------------------------------------------------------------------- IPU_PS_C6_RESIDENCY Counter 64 0 63 Groupname 0x8798 64 reserved CNTR_RESERVED_8798 Counter 64 0 63 Groupname 0x87a0 64 reserved CNTR_RESERVED_87A0 Counter 64 0 63 Groupname 0x87a8 64 reserved CNTR_RESERVED_87A8 Counter 64 0 63 Groupname 0x87b0 64 reserved CNTR_RESERVED_87B0 Counter 64 0 63 Groupname 0x87b8 64 reserved CNTR_RESERVED_87B8 Counter 64 0 63 Groupname 0x87c0 64 reserved CNTR_RESERVED_87C0 Counter 64 0 63 Groupname 0x87c8 64 C0 residency counter for Core0 C0_RESIDENCY_CORE0 Counter 64 0 63 Groupname 0x87d0 64 C0 residency counter for Core1 C0_RESIDENCY_CORE1 Counter 64 0 63 Groupname 0x87d8 64 C0 residency counter for Core2 C0_RESIDENCY_CORE2 Counter 64 0 63 Groupname 0x87e0 64 C0 residency counter for Core3 C0_RESIDENCY_CORE3 Counter 64 0 63 Groupname 0x87e8 64 C0 residency counter for Core4 C0_RESIDENCY_CORE4 Counter 64 0 63 Groupname 0x87f0 64 C0 residency counter for Core5 C0_RESIDENCY_CORE5 Counter 64 0 63 Groupname 0x87f8 64 C0 residency counter for Core6 C0_RESIDENCY_CORE6 Counter 64 0 63 Groupname 0x8800 64 C0 residency counter for Core7 C0_RESIDENCY_CORE7 Counter 64 0 63 Groupname 0x8808 64 Transition counter for when slow limit THERM has limited performance for CCP0 PERF_LIMIT_THERM_CCP_COUNTER_0 Counter 32 0 31 Transition counter for when slow limit THERM has limited performance for CCP1 PERF_LIMIT_THERM_CCP_COUNTER_1 Counter 32 32 63 Groupname 0x8810 64 Transition counter for when slow limit THERM has limited performance for CCP2 PERF_LIMIT_THERM_CCP_COUNTER_2 Counter 32 0 31 Transition counter for when slow limit THERM has limited performance for CCP3 PERF_LIMIT_THERM_CCP_COUNTER_3 Counter 32 32 63 Groupname 0x8818 64 Transition counter for when slow limit THERM has limited performance for CCP4 PERF_LIMIT_THERM_CCP_COUNTER_4 Counter 32 0 31 Transition counter for when slow limit THERM has limited performance for CLR PERF_LIMIT_THERM_CLR_COUNTER Counter 32 32 63 Groupname 0x8820 64 Transition counter for when slow limit THERM has limited performance for GT PERF_LIMIT_THERM_GT_COUNTER Counter 32 0 31 Transition counter for when slow limit THERM has limited performance for VPU PERF_LIMIT_THERM_VPU_COUNTER Counter 32 32 63 Groupname 0x8828 64 Transition counter for when slow limit THERM has limited performance for Media PERF_LIMIT_THERM_MEDIA_COUNTER Counter 32 0 31 Transition counter for when slow limit POWER has limited performance for CCP0 PERF_LIMIT_POWER_CCP_COUNTER_0 Counter 32 32 63 Groupname 0x8830 64 Transition counter for when slow limit POWER has limited performance for CCP1 PERF_LIMIT_POWER_CCP_COUNTER_1 Counter 32 0 31 Transition counter for when slow limit POWER has limited performance for CCP2 PERF_LIMIT_POWER_CCP_COUNTER_2 Counter 32 32 63 Groupname 0x8838 64 Transition counter for when slow limit POWER has limited performance for CCP3 PERF_LIMIT_POWER_CCP_COUNTER_3 Counter 32 0 31 Transition counter for when slow limit POWER has limited performance for CCP4 PERF_LIMIT_POWER_CCP_COUNTER_4 Counter 32 32 63 Groupname 0x8840 64 Transition counter for when slow limit POWER has limited performance for CLR PERF_LIMIT_POWER_CLR_COUNTER Counter 32 0 31 Transition counter for when slow limit POWER has limited performance for GT PERF_LIMIT_POWER_GT_COUNTER Counter 32 32 63 Groupname 0x8848 64 Transition counter for when slow limit POWER has limited performance for Media PERF_LIMIT_POWER_MEDIA_COUNTER Counter 32 0 31 Transition counter for when slow limit POWER has limited performance for VPU PERF_LIMIT_POWER_VPU_COUNTER Counter 32 32 63 Groupname 0x8850 64 Transition counter for when slow limit EDP has limited performance for CCP0 PERF_LIMIT_EDP_CCP_COUNTER_0 Counter 32 0 31 Transition counter for when slow limit EDP has limited performance for CCP1 PERF_LIMIT_EDP_CCP_COUNTER_1 Counter 32 32 63 Groupname 0x8858 64 Transition counter for when slow limit EDP has limited performance for CCP2 PERF_LIMIT_EDP_CCP_COUNTER_2 Counter 32 0 31 Transition counter for when slow limit EDP has limited performance for CCP3 PERF_LIMIT_EDP_CCP_COUNTER_3 Counter 32 32 63 Groupname 0x8860 64 Transition counter for when slow limit EDP has limited performance for CCP4 PERF_LIMIT_EDP_CCP_COUNTER_4 Counter 32 0 31 Transition counter for when slow limit EDP has limited performance for CLR PERF_LIMIT_EDP_CLR_COUNTER Counter 32 32 63 Groupname 0x8868 64 Transition counter for when slow limit EDP has limited performance for GT. PERF_LIMIT_EDP_GT_COUNTER Counter 32 0 31 Transition counter for when slow limit EDP has limited performance for Media PERF_LIMIT_EDP_MEDIA_COUNTER Counter 32 32 63 Groupname 0x8870 64 Transition counter for when slow limit EDP has limited performance for VPU PERF_LIMIT_EDP_VPU_COUNTER Counter 32 0 31 Transition counter for when slow limit OTHER has limited performance for CCP0 PERF_LIMIT_OTHER_CCP_COUNTER_0 Counter 32 32 63 Groupname 0x8878 64 Transition counter for when slow limit OTHER has limited performance for CCP1 PERF_LIMIT_OTHER_CCP_COUNTER_1 Counter 32 0 31 Transition counter for when slow limit OTHER has limited performance for CCP2 PERF_LIMIT_OTHER_CCP_COUNTER_2 Counter 32 32 63 Groupname 0x8880 64 Transition counter for when slow limit OTHER has limited performance for CCP3 PERF_LIMIT_OTHER_CCP_COUNTER_3 Counter 32 0 31 Transition counter for when slow limit OTHER has limited performance for CCP4 PERF_LIMIT_OTHER_CCP_COUNTER_4 Counter 32 32 63 Groupname 0x8888 64 Transition counter for when slow limit OTHER has limited performance for CLR. PERF_LIMIT_OTHER_CLR_COUNTER Counter 32 0 31 Transition counter for when slow limit OTHER has limited performance for GT. PERF_LIMIT_OTHER_GT_COUNTER Counter 32 32 63 Groupname 0x8890 64 Transition counter for when slow limit OTHER has limited performance for Media. PERF_LIMIT_OTHER_MEDIA_COUNTER Counter 32 0 31 Transition counter for when slow limit OTHER has limited performance for VPU. PERF_LIMIT_OTHER_VPU_COUNTER Counter 32 32 63 Groupname 0x8898 64 Energy reported by the Psys VR PSYS_ENERGY Counter 64 0 63 Groupname 0x88a0 64 Total package energy including Compute+GT+PCH, (should be the same as MSR package_energy_status) PACKAGE_ENERGY Counter 64 0 63 Groupname 0x88a8 64 IA VR energy (should be same as PRIMARY_PLANE_ENERGY_STATUS MSR) VCCIA_ENERGY Counter 64 0 63 Groupname 0x88b0 64 GT VR energy (should be same as SECONDARY_PLANE_ENERGY_STATUS) VCCGT_ENERGY Counter 64 0 63 Groupname 0x88b8 64 Energy estimated by Pcode using utilization factor from the VPU. Format is U18.14. https://docs.intel.com/documents/pm_doc/src/lnl/IP%20Integration/VPU%20PM%20HAS/VPU%20PM%20HAS.html#scalability-activity-factor VPU_ENERGY Counter 64 0 63 Groupname 0x88c0 64 Total I/O read bandwidth for Display (VC1) DISPLAY_IO_READ_BANDWIDTH Counter 64 0 63 Groupname 0x88c8 64 ReservedTotal I/O write bandwidth for display** NOT IMPLEMENTED ** DISPLAY_IO_WRITE_BANDWIDTH Counter 64 0 63 Groupname 0x88d0 64 ReservedTotal display VC1 (non-coherent read) bandwidth.** NOT IMPLEMENTED **~same as DISPLAY_IO_READ_BANDWIDTH DISPLAY_VC1_BANDWIDTH Counter 64 0 63 Groupname 0x88d8 64 Reserved. Moved to SoC die IO_WRITE_BANDWIDTH_IP0_3 Counter 64 0 63 Groupname 0x88e0 64 Reserved. Moved to SoC die IO_READ_BANDWIDTH_IP0_3 Counter 64 0 63 Groupname 0x88e8 64 Mufasa hit traffic MUFASA_HIT_BW Counter 64 0 63 Groupname 0x88f0 64 Mufasa miss traffic MUFASA_MISS_BW Counter 64 0 63 Groupname 0x88f8 64 HBO0 read and write traffic HBO0_BW Counter 64 0 63 Groupname 0x8900 64 HBO1 read and write traffic HBO1_BW Counter 64 0 63 Groupname 0x8908 64 SANTA (CCF) read traffic SANTA_BW_READ Counter 64 0 63 Groupname 0x8910 64 SANTA (CCF) write traffic SANTA_BW_WRITE Counter 64 0 63 Groupname 0x8918 64 IDI (Iceland) read traffic IDIBR_BW_READ Counter 64 0 63 Groupname 0x8920 64 IDI (Iceland) write traffic IDIBR_BW_WRITE Counter 64 0 63 Groupname 0x8928 64 Total MemSWITCH (previously I/O) read bandwidth. NOC_BW_MEMSWITCH_READ Counter 64 0 63 Groupname 0x8930 64 Total MemSWITCH (previously I/O) write bandwidth. NOC_BW_MEMSWITCH_WRITE Counter 64 0 63 Groupname 0x8938 64 Main NOC D2D read traffic NOC_BW_D2D_READ Counter 64 0 63 Groupname 0x8940 64 Main NOC D2D write traffic NOC_BW_D2D_WRITE Counter 64 0 63 Groupname 0x8948 64 Main NOC GT read traffic NOC_BW_GT_READ Counter 64 0 63 Groupname 0x8950 64 Main NOC GT write traffic NOC_BW_GT_WRITE Counter 64 0 63 Groupname 0x8958 64 HW counter disabled by default. Can be enabled through tap NOC_BW_MEDIA_READ Counter 64 0 63 Groupname 0x8960 64 HW counter disabled by default. Can be enabled through tap NOC_BW_MEDIA_WRITE Counter 64 0 63 Groupname 0x8968 64 HW counter disabled by default. Can be enabled through tap NOC_BW_IPU_READ Counter 64 0 63 Groupname 0x8970 64 HW counter disabled by default. Can be enabled through tap NOC_BW_IPU_WRITE Counter 64 0 63 Groupname 0x8978 64 CCE0 read and write traffic. HW counter disabled by default. Can be enabled through tap NOC_BW_CCE0 Counter 64 0 63 Groupname 0x8980 64 CCE1 read and write traffic. HW counter disabled by default. Can be enabled through tap NOC_BW_CCE1 Counter 64 0 63 Groupname 0x8988 64 ReservedDE has a joint counter for 2 linksValue is same as DISPLAY_IO_READ_BANDWIDTH NOC_BW_DISP0 Counter 64 0 63 Groupname 0x8990 64 ReservedDE has a joint counter for 2 linksValue is same as DISPLAY_IO_READ_BANDWIDTH NOC_BW_DISP1 Counter 64 0 63 Groupname 0x8998 64 Reserved. Covered in VPU_MEMORY_BW NOC_BW_VPU0 Counter 64 0 63 Groupname 0x89a0 64 Reserved. Covered in VPU_MEMORY_BW NOC_BW_VPU1 Counter 64 0 63 Groupname 0x89a8 64 reserved CNTR_RESERVED_89A8 Counter 64 0 63 Groupname 0x89b0 64 reserved CNTR_RESERVED_89B0 Counter 64 0 63 Groupname 0x89b8 64 reserved CNTR_RESERVED_89B8 Counter 64 0 63 Groupname 0x89c0 64 reserved CNTR_RESERVED_89C0 Counter 64 0 63 Groupname 0x89c8 64 prochot assertions. PROCHOT_COUNTER Counter 32 0 31 counts VCCIA VR asserted VRHOT. VCCIA_VRHOT_COUNTER Counter 32 32 63 Groupname 0x89d0 64 counts VCCGT VR asserted VRHOT. VCCGT_VRHOT_COUNTER Counter 32 0 31 counts VCCSA VR asserted VRHOT. VCCSA_VRHOT_COUNTER Counter 32 32 63 Groupname 0x89d8 64 SOC was PL3 limited PL3_LIMITED_COUNTER Counter 32 0 31 SOC was PL2 limited PL2_LIMITED_COUNTER Counter 32 32 63 Groupname 0x89e0 64 SOC was PL1 limited PL1_LIMITED_COUNTER Counter 32 0 31 SOC was Psys PL3 limited PSYS_PL3_LIMITED_COUNTER Counter 32 32 63 Groupname 0x89e8 64 SOC was Psys PL2 limited PSYS_PL2_LIMITED_COUNTER Counter 32 0 31 SOC was Psys PL1 limited PSYS_PL1_LIMITED_COUNTER Counter 32 32 63 Groupname 0x89f0 64 GT RC6 state transition counter GT_RC6_COUNTER Counter 32 0 31 Media C6 state transition counter MEDIA_C6_COUNTER Counter 32 32 63 Groupname 0x89f8 64 IPU IS C6 state transition counter IPU_IS_C6_COUNTER Counter 32 0 31 IPU PS C6 state transition counter IPU_PS_C6_COUNTER Counter 32 32 63 Groupname 0x8a00 64 reserved CNTR_RESERVED_8A00 Counter 64 0 63 Groupname 0x8a08 64 reserved CNTR_RESERVED_8A08 Counter 64 0 63 Groupname 0x8a10 64 reserved CNTR_RESERVED_8A10 Counter 64 0 63 Groupname 0x8a18 64 This register increments every SBCLK cycle that MC0 is in self refresh MC_IN_SR_COUNT_0 Counter 64 0 63 Groupname 0x8a20 64 This register increments every SBCLK cycle that MC1 is in self refresh MC_IN_SR_COUNT_1 Counter 64 0 63 Groupname 0x8a28 64 MC0 sends count Enable indications: 4 signals: two ChannelsSingle counter counts for both Channels, stands for channels 0-1Details:This register increments every SBCLK cycle that CKE of all ranks in a channel is low and all ranks are not yet in self-refresh or deep self-refresh. It will roll over to 0 when at the limit. Note: The counter will count CKE off cycles and increment even for an unpopulated channel. Software needs to detect if a channel is unpopulated (by seeing if MC_Init_State_0_0_0_MCHBAR.Rank_occupancy = 0x0) and not consume the value in this counter if channel is unpopulated.MC0_CKE_POWER_DOWN_COUNT = MC0_gv0+MC0_gv1+MC0_gv2+MC0_gv3 // stands for channels 0-1 MC0_CKE_POWER_DOWN_COUNT Counter 64 0 63 Groupname 0x8a30 64 MC1 sends count Enable indications: 4 signals: two ChannelsSingle counter counts for both Channels, stands for channels 2-3Details:This register increments every SBCLK cycle that CKE of all ranks in a channel is low and all ranks are not yet in self-refresh or deep self-refresh. It will roll over to 0 when at the limit. Note: The counter will count CKE off cycles and increment even for an unpopulated channel. Software needs to detect if a channel is unpopulated (by seeing if MC_Init_State_0_0_0_MCHBAR.Rank_occupancy = 0x0) and not consume the value in this counter if channel is unpopulated.MC1_CKE_POWER_DOWN_COUNT = MC1_gv0+MC1_gv1+MC1_gv2+MC1_gv3 // stands for channels 2-3 MC1_CKE_POWER_DOWN_COUNT Counter 64 0 63 Groupname 0x8a38 64 reserved CNTR_RESERVED_8A38 Counter 64 0 63 Groupname 0x8a40 64 reserved CNTR_RESERVED_8A40 Counter 64 0 63 Groupname 0x8a48 64 increments the counter every sideband clock when CMI PLL is locked. MC_ON_RATIO Counter 64 0 63 Groupname 0x8a50 64 increments the counter every sideband clock by '1' when CMI PLL is locked. Time_MC_ON = counter * SBclk_period MC_ON_TIME Counter 64 0 63 Groupname 0x8a58 64 Counts total MC writes. Virtual bandwidth counter based on PWM_WRDATA bulkcr sample.i.e TOTAL_WRITE_BANDWIDTH = total PWM_WRDATA_COUNT_0_0_0_MCHBAR (per MC, channel, sub-channel) TOTAL_WRITE_BANDWIDTH Counter 64 0 63 Groupname 0x8a60 64 Counts total MC reads. Virtual bandwidth counter based on PWM_RDDATA bulkcr sample.i.e TOTAL_READ_BANDWIDTH = total PWM_RDDATA_COUNT_0_0_0_MCHBAR (per MC, channel, sub-channel) TOTAL_READ_BANDWIDTH Counter 64 0 63 Groupname 0x8a68 64 The counter value is incremented as a function of the number of cores that reside in C0 and active. If N cores are simultaneously in C0, then the number of "clock ticks" that are incremented is N. Counts in XTAL units. Should be same as MSR ANY_CORE_C0 0x659. IO_PKG_IA_C0_ANY_SUM Counter 64 0 63 Groupname 0x8a70 64 This counter increments whenever GT slices or unslices are ON and in C0 state. Counter rate is the Xtal clock. Should be same as MSR ANY_GFXE_C0 0x65a IO_PKG_GT_C0_ANY Counter 64 0 63 Groupname 0x8a78 64 This counter increments whenever GT slices or unslices are active and in C0 state and in overlap with one of the IA cores that is active and in C0. Counts in XTAL units. Should be same as MSR CORE_GFXE_OVERLAP_C0 0x65b IO_PKG_GT_AND_IA_OVERLAP Counter 64 0 63 Groupname 0x8a80 64 Follow exactly the IO_PKG_GT_C0_ANY_SLICE. The only change is that they do +N (GT ratio) instead of +1 on the relevant clock edge. Counter rate is in Xtal Clock.PKG_GT_C0_ANY_SLICE Counts clocks that any GT slice is active. Reference clock is XTAL. IO_PKG_GT_C0_ANY_RATIO Counter 64 0 63 Groupname 0x8a88 64 This counter increments whenever MEDIA slices or unslices are ON and in C0 state. Counter rate is the Xtal clock. IO_PKG_MEDIA_C0_ANY Counter 64 0 63 Groupname 0x8a90 64 Follow exactly the PKG_MEDIA_C0_ANY_SLICE. The only change is that they do +N (media ratio) instead of +1 on the relevant clock edge.PKG_MEDIA_C0_ANY_SLICE Counts clocks that any Media slice is active.Counter rate is in Xtal Clock. IO_PKG_MEDIA_C0_ANY_RATIO Counter 64 0 63 Groupname 0x8a98 64 follow exactly the PKG_IA_C0_ANYThe only change is that they do +N (Max IA ratio) instead of +1 on the relevant clock edge and conditions (while any LP_AT_C0[i]=1):PCU_CR_PKG_IA_C0_ANY_RATIO_0_0_0_MCHBAR_PCU += PKG_IA_C0_CURRENT_RATIO.RATIOPKG_IA_C0_CURRENT_RATIO.RATIO = MAX(IO_WP_CV_P_STATE[IA_RATIO]).Reference clock is XTAL.More details [here](https://docs.intel.com/documents/pm_doc/src/LNL/MAS/CCP_PM/ccp_pm_mas.html#punit-counters) IO_PKG_IA_C0_ANY_RATIO Counter 64 0 63 Groupname 0x8aa0 64 Time in ms during which SoC was throttled because of platform temperature reported in PECI sensor 0. PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_0 Counter 32 0 31 Time in ms during which SoC was throttled because of platform temperature reported in PECI sensor 1. PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_1 Counter 32 32 63 Groupname 0x8aa8 64 Time in ms during which SoC was throttled because of platform temperature reported in PECI sensor 2. PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_2 Counter 32 0 31 Time in ms during which SoC was throttled because of platform temperature reported in MMIO sensor 0. PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_0_MMIO Counter 32 32 63 Groupname 0x8ab0 64 Time in ms during which SoC was throttled because of platform temperature reported in MMIO sensor 1. PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_1_MMIO Counter 32 0 31 Time in ms during which SoC was throttled because of platform temperature reported in MMIO sensor 2. PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_2_MMIO Counter 32 32 63 Groupname 0x8ab8 64 Time in state counter IPU_PARTIAL_SLEEP_RESIDENCY Counter 64 0 63 Groupname 0x8ac0 64 Time in state counter VPU_PARTIAL_SLEEP_RESIDENCY Counter 64 0 63 Groupname 0x8ac8 64 state transition counter IPU_PARTIAL_SLEEP_ENTRY_COUNTERS Counter 32 0 31 state transition counter VPU_PARTIAL_SLEEP_ENTRY_COUNTERS Counter 32 32 63 Groupname 0x8ad0 64 reserved CNTR_RESERVED_0_8AD0 Counter 64 0 63 Groupname 0x8ad8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ae0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ae8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8af0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8af8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b00 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b08 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b10 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b18 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b20 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b28 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b30 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b38 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b40 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b48 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b50 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b58 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b60 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b68 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b70 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b78 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b80 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b88 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b90 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8b98 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ba0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ba8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8bb0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8bb8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8bc0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8bc8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8bd0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8bd8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8be0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8be8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8bf0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8bf8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c00 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c08 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c10 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c18 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c20 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c28 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c30 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c38 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c40 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c48 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c50 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c58 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c60 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c68 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c70 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c78 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c80 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c88 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c90 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8c98 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ca0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ca8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8cb0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8cb8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8cc0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8cc8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8cd0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8cd8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ce0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ce8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8cf0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8cf8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d00 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d08 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d10 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d18 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d20 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d28 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d30 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d38 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d40 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d48 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d50 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d58 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d60 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d68 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d70 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d78 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d80 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d88 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d90 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8d98 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8da0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8da8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8db0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8db8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8dc0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8dc8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8dd0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8dd8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8de0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8de8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8df0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8df8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e00 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e08 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e10 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e18 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e20 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e28 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e30 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e38 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e40 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e48 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e50 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e58 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e60 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e68 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e70 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e78 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e80 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e88 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e90 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8e98 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ea0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ea8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8eb0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8eb8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ec0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ec8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ed0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ed8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ee0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ee8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ef0 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8ef8 64 reserved CNTR_RESERVED_1_to_133 Counter 64 0 63 Groupname 0x8f00 64 Average DDR BW over a time interval VPU_MEMORY_BW Counter 32 0 31 Cycle count of amount of times VPU is in D0 active state VPU_D0_ACTIVE_RESIDENCY Counter 32 32 63 Groupname 0x8f08 64 Number of times VPU enters into D0 active state VPU_D0_ACTIVE_ENTRY_COUNT Counter 32 0 31 Cycle count of amount of time VPU is in D0I2 active state VPU_D0i2_ACTIVE_RESIDENCY Counter 32 32 63 Groupname 0x8f10 64 Cycle count of amount of time VPU is in D0I2 Idle state VPU_D0i2_IDLE_RESIDENCY Counter 32 0 31 Number of times VPU enters into D0I2 active state VPU_D0i2_ACTIVE_ENTRY_COUNT Counter 32 32 63 Groupname 0x8f18 64 Number of times VPU enters into D0I2 Idle state VPU_D0i2_IDLE_ENTRY_COUNT Counter 32 0 31 Overall number of cycles for a context in RealTime priority VPU_REALTIME_PRIORITY_CONTEXT_CYCLE_COUNT Counter 32 32 63 Groupname 0x8f20 64 Overall number of cycles for a context in normal priority VPU_NORMAL_PRIORITY_CONTEXT_CYCLE_COUNT Counter 32 0 31 Overall number of cycles for a context in focus priority VPU_FOCUS_PRIORITY_CONTEXT_CYCLE_COUNT Counter 32 32 63 Groupname 0x8f28 64 Overall number of cycles for a context in background priority VPU_IDLE_PRIORITY_CONTEXT_CYCLE_COUNT Counter 32 0 31 Current value of the FRC (fixed frequency) when data is reported out - VPU fixed frequency FRC(free running counter) value VPU_FIXED_FREQ_FRC_VAL Counter 32 32 63 Groupname 0x8f30 64 Current value of the FRC (variable frequeny) when data is reported out. - VPU variable frequency (DVFS clock) FRC (free running counter) value VPU_VAR_FREQ_FRC_VAL Counter 32 0 31 reserved VPU_RSVD0_8F34 Counter 32 32 63 Groupname 0x8f38 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8f40 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8f48 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8f50 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8f58 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8f60 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8f68 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8f70 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8f78 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8f80 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8f88 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8f90 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8f98 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8fa0 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8fa8 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8fb0 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8fb8 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8fc0 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8fc8 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8fd0 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8fd8 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8fe0 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8fe8 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8ff0 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63 Groupname 0x8ff8 64 reserved VPU_RSVD_1_to_25 Counter 64 0 63