float parameter_0 $parameter_0 / 38.4 * 1e6 float parameter_0 $parameter_0 * 0.0025 float parameter_0 $parameter_0 * 64 / 1e6 float parameter_0 $parameter_0 / 1e6 float parameter_0 $parameter_0 * 32 / 1e6 float parameter_0 $parameter_0 / 1e3 float parameter_0 $parameter_0 float parameter_0 $parameter_0 float parameter_0 $parameter_0 / 1048576 float parameter_0 ( 49 + $parameter_0 ) * 0.005 integer parameter_0 ( ( ( 1 - ( ( $parameter_0 >> 7 ) & 0x1 ) ) * ( $parameter_0 & 0xff ) ) - ( ( ( $parameter_0 >> 7 ) & 0x1 ) * ( ( ( $parameter_0 & 0x7f ) ^ 0x7f ) + 1 ) ) ) float parameter_0 $parameter_0 float parameter_0 ( $parameter_0 & 0xff ) / ( 2**7 ) float parameter_0 ( $parameter_0 & 0x3ff ) / ( 2**3 ) float parameter_0 $parameter_0 * 0.1 float parameter_0 $parameter_0 * 0.01667 float parameter_0 $parameter_0 * 0.025 float parameter_0 $parameter_0 * 0.033 float parameter_0 ( $parameter_0 & 0xffff ) / ( 2**8 ) float parameter_0 ( $parameter_0 & 0x1ff ) / ( 2**8 ) float parameter_0 $parameter_0 * 100 / 16 float parameter_0 ( $parameter_0 & 0xffff ) / ( 2**15 ) float parameter_0 $parameter_0 * 0.002 float parameter_0 ( $parameter_0 & 0x7ff ) / ( 2**2 ) float parameter_0 ( $parameter_0 & 0xffffffff ) / ( 2**14 ) float parameter_0 $parameter_0 / 16384 float parameter_0 $parameter_0 * 64 float parameter_0 $parameter_0 * 0.025 * 33.33 float parameter_0 $parameter_0 * 0.025 / 1e6 float parameter_0 $parameter_0 integer parameter_0 $parameter_0 MTL MTL M/P PMT Normal telemetry in Punit samples definition and transformation rules 0x130670B2 Public 10 2024-09-06 Average DDR BW over a time interval (VPU counts in KB) Counter Container_0 VPU_MEMORY_BW bw_KB Cycle count of amount of times VPU is in D0 active state Counter Container_0 VPU_D0_ACTIVE_RESIDENCY xtal_time Number of times VPU enters into D0 active state Counter Container_1 VPU_D0_ACTIVE_ENTRY_COUNT event_counter Cycle count of amount of time VPU is in D0I2 active state Counter Container_1 VPU_D0i2_ACTIVE_RESIDENCY xtal_time Cycle count of amount of time VPU is in D0I2 Idle state Counter Container_2 VPU_D0i2_IDLE_RESIDENCY xtal_time Number of times VPU enters into D0I2 active state Counter Container_2 VPU_D0i2_ACTIVE_ENTRY_COUNT event_counter Number of times VPU enters into D0I2 Idle state Counter Container_3 VPU_D0i2_IDLE_ENTRY_COUNT event_counter Overall number of cycles for a context in RealTime priority **NOT IMPLEMENTED** Counter Container_3 VPU_REALTIME_PRIORITY_CONTEXT_CYCLE_COUNT event_counter Overall number of cycles for a context in normal priority **NOT IMPLEMENTED** Counter Container_4 VPU_NORMAL_PRIORITY_CONTEXT_CYCLE_COUNT xtal_time Overall number of cycles for a context in focus priority **NOT IMPLEMENTED** Counter Container_4 VPU_FOCUS_PRIORITY_CONTEXT_CYCLE_COUNT xtal_time Overall number of cycles for a context in background priority **NOT IMPLEMENTED** Counter Container_5 VPU_IDLE_PRIORITY_CONTEXT_CYCLE_COUNT xtal_time Current value of the FRC (fixed frequency) when data is reported out - VPU fixed frequency FRC(free running counter) value Counter Container_5 VPU_FIXED_FREQ_FRC_VAL cycle_count Current value of the FRC (variable frequeny) when data is reported out. - VPU variable frequency (DVFS clock) FRC (free running counter) value Counter Container_6 VPU_VAR_FREQ_FRC_VAL cycle_count Reserved Counter Container_7 VPU_RSVD0 passthru Reserved Counter Container_8 VPU_RSVD1 passthru Reserved Counter Container_9 VPU_RSVD2 passthru Reserved Counter Container_10 VPU_RSVD3 passthru Snapshot Container_11 LOCAL_VERSION passthru Snapshot Container_11 PRODUCT_ID passthru Snapshot Container_11 SOURCEID passthru Snapshot Container_11 reserved passthru Represents the clock rate of the XTAL on this silicon.1: 19.2MHz - 19.2e60: 24MHz - 24e63: 25MHz - 25e62: 38.4MHz - 38.4e6 Snapshot Container_11 XTAL_FREQ passthru Snapshot Container_11 reserved_1 passthru ICCMAX level for the IPU's IS system Snapshot Container_11 IS_ICCMAX_LEVEL ipu_icc ICCMAX level for the IPU's PS system Snapshot Container_11 PS_ICCMAX_LEVEL ipu_icc Qclk frequency for Mem SS - Snapshot Container_11 QCLK_FREQ ratio_33 Mem SS voltage requirement Snapshot Container_11 VOLTAGE U8.1.7 Processing system frequency. Frequency is ratio*25MHz. Zero means power down. Snapshot Container_12 PS_FREQ ratio_25 IS system frequency. Frequency is ratio*25MHz. Zero means power down. Snapshot Container_12 IS_FREQ ratio_25 IS voltage requirement Snapshot Container_12 IS_VOLTAGE U8.1.7 PS voltage requirement Snapshot Container_12 PS_VOLTAGE U8.1.7 CDCLK frequency for display Snapshot Container_12 CDCLK_FREQ clk_freq Display voltage requirement Snapshot Container_12 VOLTAGE_1 U8.1.7 NGU frequency Snapshot Container_12 FREQ ratio_100 NGU voltage requirement Snapshot Container_12 VOLTAGE_2 U8.1.7 VPU ratio Snapshot Container_13 FREQ_1 ratio_33 VPU voltage requirement Snapshot Container_13 VOLTAGE_3 U8.1.7 Indicates the tile configuration internal to VPU Snapshot Container_13 TILE_CONFIG passthru ADM frequency Snapshot Container_13 FREQ_2 ratio_100 ADM voltage requirement Snapshot Container_13 VOLTAGE_4 U8.1.7 Media voltage requirement - **ZBB - always reports '0'** Snapshot Container_14 VOLTAGE_5 wp_volts Media ratio Snapshot Container_14 FREQ_3 ratio_16 Reserved Snapshot Container_14 reserved_2 passthru Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_14 VOLTAGE_6 wp_volts Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_14 CURRENT U10.7.3 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_14 PS_OVERRIDE passthru IA Module clock ratio, in units of 100MHz. Snapshot Container_14 FREQ_4 ratio_100 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_15 VOLTAGE_7 wp_volts Reserved Snapshot Container_15 reserved_3 passthru Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_15 PS_OVERRIDE_1 passthru IA Module clock ratio, in units of 100MHz. Snapshot Container_15 FREQ_5 ratio_100 Indicates systolic config Snapshot Container_15 SYSTOLIC passthru EUs active Snapshot Container_15 EU_COUNT passthru unused in MTL Snapshot Container_15 MEDIA_ENGINE_COUNT passthru subslice count Snapshot Container_15 SUBSLICE_COUNT passthru active slices in GT Snapshot Container_15 RENDER_SLICE_COUNT passthru Snapshot Container_15 reserved_4 passthru Graphics Security Controller (GSC). 0 - GSC is power-gated. 1 - GSC is not power-gated. Snapshot Container_16 GSC passthru Total number of active media engines in Media. Inactive means power-gated, that is, no leakage. The range in MTL is 0-1. Snapshot Container_16 MEDIA_SLICE_COUNT passthru Reserved Snapshot Container_16 reserved_5 passthru beta value Snapshot Container_16 BETA U16.1.15 CEP theshold Snapshot Container_16 CEP_THRESHOLD cep_volts beta value Snapshot Container_17 BETA_1 U16.1.15 CEP theshold Snapshot Container_17 CEP_THRESHOLD_1 cep_volts VID Code. Encoding is based on SVID spec. Snapshot Container_17 VID vid VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 Snapshot Container_17 PS passthru Issue FAST ramp, instead of SLOW ramp. Snapshot Container_17 FAST passthru Issue DECAY ramp, instead of SLOW ramp. Only going down. Snapshot Container_17 DECAY passthru Snapshot Container_17 reserved_6 passthru VID Code. Encoding is based on SVID spec. Snapshot Container_17 VID_1 vid VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 Snapshot Container_17 PS_1 passthru Issue FAST ramp, instead of SLOW ramp. Snapshot Container_17 FAST_1 passthru Issue DECAY ramp, instead of SLOW ramp. Only going down. Snapshot Container_17 DECAY_1 passthru Snapshot Container_17 reserved_7 passthru Last current sample, in amps. U16.8.8 Snapshot Container_18 AMPS U16.8.8 Last current sample, in amps. Snapshot Container_18 AMPS_1 U16.8.8 IA Core C-state of SoC Atom module - Core00: C01: C13: C67: CRST Snapshot Container_18 SOC_CORE0 passthru IA Core C-state of SoC Atom module - Core10: C01: C13: C67: CRST Snapshot Container_18 SOC_CORE1 passthru GT RC-state0: C01: C13: C67: CRST Snapshot Container_18 GT passthru Snapshot Container_18 reserved_8 passthru Current PCH temperature Snapshot Container_19 PCH_TEMP S8.7.0 Current DRAM temperature. Snapshot Container_19 DRAM_TEMP S8.7.0 Current reading from System Agent "always on" temperature sensor Snapshot Container_19 SA_TEMP S8.7.0 Current reading from IPU subsystem temperature sensor Snapshot Container_19 IPU_TEMP S8.7.0 Current reading from Display subsystem temperature sensor Snapshot Container_19 DE_TEMP S8.7.0 Current reading from VPU subsystem temperature sensor Snapshot Container_19 VPU_TEMP S8.7.0 Current reading from Media subsystem temperature sensor Snapshot Container_19 Media_TEMP S8.7.0 Snapshot Container_19 reserved_9 passthru Graphics Die Min temp Snapshot Container_20 GCD_MIN S8.7.0 Graphics Die Max temp Snapshot Container_20 GCD_MAX S8.7.0 ADM Die Min temp Snapshot Container_20 ADM_MIN S8.7.0 ADM Die Max temp Snapshot Container_20 ADM_MAX S8.7.0 Snapshot Container_20 reserved_10 passthru Min temp across the module Snapshot Container_21 DTS0 S8.7.0 Max temp across the module Snapshot Container_21 DTS1 S8.7.0 NA - not updated by Pcode Snapshot Container_21 DTS2 passthru NA - not updated by Pcode Snapshot Container_21 DTS3 passthru Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_21 CORE0 U9.1.8 Snapshot Container_21 reserved_11 passthru Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_22 CORE1 U9.1.8 Snapshot Container_22 reserved_12 passthru Core0 P_alpha calculation. This represents the maximum allowed clock frequency on that core. Snapshot Container_22 CORE0_1 ratio_100 Core1 P_alpha calculation. This represents the maximum allowed clock frequency on that core. Snapshot Container_22 CORE1_1 ratio_100 Current autonomous frequency target for that IA module Snapshot Container_22 CORE0_2 ratio_100 Current autonomous frequency target for that IA module Snapshot Container_22 CORE1_2 ratio_100 Current efficient frequency target for that IA module Snapshot Container_23 CORE0_3 ratio_100 Current efficient frequency target for that IA module Snapshot Container_23 CORE1_3 ratio_100 Current GT Efficient P-state (used as the floor for autonomous control) Snapshot Container_23 GT_PE ratio_16 reserved Snapshot Container_24 rsvd passthru reserved Snapshot Container_25 rsvd_1 passthru reserved Snapshot Container_26 rsvd_2 passthru reserved Snapshot Container_27 rsvd_3 passthru reserved Snapshot Container_28 rsvd_4 passthru reserved Snapshot Container_29 rsvd_5 passthru reserved Snapshot Container_30 rsvd_6 passthru reserved Snapshot Container_31 rsvd_7 passthru reserved Snapshot Container_32 rsvd_8 passthru reserved Snapshot Container_33 rsvd_9 passthru reserved Snapshot Container_34 rsvd_10 passthru reserved Snapshot Container_35 rsvd_11 passthru reserved Snapshot Container_36 rsvd_12 passthru reserved Snapshot Container_37 rsvd_13 passthru reserved Snapshot Container_38 rsvd_14 passthru reserved Snapshot Container_39 rsvd_15 passthru reserved Snapshot Container_40 rsvd_16 passthru reserved Snapshot Container_41 rsvd_17 passthru reserved Snapshot Container_42 rsvd_18 passthru reserved Snapshot Container_43 rsvd_19 passthru reserved Snapshot Container_44 rsvd_20 passthru reserved Snapshot Container_45 rsvd_21 passthru reserved Snapshot Container_46 rsvd_22 passthru reserved Snapshot Container_47 rsvd_23 passthru reserved Snapshot Container_48 rsvd_24 passthru reserved Snapshot Container_49 rsvd_25 passthru reserved Snapshot Container_50 rsvd_26 passthru reserved Snapshot Container_51 rsvd_27 passthru reserved Snapshot Container_52 rsvd_28 passthru reserved Snapshot Container_53 rsvd_29 passthru reserved Snapshot Container_54 rsvd_30 passthru reserved Snapshot Container_55 rsvd_31 passthru reserved Snapshot Container_56 rsvd_32 passthru reserved Snapshot Container_57 rsvd_33 passthru reserved Snapshot Container_58 rsvd_34 passthru reserved Snapshot Container_59 rsvd_35 passthru reserved Snapshot Container_60 rsvd_36 passthru reserved Snapshot Container_61 rsvd_37 passthru reserved Snapshot Container_62 rsvd_38 passthru reserved Snapshot Container_63 rsvd_39 passthru reserved Snapshot Container_64 rsvd_40 passthru reserved Snapshot Container_65 rsvd_41 passthru reserved Snapshot Container_66 rsvd_42 passthru reserved Snapshot Container_67 rsvd_43 passthru reserved Snapshot Container_68 rsvd_44 passthru reserved Snapshot Container_69 rsvd_45 passthru reserved Snapshot Container_70 rsvd_46 passthru reserved Snapshot Container_71 rsvd_47 passthru reserved Snapshot Container_72 rsvd_48 passthru reserved Snapshot Container_73 rsvd_49 passthru reserved Snapshot Container_74 rsvd_50 passthru reserved Snapshot Container_75 rsvd_51 passthru reserved Snapshot Container_76 rsvd_52 passthru reserved Snapshot Container_77 rsvd_53 passthru reserved Snapshot Container_78 rsvd_54 passthru reserved Snapshot Container_79 rsvd_55 passthru reserved Snapshot Container_80 rsvd_56 passthru reserved Snapshot Container_81 rsvd_57 passthru reserved Snapshot Container_82 rsvd_58 passthru reserved Snapshot Container_83 rsvd_59 passthru reserved Snapshot Container_84 rsvd_60 passthru reserved Snapshot Container_85 rsvd_61 passthru reserved Snapshot Container_86 rsvd_62 passthru reserved Snapshot Container_87 rsvd_63 passthru reserved Snapshot Container_88 rsvd_64 passthru reserved Snapshot Container_89 rsvd_65 passthru reserved Snapshot Container_90 rsvd_66 passthru reserved Snapshot Container_91 rsvd_67 passthru reserved Snapshot Container_92 rsvd_68 passthru reserved Snapshot Container_93 rsvd_69 passthru reserved Snapshot Container_94 rsvd_70 passthru reserved Snapshot Container_95 rsvd_71 passthru reserved Snapshot Container_96 rsvd_72 passthru reserved Snapshot Container_97 rsvd_73 passthru reserved Snapshot Container_98 rsvd_74 passthru reserved Snapshot Container_99 rsvd_75 passthru reserved Snapshot Container_100 rsvd_76 passthru reserved Snapshot Container_101 rsvd_77 passthru reserved Snapshot Container_102 rsvd_78 passthru reserved Snapshot Container_103 rsvd_79 passthru reserved Snapshot Container_104 rsvd_80 passthru reserved Snapshot Container_105 rsvd_81 passthru reserved Snapshot Container_106 rsvd_82 passthru reserved Snapshot Container_107 rsvd_83 passthru reserved Snapshot Container_108 rsvd_84 passthru reserved Snapshot Container_109 rsvd_85 passthru reserved Snapshot Container_110 rsvd_86 passthru reserved Snapshot Container_111 rsvd_87 passthru reserved Snapshot Container_112 rsvd_88 passthru reserved Snapshot Container_113 rsvd_89 passthru reserved Snapshot Container_114 rsvd_90 passthru reserved Snapshot Container_115 rsvd_91 passthru reserved Snapshot Container_116 rsvd_92 passthru reserved Snapshot Container_117 rsvd_93 passthru reserved Snapshot Container_118 rsvd_94 passthru reserved Snapshot Container_119 rsvd_95 passthru reserved Snapshot Container_120 rsvd_96 passthru reserved Snapshot Container_121 rsvd_97 passthru reserved Snapshot Container_122 rsvd_98 passthru reserved Snapshot Container_123 rsvd_99 passthru reserved Snapshot Container_124 rsvd_100 passthru reserved Snapshot Container_125 rsvd_101 passthru reserved Snapshot Container_126 rsvd_102 passthru reserved Snapshot Container_127 rsvd_103 passthru reserved Snapshot Container_128 rsvd_104 passthru reserved Snapshot Container_129 rsvd_105 passthru reserved Snapshot Container_130 rsvd_106 passthru reserved Snapshot Container_131 rsvd_107 passthru reserved Snapshot Container_132 rsvd_108 passthru reserved Snapshot Container_133 rsvd_109 passthru reserved Snapshot Container_134 rsvd_110 passthru reserved Snapshot Container_135 rsvd_111 passthru reserved Snapshot Container_136 rsvd_112 passthru reserved Snapshot Container_137 rsvd_113 passthru reserved Snapshot Container_138 rsvd_114 passthru slow limit THERM has limited performance for MODULE0. Counter Container_139 PERF_LIMIT_THERM_MODULE_RESIDENCY_0 xtal_time slow limit THERM has limited performance for GT. Counter Container_140 PERF_LIMIT_THERM_GT_RESIDENCY xtal_time slow limit THERM has limited performance for IPU. Counter Container_141 PERF_LIMIT_THERM_IPU_RESIDENCY xtal_time slow limit THERM has limited performance for VPU. Counter Container_142 PERF_LIMIT_THERM_VPU_RESIDENCY xtal_time slow limit THERM has limited performance for Media. Counter Container_143 PERF_LIMIT_THERM_MEDIA_RESIDENCY xtal_time slow limit POWER has limited performance for Atom MODULE Counter Container_144 PERF_LIMIT_POWER_MODULE_RESIDENCY_0 xtal_time slow limit POWER has limited performance for GT. Counter Container_145 PERF_LIMIT_POWER_GT_RESIDENCY xtal_time slow limit POWER has limited performance for media Counter Container_146 PERF_LIMIT_POWER_MEDIA_RESIDENCY xtal_time slow limit POWER has limited performance for VPU Counter Container_147 PERF_LIMIT_POWER_VPU_RESIDENCY xtal_time slow limit EDP has limited performance for Atom MODULE Counter Container_148 PERF_LIMIT_EDP_MODULE_RESIDENCY_0 xtal_time slow limit EDP has limited performance for GT. Counter Container_149 PERF_LIMIT_EDP_GT_RESIDENCY xtal_time slow limit EDP has limited performance for Media - **NOT UPDATED always 0** Counter Container_150 PERF_LIMIT_EDP_MEDIA_RESIDENCY xtal_time slow limit EDP has limited performance for VPU - **NOT UPDATED always 0** Counter Container_151 PERF_LIMIT_EDP_VPU_RESIDENCY xtal_time slow limit OTHER has limited performance for Atom MODULE - **NOT UPDATED always 0** Counter Container_152 PERF_LIMIT_OTHER_MODULE_RESIDENCY_0 xtal_time slow limit OTHER has limited performance for GT - **NOT UPDATED always 0** Counter Container_153 PERF_LIMIT_OTHER_GT_RESIDENCY xtal_time slow limit OTHER has limited performance for Media - **UPDATED but is mapped to EDP reason** Counter Container_154 PERF_LIMIT_OTHER_MEDIA_RESIDENCY xtal_time slow limit OTHER has limited performance for VPU- **UPDATED but is mapped to EDP reason** Counter Container_155 PERF_LIMIT_OTHER_VPU_RESIDENCY xtal_time prochot assertions. Counter Container_156 PROCHOT_RESIDENCY xtal_time VCCGT VR asserted VRHOT. Counter Container_157 VCCGT_VRHOT_RESIDENCY xtal_time VCCAUX VR asserted VRHOT. Counter Container_158 VCCSA_VRHOT_RESIDENCY xtal_time SOC was PL3 limited Counter Container_159 PL3_LIMITED_RESIDENCY xtal_time SOC was PL2 limited Counter Container_160 PL2_LIMITED_RESIDENCY xtal_time SOC was PL1 limited Counter Container_161 PL1_LIMITED_RESIDENCY xtal_time SOC was Psys PL3 limited Counter Container_162 PSYS_PL3_LIMITED_RESIDENCY xtal_time SOC was Psys PL2 limited Counter Container_163 PSYS_PL2_LIMITED_RESIDENCY xtal_time SOC was Psys PL1 limited Counter Container_164 PSYS_PL1_LIMITED_RESIDENCY xtal_time GT RC6 Counter Container_165 GT_RC6_RESIDENCY xtal_time Media C6 residency Counter Container_166 MEDIA_C6_RESIDENCY xtal_time VPU C6 residency- ** NOT IMPLEMENTED** Counter Container_167 VPU_C6_RESIDENCY xtal_time IPU IS C6 Counter Container_168 IPU_IS_C6_RESIDENCY xtal_time IPU PS C6 Counter Container_169 IPU_PS_C6_RESIDENCY xtal_time Counts the time that any Gfx engine is truly busy (not simply powered up)- ** NOT IMPLEMENTED** Counter Container_170 GT_ENGINE_BUSY_RESIDENCY xtal_time Counts the time from when the all the streamers have indicated idle to GT making a Rc6 entry request- ** NOT IMPLEMENTED** Counter Container_171 GT_RC0_IDLE_RESIDENCY xtal_time Counts the time from when the all the streamers have indicated idle to GT making a Rc6 entry request Counter Container_172 GCD_GC1_2_RESIDENCY xtal_time Counts the time from when the all the streamers have indicated idle to GT making a Rc6 entry request Counter Container_173 GCD_GC3_RESIDENCY xtal_time Reserved for future expansion Counter Container_174 RESERVED_RESIDENCY_0 xtal_time Reserved for future expansion Counter Container_175 RESERVED_RESIDENCY_1 xtal_time Reserved for future expansion Counter Container_176 RESERVED_RESIDENCY_2 xtal_time Reserved for future expansion Counter Container_177 RESERVED_RESIDENCY_3 xtal_time Reserved for future expansion Counter Container_178 RESERVED_RESIDENCY_4 xtal_time Reserved for future expansion Counter Container_179 RESERVED_RESIDENCY_5 xtal_time Reserved for future expansion Counter Container_180 RESERVED_RESIDENCY_6 xtal_time Reserved for future expansion Counter Container_181 RESERVED_RESIDENCY_7 xtal_time C6 residency counter for Core0 Counter Container_182 C6_RESIDENCY_CORE0 xtal_time C6 residency counter for Core1 Counter Container_183 C6_RESIDENCY_CORE1 xtal_time C0 residency counter for Core0 Counter Container_184 C0_RESIDENCY_CORE0 xtal_time C0 residency counter for Core1 Counter Container_184 C0_RESIDENCY_CORE1 xtal_time Transition counter for when slow limit THERM has limited performance for Atom MODULE Counter Container_185 PERF_LIMIT_THERM_MODULE_COUNTER_0 event_counter Transition counter for when slow limit THERM has limited performance for GT. Counter Container_185 PERF_LIMIT_THERM_GT_COUNTER event_counter Transition counter for when slow limit THERM has limited performance for VPU Counter Container_186 PERF_LIMIT_THERM_VPU_COUNTER event_counter Transition counter for when slow limit THERM has limited performance for Media Counter Container_186 PERF_LIMIT_THERM_MEDIA_COUNTER event_counter Transition counter for when slow limit POWER has limited performance for Atom MODULE Counter Container_187 PERF_LIMIT_POWER_MODULE_COUNTER_0 event_counter Transition counter for when slow limit POWER has limited performance for GT. Counter Container_187 PERF_LIMIT_POWER_GT_COUNTER event_counter Transition counter for when slow limit POWER has limited performance for Media Counter Container_188 PERF_LIMIT_POWER_MEDIA_COUNTER event_counter Transition counter for when slow limit POWER has limited performance for VPU Counter Container_188 PERF_LIMIT_POWER_VPU_COUNTER event_counter Transition counter for when slow limit EDP has limited performance for Atom MODULE Counter Container_189 PERF_LIMIT_EDP_MODULE_COUNTER_0 event_counter Transition counter for when slow limit EDP has limited performance for GT. Counter Container_189 PERF_LIMIT_EDP_GT_COUNTER event_counter Transition counter for when slow limit EDP has limited performance for Media Counter Container_190 PERF_LIMIT_EDP_MEDIA_COUNTER event_counter Transition counter for when slow limit EDP has limited performance for VPU Counter Container_190 PERF_LIMIT_EDP_VPU_COUNTER event_counter Transition counter for when slow limit OTHER has limited performance for Atom MODULE Counter Container_191 PERF_LIMIT_OTHER_MODULE_COUNTER_0 event_counter Transition counter for when slow limit OTHER has limited performance for GT. Counter Container_191 PERF_LIMIT_OTHER_GT_COUNTER event_counter Transition counter for when slow limit OTHER has limited performance for Media. Counter Container_192 PERF_LIMIT_OTHER_MEDIA_COUNTER event_counter Transition counter for when slow limit OTHER has limited performance for VPU. Counter Container_192 PERF_LIMIT_OTHER_VPU_COUNTER event_counter Energy reported by the Psys VR Counter Container_193 PSYS_ENERGY energy_J Total package energy including Cdie + GCD+SoC, (should be the same as MSR package_energy_status)- **Protected by security** Counter Container_194 PACKAGE_ENERGY energy_J IA VR energy - **Protected by security** Counter Container_195 VCCIA_ENERGY vr_energy GT VR energy Counter Container_196 VCCGT_ENERGY vr_energy Energy estimated by Pcode using utilization factor from the VPU. Format is U18.14 Counter Container_197 VPU_ENERGY U32.18.14 Total I/O read bandwidth for Display Counter Container_198 DISPLAY_IO_READ_BANDWIDTH bw_32B Total I/O write bandwidth for display- ** NOT IMPLEMENTED** Counter Container_199 DISPLAY_IO_WRITE_BANDWIDTH bw_32B Total display VC1 (non-coherent read) bandwidth.- ** NOT IMPLEMENTED** Counter Container_200 DISPLAY_VC1_BANDWIDTH bw_32B Total I/O write bandwidth for IP0 - Counter Container_201 IO_WRITE_BANDWIDTH_IP0 bw_B Total I/O read bandwidth for IP0 Counter Container_202 IO_READ_BANDWIDTH_IP0 bw_B Total I/O write bandwidth for IP1 Counter Container_203 IO_WRITE_BANDWIDTH_IP1 bw_B Total I/O read bandwidth for IP1 Counter Container_204 IO_READ_BANDWIDTH_IP1 bw_B Total I/O write bandwidth for IP2 Counter Container_205 IO_WRITE_BANDWIDTH_IP2 bw_B Total I/O read bandwidth for IP2 Counter Container_206 IO_READ_BANDWIDTH_IP2 bw_B Total I/O write bandwidth for IP3 Counter Container_207 IO_WRITE_BANDWIDTH_IP3 bw_B Total I/O read bandwidth for IP3 Counter Container_208 IO_READ_BANDWIDTH_IP3 bw_B Total I/O read bandwidth. Counter Container_209 IO_TOTAL_READ_BANDWIDTH bw_B Total I/O write bandwidth. Counter Container_210 IO_TOTAL_WRITE_BANDWIDTH bw_B Total BW from the IP towards NoC on bridge0, PMON counts requests and almost all NoC requests are 64B Counter Container_211 NOC_BW_GCD0 bw_64B Total BW from the IP towards NoC on bridge1, PMON counts requests and almost all NoC requests are 64B Counter Container_212 NOC_BW_GCD1 bw_64B Total BW from the IP towards NoC on bridge0, PMON counts requests and almost all NoC requests are 64B Counter Container_213 NOC_BW_IOC0 bw_64B Total BW from the IP towards NoC on bridge1, PMON counts requests and almost all NoC requests are 64B Counter Container_214 NOC_BW_IOC1 bw_64B Total BW from the IP towards NoC on bridge0, PMON counts requests and almost all NoC requests are 64B (DMA traffic generated during inferences) Counter Container_215 NOC_BW_VPU0 bw_64B Total BW from the IP towards NoC on bridge1, PMON counts requests and almost all NoC requests are 64B (all traffic generated by the VPU) Counter Container_216 NOC_BW_VPU1 bw_64B Total BW from the IP towards NoC on bridge0, PMON counts requests and almost all NoC requests are 64B Counter Container_217 NOC_BW_IPU0 bw_64B Total BW from the IP towards NoC on bridge1, PMON counts requests and almost all NoC requests are 64B Counter Container_218 NOC_BW_IPU1 bw_64B Total BW from the IP towards NoC on bridge0, PMON counts requests and almost all NoC requests are 64B Counter Container_219 NOC_BW_DISP0 bw_64B Total BW from the IP towards NoC on bridge1, PMON counts requests and almost all NoC requests are 64B Counter Container_220 NOC_BW_DISP1 bw_64B Total BW from the IP towards NoC on bridge0, PMON counts requests and almost all NoC requests are 64B Counter Container_221 NOC_BW_MEDIA0 bw_64B Total BW from the IP towards NoC on bridge1, PMON counts requests and almost all NoC requests are 64B Counter Container_222 NOC_BW_MEDIA1 bw_64B Total BW from the IP towards NoC on bridge0, PMON counts requests and almost all NoC requests are 64B Counter Container_223 NOC_BW_HAC0 bw_64B Total BW from the IP towards NoC on bridge1, PMON counts requests and almost all NoC requests are 64B Counter Container_224 NOC_BW_HAC1 bw_64B Total BW from the IP towards NoC on bridge0, PMON counts requests and almost all NoC requests are 64B Counter Container_225 NOC_BW_ADM0 bw_64B Total BW from the IP towards NoC on bridge1, PMON counts requests and almost all NoC requests are 64B Counter Container_226 NOC_BW_ADM1 bw_64B Total BW from the IP towards NoC on bridge0, PMON counts requests and almost all NoC requests are 64B Counter Container_227 NOC_BW_CCE0 bw_64B Total BW from the IP towards NoC on bridge1, PMON counts requests and almost all NoC requests are 64B Counter Container_228 NOC_BW_CCE1 bw_64B Total BW from the IP towards NoC on bridge0, PMON counts requests and almost all NoC requests are 64B Counter Container_229 NOC_BW_IDI2CMI0 bw_64B Total BW from the IP towards NoC on bridge1, PMON counts requests and almost all NoC requests are 64B Counter Container_230 NOC_BW_IDI2CMI1 bw_64B Measures the number of transitions to Package C-state C2. Counter Container_231 PACKAGE_CSTATE_COUNTS_C2 event_counter Measures the number of transitions to Package C-state C3. Counter Container_231 PACKAGE_CSTATE_COUNTS_C3 event_counter Measures the number of transitions to Package C-state C6. Counter Container_232 PACKAGE_CSTATE_COUNTS_C6 event_counter Measures the number of transitions to Package C-state C7 Counter Container_232 PACKAGE_CSTATE_COUNTS_C7 event_counter Measures the number of transitions to Package C-state C8 Counter Container_233 PACKAGE_CSTATE_COUNTS_C8 event_counter Measures the number of transitions to Package C-state C9 Counter Container_233 PACKAGE_CSTATE_COUNTS_C9 event_counter Measures the number of transitions to Package C-state C10 Counter Container_234 PACKAGE_CSTATE_COUNTS_C10 event_counter Measures the number of transitions to Package C-state LLC_FLUSHED. **ZBBed NOT IMPLEMENTED - Refer to DMU telemetry** Counter Container_234 PACKAGE_CSTATE_COUNTS_LLC_FLUSHED event_counter prochot assertions. Counter Container_235 PROCHOT_COUNTER event_counter counts VCCGT VR asserted VRHOT occasions Counter Container_235 VCCGT_VRHOT_COUNTER event_counter counts VCCSA VR asserted VRHOT. Counter Container_236 VCCSA_VRHOT_COUNTER event_counter SOC was PL3 limited Counter Container_236 PL3_LIMITED_COUNTER event_counter SOC was PL2 limited Counter Container_237 PL2_LIMITED_COUNTER event_counter SOC was PL1 limited Counter Container_237 PL1_LIMITED_COUNTER event_counter SOC was Psys PL3 limited Counter Container_238 PSYS_PL3_LIMITED_COUNTER event_counter SOC was Psys PL2 limited Counter Container_238 PSYS_PL2_LIMITED_COUNTER event_counter SOC was Psys PL1 limited Counter Container_239 PSYS_PL1_LIMITED_COUNTER event_counter GT RC6 state transition counter Counter Container_239 GT_RC6_COUNTER event_counter IPU IS C6 state transition counter Counter Container_240 IPU_IS_C6_COUNTER event_counter IPU PS C6 state transition counter Counter Container_240 IPU_PS_C6_COUNTER event_counter Media C6 state transition counter Counter Container_241 MEDIA_C6_COUNTER event_counter VPU C6 state transition counter- **NOT IMPLEMENTED** Counter Container_241 VPU_C6_COUNTER event_counter C6 entry transition counter - Core0 Counter Container_242 CORE_CSTATE_C6_COUNTER_0 event_counter C6 entry transition counter - Core1 Counter Container_242 CORE_CSTATE_C6_COUNTER_1 event_counter Counts the cycles that DRAM is not in SR state while MC clocks are toggling for MC0Details to calculate Opportunustic self-refresh (Opp SR) residency: Get mc_active_dclk_cycles from MC_ON_RATIOOpp.SR = mc_active_dclk_cycles - avg(MC_NON_SR_COUNT_0/1)Opp.SR residency = OppSR/mc_active_dclk_cycles Counter Container_243 MC_NON_SR_COUNT_0 cycle_count Counts the cycles that DRAM is not in SR state while MC clocks are toggling for MC1 Counter Container_244 MC_NON_SR_COUNT_1 cycle_count Counts the cycles that all ranks within channel are in CKE power down state for channel 0Details to calculate CKE residency:CKE residency = avg(MC_CKE_POWER_DOWN_COUNT_CH0-3)/mc_active_dclk_cycles Counter Container_245 MC_CKE_POWER_DOWN_COUNT_CH0 cycle_count Counts the cycles that all ranks within channel are in CKE power down state for channel 1 Counter Container_246 MC_CKE_POWER_DOWN_COUNT_CH1 cycle_count Counts the cycles that all ranks within channel are in CKE power down state for channel 2 Counter Container_247 MC_CKE_POWER_DOWN_COUNT_CH2 cycle_count Counts the cycles that all ranks within channel are in CKE power down state for channel 3 Counter Container_248 MC_CKE_POWER_DOWN_COUNT_CH3 cycle_count increments the counter every sideband clock by CMI PLL ratio (33.33 MHz) when CMI PLL is locked.mc_active_dclk_cycles = MC_ON_RATIO *SBclk_period (0.025us) * 33.33 (cycles/us) Counter Container_249 MC_ON_RATIO_LOW mc_cycles increments the counter every sideband clock by CMI PLL ratio (33.33 MHz) when CMI PLL is locked.mc_active_dclk_cycles = MC_ON_RATIO *SBclk_period (0.025us) * 33.33 (cycles/us) Counter Container_249 MC_ON_RATIO_HIGH mc_cycles increments the counter every sideband clock by '1' when CMI PLL is locked. Time_MC_ON = counter * SBclk_period Counter Container_250 MC_ON_TIME_LOW mc_on_time increments the counter every sideband clock by '1' when CMI PLL is locked. Time_MC_ON = counter * SBclk_period Counter Container_250 MC_ON_TIME_HIGH mc_on_time Virtual bandwidth counter based on PWM_WRDATA bulkcr sample Counter Container_251 TOTAL_WRITE_BANDWIDTH bw_32B Virtual bandwidth counter based on PWM_RDDATA bulkcr sample Counter Container_252 TOTAL_READ_BANDWIDTH bw_32B The counter value is incremented as a function of the number of cores that reside in C0 and active. If N cores are simultaneously in C0, then the number of "clock ticks" that are incremented is N. Counts in XTAL units. Counter Container_253 IO_PKG_IA_C0_ANY_SUM event_counter This counter increments whenever GCD slices or unslices are ON and in C0 state. Counter rate is the Xtal clock. Counter Container_253 IO_PKG_GCD_C0_ANY event_counter This counter increments whenever any GCD slice is ON. Counter rate is in Xtal clock. **ZBBEd NOT IMPLEMENTED** Counter Container_254 IO_PKG_GCD_C0_ANY_SLICE event_counter This counter increments by the sum of ON GCD slices. Counter rate is in Xtal clock.**ZBBEd NOT IMPLEMENTED** Counter Container_254 IO_PKG_GCD_C0_SLICES_SUM event_counter Follow exactly the PKG_GCD_C0_ANY. The only change is to do +N (GCD ratio) instead of +1 on the relevant clock edge. Counter rate is in Xtal Clock.**ZBBEd NOT IMPLEMENTED** Counter Container_255 IO_PKG_GCD_C0_ANY_SLICE_RATIO event_counter Follow exactly the PKG_GCD_C0_ANY_SLICE. The only change is that they do +N (GCD ratio) instead of +1 on the relevant clock edge. Counter rate is in Xtal Clock. Counter Container_255 IO_PKG_GCD_C0_ANY_RATIO event_counter This counter increments whenever MEDIA slices or unslices are ON and in C0 state. Counter rate is the Xtal clock. Counter Container_256 IO_PKG_MEDIA_C0_ANY event_counter This counter increments whenever any MEDIA slice is ON. Counter rate is in Xtal clock. Counter Container_256 IO_PKG_MEDIA_C0_ANY_SLICE event_counter This counter increments by the sum of ON MEDIA slices. Counter rate is in Xtal clock. Counter Container_257 IO_PKG_MEDIA_C0_SLICES_SUM event_counter Follow exactly the PKG_MEDIA_C0_ANY. The only change is to do +N (MEDIA ratio) instead of +1 on the relevant clock edge. Counter rate is in Xtal Clock. Counter Container_257 IO_PKG_MEDIA_C0_ANY_SLICE_RATIO event_counter Follow exactly the PKG_GCD_C0_ANY_SLICE. The only change is that they do +N (GCD ratio) instead of +1 on the relevant clock edge. Counter rate is in Xtal Clock. Counter Container_258 IO_PKG_MEDIA_C0_ANY_RATIO event_counter Counts clocks that any IA core is active. Reference clock is XTAL. Counter Container_258 IO_PKG_IA_C0_ANY_RATIO event_counter Accumulates the number of active (RC0) GT clock cycles. The original counter is in 64 clocks increments.**NOT IMPLEMENTED** Counter Container_259 GT_RC0_CLOCKS gt_clk_cnt Counts the time that GT took to go through the RC6 flow (including context save) after all conditions to enter RC6 were met. **NOT IMPLEMENTED** Counter Container_260 RC6_ENTRY_OVERHEAD xtal_time Counts the dead time spent between end of GT RC6 wake sequence and GT engine actually starting to execute**NOT IMPLEMENTED** Counter Container_261 RC6_WAKE_OVERHEAD xtal_time CEP EVENT1 counter Counter Container_262 CEP_SA_RESIDENCY_COUNTER event_counter CEP EVENT1 counter Counter Container_262 CEP_GT_RESIDENCY_COUNTER event_counter FastVmode counter Counter Container_263 FAST_VMODE_SA_COUNTER event_counter FastVmode counter Counter Container_263 FAST_VMODE_GT_COUNTER event_counter Reserved for future expansion Counter Container_264 CNTR_RESERVED_0 passthru Reserved for future expansion Counter Container_265 CNTR_RESERVED_1_to_152 passthru Reserved for future expansion Counter Container_266 CNTR_RESERVED_1_to_152_1 passthru Reserved for future expansion Counter Container_267 CNTR_RESERVED_1_to_152_2 passthru Reserved for future expansion Counter Container_268 CNTR_RESERVED_1_to_152_3 passthru Reserved for future expansion Counter Container_269 CNTR_RESERVED_1_to_152_4 passthru Reserved for future expansion Counter Container_270 CNTR_RESERVED_1_to_152_5 passthru Reserved for future expansion Counter Container_271 CNTR_RESERVED_1_to_152_6 passthru Reserved for future expansion Counter Container_272 CNTR_RESERVED_1_to_152_7 passthru Reserved for future expansion Counter Container_273 CNTR_RESERVED_1_to_152_8 passthru Reserved for future expansion Counter Container_274 CNTR_RESERVED_1_to_152_9 passthru Reserved for future expansion Counter Container_275 CNTR_RESERVED_1_to_152_10 passthru Reserved for future expansion Counter Container_276 CNTR_RESERVED_1_to_152_11 passthru Reserved for future expansion Counter Container_277 CNTR_RESERVED_1_to_152_12 passthru Reserved for future expansion Counter Container_278 CNTR_RESERVED_1_to_152_13 passthru Reserved for future expansion Counter Container_279 CNTR_RESERVED_1_to_152_14 passthru Reserved for future expansion Counter Container_280 CNTR_RESERVED_1_to_152_15 passthru Reserved for future expansion Counter Container_281 CNTR_RESERVED_1_to_152_16 passthru Reserved for future expansion Counter Container_282 CNTR_RESERVED_1_to_152_17 passthru Reserved for future expansion Counter Container_283 CNTR_RESERVED_1_to_152_18 passthru Reserved for future expansion Counter Container_284 CNTR_RESERVED_1_to_152_19 passthru Reserved for future expansion Counter Container_285 CNTR_RESERVED_1_to_152_20 passthru Reserved for future expansion Counter Container_286 CNTR_RESERVED_1_to_152_21 passthru Reserved for future expansion Counter Container_287 CNTR_RESERVED_1_to_152_22 passthru Reserved for future expansion Counter Container_288 CNTR_RESERVED_1_to_152_23 passthru Reserved for future expansion Counter Container_289 CNTR_RESERVED_1_to_152_24 passthru Reserved for future expansion Counter Container_290 CNTR_RESERVED_1_to_152_25 passthru Reserved for future expansion Counter Container_291 CNTR_RESERVED_1_to_152_26 passthru Reserved for future expansion Counter Container_292 CNTR_RESERVED_1_to_152_27 passthru Reserved for future expansion Counter Container_293 CNTR_RESERVED_1_to_152_28 passthru Reserved for future expansion Counter Container_294 CNTR_RESERVED_1_to_152_29 passthru Reserved for future expansion Counter Container_295 CNTR_RESERVED_1_to_152_30 passthru Reserved for future expansion Counter Container_296 CNTR_RESERVED_1_to_152_31 passthru Reserved for future expansion Counter Container_297 CNTR_RESERVED_1_to_152_32 passthru Reserved for future expansion Counter Container_298 CNTR_RESERVED_1_to_152_33 passthru Reserved for future expansion Counter Container_299 CNTR_RESERVED_1_to_152_34 passthru Reserved for future expansion Counter Container_300 CNTR_RESERVED_1_to_152_35 passthru Reserved for future expansion Counter Container_301 CNTR_RESERVED_1_to_152_36 passthru Reserved for future expansion Counter Container_302 CNTR_RESERVED_1_to_152_37 passthru Reserved for future expansion Counter Container_303 CNTR_RESERVED_1_to_152_38 passthru Reserved for future expansion Counter Container_304 CNTR_RESERVED_1_to_152_39 passthru Reserved for future expansion Counter Container_305 CNTR_RESERVED_1_to_152_40 passthru Reserved for future expansion Counter Container_306 CNTR_RESERVED_1_to_152_41 passthru Reserved for future expansion Counter Container_307 CNTR_RESERVED_1_to_152_42 passthru Reserved for future expansion Counter Container_308 CNTR_RESERVED_1_to_152_43 passthru Reserved for future expansion Counter Container_309 CNTR_RESERVED_1_to_152_44 passthru Reserved for future expansion Counter Container_310 CNTR_RESERVED_1_to_152_45 passthru Reserved for future expansion Counter Container_311 CNTR_RESERVED_1_to_152_46 passthru Reserved for future expansion Counter Container_312 CNTR_RESERVED_1_to_152_47 passthru Reserved for future expansion Counter Container_313 CNTR_RESERVED_1_to_152_48 passthru Reserved for future expansion Counter Container_314 CNTR_RESERVED_1_to_152_49 passthru Reserved for future expansion Counter Container_315 CNTR_RESERVED_1_to_152_50 passthru Reserved for future expansion Counter Container_316 CNTR_RESERVED_1_to_152_51 passthru Reserved for future expansion Counter Container_317 CNTR_RESERVED_1_to_152_52 passthru Reserved for future expansion Counter Container_318 CNTR_RESERVED_1_to_152_53 passthru Reserved for future expansion Counter Container_319 CNTR_RESERVED_1_to_152_54 passthru Reserved for future expansion Counter Container_320 CNTR_RESERVED_1_to_152_55 passthru Reserved for future expansion Counter Container_321 CNTR_RESERVED_1_to_152_56 passthru Reserved for future expansion Counter Container_322 CNTR_RESERVED_1_to_152_57 passthru Reserved for future expansion Counter Container_323 CNTR_RESERVED_1_to_152_58 passthru Reserved for future expansion Counter Container_324 CNTR_RESERVED_1_to_152_59 passthru Reserved for future expansion Counter Container_325 CNTR_RESERVED_1_to_152_60 passthru Reserved for future expansion Counter Container_326 CNTR_RESERVED_1_to_152_61 passthru Reserved for future expansion Counter Container_327 CNTR_RESERVED_1_to_152_62 passthru Reserved for future expansion Counter Container_328 CNTR_RESERVED_1_to_152_63 passthru Reserved for future expansion Counter Container_329 CNTR_RESERVED_1_to_152_64 passthru Reserved for future expansion Counter Container_330 CNTR_RESERVED_1_to_152_65 passthru Reserved for future expansion Counter Container_331 CNTR_RESERVED_1_to_152_66 passthru Reserved for future expansion Counter Container_332 CNTR_RESERVED_1_to_152_67 passthru Reserved for future expansion Counter Container_333 CNTR_RESERVED_1_to_152_68 passthru Reserved for future expansion Counter Container_334 CNTR_RESERVED_1_to_152_69 passthru Reserved for future expansion Counter Container_335 CNTR_RESERVED_1_to_152_70 passthru Reserved for future expansion Counter Container_336 CNTR_RESERVED_1_to_152_71 passthru Reserved for future expansion Counter Container_337 CNTR_RESERVED_1_to_152_72 passthru Reserved for future expansion Counter Container_338 CNTR_RESERVED_1_to_152_73 passthru Reserved for future expansion Counter Container_339 CNTR_RESERVED_1_to_152_74 passthru Reserved for future expansion Counter Container_340 CNTR_RESERVED_1_to_152_75 passthru Reserved for future expansion Counter Container_341 CNTR_RESERVED_1_to_152_76 passthru Reserved for future expansion Counter Container_342 CNTR_RESERVED_1_to_152_77 passthru Reserved for future expansion Counter Container_343 CNTR_RESERVED_1_to_152_78 passthru Reserved for future expansion Counter Container_344 CNTR_RESERVED_1_to_152_79 passthru Reserved for future expansion Counter Container_345 CNTR_RESERVED_1_to_152_80 passthru Reserved for future expansion Counter Container_346 CNTR_RESERVED_1_to_152_81 passthru Reserved for future expansion Counter Container_347 CNTR_RESERVED_1_to_152_82 passthru Reserved for future expansion Counter Container_348 CNTR_RESERVED_1_to_152_83 passthru Reserved for future expansion Counter Container_349 CNTR_RESERVED_1_to_152_84 passthru Reserved for future expansion Counter Container_350 CNTR_RESERVED_1_to_152_85 passthru Reserved for future expansion Counter Container_351 CNTR_RESERVED_1_to_152_86 passthru Reserved for future expansion Counter Container_352 CNTR_RESERVED_1_to_152_87 passthru Reserved for future expansion Counter Container_353 CNTR_RESERVED_1_to_152_88 passthru Reserved for future expansion Counter Container_354 CNTR_RESERVED_1_to_152_89 passthru Reserved for future expansion Counter Container_355 CNTR_RESERVED_1_to_152_90 passthru Reserved for future expansion Counter Container_356 CNTR_RESERVED_1_to_152_91 passthru Reserved for future expansion Counter Container_357 CNTR_RESERVED_1_to_152_92 passthru Reserved for future expansion Counter Container_358 CNTR_RESERVED_1_to_152_93 passthru Reserved for future expansion Counter Container_359 CNTR_RESERVED_1_to_152_94 passthru Reserved for future expansion Counter Container_360 CNTR_RESERVED_1_to_152_95 passthru Reserved for future expansion Counter Container_361 CNTR_RESERVED_1_to_152_96 passthru Reserved for future expansion Counter Container_362 CNTR_RESERVED_1_to_152_97 passthru Reserved for future expansion Counter Container_363 CNTR_RESERVED_1_to_152_98 passthru Reserved for future expansion Counter Container_364 CNTR_RESERVED_1_to_152_99 passthru Reserved for future expansion Counter Container_365 CNTR_RESERVED_1_to_152_100 passthru Reserved for future expansion Counter Container_366 CNTR_RESERVED_1_to_152_101 passthru Reserved for future expansion Counter Container_367 CNTR_RESERVED_1_to_152_102 passthru Reserved for future expansion Counter Container_368 CNTR_RESERVED_1_to_152_103 passthru Reserved for future expansion Counter Container_369 CNTR_RESERVED_1_to_152_104 passthru Reserved for future expansion Counter Container_370 CNTR_RESERVED_1_to_152_105 passthru Reserved for future expansion Counter Container_371 CNTR_RESERVED_1_to_152_106 passthru Reserved for future expansion Counter Container_372 CNTR_RESERVED_1_to_152_107 passthru Reserved for future expansion Counter Container_373 CNTR_RESERVED_1_to_152_108 passthru Reserved for future expansion Counter Container_374 CNTR_RESERVED_1_to_152_109 passthru Reserved for future expansion Counter Container_375 CNTR_RESERVED_1_to_152_110 passthru Reserved for future expansion Counter Container_376 CNTR_RESERVED_1_to_152_111 passthru Reserved for future expansion Counter Container_377 CNTR_RESERVED_1_to_152_112 passthru Reserved for future expansion Counter Container_378 CNTR_RESERVED_1_to_152_113 passthru Reserved for future expansion Counter Container_379 CNTR_RESERVED_1_to_152_114 passthru Reserved for future expansion Counter Container_380 CNTR_RESERVED_1_to_152_115 passthru Reserved for future expansion Counter Container_381 CNTR_RESERVED_1_to_152_116 passthru Reserved for future expansion Counter Container_382 CNTR_RESERVED_1_to_152_117 passthru Reserved for future expansion Counter Container_383 CNTR_RESERVED_1_to_152_118 passthru Reserved for future expansion Counter Container_384 CNTR_RESERVED_1_to_152_119 passthru Reserved for future expansion Counter Container_385 CNTR_RESERVED_1_to_152_120 passthru Reserved for future expansion Counter Container_386 CNTR_RESERVED_1_to_152_121 passthru Reserved for future expansion Counter Container_387 CNTR_RESERVED_1_to_152_122 passthru Reserved for future expansion Counter Container_388 CNTR_RESERVED_1_to_152_123 passthru Reserved for future expansion Counter Container_389 CNTR_RESERVED_1_to_152_124 passthru Reserved for future expansion Counter Container_390 CNTR_RESERVED_1_to_152_125 passthru Reserved for future expansion Counter Container_391 CNTR_RESERVED_1_to_152_126 passthru Reserved for future expansion Counter Container_392 CNTR_RESERVED_1_to_152_127 passthru Reserved for future expansion Counter Container_393 CNTR_RESERVED_1_to_152_128 passthru Reserved for future expansion Counter Container_394 CNTR_RESERVED_1_to_152_129 passthru Reserved for future expansion Counter Container_395 CNTR_RESERVED_1_to_152_130 passthru Reserved for future expansion Counter Container_396 CNTR_RESERVED_1_to_152_131 passthru Reserved for future expansion Counter Container_397 CNTR_RESERVED_1_to_152_132 passthru Reserved for future expansion Counter Container_398 CNTR_RESERVED_1_to_152_133 passthru Reserved for future expansion Counter Container_399 CNTR_RESERVED_1_to_152_134 passthru Reserved for future expansion Counter Container_400 CNTR_RESERVED_1_to_152_135 passthru Reserved for future expansion Counter Container_401 CNTR_RESERVED_1_to_152_136 passthru Reserved for future expansion Counter Container_402 CNTR_RESERVED_1_to_152_137 passthru Reserved for future expansion Counter Container_403 CNTR_RESERVED_1_to_152_138 passthru Reserved for future expansion Counter Container_404 CNTR_RESERVED_1_to_152_139 passthru Reserved for future expansion Counter Container_405 CNTR_RESERVED_1_to_152_140 passthru Reserved for future expansion Counter Container_406 CNTR_RESERVED_1_to_152_141 passthru Reserved for future expansion Counter Container_407 CNTR_RESERVED_1_to_152_142 passthru Reserved for future expansion Counter Container_408 CNTR_RESERVED_1_to_152_143 passthru Reserved for future expansion Counter Container_409 CNTR_RESERVED_1_to_152_144 passthru Reserved for future expansion Counter Container_410 CNTR_RESERVED_1_to_152_145 passthru Reserved for future expansion Counter Container_411 CNTR_RESERVED_1_to_152_146 passthru Reserved for future expansion Counter Container_412 CNTR_RESERVED_1_to_152_147 passthru Reserved for future expansion Counter Container_413 CNTR_RESERVED_1_to_152_148 passthru Reserved for future expansion Counter Container_414 CNTR_RESERVED_1_to_152_149 passthru Reserved for future expansion Counter Container_415 CNTR_RESERVED_1_to_152_150 passthru Reserved for future expansion Counter Container_416 CNTR_RESERVED_1_to_152_151 passthru