float parameter_0 $parameter_0 / 38.4 * 1e6 float parameter_0 $parameter_0 * 0.0025 float parameter_0 $parameter_0 * 64 / 1e6 float parameter_0 $parameter_0 / 1e6 float parameter_0 $parameter_0 * 32 / 1e6 float parameter_0 $parameter_0 / 1e3 float parameter_0 $parameter_0 float parameter_0 $parameter_0 float parameter_0 $parameter_0 / 1048576 float parameter_0 ( 49 + $parameter_0 ) * 0.005 integer parameter_0 ( ( ( 1 - ( ( $parameter_0 >> 7 ) & 0x1 ) ) * ( $parameter_0 & 0xff ) ) - ( ( ( $parameter_0 >> 7 ) & 0x1 ) * ( ( ( $parameter_0 & 0x7f ) ^ 0x7f ) + 1 ) ) ) float parameter_0 $parameter_0 float parameter_0 ( $parameter_0 & 0xff ) / ( 2**7 ) float parameter_0 ( $parameter_0 & 0x3ff ) / ( 2**3 ) float parameter_0 $parameter_0 * 0.1 float parameter_0 $parameter_0 * 0.01667 float parameter_0 $parameter_0 * 0.025 float parameter_0 $parameter_0 * 0.033 float parameter_0 ( $parameter_0 & 0xffff ) / ( 2**8 ) float parameter_0 ( $parameter_0 & 0x1ff ) / ( 2**8 ) float parameter_0 $parameter_0 * 100 / 16 float parameter_0 ( $parameter_0 & 0xffff ) / ( 2**15 ) float parameter_0 $parameter_0 * 0.002 float parameter_0 ( $parameter_0 & 0x7ff ) / ( 2**2 ) float parameter_0 ( $parameter_0 & 0xffffffff ) / ( 2**14 ) float parameter_0 $parameter_0 / 16384 float parameter_0 $parameter_0 * 64 float parameter_0 $parameter_0 * 0.025 * 33.33 float parameter_0 $parameter_0 * 0.025 / 1e6 float parameter_0 $parameter_0 integer parameter_0 $parameter_0 MTL MTL M/P PMT Normal telemetry in DMU samples definition and transformation rules 0x1A067002 Public 10 2024-09-06 revision of the xml Snapshot Container_0 LOCAL_VERSION passthru product id Snapshot Container_0 PRODUCT_ID passthru source id for data provider Snapshot Container_0 SOURCEID passthru reserved Snapshot Container_0 reserved passthru Represents the clock rate of the XTAL on this silicon.1: 19.2MHz - 19.2e60: 24MHz - 24e63: 25MHz - 25e62: 38.4MHz - 38.4e6 Snapshot Container_0 XTAL_FREQ passthru Snapshot Container_0 reserved_1 passthru Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_1 VOLTAGE wp_volts Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_1 CURRENT U10.7.3 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_1 PS_OVERRIDE passthru IA Module clock ratio, in units of 100MHz. Snapshot Container_1 FREQ ratio_100 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_1 VOLTAGE_1 wp_volts Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_1 CURRENT_1 U10.7.3 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_1 PS_OVERRIDE_1 passthru IA Module clock ratio, in units of 100MHz. Snapshot Container_1 FREQ_1 ratio_100 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_2 VOLTAGE_2 wp_volts Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_2 CURRENT_2 U10.7.3 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_2 PS_OVERRIDE_2 passthru IA Module clock ratio, in units of 100MHz. Snapshot Container_2 FREQ_2 ratio_100 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_2 VOLTAGE_3 wp_volts Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_2 CURRENT_3 U10.7.3 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_2 PS_OVERRIDE_3 passthru IA Module clock ratio, in units of 100MHz. Snapshot Container_2 FREQ_3 ratio_100 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_3 VOLTAGE_4 wp_volts Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_3 CURRENT_4 U10.7.3 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_3 PS_OVERRIDE_4 passthru IA Module clock ratio, in units of 100MHz. Snapshot Container_3 FREQ_4 ratio_100 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_3 VOLTAGE_5 wp_volts Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_3 CURRENT_5 U10.7.3 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_3 PS_OVERRIDE_5 passthru IA Module clock ratio, in units of 100MHz. Snapshot Container_3 FREQ_5 ratio_100 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_4 VOLTAGE_6 wp_volts Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_4 CURRENT_6 U10.7.3 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_4 PS_OVERRIDE_6 passthru IA Module clock ratio, in units of 100MHz. Snapshot Container_4 FREQ_6 ratio_100 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_4 VOLTAGE_7 wp_volts Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_4 CURRENT_7 U10.7.3 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_4 PS_OVERRIDE_7 passthru IA Module clock ratio, in units of 100MHz. Snapshot Container_4 FREQ_7 ratio_100 Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_5 VOLTAGE_8 wp_volts Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_5 CURRENT_8 U10.7.3 Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. Snapshot Container_5 PS_OVERRIDE_8 passthru Ring clock ratio, in units of 100MHz. Snapshot Container_5 FREQ_8 ratio_100 beta value Snapshot Container_5 BETA U16.1.15 CEP theshold Snapshot Container_5 CEP_THRESHOLD cep_volts VID Code. Encoding is based on SVID spec. Snapshot Container_6 VID vid VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 Snapshot Container_6 PS passthru Issue FAST ramp, instead of SLOW ramp. Snapshot Container_6 FAST passthru Issue DECAY ramp, instead of SLOW ramp. Only going down. Snapshot Container_6 DECAY passthru Snapshot Container_6 reserved_2 passthru Last current sample, in amps. Snapshot Container_6 AMPS U16.8.8 IA Core C-state of BigCore0: C01: C13: C67: CRST Snapshot Container_7 CORE0 passthru IA Core C-state of BigCore0: C01: C13: C67: CRST Snapshot Container_7 CORE1 passthru IA Core C-state of BigCore0: C01: C13: C67: CRST Snapshot Container_7 CORE2 passthru IA Core C-state of BigCore0: C01: C13: C67: CRST Snapshot Container_7 CORE3 passthru IA Core C-state of BigCore0: C01: C13: C67: CRST Snapshot Container_7 CORE4 passthru IA Core C-state of BigCore0: C01: C13: C67: CRST Snapshot Container_7 CORE5 passthru IA Core C-state of Atom core0: C01: C13: C67: CRST Snapshot Container_7 Atom_Core0 passthru IA Core C-state of Atom core0: C01: C13: C67: CRST Snapshot Container_7 Atom_Core1 passthru IA Core C-state of Atom core0: C01: C13: C67: CRST Snapshot Container_7 Atom_Core2 passthru IA Core C-state of Atom core0: C01: C13: C67: CRST Snapshot Container_7 Atom_Core3 passthru IA Core C-state of Atom core0: C01: C13: C67: CRST Snapshot Container_7 Atom_Core4 passthru IA Core C-state of Atom core0: C01: C13: C67: CRST Snapshot Container_7 Atom_Core5 passthru IA Core C-state of Atom core0: C01: C13: C67: CRST Snapshot Container_7 Atom_Core6 passthru IA Core C-state of Atom core0: C01: C13: C67: CRST Snapshot Container_7 Atom_Core7 passthru LLC/Ring C-state0: C0 - 02: C3 - 23: C6 - 37: RST - 7 Snapshot Container_7 Ring passthru reserved Snapshot Container_7 reserved_3 passthru Cdyn level granted Snapshot Container_8 CORE0_1 passthru Cdyn level granted Snapshot Container_8 CORE1_1 passthru Cdyn level granted Snapshot Container_8 CORE2_1 passthru Cdyn level granted Snapshot Container_8 CORE3_1 passthru Cdyn level granted Snapshot Container_8 CORE4_1 passthru Cdyn level granted Snapshot Container_8 CORE5_1 passthru Snapshot Container_8 reserved_4 passthru Min temp Snapshot Container_8 DTS0 S8.7.0 Max temp Snapshot Container_8 DTS1 S8.7.0 NA - not updated by Pcode Snapshot Container_8 DTS2 passthru NA - not updated by Pcode Snapshot Container_8 DTS3 passthru Min temp Snapshot Container_9 DTS0_1 S8.7.0 Max temp Snapshot Container_9 DTS1_1 S8.7.0 NA - not updated by Pcode Snapshot Container_9 DTS2_1 passthru NA - not updated by Pcode Snapshot Container_9 DTS3_1 passthru Min temp Snapshot Container_9 DTS0_2 S8.7.0 Max temp Snapshot Container_9 DTS1_2 S8.7.0 NA - not updated by Pcode Snapshot Container_9 DTS2_2 passthru NA - not updated by Pcode Snapshot Container_9 DTS3_2 passthru Min temp Snapshot Container_10 DTS0_3 S8.7.0 Max temp Snapshot Container_10 DTS1_3 S8.7.0 NA - not updated by Pcode Snapshot Container_10 DTS2_3 passthru NA - not updated by Pcode Snapshot Container_10 DTS3_3 passthru Min temp Snapshot Container_10 DTS0_4 S8.7.0 Max temp Snapshot Container_10 DTS1_4 S8.7.0 NA - not updated by Pcode Snapshot Container_10 DTS2_4 passthru NA - not updated by Pcode Snapshot Container_10 DTS3_4 passthru Min temp Snapshot Container_11 DTS0_5 S8.7.0 Max temp Snapshot Container_11 DTS1_5 S8.7.0 NA - not updated by Pcode Snapshot Container_11 DTS2_5 passthru NA - not updated by Pcode Snapshot Container_11 DTS3_5 passthru Min temp Snapshot Container_11 DTS0_6 S8.7.0 Max temp Snapshot Container_11 DTS1_6 S8.7.0 NA - not updated by Pcode Snapshot Container_11 DTS2_6 passthru NA - not updated by Pcode Snapshot Container_11 DTS3_6 passthru Min temp Snapshot Container_12 DTS0_7 S8.7.0 Max temp Snapshot Container_12 DTS1_7 S8.7.0 NA - not updated by Pcode Snapshot Container_12 DTS2_7 passthru NA - not updated by Pcode Snapshot Container_12 DTS3_7 passthru Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_12 CORE U9.1.8 Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_12 CORE_1 U9.1.8 Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_13 CORE_2 U9.1.8 Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_13 CORE_3 U9.1.8 Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_13 CORE_4 U9.1.8 Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_13 CORE_5 U9.1.8 Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_14 CORE_6 U9.1.8 Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_14 CORE_7 U9.1.8 Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_14 CORE_8 U9.1.8 Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_14 CORE_9 U9.1.8 Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_15 CORE_10 U9.1.8 Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_15 CORE_11 U9.1.8 Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_15 CORE_12 U9.1.8 Current atom module scalability measurement. Calculated as unstalled clocks divided by total active clocks. Snapshot Container_15 CORE_13 U9.1.8 P_alpha calculation. This represents the maximum allowed clock frequency on that core. Snapshot Container_16 RATIO ratio_100 P_alpha calculation. This represents the maximum allowed clock frequency on that core. Snapshot Container_16 RATIO_1 ratio_100 P_alpha calculation. This represents the maximum allowed clock frequency on that core. Snapshot Container_16 RATIO_2 ratio_100 P_alpha calculation. This represents the maximum allowed clock frequency on that core. Snapshot Container_16 RATIO_3 ratio_100 P_alpha calculation. This represents the maximum allowed clock frequency on that core. Snapshot Container_16 RATIO_4 ratio_100 P_alpha calculation. This represents the maximum allowed clock frequency on that core. Snapshot Container_16 RATIO_5 ratio_100 P_alpha calculation. This represents the maximum allowed clock frequency on that core. Snapshot Container_16 RATIO_6 ratio_100 P_alpha calculation. This represents the maximum allowed clock frequency on that core. Snapshot Container_16 RATIO_7 ratio_100 Current autonomous frequency target for that IA module Snapshot Container_17 RATIO_8 ratio_100 Current autonomous frequency target for that IA module Snapshot Container_17 RATIO_9 ratio_100 Current autonomous frequency target for that IA module Snapshot Container_17 RATIO_10 ratio_100 Current autonomous frequency target for that IA module Snapshot Container_17 RATIO_11 ratio_100 Current autonomous frequency target for that IA module Snapshot Container_17 RATIO_12 ratio_100 Current autonomous frequency target for that IA module Snapshot Container_17 RATIO_13 ratio_100 Current autonomous frequency target for that IA module Snapshot Container_17 RATIO_14 ratio_100 Current autonomous frequency target for that IA module Snapshot Container_17 RATIO_15 ratio_100 Current efficient frequency target for that IA module Snapshot Container_18 IA_PE ratio_100 Current efficient frequency target for that IA module Snapshot Container_18 IA_PE_1 ratio_100 Current efficient frequency target for that IA module Snapshot Container_18 IA_PE_2 ratio_100 Current efficient frequency target for that IA module Snapshot Container_18 IA_PE_3 ratio_100 Current efficient frequency target for that IA module Snapshot Container_18 IA_PE_4 ratio_100 Current efficient frequency target for that IA module Snapshot Container_18 IA_PE_5 ratio_100 Current efficient frequency target for that IA module Snapshot Container_18 IA_PE_6 ratio_100 Current efficient frequency target for that IA module Snapshot Container_18 IA_PE_7 ratio_100 Peak current observed Snapshot Container_19 PEAK_CURRENT U11.9.2 Sample current Global IMON Summation input Snapshot Container_19 SIRP_CURRENT_INPUT_TOTAL_IMON U11.9.2 Upper 10 bits of a 16 bit counter, incremented for each 2.5ns clock cycle Throttle is asserted. 16 bit counter incr @ 2.5n = 163 us with ~150 ns granularity due to lower 6 bits hidden. Snapshot Container_19 THROTTLE_ACCUM passthru Low Threshold for Global IMON Sum Snapshot Container_19 IMON_LOW_THRESHOLD U11.9.2 High Threshold for Global IMON Sum Snapshot Container_19 IMON_HIGH_THRESHOLD U11.9.2 reserved Snapshot Container_19 res passthru reserved Snapshot Container_20 rsvd passthru reserved Snapshot Container_21 rsvd_1 passthru reserved Snapshot Container_22 rsvd_2 passthru reserved Snapshot Container_23 rsvd_3 passthru reserved Snapshot Container_24 rsvd_4 passthru reserved Snapshot Container_25 rsvd_5 passthru reserved Snapshot Container_26 rsvd_6 passthru reserved Snapshot Container_27 rsvd_7 passthru reserved Snapshot Container_28 rsvd_8 passthru reserved Snapshot Container_29 rsvd_9 passthru reserved Snapshot Container_30 rsvd_10 passthru reserved Snapshot Container_31 rsvd_11 passthru reserved Snapshot Container_32 rsvd_12 passthru reserved Snapshot Container_33 rsvd_13 passthru reserved Snapshot Container_34 rsvd_14 passthru reserved Snapshot Container_35 rsvd_15 passthru reserved Snapshot Container_36 rsvd_16 passthru slow limit THERM has limited performance for CCP0 Counter Container_37 PERF_LIMIT_THERM_RESIDENCY_CCP_0 xtal_time slow limit THERM has limited performance for CCP1 Counter Container_38 PERF_LIMIT_THERM_RESIDENCY_CCP_1 xtal_time slow limit THERM has limited performance for CCP2 Counter Container_39 PERF_LIMIT_THERM_RESIDENCY_CCP_2 xtal_time slow limit THERM has limited performance for CCP3 Counter Container_40 PERF_LIMIT_THERM_RESIDENCY_CCP_3 xtal_time slow limit THERM has limited performance for CCP4 Counter Container_41 PERF_LIMIT_THERM_RESIDENCY_CCP_4 xtal_time slow limit THERM has limited performance for CCP5 Counter Container_42 PERF_LIMIT_THERM_RESIDENCY_CCP_5 xtal_time slow limit THERM has limited performance for CCP6 Counter Container_43 PERF_LIMIT_THERM_RESIDENCY_CCP_6 xtal_time slow limit THERM has limited performance for CCP7 Counter Container_44 PERF_LIMIT_THERM_RESIDENCY_CCP_7 xtal_time slow limit THERM has limited performance for LLC. Counter Container_45 PERF_LIMIT_THERM_LLC_RESIDENCY xtal_time slow limit POWER has limited performance for CCP0 Counter Container_46 PERF_LIMIT_POWER_RESIDENCY_CCP_0 xtal_time slow limit POWER has limited performance for CCP1 Counter Container_47 PERF_LIMIT_POWER_RESIDENCY_CCP_1 xtal_time slow limit POWER has limited performance for CCP2 Counter Container_48 PERF_LIMIT_POWER_RESIDENCY_CCP_2 xtal_time slow limit POWER has limited performance for CCP3 Counter Container_49 PERF_LIMIT_POWER_RESIDENCY_CCP_3 xtal_time slow limit POWER has limited performance for CCP4 Counter Container_50 PERF_LIMIT_POWER_RESIDENCY_CCP_4 xtal_time slow limit POWER has limited performance for CCP5 Counter Container_51 PERF_LIMIT_POWER_RESIDENCY_CCP_5 xtal_time slow limit POWER has limited performance for CCP6 Counter Container_52 PERF_LIMIT_POWER_RESIDENCY_CCP_6 xtal_time slow limit POWER has limited performance for CCP7 Counter Container_53 PERF_LIMIT_POWER_RESIDENCY_CCP_7 xtal_time slow limit EDP has limited performance for CCP0 Counter Container_54 PERF_LIMIT_EDP_RESIDENCY_CCP_0 xtal_time slow limit EDP has limited performance for CCP1 Counter Container_55 PERF_LIMIT_EDP_RESIDENCY_CCP_1 xtal_time slow limit EDP has limited performance for CCP2 Counter Container_56 PERF_LIMIT_EDP_RESIDENCY_CCP_2 xtal_time slow limit EDP has limited performance for CCP3 Counter Container_57 PERF_LIMIT_EDP_RESIDENCY_CCP_3 xtal_time slow limit EDP has limited performance for CCP4 Counter Container_58 PERF_LIMIT_EDP_RESIDENCY_CCP_4 xtal_time slow limit EDP has limited performance for CCP5 Counter Container_59 PERF_LIMIT_EDP_RESIDENCY_CCP_5 xtal_time slow limit EDP has limited performance for CCP6 Counter Container_60 PERF_LIMIT_EDP_RESIDENCY_CCP_6 xtal_time slow limit EDP has limited performance for CCP7 Counter Container_61 PERF_LIMIT_EDP_RESIDENCY_CCP_7 xtal_time slow limit EDP has limited performance for LLC. Counter Container_62 PERF_LIMIT_EDP_LLC_RESIDENCY xtal_time slow limit OTHER has limited performance for CCP0 Counter Container_63 PERF_LIMIT_OTHER_RESIDENCY_CCP_0 xtal_time slow limit OTHER has limited performance for CCP1 Counter Container_64 PERF_LIMIT_OTHER_RESIDENCY_CCP_1 xtal_time slow limit OTHER has limited performance for CCP2 Counter Container_65 PERF_LIMIT_OTHER_RESIDENCY_CCP_2 xtal_time slow limit OTHER has limited performance for CCP3 Counter Container_66 PERF_LIMIT_OTHER_RESIDENCY_CCP_3 xtal_time slow limit OTHER has limited performance for CCP4 Counter Container_67 PERF_LIMIT_OTHER_RESIDENCY_CCP_4 xtal_time slow limit OTHER has limited performance for CCP5 Counter Container_68 PERF_LIMIT_OTHER_RESIDENCY_CCP_5 xtal_time slow limit OTHER has limited performance for CCP6 Counter Container_69 PERF_LIMIT_OTHER_RESIDENCY_CCP_6 xtal_time slow limit OTHER has limited performance for CCP7 Counter Container_70 PERF_LIMIT_OTHER_RESIDENCY_CCP_7 xtal_time slow limit OTHER has limited performance for LLC. Counter Container_71 PERF_LIMIT_OTHER_LLC_RESIDENCY xtal_time prochot assertions. Counter Container_72 PROCHOT_RESIDENCY xtal_time VCCIA VR asserted VRHOT. Counter Container_73 VCCIA_VRHOT_RESIDENCY xtal_time C6 residency counter for Core0 Counter Container_74 C6_RESIDENCY_CORE0 xtal_time C6 residency counter for Core1 Counter Container_75 C6_RESIDENCY_CORE1 xtal_time C6 residency counter for Core2 Counter Container_76 C6_RESIDENCY_CORE2 xtal_time C6 residency counter for Core3 Counter Container_77 C6_RESIDENCY_CORE3 xtal_time C6 residency counter for Core4 Counter Container_78 C6_RESIDENCY_CORE4 xtal_time C6 residency counter for Core5 Counter Container_79 C6_RESIDENCY_CORE5 xtal_time C6 residency counter for Core6 Counter Container_80 C6_RESIDENCY_CORE6 xtal_time C6 residency counter for Core7 Counter Container_81 C6_RESIDENCY_CORE7 xtal_time C6 residency counter for Core8 Counter Container_82 C6_RESIDENCY_CORE8 xtal_time C6 residency counter for Core9 Counter Container_83 C6_RESIDENCY_CORE9 xtal_time C6 residency counter for Core10 Counter Container_84 C6_RESIDENCY_CORE10 xtal_time C6 residency counter for Core11 Counter Container_85 C6_RESIDENCY_CORE11 xtal_time C6 residency counter for Core12 Counter Container_86 C6_RESIDENCY_CORE12 xtal_time C6 residency counter for Core13 Counter Container_87 C6_RESIDENCY_CORE13 xtal_time LLC retention Counter Container_88 RING_C3_RESIDENCY xtal_time LLC flushed and off Counter Container_89 RING_C6_RESIDENCY xtal_time C0 residency counter - Core0 Counter Container_90 C0_RESIDENCY_CORE0 xtal_time C0 residency counter - Core1 Counter Container_90 C0_RESIDENCY_CORE1 xtal_time C0 residency counter - Core2 Counter Container_91 C0_RESIDENCY_CORE2 xtal_time C0 residency counter - Core3 Counter Container_91 C0_RESIDENCY_CORE3 xtal_time C0 residency counter - Core4 Counter Container_92 C0_RESIDENCY_CORE4 xtal_time C0 residency counter - Core5 Counter Container_92 C0_RESIDENCY_CORE5 xtal_time C0 residency counter - Core6 Counter Container_93 C0_RESIDENCY_CORE6 xtal_time C0 residency counter - Core7 Counter Container_93 C0_RESIDENCY_CORE7 xtal_time C0 residency counter - Core8 Counter Container_94 C0_RESIDENCY_CORE8 xtal_time C0 residency counter - Core9 Counter Container_94 C0_RESIDENCY_CORE9 xtal_time C0 residency counter - Core10 Counter Container_95 C0_RESIDENCY_CORE10 xtal_time C0 residency counter - Core11 Counter Container_95 C0_RESIDENCY_CORE11 xtal_time C0 residency counter - Core12 Counter Container_96 C0_RESIDENCY_CORE12 xtal_time C0 residency counter - Core13 Counter Container_96 C0_RESIDENCY_CORE13 xtal_time Transition counter for when slow limit THERM has limited performance for CCP0 Counter Container_97 PERF_LIMIT_THERM_COUNTER_CCP_0 event_counter Transition counter for when slow limit THERM has limited performance for CCP1 Counter Container_97 PERF_LIMIT_THERM_COUNTER_CCP_1 event_counter Transition counter for when slow limit THERM has limited performance for CCP2 Counter Container_98 PERF_LIMIT_THERM_COUNTER_CCP_2 event_counter Transition counter for when slow limit THERM has limited performance for CCP3 Counter Container_98 PERF_LIMIT_THERM_COUNTER_CCP_3 event_counter Transition counter for when slow limit THERM has limited performance for CCP4 Counter Container_99 PERF_LIMIT_THERM_COUNTER_CCP_4 event_counter Transition counter for when slow limit THERM has limited performance for CCP5 Counter Container_99 PERF_LIMIT_THERM_COUNTER_CCP_5 event_counter Transition counter for when slow limit THERM has limited performance for CCP6 Counter Container_100 PERF_LIMIT_THERM_COUNTER_CCP_6 event_counter Transition counter for when slow limit THERM has limited performance for CCP7 Counter Container_100 PERF_LIMIT_THERM_COUNTER_CCP_7 event_counter Transition counter for when slow limit THERM has limited performance for LLC. Counter Container_101 PERF_LIMIT_THERM_LLC_COUNTER event_counter Transition counter for when slow limit POWER has limited performance for CCP0 Counter Container_101 PERF_LIMIT_POWER_COUNTER_CCP_0 event_counter Transition counter for when slow limit POWER has limited performance for CCP1 Counter Container_102 PERF_LIMIT_POWER_COUNTER_CCP_1 event_counter Transition counter for when slow limit POWER has limited performance for CCP2 Counter Container_102 PERF_LIMIT_POWER_COUNTER_CCP_2 event_counter Transition counter for when slow limit POWER has limited performance for CCP3 Counter Container_103 PERF_LIMIT_POWER_COUNTER_CCP_3 event_counter Transition counter for when slow limit POWER has limited performance for CCP4 Counter Container_103 PERF_LIMIT_POWER_COUNTER_CCP_4 event_counter Transition counter for when slow limit POWER has limited performance for CCP5 Counter Container_104 PERF_LIMIT_POWER_COUNTER_CCP_5 event_counter Transition counter for when slow limit POWER has limited performance for CCP6 Counter Container_104 PERF_LIMIT_POWER_COUNTER_CCP_6 event_counter Transition counter for when slow limit POWER has limited performance for CCP7 Counter Container_105 PERF_LIMIT_POWER_COUNTER_CCP_7 event_counter Transition counter for when slow limit POWER has limited performance for LLC. Counter Container_105 PERF_LIMIT_POWER_LLC_COUNTER event_counter Transition counter for when slow limit EDP has limited performance for CCP0 Counter Container_106 PERF_LIMIT_EDP_COUNTER_CCP_0 event_counter Transition counter for when slow limit EDP has limited performance for CCP1 Counter Container_106 PERF_LIMIT_EDP_COUNTER_CCP_1 event_counter Transition counter for when slow limit EDP has limited performance for CCP2 Counter Container_107 PERF_LIMIT_EDP_COUNTER_CCP_2 event_counter Transition counter for when slow limit EDP has limited performance for CCP3 Counter Container_107 PERF_LIMIT_EDP_COUNTER_CCP_3 event_counter Transition counter for when slow limit EDP has limited performance for CCP4 Counter Container_108 PERF_LIMIT_EDP_COUNTER_CCP_4 event_counter Transition counter for when slow limit EDP has limited performance for CCP5 Counter Container_108 PERF_LIMIT_EDP_COUNTER_CCP_5 event_counter Transition counter for when slow limit EDP has limited performance for CCP6 Counter Container_109 PERF_LIMIT_EDP_COUNTER_CCP_6 event_counter Transition counter for when slow limit EDP has limited performance for CCP7 Counter Container_109 PERF_LIMIT_EDP_COUNTER_CCP_7 event_counter Transition counter for when slow limit EDP has limited performance for LLC. Counter Container_110 PERF_LIMIT_EDP_LLC_COUNTER event_counter Transition counter for when slow limit OTHER has limited performance for CCP0 Counter Container_110 PERF_LIMIT_OTHER_COUNTER_CCP_0 event_counter Transition counter for when slow limit OTHER has limited performance for CCP1 Counter Container_111 PERF_LIMIT_OTHER_COUNTER_CCP_1 event_counter Transition counter for when slow limit OTHER has limited performance for CCP2 Counter Container_111 PERF_LIMIT_OTHER_COUNTER_CCP_2 event_counter Transition counter for when slow limit OTHER has limited performance for CCP3 Counter Container_112 PERF_LIMIT_OTHER_COUNTER_CCP_3 event_counter Transition counter for when slow limit OTHER has limited performance for CCP4 Counter Container_112 PERF_LIMIT_OTHER_COUNTER_CCP_4 event_counter Transition counter for when slow limit OTHER has limited performance for CCP5 Counter Container_113 PERF_LIMIT_OTHER_COUNTER_CCP_5 event_counter Transition counter for when slow limit OTHER has limited performance for CCP6 Counter Container_113 PERF_LIMIT_OTHER_COUNTER_CCP_6 event_counter Transition counter for when slow limit OTHER has limited performance for CCP7 Counter Container_114 PERF_LIMIT_OTHER_COUNTER_CCP_7 event_counter Transition counter for when slow limit OTHER has limited performance for LLC. Counter Container_114 PERF_LIMIT_OTHER_LLC_COUNTER event_counter IA VR energy Counter Container_115 VCCIA_ENERGY vr_energy Total LLC read bandwidth from CCP0 Counter Container_116 CCP_LLC_READS_0 bw_64B Total LLC read bandwidth from CCP1 Counter Container_117 CCP_LLC_READS_1 bw_64B Total LLC read bandwidth from CCP2 Counter Container_118 CCP_LLC_READS_2 bw_64B Total LLC read bandwidth from CCP3 Counter Container_119 CCP_LLC_READS_3 bw_64B Total LLC read bandwidth from CCP4 Counter Container_120 CCP_LLC_READS_4 bw_64B Total LLC read bandwidth from CCP5 Counter Container_121 CCP_LLC_READS_5 bw_64B Total LLC read bandwidth from CCP6 Counter Container_122 CCP_LLC_READS_6 bw_64B Total LLC read bandwidth from CCP7 Counter Container_123 CCP_LLC_READS_7 bw_64B Total LLC write bandwidth from CCP0 Counter Container_124 CCP_LLC_WRITES_0 bw_64B Total LLC write bandwidth from CCP1 Counter Container_125 CCP_LLC_WRITES_1 bw_64B Total LLC write bandwidth from CCP2 Counter Container_126 CCP_LLC_WRITES_2 bw_64B Total LLC write bandwidth from CCP3 Counter Container_127 CCP_LLC_WRITES_3 bw_64B Total LLC write bandwidth from CCP4 Counter Container_128 CCP_LLC_WRITES_4 bw_64B Total LLC write bandwidth from CCP5 Counter Container_129 CCP_LLC_WRITES_5 bw_64B Total LLC write bandwidth from CCP6 Counter Container_130 CCP_LLC_WRITES_6 bw_64B Total LLC write bandwidth from CCP7 Counter Container_131 CCP_LLC_WRITES_7 bw_64B Total active LLC clocks, simple counter in UCLK Counter Container_132 LLC_CLOCKS_ACTIVE event_counter prochot assertions. Counter Container_133 PROCHOT_COUNTER event_counter counts VCCIA VR asserted VRHOT occasions Counter Container_133 VCCIA_VRHOT_COUNTER event_counter C6 entry transition counter - Core0 Counter Container_134 CORE_CSTATE_C6_COUNTER_0 event_counter C6 entry transition counter - Core1 Counter Container_134 CORE_CSTATE_C6_COUNTER_1 event_counter C6 entry transition counter - Core2 Counter Container_135 CORE_CSTATE_C6_COUNTER_2 event_counter C6 entry transition counter - Core3 Counter Container_135 CORE_CSTATE_C6_COUNTER_3 event_counter C6 entry transition counter - Core4 Counter Container_136 CORE_CSTATE_C6_COUNTER_4 event_counter C6 entry transition counter - Core5 Counter Container_136 CORE_CSTATE_C6_COUNTER_5 event_counter RING retention counter Counter Container_137 RING_C3_COUNTER event_counter RING flushed and off counter Counter Container_137 RING_C6_COUNTER event_counter Counts the number of transitions (entry) to Die C-state with LLC_FLUSHED. Counter Container_138 DIE_CSTATE_COUNTS_LLC_FLUSHED event_counter Measures the number of transitions to DC2.1 Counter Container_138 DIE_CSTATE_COUNTS_C2p1 event_counter Measures the number of transitions to DCC2.2 Counter Container_139 DIE_CSTATE_COUNTS_C2p2 event_counter Measures the number of transitions to DC3.1. Counter Container_139 DIE_CSTATE_COUNTS_C3p1 event_counter Measures the number of transitions to DC3.2 Counter Container_140 DIE_CSTATE_COUNTS_C3p2 event_counter Measures the number of transitions to DC6 Counter Container_140 DIE_CSTATE_COUNTS_C6 event_counter CEP EVENT1 counter: Counts the x4 (400MHz) clocks spent in throttling Counter Container_141 CEP_IA_RESIDENCY_COUNTER cycle_count DLVR OUT accumulator - ** NOT IMPLEMENTED ZBBed** Counter Container_141 DLVR_IA_CORE_OUT_ACCUMULATOR_0 event_counter DLVR OUT accumulator - ** NOT IMPLEMENTED ZBBed** Counter Container_142 DLVR_IA_CORE_OUT_ACCUMULATOR_1 event_counter DLVR OUT accumulator- ** NOT IMPLEMENTED ZBBed** Counter Container_142 DLVR_IA_CORE_OUT_ACCUMULATOR_2 event_counter DLVR OUT accumulator- ** NOT IMPLEMENTED ZBBed** Counter Container_143 DLVR_IA_CORE_OUT_ACCUMULATOR_3 event_counter DLVR OUT accumulator- ** NOT IMPLEMENTED ZBBed** Counter Container_143 DLVR_IA_CORE_OUT_ACCUMULATOR_4 event_counter DLVR OUT accumulator- ** NOT IMPLEMENTED ZBBed** Counter Container_144 DLVR_IA_CORE_OUT_ACCUMULATOR_5 event_counter DLVR OUT accumulator- ** NOT IMPLEMENTED ZBBed** Counter Container_144 DLVR_IA_CORE_OUT_ACCUMULATOR_6 event_counter DLVR OUT accumulator- ** NOT IMPLEMENTED ZBBed** Counter Container_145 DLVR_IA_CORE_OUT_ACCUMULATOR_7 event_counter DLVR OUT num samples- ** NOT IMPLEMENTED ZBBed** Counter Container_145 DLVR_IA_CORE_OUT_NUM_SAMPLES_0 event_counter DLVR OUT num samples- ** NOT IMPLEMENTED ZBBed** Counter Container_146 DLVR_IA_CORE_OUT_NUM_SAMPLES_1 event_counter DLVR OUT num samples- ** NOT IMPLEMENTED ZBBed** Counter Container_146 DLVR_IA_CORE_OUT_NUM_SAMPLES_2 event_counter DLVR OUT num samples- ** NOT IMPLEMENTED ZBBed** Counter Container_147 DLVR_IA_CORE_OUT_NUM_SAMPLES_3 event_counter DLVR OUT num samples- ** NOT IMPLEMENTED ZBBed** Counter Container_147 DLVR_IA_CORE_OUT_NUM_SAMPLES_4 event_counter DLVR OUT num samples- ** NOT IMPLEMENTED ZBBed** Counter Container_148 DLVR_IA_CORE_OUT_NUM_SAMPLES_5 event_counter DLVR OUT num samples- ** NOT IMPLEMENTED ZBBed** Counter Container_148 DLVR_IA_CORE_OUT_NUM_SAMPLES_6 event_counter DLVR OUT num samples- ** NOT IMPLEMENTED ZBBed** Counter Container_149 DLVR_IA_CORE_OUT_NUM_SAMPLES_7 event_counter Event counter which count the number of fastvmode excursions Counter Container_149 FAST_VMODE_IA_COUNTER event_counter Reserved for future expansion Counter Container_150 CNTR_RESERVED_0 passthru Reserved for future expansion Counter Container_151 CNTR_RESERVED_1_to_1 passthru