float parameter_0 $parameter_0 * 61 integer parameter_0 ( $parameter_0 & 0xffffffff ) integer parameter_0 ( $parameter_0 & 0xfffffff ) integer parameter_0 ( $parameter_0 & 0xff ) integer parameter_0 ( $parameter_0 & 0xffffff ) float parameter_0 ( ( $parameter_0 >> 8 ) & 0xff ) + ( ( $parameter_0 & 0xff ) / ( 2 ** 8 ) ) - 64 float parameter_0 $parameter_0 * 61 float parameter_0 $parameter_0 * 61 float parameter_0 2.3 * ( 2 ** $parameter_0 ) float parameter_0 parameter_1 $parameter_0 / $parameter_1 integer parameter_0 $parameter_0 spr Sapphire Rapids PM PMT Telemetry samples definition and transformation rules 0x9956f43f Public 10 2024-07-23 Local Revision ID for this product. Snapshot Container_0 LOCAL_REVISION passthru Product ID Snapshot Container_0 PRODUCT_ID passthru Record Type Snapshot Container_0 RECORD_TYPE passthru Represents the clock rate of the crystal oscillator on this silicon. Snapshot Container_0 XTAL_FREQ passthru Core 0 / IDI Port 0 - core to uncore bandwidth Counter Container_1 C2U_BW U32.0 Core 0 / IDI Port 0 - uncore to core bandwidth Counter Container_1 U2C_BW U32.0 Core 1 / IDI Port 0 - core to uncore bandwidth Counter Container_2 C2U_BW_1 U32.0 Core 1 / IDI Port 0 - uncore to core bandwidth Counter Container_2 U2C_BW_1 U32.0 Core 2 / IDI Port 0 - core to uncore bandwidth Counter Container_3 C2U_BW_2 U32.0 Core 2 / IDI Port 0 - uncore to core bandwidth Counter Container_3 U2C_BW_2 U32.0 Core 3 / IDI Port 0 - core to uncore bandwidth Counter Container_4 C2U_BW_3 U32.0 Core 3 / IDI Port 0 - uncore to core bandwidth Counter Container_4 U2C_BW_3 U32.0 Core 4 / IDI Port 0 - core to uncore bandwidth Counter Container_5 C2U_BW_4 U32.0 Core 4 / IDI Port 0 - uncore to core bandwidth Counter Container_5 U2C_BW_4 U32.0 Core 5 / IDI Port 0 - core to uncore bandwidth Counter Container_6 C2U_BW_5 U32.0 Core 5 / IDI Port 0 - uncore to core bandwidth Counter Container_6 U2C_BW_5 U32.0 Core 6 / IDI Port 0 - core to uncore bandwidth Counter Container_7 C2U_BW_6 U32.0 Core 6 / IDI Port 0 - uncore to core bandwidth Counter Container_7 U2C_BW_6 U32.0 Core 7 / IDI Port 0 - core to uncore bandwidth Counter Container_8 C2U_BW_7 U32.0 Core 7 / IDI Port 0 - uncore to core bandwidth Counter Container_8 U2C_BW_7 U32.0 Core 8 / IDI Port 0 - core to uncore bandwidth Counter Container_9 C2U_BW_8 U32.0 Core 8 / IDI Port 0 - uncore to core bandwidth Counter Container_9 U2C_BW_8 U32.0 Core 9 / IDI Port 0 - core to uncore bandwidth Counter Container_10 C2U_BW_9 U32.0 Core 9 / IDI Port 0 - uncore to core bandwidth Counter Container_10 U2C_BW_9 U32.0 Core 10 / IDI Port 0 - core to uncore bandwidth Counter Container_11 C2U_BW_10 U32.0 Core 10 / IDI Port 0 - uncore to core bandwidth Counter Container_11 U2C_BW_10 U32.0 Core 11 / IDI Port 0 - core to uncore bandwidth Counter Container_12 C2U_BW_11 U32.0 Core 11 / IDI Port 0 - uncore to core bandwidth Counter Container_12 U2C_BW_11 U32.0 Core 12 / IDI Port 0 - core to uncore bandwidth Counter Container_13 C2U_BW_12 U32.0 Core 12 / IDI Port 0 - uncore to core bandwidth Counter Container_13 U2C_BW_12 U32.0 Core 13 / IDI Port 0 - core to uncore bandwidth Counter Container_14 C2U_BW_13 U32.0 Core 13 / IDI Port 0 - uncore to core bandwidth Counter Container_14 U2C_BW_13 U32.0 Core 14 / IDI Port 0 - core to uncore bandwidth Counter Container_15 C2U_BW_14 U32.0 Core 14 / IDI Port 0 - uncore to core bandwidth Counter Container_15 U2C_BW_14 U32.0 Core 15 / IDI Port 0 - core to uncore bandwidth Counter Container_16 C2U_BW_15 U32.0 Core 15 / IDI Port 0 - uncore to core bandwidth Counter Container_16 U2C_BW_15 U32.0 Core 16 / IDI Port 0 - core to uncore bandwidth Counter Container_17 C2U_BW_16 U32.0 Core 16 / IDI Port 0 - uncore to core bandwidth Counter Container_17 U2C_BW_16 U32.0 Core 17 / IDI Port 0 - core to uncore bandwidth Counter Container_18 C2U_BW_17 U32.0 Core 17 / IDI Port 0 - uncore to core bandwidth Counter Container_18 U2C_BW_17 U32.0 Core 18 / IDI Port 0 - core to uncore bandwidth Counter Container_19 C2U_BW_18 U32.0 Core 18 / IDI Port 0 - uncore to core bandwidth Counter Container_19 U2C_BW_18 U32.0 Core 19 / IDI Port 0 - core to uncore bandwidth Counter Container_20 C2U_BW_19 U32.0 Core 19 / IDI Port 0 - uncore to core bandwidth Counter Container_20 U2C_BW_19 U32.0 Core 20 / IDI Port 0 - core to uncore bandwidth Counter Container_21 C2U_BW_20 U32.0 Core 20 / IDI Port 0 - uncore to core bandwidth Counter Container_21 U2C_BW_20 U32.0 Core 21 / IDI Port 0 - core to uncore bandwidth Counter Container_22 C2U_BW_21 U32.0 Core 21 / IDI Port 0 - uncore to core bandwidth Counter Container_22 U2C_BW_21 U32.0 Core 22 / IDI Port 0 - core to uncore bandwidth Counter Container_23 C2U_BW_22 U32.0 Core 22 / IDI Port 0 - uncore to core bandwidth Counter Container_23 U2C_BW_22 U32.0 Core 23 / IDI Port 0 - core to uncore bandwidth Counter Container_24 C2U_BW_23 U32.0 Core 23 / IDI Port 0 - uncore to core bandwidth Counter Container_24 U2C_BW_23 U32.0 Core 24 / IDI Port 0 - core to uncore bandwidth Counter Container_25 C2U_BW_24 U32.0 Core 24 / IDI Port 0 - uncore to core bandwidth Counter Container_25 U2C_BW_24 U32.0 Core 25 / IDI Port 0 - core to uncore bandwidth Counter Container_26 C2U_BW_25 U32.0 Core 25 / IDI Port 0 - uncore to core bandwidth Counter Container_26 U2C_BW_25 U32.0 Core 26 / IDI Port 0 - core to uncore bandwidth Counter Container_27 C2U_BW_26 U32.0 Core 26 / IDI Port 0 - uncore to core bandwidth Counter Container_27 U2C_BW_26 U32.0 Core 27 / IDI Port 0 - core to uncore bandwidth Counter Container_28 C2U_BW_27 U32.0 Core 27 / IDI Port 0 - uncore to core bandwidth Counter Container_28 U2C_BW_27 U32.0 Core 28 / IDI Port 0 - core to uncore bandwidth Counter Container_29 C2U_BW_28 U32.0 Core 28 / IDI Port 0 - uncore to core bandwidth Counter Container_29 U2C_BW_28 U32.0 Core 29 / IDI Port 0 - core to uncore bandwidth Counter Container_30 C2U_BW_29 U32.0 Core 29 / IDI Port 0 - uncore to core bandwidth Counter Container_30 U2C_BW_29 U32.0 Core 30 / IDI Port 0 - core to uncore bandwidth Counter Container_31 C2U_BW_30 U32.0 Core 30 / IDI Port 0 - uncore to core bandwidth Counter Container_31 U2C_BW_30 U32.0 Core 31 / IDI Port 0 - core to uncore bandwidth Counter Container_32 C2U_BW_31 U32.0 Core 31 / IDI Port 0 - uncore to core bandwidth Counter Container_32 U2C_BW_31 U32.0 Core 32 / IDI Port 0 - core to uncore bandwidth Counter Container_33 C2U_BW_32 U32.0 Core 32 / IDI Port 0 - uncore to core bandwidth Counter Container_33 U2C_BW_32 U32.0 Core 33 / IDI Port 0 - core to uncore bandwidth Counter Container_34 C2U_BW_33 U32.0 Core 33 / IDI Port 0 - uncore to core bandwidth Counter Container_34 U2C_BW_33 U32.0 Core 34 / IDI Port 0 - core to uncore bandwidth Counter Container_35 C2U_BW_34 U32.0 Core 34 / IDI Port 0 - uncore to core bandwidth Counter Container_35 U2C_BW_34 U32.0 Core 35 / IDI Port 0 - core to uncore bandwidth Counter Container_36 C2U_BW_35 U32.0 Core 35 / IDI Port 0 - uncore to core bandwidth Counter Container_36 U2C_BW_35 U32.0 Core 36 / IDI Port 0 - core to uncore bandwidth Counter Container_37 C2U_BW_36 U32.0 Core 36 / IDI Port 0 - uncore to core bandwidth Counter Container_37 U2C_BW_36 U32.0 Core 37 / IDI Port 0 - core to uncore bandwidth Counter Container_38 C2U_BW_37 U32.0 Core 37 / IDI Port 0 - uncore to core bandwidth Counter Container_38 U2C_BW_37 U32.0 Core 38 / IDI Port 0 - core to uncore bandwidth Counter Container_39 C2U_BW_38 U32.0 Core 38 / IDI Port 0 - uncore to core bandwidth Counter Container_39 U2C_BW_38 U32.0 Core 39 / IDI Port 0 - core to uncore bandwidth Counter Container_40 C2U_BW_39 U32.0 Core 39 / IDI Port 0 - uncore to core bandwidth Counter Container_40 U2C_BW_39 U32.0 Core 40 / IDI Port 0 - core to uncore bandwidth Counter Container_41 C2U_BW_40 U32.0 Core 40 / IDI Port 0 - uncore to core bandwidth Counter Container_41 U2C_BW_40 U32.0 Core 41 / IDI Port 0 - core to uncore bandwidth Counter Container_42 C2U_BW_41 U32.0 Core 41 / IDI Port 0 - uncore to core bandwidth Counter Container_42 U2C_BW_41 U32.0 Core 42 / IDI Port 0 - core to uncore bandwidth Counter Container_43 C2U_BW_42 U32.0 Core 42 / IDI Port 0 - uncore to core bandwidth Counter Container_43 U2C_BW_42 U32.0 Core 43 / IDI Port 0 - core to uncore bandwidth Counter Container_44 C2U_BW_43 U32.0 Core 43 / IDI Port 0 - uncore to core bandwidth Counter Container_44 U2C_BW_43 U32.0 Core 44 / IDI Port 0 - core to uncore bandwidth Counter Container_45 C2U_BW_44 U32.0 Core 44 / IDI Port 0 - uncore to core bandwidth Counter Container_45 U2C_BW_44 U32.0 Core 45 / IDI Port 0 - core to uncore bandwidth Counter Container_46 C2U_BW_45 U32.0 Core 45 / IDI Port 0 - uncore to core bandwidth Counter Container_46 U2C_BW_45 U32.0 Core 46 / IDI Port 0 - core to uncore bandwidth Counter Container_47 C2U_BW_46 U32.0 Core 46 / IDI Port 0 - uncore to core bandwidth Counter Container_47 U2C_BW_46 U32.0 Core 47 / IDI Port 0 - core to uncore bandwidth Counter Container_48 C2U_BW_47 U32.0 Core 47 / IDI Port 0 - uncore to core bandwidth Counter Container_48 U2C_BW_47 U32.0 Core 48 / IDI Port 0 - core to uncore bandwidth Counter Container_49 C2U_BW_48 U32.0 Core 48 / IDI Port 0 - uncore to core bandwidth Counter Container_49 U2C_BW_48 U32.0 Core 49 / IDI Port 0 - core to uncore bandwidth Counter Container_50 C2U_BW_49 U32.0 Core 49 / IDI Port 0 - uncore to core bandwidth Counter Container_50 U2C_BW_49 U32.0 Core 50 / IDI Port 0 - core to uncore bandwidth Counter Container_51 C2U_BW_50 U32.0 Core 50 / IDI Port 0 - uncore to core bandwidth Counter Container_51 U2C_BW_50 U32.0 Core 51 / IDI Port 0 - core to uncore bandwidth Counter Container_52 C2U_BW_51 U32.0 Core 51 / IDI Port 0 - uncore to core bandwidth Counter Container_52 U2C_BW_51 U32.0 Core 52 / IDI Port 0 - core to uncore bandwidth Counter Container_53 C2U_BW_52 U32.0 Core 52 / IDI Port 0 - uncore to core bandwidth Counter Container_53 U2C_BW_52 U32.0 Core 53 / IDI Port 0 - core to uncore bandwidth Counter Container_54 C2U_BW_53 U32.0 Core 53 / IDI Port 0 - uncore to core bandwidth Counter Container_54 U2C_BW_53 U32.0 Core 54 / IDI Port 0 - core to uncore bandwidth Counter Container_55 C2U_BW_54 U32.0 Core 54 / IDI Port 0 - uncore to core bandwidth Counter Container_55 U2C_BW_54 U32.0 Core 55 / IDI Port 0 - core to uncore bandwidth Counter Container_56 C2U_BW_55 U32.0 Core 55 / IDI Port 0 - uncore to core bandwidth Counter Container_56 U2C_BW_55 U32.0 Core 56 / IDI Port 0 - core to uncore bandwidth Counter Container_57 C2U_BW_56 U32.0 Core 56 / IDI Port 0 - uncore to core bandwidth Counter Container_57 U2C_BW_56 U32.0 Core 57 / IDI Port 0 - core to uncore bandwidth Counter Container_58 C2U_BW_57 U32.0 Core 57 / IDI Port 0 - uncore to core bandwidth Counter Container_58 U2C_BW_57 U32.0 Core 58 / IDI Port 0 - core to uncore bandwidth Counter Container_59 C2U_BW_58 U32.0 Core 58 / IDI Port 0 - uncore to core bandwidth Counter Container_59 U2C_BW_58 U32.0 Core 59 / IDI Port 0 - core to uncore bandwidth Counter Container_60 C2U_BW_59 U32.0 Core 59 / IDI Port 0 - uncore to core bandwidth Counter Container_60 U2C_BW_59 U32.0 Core 60 / IDI Port 0 - core to uncore bandwidth Counter Container_61 C2U_BW_60 U32.0 Core 60 / IDI Port 0 - uncore to core bandwidth Counter Container_61 U2C_BW_60 U32.0 Core 61 / IDI Port 0 - core to uncore bandwidth Counter Container_62 C2U_BW_61 U32.0 Core 61 / IDI Port 0 - uncore to core bandwidth Counter Container_62 U2C_BW_61 U32.0 Core 62 / IDI Port 0 - core to uncore bandwidth Counter Container_63 C2U_BW_62 U32.0 Core 62 / IDI Port 0 - uncore to core bandwidth Counter Container_63 U2C_BW_62 U32.0 Core 63 / IDI Port 0 - core to uncore bandwidth Counter Container_64 C2U_BW_63 U32.0 Core 63 / IDI Port 0 - uncore to core bandwidth Counter Container_64 U2C_BW_63 U32.0 Core 0 / IDI Port 1 - core to uncore bandwidth Counter Container_65 C2U_BW_64 U32.0 Core 0 / IDI Port 1 - uncore to core bandwidth Counter Container_65 U2C_BW_64 U32.0 Core 1 / IDI Port 1 - core to uncore bandwidth Counter Container_66 C2U_BW_65 U32.0 Core 1 / IDI Port 1 - uncore to core bandwidth Counter Container_66 U2C_BW_65 U32.0 Core 2 / IDI Port 1 - core to uncore bandwidth Counter Container_67 C2U_BW_66 U32.0 Core 2 / IDI Port 1 - uncore to core bandwidth Counter Container_67 U2C_BW_66 U32.0 Core 3 / IDI Port 1 - core to uncore bandwidth Counter Container_68 C2U_BW_67 U32.0 Core 3 / IDI Port 1 - uncore to core bandwidth Counter Container_68 U2C_BW_67 U32.0 Core 4 / IDI Port 1 - core to uncore bandwidth Counter Container_69 C2U_BW_68 U32.0 Core 4 / IDI Port 1 - uncore to core bandwidth Counter Container_69 U2C_BW_68 U32.0 Core 5 / IDI Port 1 - core to uncore bandwidth Counter Container_70 C2U_BW_69 U32.0 Core 5 / IDI Port 1 - uncore to core bandwidth Counter Container_70 U2C_BW_69 U32.0 Core 6 / IDI Port 1 - core to uncore bandwidth Counter Container_71 C2U_BW_70 U32.0 Core 6 / IDI Port 1 - uncore to core bandwidth Counter Container_71 U2C_BW_70 U32.0 Core 7 / IDI Port 1 - core to uncore bandwidth Counter Container_72 C2U_BW_71 U32.0 Core 7 / IDI Port 1 - uncore to core bandwidth Counter Container_72 U2C_BW_71 U32.0 Core 8 / IDI Port 1 - core to uncore bandwidth Counter Container_73 C2U_BW_72 U32.0 Core 8 / IDI Port 1 - uncore to core bandwidth Counter Container_73 U2C_BW_72 U32.0 Core 9 / IDI Port 1 - core to uncore bandwidth Counter Container_74 C2U_BW_73 U32.0 Core 9 / IDI Port 1 - uncore to core bandwidth Counter Container_74 U2C_BW_73 U32.0 Core 10 / IDI Port 1 - core to uncore bandwidth Counter Container_75 C2U_BW_74 U32.0 Core 10 / IDI Port 1 - uncore to core bandwidth Counter Container_75 U2C_BW_74 U32.0 Core 11 / IDI Port 1 - core to uncore bandwidth Counter Container_76 C2U_BW_75 U32.0 Core 11 / IDI Port 1 - uncore to core bandwidth Counter Container_76 U2C_BW_75 U32.0 Core 12 / IDI Port 1 - core to uncore bandwidth Counter Container_77 C2U_BW_76 U32.0 Core 12 / IDI Port 1 - uncore to core bandwidth Counter Container_77 U2C_BW_76 U32.0 Core 13 / IDI Port 1 - core to uncore bandwidth Counter Container_78 C2U_BW_77 U32.0 Core 13 / IDI Port 1 - uncore to core bandwidth Counter Container_78 U2C_BW_77 U32.0 Core 14 / IDI Port 1 - core to uncore bandwidth Counter Container_79 C2U_BW_78 U32.0 Core 14 / IDI Port 1 - uncore to core bandwidth Counter Container_79 U2C_BW_78 U32.0 Core 15 / IDI Port 1 - core to uncore bandwidth Counter Container_80 C2U_BW_79 U32.0 Core 15 / IDI Port 1 - uncore to core bandwidth Counter Container_80 U2C_BW_79 U32.0 Core 16 / IDI Port 1 - core to uncore bandwidth Counter Container_81 C2U_BW_80 U32.0 Core 16 / IDI Port 1 - uncore to core bandwidth Counter Container_81 U2C_BW_80 U32.0 Core 17 / IDI Port 1 - core to uncore bandwidth Counter Container_82 C2U_BW_81 U32.0 Core 17 / IDI Port 1 - uncore to core bandwidth Counter Container_82 U2C_BW_81 U32.0 Core 18 / IDI Port 1 - core to uncore bandwidth Counter Container_83 C2U_BW_82 U32.0 Core 18 / IDI Port 1 - uncore to core bandwidth Counter Container_83 U2C_BW_82 U32.0 Core 19 / IDI Port 1 - core to uncore bandwidth Counter Container_84 C2U_BW_83 U32.0 Core 19 / IDI Port 1 - uncore to core bandwidth Counter Container_84 U2C_BW_83 U32.0 Core 20 / IDI Port 1 - core to uncore bandwidth Counter Container_85 C2U_BW_84 U32.0 Core 20 / IDI Port 1 - uncore to core bandwidth Counter Container_85 U2C_BW_84 U32.0 Core 21 / IDI Port 1 - core to uncore bandwidth Counter Container_86 C2U_BW_85 U32.0 Core 21 / IDI Port 1 - uncore to core bandwidth Counter Container_86 U2C_BW_85 U32.0 Core 22 / IDI Port 1 - core to uncore bandwidth Counter Container_87 C2U_BW_86 U32.0 Core 22 / IDI Port 1 - uncore to core bandwidth Counter Container_87 U2C_BW_86 U32.0 Core 23 / IDI Port 1 - core to uncore bandwidth Counter Container_88 C2U_BW_87 U32.0 Core 23 / IDI Port 1 - uncore to core bandwidth Counter Container_88 U2C_BW_87 U32.0 Core 24 / IDI Port 1 - core to uncore bandwidth Counter Container_89 C2U_BW_88 U32.0 Core 24 / IDI Port 1 - uncore to core bandwidth Counter Container_89 U2C_BW_88 U32.0 Core 25 / IDI Port 1 - core to uncore bandwidth Counter Container_90 C2U_BW_89 U32.0 Core 25 / IDI Port 1 - uncore to core bandwidth Counter Container_90 U2C_BW_89 U32.0 Core 26 / IDI Port 1 - core to uncore bandwidth Counter Container_91 C2U_BW_90 U32.0 Core 26 / IDI Port 1 - uncore to core bandwidth Counter Container_91 U2C_BW_90 U32.0 Core 27 / IDI Port 1 - core to uncore bandwidth Counter Container_92 C2U_BW_91 U32.0 Core 27 / IDI Port 1 - uncore to core bandwidth Counter Container_92 U2C_BW_91 U32.0 Core 28 / IDI Port 1 - core to uncore bandwidth Counter Container_93 C2U_BW_92 U32.0 Core 28 / IDI Port 1 - uncore to core bandwidth Counter Container_93 U2C_BW_92 U32.0 Core 29 / IDI Port 1 - core to uncore bandwidth Counter Container_94 C2U_BW_93 U32.0 Core 29 / IDI Port 1 - uncore to core bandwidth Counter Container_94 U2C_BW_93 U32.0 Core 30 / IDI Port 1 - core to uncore bandwidth Counter Container_95 C2U_BW_94 U32.0 Core 30 / IDI Port 1 - uncore to core bandwidth Counter Container_95 U2C_BW_94 U32.0 Core 31 / IDI Port 1 - core to uncore bandwidth Counter Container_96 C2U_BW_95 U32.0 Core 31 / IDI Port 1 - uncore to core bandwidth Counter Container_96 U2C_BW_95 U32.0 Core 32 / IDI Port 1 - core to uncore bandwidth Counter Container_97 C2U_BW_96 U32.0 Core 32 / IDI Port 1 - uncore to core bandwidth Counter Container_97 U2C_BW_96 U32.0 Core 33 / IDI Port 1 - core to uncore bandwidth Counter Container_98 C2U_BW_97 U32.0 Core 33 / IDI Port 1 - uncore to core bandwidth Counter Container_98 U2C_BW_97 U32.0 Core 34 / IDI Port 1 - core to uncore bandwidth Counter Container_99 C2U_BW_98 U32.0 Core 34 / IDI Port 1 - uncore to core bandwidth Counter Container_99 U2C_BW_98 U32.0 Core 35 / IDI Port 1 - core to uncore bandwidth Counter Container_100 C2U_BW_99 U32.0 Core 35 / IDI Port 1 - uncore to core bandwidth Counter Container_100 U2C_BW_99 U32.0 Core 36 / IDI Port 1 - core to uncore bandwidth Counter Container_101 C2U_BW_100 U32.0 Core 36 / IDI Port 1 - uncore to core bandwidth Counter Container_101 U2C_BW_100 U32.0 Core 37 / IDI Port 1 - core to uncore bandwidth Counter Container_102 C2U_BW_101 U32.0 Core 37 / IDI Port 1 - uncore to core bandwidth Counter Container_102 U2C_BW_101 U32.0 Core 38 / IDI Port 1 - core to uncore bandwidth Counter Container_103 C2U_BW_102 U32.0 Core 38 / IDI Port 1 - uncore to core bandwidth Counter Container_103 U2C_BW_102 U32.0 Core 39 / IDI Port 1 - core to uncore bandwidth Counter Container_104 C2U_BW_103 U32.0 Core 39 / IDI Port 1 - uncore to core bandwidth Counter Container_104 U2C_BW_103 U32.0 Core 40 / IDI Port 1 - core to uncore bandwidth Counter Container_105 C2U_BW_104 U32.0 Core 40 / IDI Port 1 - uncore to core bandwidth Counter Container_105 U2C_BW_104 U32.0 Core 41 / IDI Port 1 - core to uncore bandwidth Counter Container_106 C2U_BW_105 U32.0 Core 41 / IDI Port 1 - uncore to core bandwidth Counter Container_106 U2C_BW_105 U32.0 Core 42 / IDI Port 1 - core to uncore bandwidth Counter Container_107 C2U_BW_106 U32.0 Core 42 / IDI Port 1 - uncore to core bandwidth Counter Container_107 U2C_BW_106 U32.0 Core 43 / IDI Port 1 - core to uncore bandwidth Counter Container_108 C2U_BW_107 U32.0 Core 43 / IDI Port 1 - uncore to core bandwidth Counter Container_108 U2C_BW_107 U32.0 Core 44 / IDI Port 1 - core to uncore bandwidth Counter Container_109 C2U_BW_108 U32.0 Core 44 / IDI Port 1 - uncore to core bandwidth Counter Container_109 U2C_BW_108 U32.0 Core 45 / IDI Port 1 - core to uncore bandwidth Counter Container_110 C2U_BW_109 U32.0 Core 45 / IDI Port 1 - uncore to core bandwidth Counter Container_110 U2C_BW_109 U32.0 Core 46 / IDI Port 1 - core to uncore bandwidth Counter Container_111 C2U_BW_110 U32.0 Core 46 / IDI Port 1 - uncore to core bandwidth Counter Container_111 U2C_BW_110 U32.0 Core 47 / IDI Port 1 - core to uncore bandwidth Counter Container_112 C2U_BW_111 U32.0 Core 47 / IDI Port 1 - uncore to core bandwidth Counter Container_112 U2C_BW_111 U32.0 Core 48 / IDI Port 1 - core to uncore bandwidth Counter Container_113 C2U_BW_112 U32.0 Core 48 / IDI Port 1 - uncore to core bandwidth Counter Container_113 U2C_BW_112 U32.0 Core 49 / IDI Port 1 - core to uncore bandwidth Counter Container_114 C2U_BW_113 U32.0 Core 49 / IDI Port 1 - uncore to core bandwidth Counter Container_114 U2C_BW_113 U32.0 Core 50 / IDI Port 1 - core to uncore bandwidth Counter Container_115 C2U_BW_114 U32.0 Core 50 / IDI Port 1 - uncore to core bandwidth Counter Container_115 U2C_BW_114 U32.0 Core 51 / IDI Port 1 - core to uncore bandwidth Counter Container_116 C2U_BW_115 U32.0 Core 51 / IDI Port 1 - uncore to core bandwidth Counter Container_116 U2C_BW_115 U32.0 Core 52 / IDI Port 1 - core to uncore bandwidth Counter Container_117 C2U_BW_116 U32.0 Core 52 / IDI Port 1 - uncore to core bandwidth Counter Container_117 U2C_BW_116 U32.0 Core 53 / IDI Port 1 - core to uncore bandwidth Counter Container_118 C2U_BW_117 U32.0 Core 53 / IDI Port 1 - uncore to core bandwidth Counter Container_118 U2C_BW_117 U32.0 Core 54 / IDI Port 1 - core to uncore bandwidth Counter Container_119 C2U_BW_118 U32.0 Core 54 / IDI Port 1 - uncore to core bandwidth Counter Container_119 U2C_BW_118 U32.0 Core 55 / IDI Port 1 - core to uncore bandwidth Counter Container_120 C2U_BW_119 U32.0 Core 55 / IDI Port 1 - uncore to core bandwidth Counter Container_120 U2C_BW_119 U32.0 Core 56 / IDI Port 1 - core to uncore bandwidth Counter Container_121 C2U_BW_120 U32.0 Core 56 / IDI Port 1 - uncore to core bandwidth Counter Container_121 U2C_BW_120 U32.0 Core 57 / IDI Port 1 - core to uncore bandwidth Counter Container_122 C2U_BW_121 U32.0 Core 57 / IDI Port 1 - uncore to core bandwidth Counter Container_122 U2C_BW_121 U32.0 Core 58 / IDI Port 1 - core to uncore bandwidth Counter Container_123 C2U_BW_122 U32.0 Core 58 / IDI Port 1 - uncore to core bandwidth Counter Container_123 U2C_BW_122 U32.0 Core 59 / IDI Port 1 - core to uncore bandwidth Counter Container_124 C2U_BW_123 U32.0 Core 59 / IDI Port 1 - uncore to core bandwidth Counter Container_124 U2C_BW_123 U32.0 Core 60 / IDI Port 1 - core to uncore bandwidth Counter Container_125 C2U_BW_124 U32.0 Core 60 / IDI Port 1 - uncore to core bandwidth Counter Container_125 U2C_BW_124 U32.0 Core 61 / IDI Port 1 - core to uncore bandwidth Counter Container_126 C2U_BW_125 U32.0 Core 61 / IDI Port 1 - uncore to core bandwidth Counter Container_126 U2C_BW_125 U32.0 Core 62 / IDI Port 1 - core to uncore bandwidth Counter Container_127 C2U_BW_126 U32.0 Core 62 / IDI Port 1 - uncore to core bandwidth Counter Container_127 U2C_BW_126 U32.0 Core 63 / IDI Port 1 - core to uncore bandwidth Counter Container_128 C2U_BW_127 U32.0 Core 63 / IDI Port 1 - uncore to core bandwidth Counter Container_128 U2C_BW_127 U32.0 Core 0 C0 Residency Counter Container_129 C0Residency U28.0 Core 0 C1 Residency Counter Container_129 C1Residency U28.0 Core 1 C0 Residency Counter Container_130 C0Residency_1 U28.0 Core 1 C1 Residency Counter Container_130 C1Residency_1 U28.0 Core 2 C0 Residency Counter Container_131 C0Residency_2 U28.0 Core 2 C1 Residency Counter Container_131 C1Residency_2 U28.0 Core 3 C0 Residency Counter Container_132 C0Residency_3 U28.0 Core 3 C1 Residency Counter Container_132 C1Residency_3 U28.0 Core 4 C0 Residency Counter Container_133 C0Residency_4 U28.0 Core 4 C1 Residency Counter Container_133 C1Residency_4 U28.0 Core 5 C0 Residency Counter Container_134 C0Residency_5 U28.0 Core 5 C1 Residency Counter Container_134 C1Residency_5 U28.0 Core 6 C0 Residency Counter Container_135 C0Residency_6 U28.0 Core 6 C1 Residency Counter Container_135 C1Residency_6 U28.0 Core 7 C0 Residency Counter Container_136 C0Residency_7 U28.0 Core 7 C1 Residency Counter Container_136 C1Residency_7 U28.0 Core 8 C0 Residency Counter Container_137 C0Residency_8 U28.0 Core 8 C1 Residency Counter Container_137 C1Residency_8 U28.0 Core 9 C0 Residency Counter Container_138 C0Residency_9 U28.0 Core 9 C1 Residency Counter Container_138 C1Residency_9 U28.0 Core 10 C0 Residency Counter Container_139 C0Residency_10 U28.0 Core 10 C1 Residency Counter Container_139 C1Residency_10 U28.0 Core 11 C0 Residency Counter Container_140 C0Residency_11 U28.0 Core 11 C1 Residency Counter Container_140 C1Residency_11 U28.0 Core 12 C0 Residency Counter Container_141 C0Residency_12 U28.0 Core 12 C1 Residency Counter Container_141 C1Residency_12 U28.0 Core 13 C0 Residency Counter Container_142 C0Residency_13 U28.0 Core 13 C1 Residency Counter Container_142 C1Residency_13 U28.0 Core 14 C0 Residency Counter Container_143 C0Residency_14 U28.0 Core 14 C1 Residency Counter Container_143 C1Residency_14 U28.0 Core 15 C0 Residency Counter Container_144 C0Residency_15 U28.0 Core 15 C1 Residency Counter Container_144 C1Residency_15 U28.0 Core 16 C0 Residency Counter Container_145 C0Residency_16 U28.0 Core 16 C1 Residency Counter Container_145 C1Residency_16 U28.0 Core 17 C0 Residency Counter Container_146 C0Residency_17 U28.0 Core 17 C1 Residency Counter Container_146 C1Residency_17 U28.0 Core 18 C0 Residency Counter Container_147 C0Residency_18 U28.0 Core 18 C1 Residency Counter Container_147 C1Residency_18 U28.0 Core 19 C0 Residency Counter Container_148 C0Residency_19 U28.0 Core 19 C1 Residency Counter Container_148 C1Residency_19 U28.0 Core 20 C0 Residency Counter Container_149 C0Residency_20 U28.0 Core 20 C1 Residency Counter Container_149 C1Residency_20 U28.0 Core 21 C0 Residency Counter Container_150 C0Residency_21 U28.0 Core 21 C1 Residency Counter Container_150 C1Residency_21 U28.0 Core 22 C0 Residency Counter Container_151 C0Residency_22 U28.0 Core 22 C1 Residency Counter Container_151 C1Residency_22 U28.0 Core 23 C0 Residency Counter Container_152 C0Residency_23 U28.0 Core 23 C1 Residency Counter Container_152 C1Residency_23 U28.0 Core 24 C0 Residency Counter Container_153 C0Residency_24 U28.0 Core 24 C1 Residency Counter Container_153 C1Residency_24 U28.0 Core 25 C0 Residency Counter Container_154 C0Residency_25 U28.0 Core 25 C1 Residency Counter Container_154 C1Residency_25 U28.0 Core 26 C0 Residency Counter Container_155 C0Residency_26 U28.0 Core 26 C1 Residency Counter Container_155 C1Residency_26 U28.0 Core 27 C0 Residency Counter Container_156 C0Residency_27 U28.0 Core 27 C1 Residency Counter Container_156 C1Residency_27 U28.0 Core 28 C0 Residency Counter Container_157 C0Residency_28 U28.0 Core 28 C1 Residency Counter Container_157 C1Residency_28 U28.0 Core 29 C0 Residency Counter Container_158 C0Residency_29 U28.0 Core 29 C1 Residency Counter Container_158 C1Residency_29 U28.0 Core 30 C0 Residency Counter Container_159 C0Residency_30 U28.0 Core 30 C1 Residency Counter Container_159 C1Residency_30 U28.0 Core 31 C0 Residency Counter Container_160 C0Residency_31 U28.0 Core 31 C1 Residency Counter Container_160 C1Residency_31 U28.0 Core 32 C0 Residency Counter Container_161 C0Residency_32 U28.0 Core 32 C1 Residency Counter Container_161 C1Residency_32 U28.0 Core 33 C0 Residency Counter Container_162 C0Residency_33 U28.0 Core 33 C1 Residency Counter Container_162 C1Residency_33 U28.0 Core 34 C0 Residency Counter Container_163 C0Residency_34 U28.0 Core 34 C1 Residency Counter Container_163 C1Residency_34 U28.0 Core 35 C0 Residency Counter Container_164 C0Residency_35 U28.0 Core 35 C1 Residency Counter Container_164 C1Residency_35 U28.0 Core 36 C0 Residency Counter Container_165 C0Residency_36 U28.0 Core 36 C1 Residency Counter Container_165 C1Residency_36 U28.0 Core 37 C0 Residency Counter Container_166 C0Residency_37 U28.0 Core 37 C1 Residency Counter Container_166 C1Residency_37 U28.0 Core 38 C0 Residency Counter Container_167 C0Residency_38 U28.0 Core 38 C1 Residency Counter Container_167 C1Residency_38 U28.0 Core 39 C0 Residency Counter Container_168 C0Residency_39 U28.0 Core 39 C1 Residency Counter Container_168 C1Residency_39 U28.0 Core 40 C0 Residency Counter Container_169 C0Residency_40 U28.0 Core 40 C1 Residency Counter Container_169 C1Residency_40 U28.0 Core 41 C0 Residency Counter Container_170 C0Residency_41 U28.0 Core 41 C1 Residency Counter Container_170 C1Residency_41 U28.0 Core 42 C0 Residency Counter Container_171 C0Residency_42 U28.0 Core 42 C1 Residency Counter Container_171 C1Residency_42 U28.0 Core 43 C0 Residency Counter Container_172 C0Residency_43 U28.0 Core 43 C1 Residency Counter Container_172 C1Residency_43 U28.0 Core 44 C0 Residency Counter Container_173 C0Residency_44 U28.0 Core 44 C1 Residency Counter Container_173 C1Residency_44 U28.0 Core 45 C0 Residency Counter Container_174 C0Residency_45 U28.0 Core 45 C1 Residency Counter Container_174 C1Residency_45 U28.0 Core 46 C0 Residency Counter Container_175 C0Residency_46 U28.0 Core 46 C1 Residency Counter Container_175 C1Residency_46 U28.0 Core 47 C0 Residency Counter Container_176 C0Residency_47 U28.0 Core 47 C1 Residency Counter Container_176 C1Residency_47 U28.0 Core 48 C0 Residency Counter Container_177 C0Residency_48 U28.0 Core 48 C1 Residency Counter Container_177 C1Residency_48 U28.0 Core 49 C0 Residency Counter Container_178 C0Residency_49 U28.0 Core 49 C1 Residency Counter Container_178 C1Residency_49 U28.0 Core 50 C0 Residency Counter Container_179 C0Residency_50 U28.0 Core 50 C1 Residency Counter Container_179 C1Residency_50 U28.0 Core 51 C0 Residency Counter Container_180 C0Residency_51 U28.0 Core 51 C1 Residency Counter Container_180 C1Residency_51 U28.0 Core 52 C0 Residency Counter Container_181 C0Residency_52 U28.0 Core 52 C1 Residency Counter Container_181 C1Residency_52 U28.0 Core 53 C0 Residency Counter Container_182 C0Residency_53 U28.0 Core 53 C1 Residency Counter Container_182 C1Residency_53 U28.0 Core 54 C0 Residency Counter Container_183 C0Residency_54 U28.0 Core 54 C1 Residency Counter Container_183 C1Residency_54 U28.0 Core 55 C0 Residency Counter Container_184 C0Residency_55 U28.0 Core 55 C1 Residency Counter Container_184 C1Residency_55 U28.0 Core 56 C0 Residency Counter Container_185 C0Residency_56 U28.0 Core 56 C1 Residency Counter Container_185 C1Residency_56 U28.0 Core 57 C0 Residency Counter Container_186 C0Residency_57 U28.0 Core 57 C1 Residency Counter Container_186 C1Residency_57 U28.0 Core 58 C0 Residency Counter Container_187 C0Residency_58 U28.0 Core 58 C1 Residency Counter Container_187 C1Residency_58 U28.0 Core 59 C0 Residency Counter Container_188 C0Residency_59 U28.0 Core 59 C1 Residency Counter Container_188 C1Residency_59 U28.0 Core 60 C0 Residency Counter Container_189 C0Residency_60 U28.0 Core 60 C1 Residency Counter Container_189 C1Residency_60 U28.0 Core 61 C0 Residency Counter Container_190 C0Residency_61 U28.0 Core 61 C1 Residency Counter Container_190 C1Residency_61 U28.0 Core 62 C0 Residency Counter Container_191 C0Residency_62 U28.0 Core 62 C1 Residency Counter Container_191 C1Residency_62 U28.0 Core 63 C0 Residency Counter Container_192 C0Residency_63 U28.0 Core 63 C1 Residency Counter Container_192 C1Residency_63 U28.0 Current temperature on core 0 Snapshot Container_193 CORE_TEMP temperature Current temperature on core 1 Snapshot Container_193 CORE_TEMP_1 temperature Current temperature on core 2 Snapshot Container_193 CORE_TEMP_2 temperature Current temperature on core 3 Snapshot Container_193 CORE_TEMP_3 temperature Current temperature on core 4 Snapshot Container_194 CORE_TEMP_4 temperature Current temperature on core 5 Snapshot Container_194 CORE_TEMP_5 temperature Current temperature on core 6 Snapshot Container_194 CORE_TEMP_6 temperature Current temperature on core 7 Snapshot Container_194 CORE_TEMP_7 temperature Current temperature on core 8 Snapshot Container_195 CORE_TEMP_8 temperature Current temperature on core 9 Snapshot Container_195 CORE_TEMP_9 temperature Current temperature on core 10 Snapshot Container_195 CORE_TEMP_10 temperature Current temperature on core 11 Snapshot Container_195 CORE_TEMP_11 temperature Current temperature on core 12 Snapshot Container_196 CORE_TEMP_12 temperature Current temperature on core 13 Snapshot Container_196 CORE_TEMP_13 temperature Current temperature on core 14 Snapshot Container_196 CORE_TEMP_14 temperature Current temperature on core 15 Snapshot Container_196 CORE_TEMP_15 temperature Current temperature on core 16 Snapshot Container_197 CORE_TEMP_16 temperature Current temperature on core 17 Snapshot Container_197 CORE_TEMP_17 temperature Current temperature on core 18 Snapshot Container_197 CORE_TEMP_18 temperature Current temperature on core 19 Snapshot Container_197 CORE_TEMP_19 temperature Current temperature on core 20 Snapshot Container_198 CORE_TEMP_20 temperature Current temperature on core 21 Snapshot Container_198 CORE_TEMP_21 temperature Current temperature on core 22 Snapshot Container_198 CORE_TEMP_22 temperature Current temperature on core 23 Snapshot Container_198 CORE_TEMP_23 temperature Current temperature on core 24 Snapshot Container_199 CORE_TEMP_24 temperature Current temperature on core 25 Snapshot Container_199 CORE_TEMP_25 temperature Current temperature on core 26 Snapshot Container_199 CORE_TEMP_26 temperature Current temperature on core 27 Snapshot Container_199 CORE_TEMP_27 temperature Current temperature on core 28 Snapshot Container_200 CORE_TEMP_28 temperature Current temperature on core 29 Snapshot Container_200 CORE_TEMP_29 temperature Current temperature on core 30 Snapshot Container_200 CORE_TEMP_30 temperature Current temperature on core 31 Snapshot Container_200 CORE_TEMP_31 temperature Current temperature on core 32 Snapshot Container_201 CORE_TEMP_32 temperature Current temperature on core 33 Snapshot Container_201 CORE_TEMP_33 temperature Current temperature on core 34 Snapshot Container_201 CORE_TEMP_34 temperature Current temperature on core 35 Snapshot Container_201 CORE_TEMP_35 temperature Current temperature on core 36 Snapshot Container_202 CORE_TEMP_36 temperature Current temperature on core 37 Snapshot Container_202 CORE_TEMP_37 temperature Current temperature on core 38 Snapshot Container_202 CORE_TEMP_38 temperature Current temperature on core 39 Snapshot Container_202 CORE_TEMP_39 temperature Current temperature on core 40 Snapshot Container_203 CORE_TEMP_40 temperature Current temperature on core 41 Snapshot Container_203 CORE_TEMP_41 temperature Current temperature on core 42 Snapshot Container_203 CORE_TEMP_42 temperature Current temperature on core 43 Snapshot Container_203 CORE_TEMP_43 temperature Current temperature on core 44 Snapshot Container_204 CORE_TEMP_44 temperature Current temperature on core 45 Snapshot Container_204 CORE_TEMP_45 temperature Current temperature on core 46 Snapshot Container_204 CORE_TEMP_46 temperature Current temperature on core 47 Snapshot Container_204 CORE_TEMP_47 temperature Current temperature on core 48 Snapshot Container_205 CORE_TEMP_48 temperature Current temperature on core 49 Snapshot Container_205 CORE_TEMP_49 temperature Current temperature on core 50 Snapshot Container_205 CORE_TEMP_50 temperature Current temperature on core 51 Snapshot Container_205 CORE_TEMP_51 temperature Current temperature on core 52 Snapshot Container_206 CORE_TEMP_52 temperature Current temperature on core 53 Snapshot Container_206 CORE_TEMP_53 temperature Current temperature on core 54 Snapshot Container_206 CORE_TEMP_54 temperature Current temperature on core 55 Snapshot Container_206 CORE_TEMP_55 temperature Current temperature on core 56 Snapshot Container_207 CORE_TEMP_56 temperature Current temperature on core 57 Snapshot Container_207 CORE_TEMP_57 temperature Current temperature on core 58 Snapshot Container_207 CORE_TEMP_58 temperature Current temperature on core 59 Snapshot Container_207 CORE_TEMP_59 temperature Current temperature on core 60 Snapshot Container_208 CORE_TEMP_60 temperature Current temperature on core 61 Snapshot Container_208 CORE_TEMP_61 temperature Current temperature on core 62 Snapshot Container_208 CORE_TEMP_62 temperature Current temperature on core 63 Snapshot Container_208 CORE_TEMP_63 temperature Time spent in the Package C-State 2 (PC2) Counter Container_209 PC2_LOW U32.0 Time spent in the Package C-State 2 (PC2) Counter Container_209 PC2_HIGH U32.0 Time spent in the Package C-State 6 (PC6) Counter Container_210 PC6_LOW U32.0 Time spent in the Package C-State 6 (PC6) Counter Container_210 PC6_HIGH U32.0 IO Bandwidth for DMI or PCIE port 0 Counter Container_211 UFS_MAX_RING_TRAFFIC U24.0 IO Bandwidth for DMI or PCIE port 1 Counter Container_211 UFS_MAX_RING_TRAFFIC_1 U24.0 IO Bandwidth for DMI or PCIE port 2 Counter Container_212 UFS_MAX_RING_TRAFFIC_2 U24.0 IO Bandwidth for DMI or PCIE port 3 Counter Container_212 UFS_MAX_RING_TRAFFIC_3 U24.0 IO Bandwidth for DMI or PCIE port 4 Counter Container_213 UFS_MAX_RING_TRAFFIC_4 U24.0 IO Bandwidth for DMI or PCIE port 5 Counter Container_213 UFS_MAX_RING_TRAFFIC_5 U24.0 IO Bandwidth for DMI or PCIE port 6 Counter Container_214 UFS_MAX_RING_TRAFFIC_6 U24.0 IO Bandwidth for DMI or PCIE port 7 Counter Container_214 UFS_MAX_RING_TRAFFIC_7 U24.0 IO Bandwidth for DMI or PCIE port 8 Counter Container_215 UFS_MAX_RING_TRAFFIC_8 U24.0 IO Bandwidth for DMI or PCIE port 9 Counter Container_215 UFS_MAX_RING_TRAFFIC_9 U24.0 IO Bandwidth for DMI or PCIE port 10 Counter Container_216 UFS_MAX_RING_TRAFFIC_10 U24.0 IO Bandwidth for DMI or PCIE port 11 Counter Container_216 UFS_MAX_RING_TRAFFIC_11 U24.0 IO Bandwidth for DMI or PCIE port 12 Counter Container_217 UFS_MAX_RING_TRAFFIC_12 U24.0 IO Bandwidth for DMI or PCIE port 13 Counter Container_217 UFS_MAX_RING_TRAFFIC_13 U24.0 IO Bandwidth for DMI or PCIE port 14 Counter Container_218 UFS_MAX_RING_TRAFFIC_14 U24.0 IO Bandwidth for DMI or PCIE port 15 Counter Container_218 UFS_MAX_RING_TRAFFIC_15 U24.0 UPI Bandwidth port 0 Counter Container_219 UFS_MAX_RING_TRAFFIC_16 U24.0 UPI Bandwidth port 1 Counter Container_219 UFS_MAX_RING_TRAFFIC_17 U24.0 UPI Bandwidth port 2 Counter Container_220 UFS_MAX_RING_TRAFFIC_18 U24.0 UPI Bandwidth port 3 Counter Container_220 UFS_MAX_RING_TRAFFIC_19 U24.0 UPI Bandwidth port 4 Counter Container_221 UFS_MAX_RING_TRAFFIC_20 U24.0 UPI Bandwidth port 5 Counter Container_221 UFS_MAX_RING_TRAFFIC_21 U24.0 UPI Bandwidth port 6 Counter Container_222 UFS_MAX_RING_TRAFFIC_22 U24.0 UPI Bandwidth port 7 Counter Container_222 UFS_MAX_RING_TRAFFIC_23 U24.0 DRAM energy consumed by all the DIMMS in all the Channels. Counter Container_223 DRAM_ENERGY_LOW dram_energy DRAM energy consumed by all the DIMMS in all the Channels. Counter Container_223 DRAM_ENERGY_HIGH dram_energy Memory Read Bandwidth IMC channel 0 Counter Container_224 MEM_RD_BW U32.0 Memory Write Bandwidth IMC channel 0 Counter Container_224 MEM_WR_BW U32.0 Memory Read Bandwidth IMC channel 1 Counter Container_225 MEM_RD_BW_1 U32.0 Memory Write Bandwidth IMC channel 1 Counter Container_225 MEM_WR_BW_1 U32.0 Memory Read Bandwidth IMC channel 2 Counter Container_226 MEM_RD_BW_2 U32.0 Memory Write Bandwidth IMC channel 2 Counter Container_226 MEM_WR_BW_2 U32.0 Memory Read Bandwidth IMC channel 3 Counter Container_227 MEM_RD_BW_3 U32.0 Memory Write Bandwidth IMC channel 3 Counter Container_227 MEM_WR_BW_3 U32.0 Memory Read Bandwidth IMC channel 4 Counter Container_228 MEM_RD_BW_4 U32.0 Memory Write Bandwidth IMC channel 4 Counter Container_228 MEM_WR_BW_4 U32.0 Memory Read Bandwidth IMC channel 5 Counter Container_229 MEM_RD_BW_5 U32.0 Memory Write Bandwidth IMC channel 5 Counter Container_229 MEM_WR_BW_5 U32.0 Memory Read Bandwidth IMC channel 6 Counter Container_230 MEM_RD_BW_6 U32.0 Memory Write Bandwidth IMC channel 6 Counter Container_230 MEM_WR_BW_6 U32.0 Memory Read Bandwidth IMC channel 7 Counter Container_231 MEM_RD_BW_7 U32.0 Memory Write Bandwidth IMC channel 7 Counter Container_231 MEM_WR_BW_7 U32.0 DDRT Read Bandwidth IMC channel 0 Counter Container_232 DDRT_READ_BW U32.0 DDRT Write Bandwidth IMC channel 0 Counter Container_232 DDRT_WR_BW U32.0 DDRT Read Bandwidth IMC channel 1 Counter Container_233 DDRT_READ_BW_1 U32.0 DDRT Write Bandwidth IMC channel 1 Counter Container_233 DDRT_WR_BW_1 U32.0 DDRT Read Bandwidth IMC channel 2 Counter Container_234 DDRT_READ_BW_2 U32.0 DDRT Write Bandwidth IMC channel 2 Counter Container_234 DDRT_WR_BW_2 U32.0 DDRT Read Bandwidth IMC channel 3 Counter Container_235 DDRT_READ_BW_3 U32.0 DDRT Write Bandwidth IMC channel 3 Counter Container_235 DDRT_WR_BW_3 U32.0 DDRT Read Bandwidth IMC channel 4 Counter Container_236 DDRT_READ_BW_4 U32.0 DDRT Write Bandwidth IMC channel 4 Counter Container_236 DDRT_WR_BW_4 U32.0 DDRT Read Bandwidth IMC channel 5 Counter Container_237 DDRT_READ_BW_5 U32.0 DDRT Write Bandwidth IMC channel 5 Counter Container_237 DDRT_WR_BW_5 U32.0 DDRT Read Bandwidth IMC channel 6 Counter Container_238 DDRT_READ_BW_6 U32.0 DDRT Write Bandwidth IMC channel 6 Counter Container_238 DDRT_WR_BW_6 U32.0 DDRT Read Bandwidth IMC channel 7 Counter Container_239 DDRT_READ_BW_7 U32.0 DDRT Write Bandwidth IMC channel 7 Counter Container_239 DDRT_WR_BW_7 U32.0 Number of clock ticks when throttling occurred on IMC channel 0 Counter Container_240 THRT_COUNT U32.0 Energy accumulated by IMC channel 0 Counter Container_240 PMSUM U32.0 Number of clock ticks when throttling occurred on IMC channel 1 Counter Container_241 THRT_COUNT_1 U32.0 Energy accumulated by IMC channel 1 Counter Container_241 PMSUM_1 U32.0 Number of clock ticks when throttling occurred on IMC channel 2 Counter Container_242 THRT_COUNT_2 U32.0 Energy accumulated by IMC channel 2 Counter Container_242 PMSUM_2 U32.0 Number of clock ticks when throttling occurred on IMC channel 3 Counter Container_243 THRT_COUNT_3 U32.0 Energy accumulated by IMC channel 3 Counter Container_243 PMSUM_3 U32.0 Number of clock ticks when throttling occurred on IMC channel 4 Counter Container_244 THRT_COUNT_4 U32.0 Energy accumulated by IMC channel 4 Counter Container_244 PMSUM_4 U32.0 Number of clock ticks when throttling occurred on IMC channel 5 Counter Container_245 THRT_COUNT_5 U32.0 Energy accumulated by IMC channel 5 Counter Container_245 PMSUM_5 U32.0 Number of clock ticks when throttling occurred on IMC channel 6 Counter Container_246 THRT_COUNT_6 U32.0 Energy accumulated by IMC channel 6 Counter Container_246 PMSUM_6 U32.0 Number of clock ticks when throttling occurred on IMC channel 7 Counter Container_247 THRT_COUNT_7 U32.0 Energy accumulated by IMC channel 7 Counter Container_247 PMSUM_7 U32.0 Command count for IMC channel 0 subchannel 0 Counter Container_248 CMD_CNT_CH0 U32.0 Command count for IMC channel 0 subchannel 1 Counter Container_248 CMD_CNT_CH1 U32.0 Command count for IMC channel 1 subchannel 0 Counter Container_249 CMD_CNT_CH0_1 U32.0 Command count for IMC channel 1 subchannel 1 Counter Container_249 CMD_CNT_CH1_1 U32.0 Command count for IMC channel 2 subchannel 0 Counter Container_250 CMD_CNT_CH0_2 U32.0 Command count for IMC channel 2 subchannel 1 Counter Container_250 CMD_CNT_CH1_2 U32.0 Command count for IMC channel 3 subchannel 0 Counter Container_251 CMD_CNT_CH0_3 U32.0 Command count for IMC channel 3 subchannel 1 Counter Container_251 CMD_CNT_CH1_3 U32.0 Command count for IMC channel 4 subchannel 0 Counter Container_252 CMD_CNT_CH0_4 U32.0 Command count for IMC channel 4 subchannel 1 Counter Container_252 CMD_CNT_CH1_4 U32.0 Command count for IMC channel 5 subchannel 0 Counter Container_253 CMD_CNT_CH0_5 U32.0 Command count for IMC channel 5 subchannel 1 Counter Container_253 CMD_CNT_CH1_5 U32.0 Command count for IMC channel 6 subchannel 0 Counter Container_254 CMD_CNT_CH0_6 U32.0 Command count for IMC channel 6 subchannel 1 Counter Container_254 CMD_CNT_CH1_6 U32.0 Command count for IMC channel 7 subchannel 0 Counter Container_255 CMD_CNT_CH0_7 U32.0 Command count for IMC channel 7 subchannel 1 Counter Container_255 CMD_CNT_CH1_7 U32.0 Specify the Frequency Excursion Threshold. It is the ratio of the core frequency. Pcode Clips betwen Pm and P01. Snapshot Container_256 FET U8.0 0 < X < 17 unit is 2.3 * power(2, TW) ms and (2^17 ms = ~302 seconds) X is clipped to betwen 0 and 17. Time windows may become inaccurate for TW < 5. Valid TW range is 0 to 17. I.e. Max time window is about 302 seconds. Snapshot Container_256 TW tw_unit For SPR it's currently 0. New feature version come in the future will need to uprev this. Snapshot Container_256 VERSION U8.0 0x0 (Default)=Inband interface for PEM is enabled. 0x1=OOB interface for PEM is enabled. Snapshot Container_256 OOB_PEM_ENABLE passthru 0 (Default): Disable PEM. 1: Enable PEM Snapshot Container_256 ENABLE_PEM passthru Set if core frequency excursion occurs due to listed or unlisted reason. Snapshot Container_256 ANY passthru Set if core frequency excursion occurs due to any thermal event in core/uncore. Snapshot Container_256 THERMAL passthru Set if core frequency excursion occurs due to external PROCHOT assertion. Snapshot Container_256 EXT_PROCHOT passthru Set if core frequency excursion occurs due to power limit (socket RAPL and/or platform RAPL). Snapshot Container_256 PBM passthru Set if core frequency excursion occurs due to PL1 input from any interfaces. Snapshot Container_256 PL1 passthru Status bits reserved for future PEM. Returns 0. Snapshot Container_256 RESERVED0 passthru Set if core frequency excursion occurs due to PL2 input from any interfaces. Snapshot Container_256 PL2 passthru Status bits reserved for future PEM. Returns 0. Snapshot Container_256 RESERVED1 passthru Set if core frequency excursion occurs due to PMAX. Snapshot Container_256 PMAX passthru Status bits reserved for future PEM. Returns 0. Snapshot Container_256 RESERVED2 passthru Free running duration counter. Duration for which core frequency excursion occurred due to listed or unlisted reason. Counter Container_257 PEM_ANY U32.0 Free running duration counter. Duration for which core frequency excursion occurred due to EMTTM Counter Container_257 PEM_THERMAL U32.0 Free running duration counter. Duration for which core frequency excursion occurred due to external PROCHOT assertion. Counter Container_258 PEM_EXT_PROCHOT U32.0 Free running duration counter. Duration for which core frequency excursion occurred due to PBM Counter Container_258 PEM_PBM U32.0 Free running duration counter. Duration for which core frequency excursion occurred due to PL1. Counter Container_259 PEM_PL1 U32.0 Reserved for PEM. Counter Container_259 PEM_RESERVED U32.0 Reserved for PEM. Counter Container_260 PEM_RESERVED_1 U32.0 Free running duration counter. Duration for which core frequency excursion occurred due to PL2. Counter Container_260 PEM_PL2 U32.0 Reserved for PEM. Counter Container_261 PEM_RESERVED_2 U32.0 Reserved for PEM. Counter Container_261 PEM_RESERVED_3 U32.0 Reserved for PEM. Counter Container_262 PEM_RESERVED_4 U32.0 Reserved for PEM. Counter Container_262 PEM_RESERVED_5 U32.0 Reserved for PEM. Counter Container_263 PEM_RESERVED_6 U32.0 Reserved for PEM. Counter Container_263 PEM_RESERVED_7 U32.0 Reserved for PEM. Counter Container_264 PEM_RESERVED_8 U32.0 Reserved for PEM. Counter Container_264 PEM_RESERVED_9 U32.0 Free running duration counter. Duration for which core frequency excursion occurred due to PMAX. Counter Container_265 PEM_PMAX U32.0 Reserved for PEM. Counter Container_265 PEM_RESERVED_10 U32.0 Reserved for PEM. Counter Container_266 PEM_RESERVED_11 U32.0 Reserved for PEM. Counter Container_266 PEM_RESERVED_12 U32.0 Reserved for PEM. Counter Container_267 PEM_RESERVED_13 U32.0 Reserved for PEM. Counter Container_267 PEM_RESERVED_14 U32.0 Reserved for PEM. Counter Container_268 PEM_RESERVED_15 U32.0 Reserved for PEM. Counter Container_268 PEM_RESERVED_16 U32.0 Reserved for PEM. Counter Container_269 PEM_RESERVED_17 U32.0 Reserved for PEM. Counter Container_269 PEM_RESERVED_18 U32.0 Reserved for PEM. Counter Container_270 PEM_RESERVED_19 U32.0 Reserved for PEM. Counter Container_270 PEM_RESERVED_20 U32.0 Reserved for PEM. Counter Container_271 PEM_RESERVED_21 U32.0 Reserved for PEM. Counter Container_271 PEM_RESERVED_22 U32.0 Reserved for PEM. Counter Container_272 PEM_RESERVED_23 U32.0 Reserved for PEM. Counter Container_272 PEM_RESERVED_24 U32.0 FIVR HBM Energy in uJ HBM 0 Snapshot Container_273 FIVR_HBM_ENERGY ebb_energy TSC Delta HBM 0. Snapshot Container_273 ART Container_0 XTAL_FREQ tsc FIVR HBM Energy in uJ HBM 1. Snapshot Container_274 FIVR_HBM_ENERGY_1 ebb_energy TSC Delta HBM 1. Snapshot Container_274 ART_1 Container_0 XTAL_FREQ tsc FIVR HBM Energy in uJ HBM 2. Snapshot Container_275 FIVR_HBM_ENERGY_2 ebb_energy TSC Delta HBM 2. Snapshot Container_275 ART_2 Container_0 XTAL_FREQ tsc FIVR HBM Energy in uJ HBM 3. Snapshot Container_276 FIVR_HBM_ENERGY_3 ebb_energy TSC Delta HBM 3. Snapshot Container_276 ART_3 Container_0 XTAL_FREQ tsc