/* * Copyright (C) 2022 MediaTek Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef HW_IMGSTREAM_INC_DRV_COMMON_7_1_MT8188_MTK_IMG_REG_USER_H_ #define HW_IMGSTREAM_INC_DRV_COMMON_7_1_MT8188_MTK_IMG_REG_USER_H_ #include #include "cam_raw_register.h" /** * Mediatek camera aks tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_aks { REG_R_AKS_TUNING AKS_TUNING; REG_R_AKS_CTRL AKS_CTRL; REG_R_AKS_SIZE AKS_SIZE; }; /** * Mediatek camera bpc tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_bpc { REG_R_BPC_BPC_FUNC_CON BPC_BPC_FUNC_CON; REG_R_BPC_BPC_IN_TH_1 BPC_BPC_IN_TH_1; REG_R_BPC_BPC_IN_TH_2 BPC_BPC_IN_TH_2; REG_R_BPC_BPC_IN_TH_3 BPC_BPC_IN_TH_3; REG_R_BPC_BPC_IN_TH_4 BPC_BPC_IN_TH_4; REG_R_BPC_BPC_IN_TH_5 BPC_BPC_IN_TH_5; REG_R_BPC_BPC_C_TH_1 BPC_BPC_C_TH_1; REG_R_BPC_BPC_C_TH_2 BPC_BPC_C_TH_2; REG_R_BPC_BPC_C_TH_3 BPC_BPC_C_TH_3; REG_R_BPC_BPC_DET BPC_BPC_DET; REG_R_BPC_BPC_COR BPC_BPC_COR; REG_R_BPC_BPC_RANK BPC_BPC_RANK; REG_R_BPC_BPC_BLD_1 BPC_BPC_BLD_1; REG_R_BPC_BPC_BLD_2 BPC_BPC_BLD_2; REG_R_BPC_BPC_LL BPC_BPC_LL; REG_R_BPC_CT_CON BPC_CT_CON; REG_R_BPC_CT_BLD_1 BPC_CT_BLD_1; REG_R_BPC_CT_BLD_2 BPC_CT_BLD_2; REG_R_BPC_PDC_CON BPC_PDC_CON; REG_R_BPC_PDC_CUR_BI BPC_PDC_CUR_BI; REG_R_BPC_PDC_CUR_AG BPC_PDC_CUR_AG; REG_R_BPC_PDC_TH_N BPC_PDC_TH_N; REG_R_BPC_PDC_DIFF_TH_GR_1 BPC_PDC_DIFF_TH_GR_1; REG_R_BPC_PDC_DIFF_TH_GR_2 BPC_PDC_DIFF_TH_GR_2; REG_R_BPC_PDC_DIFF_TH_GR_3 BPC_PDC_DIFF_TH_GR_3; REG_R_BPC_PDC_DIFF_TH_GB_1 BPC_PDC_DIFF_TH_GB_1; REG_R_BPC_PDC_DIFF_TH_GB_2 BPC_PDC_DIFF_TH_GB_2; REG_R_BPC_PDC_DIFF_TH_GB_3 BPC_PDC_DIFF_TH_GB_3; REG_R_BPC_PDC_DIFF_TH_R_1 BPC_PDC_DIFF_TH_R_1; REG_R_BPC_PDC_DIFF_TH_R_2 BPC_PDC_DIFF_TH_R_2; REG_R_BPC_PDC_DIFF_TH_R_3 BPC_PDC_DIFF_TH_R_3; REG_R_BPC_PDC_DIFF_TH_B_1 BPC_PDC_DIFF_TH_B_1; REG_R_BPC_PDC_DIFF_TH_B_2 BPC_PDC_DIFF_TH_B_2; REG_R_BPC_PDC_DIFF_TH_B_3 BPC_PDC_DIFF_TH_B_3; REG_R_BPC_PDC_BLD_WT BPC_PDC_BLD_WT; REG_R_BPC_PDC_GAIN_G BPC_PDC_GAIN_G; REG_R_BPC_PDC_GAIN_RB BPC_PDC_GAIN_RB; REG_R_BPC_PDC_OS_TH BPC_PDC_OS_TH; REG_R_BPC_BPC_ZHDR_TUN BPC_BPC_ZHDR_TUN; REG_R_BPC_BPC_OBC_ZOFST BPC_BPC_OBC_ZOFST; REG_R_BPC_BPC_PD_EXC_CON BPC_BPC_PD_EXC_CON; REG_R_BPC_BPC_AUX_MAP_FW BPC_BPC_AUX_MAP_FW; REG_R_BPC_CT_RCCC_CT_FW BPC_CT_RCCC_CT_FW; REG_R_BPC_PDC_CUR_AG_FW BPC_PDC_CUR_AG_FW; REG_R_BPC_BPC_ZHDR_CON_FW BPC_BPC_ZHDR_CON_FW; REG_R_BPC_BPC_ZHDR_RMG_FW BPC_BPC_ZHDR_RMG_FW; REG_R_BPC_BPC_OBC_OFST_R_FW BPC_BPC_OBC_OFST_R_FW; REG_R_BPC_BPC_OBC_OFST_B_FW BPC_BPC_OBC_OFST_B_FW; REG_R_BPC_BPC_OBC_OFST_GR_FW BPC_BPC_OBC_OFST_GR_FW; REG_R_BPC_BPC_OBC_OFST_GB_FW BPC_BPC_OBC_OFST_GB_FW; REG_R_BPC_BPC_CON_TILE BPC_BPC_CON_TILE; REG_R_BPC_BPC_OFFSET_TILE BPC_BPC_OFFSET_TILE; REG_R_BPC_BPC_SIZE_TILE BPC_BPC_SIZE_TILE; }; /** * Mediatek camera c2g tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_c2g { REG_R_C2G_CONV_0A C2G_CONV_0A; REG_R_C2G_CONV_0B C2G_CONV_0B; REG_R_C2G_CONV_1A C2G_CONV_1A; REG_R_C2G_CONV_1B C2G_CONV_1B; REG_R_C2G_CONV_2A C2G_CONV_2A; REG_R_C2G_CONV_2B C2G_CONV_2B; }; /** * Mediatek camera ccm tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_ccm { REG_R_CCM_CNV_1 CCM_CNV_1; REG_R_CCM_CNV_2 CCM_CNV_2; REG_R_CCM_CNV_3 CCM_CNV_3; REG_R_CCM_CNV_4 CCM_CNV_4; REG_R_CCM_CNV_5 CCM_CNV_5; REG_R_CCM_CNV_6 CCM_CNV_6; REG_R_CCM_CTRL CCM_CTRL; REG_R_CCM_CFC_CTRL1 CCM_CFC_CTRL1; REG_R_CCM_CFC_CTRL2 CCM_CFC_CTRL2; REG_R_CCM_HLT_CY_T1 CCM_HLT_CY_T1; REG_R_CCM_HLT_CY_T2 CCM_HLT_CY_T2; REG_R_CCM_HLT_RB_T1 CCM_HLT_RB_T1; REG_R_CCM_HLT_RB_T2 CCM_HLT_RB_T2; REG_R_CCM_HLT_GN_T1 CCM_HLT_GN_T1; REG_R_CCM_HLT_GN_T2 CCM_HLT_GN_T2; REG_R_CCM_HLT_CY_S CCM_HLT_CY_S; REG_R_CCM_HLT_RB_S CCM_HLT_RB_S; REG_R_CCM_HLT_GN_S CCM_HLT_GN_S; REG_R_CCM_HLT_CY_W CCM_HLT_CY_W; REG_R_CCM_HLT_RB_W CCM_HLT_RB_W; REG_R_CCM_HLT_GN_W CCM_HLT_GN_W; }; /** * Mediatek camera cnr tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_cnr { REG_R_CNR_CNR_CTRL CNR_CNR_CTRL; REG_R_CNR_CNR_YLUT1 CNR_CNR_YLUT1; REG_R_CNR_CNR_YLUT2 CNR_CNR_YLUT2; REG_R_CNR_CNR_YLUT3 CNR_CNR_YLUT3; REG_R_CNR_CNR_SLUT1 CNR_CNR_SLUT1; REG_R_CNR_CNR_SLUT2 CNR_CNR_SLUT2; REG_R_CNR_CNR_SLUT3 CNR_CNR_SLUT3; REG_R_CNR_CNR_RNG1 CNR_CNR_RNG1; REG_R_CNR_CNR_RNG2 CNR_CNR_RNG2; REG_R_CNR_CNR_STD1 CNR_CNR_STD1; REG_R_CNR_CNR_STD2 CNR_CNR_STD2; REG_R_CNR_CNR_LLUT1 CNR_CNR_LLUT1; REG_R_CNR_CNR_LLUT2 CNR_CNR_LLUT2; REG_R_CNR_CNR_LLUT3 CNR_CNR_LLUT3; REG_R_CNR_CNR_CBLD CNR_CNR_CBLD; UINT32 rsv_983C; REG_R_CNR_CNR_MED1 CNR_CNR_MED1; REG_R_CNR_CNR_MED2 CNR_CNR_MED2; REG_R_CNR_CNR_MED3 CNR_CNR_MED3; REG_R_CNR_CNR_MED4 CNR_CNR_MED4; REG_R_CNR_CNR_MED5 CNR_CNR_MED5; REG_R_CNR_CNR_MED6 CNR_CNR_MED6; REG_R_CNR_CNR_MED7 CNR_CNR_MED7; REG_R_CNR_CNR_MED8 CNR_CNR_MED8; REG_R_CNR_CNR_MED9 CNR_CNR_MED9; REG_R_CNR_CNR_MED10 CNR_CNR_MED10; REG_R_CNR_CNR_MED11 CNR_CNR_MED11; REG_R_CNR_CNR_MED12 CNR_CNR_MED12; REG_R_CNR_CNR_MED13 CNR_CNR_MED13; REG_R_CNR_TILE_SIZE CNR_TILE_SIZE; REG_R_CNR_CNR_RSV1 CNR_CNR_RSV1; REG_R_CNR_CNR_RSV2 CNR_CNR_RSV2; REG_R_CNR_CCR_CON CNR_CCR_CON; REG_R_CNR_CCR_YLUT CNR_CCR_YLUT; REG_R_CNR_CCR_UVLUT CNR_CCR_UVLUT; REG_R_CNR_CCR_YLUT2 CNR_CCR_YLUT2; REG_R_CNR_CCR_SAT_CTRL CNR_CCR_SAT_CTRL; REG_R_CNR_CCR_UVLUT_SP CNR_CCR_UVLUT_SP; REG_R_CNR_CCR_HUE1 CNR_CCR_HUE1; REG_R_CNR_CCR_HUE2 CNR_CCR_HUE2; REG_R_CNR_CCR_HUE3 CNR_CCR_HUE3; REG_R_CNR_CCR_L4LUT1 CNR_CCR_L4LUT1; REG_R_CNR_CCR_L4LUT2 CNR_CCR_L4LUT2; REG_R_CNR_CCR_L4LUT3 CNR_CCR_L4LUT3; REG_R_CNR_ABF_CON1 CNR_ABF_CON1; REG_R_CNR_ABF_CON2 CNR_ABF_CON2; REG_R_CNR_ABF_RCON CNR_ABF_RCON; REG_R_CNR_ABF_YLUT CNR_ABF_YLUT; REG_R_CNR_ABF_CXLUT CNR_ABF_CXLUT; REG_R_CNR_ABF_CYLUT CNR_ABF_CYLUT; REG_R_CNR_ABF_YSP CNR_ABF_YSP; REG_R_CNR_ABF_CXSP CNR_ABF_CXSP; REG_R_CNR_ABF_CYSP CNR_ABF_CYSP; REG_R_CNR_ABF_CLP CNR_ABF_CLP; REG_R_CNR_ABF_RSV1 CNR_ABF_RSV1; REG_R_CNR_BOK_TUN CNR_BOK_TUN; REG_R_CNR_BOK_A_TBL00 CNR_BOK_A_TBL00; REG_R_CNR_BOK_A_TBL01 CNR_BOK_A_TBL01; REG_R_CNR_BOK_A_TBL02 CNR_BOK_A_TBL02; REG_R_CNR_BOK_A_TBL03 CNR_BOK_A_TBL03; REG_R_CNR_BOK_A_TBL04 CNR_BOK_A_TBL04; REG_R_CNR_BOK_A_TBL05 CNR_BOK_A_TBL05; REG_R_CNR_BOK_A_TBL06 CNR_BOK_A_TBL06; REG_R_CNR_BOK_A_TBL07 CNR_BOK_A_TBL07; REG_R_CNR_BOK_A_TBL08 CNR_BOK_A_TBL08; REG_R_CNR_BOK_A_TBL09 CNR_BOK_A_TBL09; REG_R_CNR_BOK_A_TBL10 CNR_BOK_A_TBL10; REG_R_CNR_BOK_A_TBL11 CNR_BOK_A_TBL11; REG_R_CNR_BOK_A_TBL12 CNR_BOK_A_TBL12; REG_R_CNR_BOK_A_TBL13 CNR_BOK_A_TBL13; REG_R_CNR_BOK_A_TBL14 CNR_BOK_A_TBL14; REG_R_CNR_BOK_A_TBL15 CNR_BOK_A_TBL15; REG_R_CNR_BOK_PD_TBL00 CNR_BOK_PD_TBL00; REG_R_CNR_BOK_PD_TBL01 CNR_BOK_PD_TBL01; REG_R_CNR_BOK_PD_TBL02 CNR_BOK_PD_TBL02; REG_R_CNR_BOK_PS_TBL00 CNR_BOK_PS_TBL00; REG_R_CNR_BOK_PS_TBL01 CNR_BOK_PS_TBL01; REG_R_CNR_BOK_PS_TBL02 CNR_BOK_PS_TBL02; REG_R_CNR_SLK_CEN CNR_SLK_CEN; REG_R_CNR_SLK_RR_CON0 CNR_SLK_RR_CON0; REG_R_CNR_SLK_RR_CON1 CNR_SLK_RR_CON1; REG_R_CNR_SLK_GAIN CNR_SLK_GAIN; REG_R_CNR_SLK_HRZ CNR_SLK_HRZ; REG_R_CNR_SLK_VRZ CNR_SLK_VRZ; REG_R_CNR_SLK_CROPX CNR_SLK_CROPX; REG_R_CNR_SLK_CROPY CNR_SLK_CROPY; REG_R_CNR_SLK_XOFF CNR_SLK_XOFF; REG_R_CNR_SLK_YOFF CNR_SLK_YOFF; REG_R_CNR_SLK_SLP_CON0 CNR_SLK_SLP_CON0; REG_R_CNR_SLK_SLP_CON1 CNR_SLK_SLP_CON1; REG_R_CNR_SLK_SLP_CON2 CNR_SLK_SLP_CON2; REG_R_CNR_SLK_SLP_CON3 CNR_SLK_SLP_CON3; REG_R_CNR_SLK_SIZE CNR_SLK_SIZE; }; /** * Mediatek camera dgn tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_dgn { REG_R_DGN_GN0 DGN_GN0; REG_R_DGN_GN1 DGN_GN1; REG_R_DGN_GN2 DGN_GN2; REG_R_DGN_GN3 DGN_GN3; REG_R_DGN_LINK DGN_LINK; }; /** * Mediatek camera dm tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_dm { REG_R_DM_INTP_CRS DM_INTP_CRS; REG_R_DM_INTP_NAT DM_INTP_NAT; REG_R_DM_INTP_AUG DM_INTP_AUG; REG_R_DM_LUMA_LUT1 DM_LUMA_LUT1; REG_R_DM_LUMA_LUT2 DM_LUMA_LUT2; REG_R_DM_SL_CTL DM_SL_CTL; REG_R_DM_HFTD_CTL DM_HFTD_CTL; REG_R_DM_NR_STR DM_NR_STR; REG_R_DM_NR_ACT DM_NR_ACT; REG_R_DM_HF_STR DM_HF_STR; REG_R_DM_HF_ACT1 DM_HF_ACT1; REG_R_DM_HF_ACT2 DM_HF_ACT2; REG_R_DM_CLIP DM_CLIP; REG_R_DM_DSB DM_DSB; REG_R_DM_TILE_EDGE DM_TILE_EDGE; REG_R_DM_P1_ACT DM_P1_ACT; REG_R_DM_LR_RAT DM_LR_RAT; REG_R_DM_HFTD_CTL2 DM_HFTD_CTL2; REG_R_DM_EST_CTL DM_EST_CTL; REG_R_DM_SPARE_2 DM_SPARE_2; REG_R_DM_SPARE_3 DM_SPARE_3; REG_R_DM_INT_CTL DM_INT_CTL; REG_R_DM_EE DM_EE; REG_R_DM_SPARE_1 DM_SPARE_1; REG_R_DM_LMT DM_LMT; REG_R_DM_RCCC DM_RCCC; REG_R_DM_HFD_1 DM_HFD_1; REG_R_DM_HFD_2 DM_HFD_2; UINT32 rsv_9070; REG_R_DM_SLK_CEN DM_SLK_CEN; REG_R_DM_SLK_RR_CON0 DM_SLK_RR_CON0; REG_R_DM_SLK_RR_CON1 DM_SLK_RR_CON1; REG_R_DM_SLK_GAIN DM_SLK_GAIN; REG_R_DM_SLK_HRZ DM_SLK_HRZ; REG_R_DM_SLK_VRZ DM_SLK_VRZ; REG_R_DM_SLK_CROPX DM_SLK_CROPX; REG_R_DM_SLK_CROPY DM_SLK_CROPY; REG_R_DM_SLK_XOFF DM_SLK_XOFF; REG_R_DM_SLK_YOFF DM_SLK_YOFF; REG_R_DM_SLK_SLP_CON0 DM_SLK_SLP_CON0; REG_R_DM_SLK_SLP_CON1 DM_SLK_SLP_CON1; REG_R_DM_SLK_SLP_CON2 DM_SLK_SLP_CON2; REG_R_DM_SLK_SLP_CON3 DM_SLK_SLP_CON3; REG_R_DM_SLK_SIZE DM_SLK_SIZE; }; /** * Mediatek camera drz8t tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_drz8t { REG_R_DRZ8T_CTL DRZ8T_CTL; REG_R_DRZ8T_C24_CROP_CTL DRZ8T_C24_CROP_CTL; REG_R_DRZ8T_IN_IMG DRZ8T_IN_IMG; REG_R_DRZ8T_OUT_IMG DRZ8T_OUT_IMG; REG_R_DRZ8T_HORI_STEP DRZ8T_HORI_STEP; REG_R_DRZ8T_VERT_STEP DRZ8T_VERT_STEP; REG_R_DRZ8T_HORI_INT_OFST DRZ8T_HORI_INT_OFST; REG_R_DRZ8T_HORI_SUB_OFST DRZ8T_HORI_SUB_OFST; REG_R_DRZ8T_VERT_INT_OFST DRZ8T_VERT_INT_OFST; REG_R_DRZ8T_VERT_SUB_OFST DRZ8T_VERT_SUB_OFST; }; /** * Mediatek camera drzh2n tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_drzh2n { REG_R_DRZH2N_CONTROL DRZH2N_CONTROL; REG_R_DRZH2N_IN_IMG DRZH2N_IN_IMG; REG_R_DRZH2N_OUT_IMG DRZH2N_OUT_IMG; REG_R_DRZH2N_HORI_INT_OFST DRZH2N_HORI_INT_OFST; REG_R_DRZH2N_HORI_SUB_OFST DRZH2N_HORI_SUB_OFST; REG_R_DRZH2N_VERT_INT_OFST DRZH2N_VERT_INT_OFST; REG_R_DRZH2N_VERT_SUB_OFST DRZH2N_VERT_SUB_OFST; REG_R_DRZH2N_HORI_STEP DRZH2N_HORI_STEP; REG_R_DRZH2N_VERT_STEP DRZH2N_VERT_STEP; UINT32 rsv_B024[7]; REG_R_DRZH2N_SHADOW_CTRL DRZH2N_SHADOW_CTRL; }; /** * Mediatek camera drzs4n tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_drzs4n { REG_R_DRZS4N_CONTROL DRZS4N_CONTROL; REG_R_DRZS4N_IN_IMG DRZS4N_IN_IMG; REG_R_DRZS4N_OUT_IMG DRZS4N_OUT_IMG; REG_R_DRZS4N_HORI_STEP DRZS4N_HORI_STEP; REG_R_DRZS4N_VERT_STEP DRZS4N_VERT_STEP; REG_R_DRZS4N_LUMA_HORI_INT_OFST DRZS4N_LUMA_HORI_INT_OFST; REG_R_DRZS4N_LUMA_HORI_SUB_OFST DRZS4N_LUMA_HORI_SUB_OFST; REG_R_DRZS4N_LUMA_VERT_INT_OFST DRZS4N_LUMA_VERT_INT_OFST; REG_R_DRZS4N_LUMA_VERT_SUB_OFST DRZS4N_LUMA_VERT_SUB_OFST; REG_R_DRZS4N_SHADOW_CTRL DRZS4N_SHADOW_CTRL; }; /** * Mediatek camera drzs8t tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_drzs8t { REG_R_DRZS8T_CTL DRZS8T_CTL; REG_R_DRZS8T_IN_IMG DRZS8T_IN_IMG; REG_R_DRZS8T_OUT_IMG DRZS8T_OUT_IMG; REG_R_DRZS8T_HORI_STEP DRZS8T_HORI_STEP; REG_R_DRZS8T_VERT_STEP DRZS8T_VERT_STEP; REG_R_DRZS8T_HORI_INT_OFST DRZS8T_HORI_INT_OFST; REG_R_DRZS8T_HORI_SUB_OFST DRZS8T_HORI_SUB_OFST; REG_R_DRZS8T_VERT_INT_OFST DRZS8T_VERT_INT_OFST; REG_R_DRZS8T_VERT_SUB_OFST DRZS8T_VERT_SUB_OFST; }; /** * Mediatek camera ee tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_ee { REG_R_EE_CTRL EE_CTRL; REG_R_EE_TOP_CTRL EE_TOP_CTRL; REG_R_EE_BLND_CTRL_1 EE_BLND_CTRL_1; REG_R_EE_BLND_CTRL_2 EE_BLND_CTRL_2; REG_R_EE_CORE_CTRL EE_CORE_CTRL; REG_R_EE_GN_CTRL_1 EE_GN_CTRL_1; REG_R_EE_LUMA_CTRL_1 EE_LUMA_CTRL_1; REG_R_EE_LUMA_CTRL_2 EE_LUMA_CTRL_2; REG_R_EE_LUMA_SLNK_CTRL EE_LUMA_SLNK_CTRL; REG_R_EE_GLUT_CTRL_1 EE_GLUT_CTRL_1; REG_R_EE_GLUT_CTRL_2 EE_GLUT_CTRL_2; REG_R_EE_GLUT_CTRL_3 EE_GLUT_CTRL_3; REG_R_EE_GLUT_CTRL_4 EE_GLUT_CTRL_4; REG_R_EE_GLUT_CTRL_5 EE_GLUT_CTRL_5; REG_R_EE_GLUT_CTRL_6 EE_GLUT_CTRL_6; REG_R_EE_ARTIFACT_CTRL EE_ARTIFACT_CTRL; REG_R_EE_CLIP_CTRL EE_CLIP_CTRL; REG_R_EE_GN_CTRL_2 EE_GN_CTRL_2; REG_R_EE_ST_CTRL_1 EE_ST_CTRL_1; REG_R_EE_ST_CTRL_2 EE_ST_CTRL_2; REG_R_EE_CE_CTRL EE_CE_CTRL; REG_R_EE_CE_SL_CTRL EE_CE_SL_CTRL; REG_R_EE_CBOOST_CTRL_1 EE_CBOOST_CTRL_1; REG_R_EE_CBOOST_CTRL_2 EE_CBOOST_CTRL_2; REG_R_EE_PBC1_CTRL_0 EE_PBC1_CTRL_0; REG_R_EE_PBC1_CTRL_1 EE_PBC1_CTRL_1; REG_R_EE_PBC1_CTRL_2 EE_PBC1_CTRL_2; REG_R_EE_PBC1_CTRL_3 EE_PBC1_CTRL_3; REG_R_EE_PBC2_CTRL_0 EE_PBC2_CTRL_0; REG_R_EE_PBC2_CTRL_1 EE_PBC2_CTRL_1; REG_R_EE_PBC2_CTRL_2 EE_PBC2_CTRL_2; REG_R_EE_PBC2_CTRL_3 EE_PBC2_CTRL_3; REG_R_EE_PBC3_CTRL_0 EE_PBC3_CTRL_0; REG_R_EE_PBC3_CTRL_1 EE_PBC3_CTRL_1; REG_R_EE_PBC3_CTRL_2 EE_PBC3_CTRL_2; REG_R_EE_PBC3_CTRL_3 EE_PBC3_CTRL_3; REG_R_EE_SE_Y_SPECL_CTRL EE_SE_Y_SPECL_CTRL; REG_R_EE_SE_EDGE_CTRL_1 EE_SE_EDGE_CTRL_1; REG_R_EE_SE_EDGE_CTRL_2 EE_SE_EDGE_CTRL_2; REG_R_EE_SE_CORE_CTRL_1 EE_SE_CORE_CTRL_1; REG_R_EE_SE_CORE_CTRL_2 EE_SE_CORE_CTRL_2; UINT32 rsv_9724; REG_R_EE_SLK_CEN EE_SLK_CEN; REG_R_EE_SLK_RR_CON0 EE_SLK_RR_CON0; REG_R_EE_SLK_RR_CON1 EE_SLK_RR_CON1; REG_R_EE_SLK_GAIN EE_SLK_GAIN; REG_R_EE_SLK_HRZ EE_SLK_HRZ; REG_R_EE_SLK_VRZ EE_SLK_VRZ; REG_R_EE_SLK_CROPX EE_SLK_CROPX; REG_R_EE_SLK_CROPY EE_SLK_CROPY; REG_R_EE_SLK_XOFF EE_SLK_XOFF; REG_R_EE_SLK_YOFF EE_SLK_YOFF; REG_R_EE_SLK_SLP_CON0 EE_SLK_SLP_CON0; REG_R_EE_SLK_SLP_CON1 EE_SLK_SLP_CON1; REG_R_EE_SLK_SLP_CON2 EE_SLK_SLP_CON2; REG_R_EE_SLK_SLP_CON3 EE_SLK_SLP_CON3; REG_R_EE_SLK_SIZE EE_SLK_SIZE; }; /** * Mediatek camera g2cx tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_g2cx { REG_R_G2CX_CONV_0A G2CX_CONV_0A; REG_R_G2CX_CONV_0B G2CX_CONV_0B; REG_R_G2CX_CONV_1A G2CX_CONV_1A; REG_R_G2CX_CONV_1B G2CX_CONV_1B; REG_R_G2CX_CONV_2A G2CX_CONV_2A; REG_R_G2CX_CONV_2B G2CX_CONV_2B; REG_R_G2CX_SHADE_CON_1 G2CX_SHADE_CON_1; REG_R_G2CX_SHADE_CON_2 G2CX_SHADE_CON_2; REG_R_G2CX_SHADE_CON_3 G2CX_SHADE_CON_3; REG_R_G2CX_SHADE_TAR G2CX_SHADE_TAR; REG_R_G2CX_SHADE_SP G2CX_SHADE_SP; }; /** * Mediatek camera ggm tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_ggm { REG_R_GGM_LUT GGM_LUT[256]; REG_R_GGM_CTRL GGM_CTRL; }; /** * Mediatek camera hlr tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_hlr { REG_R_HLR_EST_Y0 HLR_EST_Y0; REG_R_HLR_EST_Y1 HLR_EST_Y1; REG_R_HLR_EST_Y2 HLR_EST_Y2; REG_R_HLR_EST_Y3 HLR_EST_Y3; REG_R_HLR_EST_X0 HLR_EST_X0; REG_R_HLR_EST_X1 HLR_EST_X1; REG_R_HLR_EST_X2 HLR_EST_X2; REG_R_HLR_EST_X3 HLR_EST_X3; REG_R_HLR_EST_S0 HLR_EST_S0; REG_R_HLR_EST_S1 HLR_EST_S1; REG_R_HLR_EST_S2 HLR_EST_S2; REG_R_HLR_LMG HLR_LMG; REG_R_HLR_PRT HLR_PRT; REG_R_HLR_CLP HLR_CLP; REG_R_HLR_EFCT HLR_EFCT; REG_R_HLR_EST_DYN HLR_EST_DYN; REG_R_HLR_LINK HLR_LINK; REG_R_HLR_CTL HLR_CTL; REG_R_HLR_CTL2 HLR_CTL2; }; /** * Mediatek camera iggm tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_iggm { REG_R_IGGM_LUT IGGM_LUT[256]; REG_R_IGGM_CTRL IGGM_CTRL; }; /** * Mediatek camera lsc tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_lsc { REG_R_LSC_CTL1 LSC_CTL1; REG_R_LSC_CTL2 LSC_CTL2; REG_R_LSC_CTL3 LSC_CTL3; REG_R_LSC_LBLOCK LSC_LBLOCK; REG_R_LSC_FBLOCK LSC_FBLOCK; REG_R_LSC_RATIO LSC_RATIO; REG_R_LSC_TPIPE_OFST LSC_TPIPE_OFST; REG_R_LSC_TPIPE_SIZE LSC_TPIPE_SIZE; }; /** * Mediatek camera ltm tuning setting * All the member of this structure are confidential */ #define LTM_CURVE_SIZE_2 (1728) #define LTM_CLP_SIZE_2 (108) struct mtk_img_uapi_regmap_raw_ltm { REG_R_LTM_CTRL LTM_CTRL; REG_R_LTM_BLK_NUM LTM_BLK_NUM; REG_R_LTM_BLK_SZ LTM_BLK_SZ; REG_R_LTM_BLK_DIVX LTM_BLK_DIVX; REG_R_LTM_BLK_DIVY LTM_BLK_DIVY; REG_R_LTM_MAX_DIV LTM_MAX_DIV; UINT32 rsv_8818; REG_R_LTM_CLIP LTM_CLIP; REG_R_LTM_TILE_NUM LTM_TILE_NUM; REG_R_LTM_TILE_CNTX LTM_TILE_CNTX; REG_R_LTM_TILE_CNTY LTM_TILE_CNTY; UINT32 rsv_882C[2]; REG_R_LTM_CFG LTM_CFG; UINT32 rsv_8838[6]; REG_R_LTM_RESET LTM_RESET; REG_R_LTM_INTEN LTM_INTEN; REG_R_LTM_INTSTA LTM_INTSTA; REG_R_LTM_STATUS LTM_STATUS; REG_R_LTM_INPUT_COUNT LTM_INPUT_COUNT; REG_R_LTM_OUTPUT_COUNT LTM_OUTPUT_COUNT; REG_R_LTM_CHKSUM LTM_CHKSUM; REG_R_LTM_TILE_SIZE LTM_TILE_SIZE; REG_R_LTM_TILE_EDGE LTM_TILE_EDGE; REG_R_LTM_TILE_CROP LTM_TILE_CROP; REG_R_LTM_DUMMY_REG LTM_DUMMY_REG; REG_R_LTM_SRAM_CFG LTM_SRAM_CFG; REG_R_LTM_SRAM_STATUS LTM_SRAM_STATUS; UINT32 rsv_8884[4]; REG_R_LTM_ATPG LTM_ATPG; REG_R_LTM_SHADOW_CTRL LTM_SHADOW_CTRL; REG_R_LTM_CLIP_TH LTM_CLIP_TH; REG_R_LTM_GAIN_MAP LTM_GAIN_MAP; REG_R_LTM_CVNODE_GRP0 LTM_CVNODE_GRP0; REG_R_LTM_CVNODE_GRP1 LTM_CVNODE_GRP1; REG_R_LTM_CVNODE_GRP2 LTM_CVNODE_GRP2; REG_R_LTM_CVNODE_GRP3 LTM_CVNODE_GRP3; REG_R_LTM_CVNODE_GRP4 LTM_CVNODE_GRP4; REG_R_LTM_CVNODE_GRP5 LTM_CVNODE_GRP5; REG_R_LTM_CVNODE_GRP6 LTM_CVNODE_GRP6; REG_R_LTM_CVNODE_GRP7 LTM_CVNODE_GRP7; REG_R_LTM_CVNODE_GRP8 LTM_CVNODE_GRP8; REG_R_LTM_CVNODE_GRP9 LTM_CVNODE_GRP9; REG_R_LTM_CVNODE_GRP10 LTM_CVNODE_GRP10; REG_R_LTM_CVNODE_GRP11 LTM_CVNODE_GRP11; REG_R_LTM_CVNODE_GRP12 LTM_CVNODE_GRP12; REG_R_LTM_CVNODE_GRP13 LTM_CVNODE_GRP13; REG_R_LTM_CVNODE_GRP14 LTM_CVNODE_GRP14; REG_R_LTM_CVNODE_GRP15 LTM_CVNODE_GRP15; REG_R_LTM_CVNODE_GRP16 LTM_CVNODE_GRP16; REG_R_LTM_OUT_STR LTM_OUT_STR; UINT32 rsv_88EC; REG_R_LTM_AE_DEBUG_B_MSB LTM_AE_DEBUG_B_MSB; REG_R_LTM_AE_DEBUG_B_LSB LTM_AE_DEBUG_B_LSB; REG_R_LTM_AE_DEBUG_GB_MSB LTM_AE_DEBUG_GB_MSB; REG_R_LTM_AE_DEBUG_GB_LSB LTM_AE_DEBUG_GB_LSB; REG_R_LTM_AE_DEBUG_GR_MSB LTM_AE_DEBUG_GR_MSB; REG_R_LTM_AE_DEBUG_GR_LSB LTM_AE_DEBUG_GR_LSB; REG_R_LTM_AE_DEBUG_R_MSB LTM_AE_DEBUG_R_MSB; REG_R_LTM_AE_DEBUG_R_LSB LTM_AE_DEBUG_R_LSB; REG_R_LTM_ACT_WIN_X LTM_ACT_WIN_X; REG_R_LTM_ACT_WIN_Y LTM_ACT_WIN_Y; REG_R_LTMTC_CURVE LTMTC_CURVE[LTM_CURVE_SIZE_2]; REG_R_LTMTC_CLP LTMTC_CLP[LTM_CLP_SIZE_2]; }; /** * Mediatek camera me tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_me { REG_R_ME_TOP ME_TOP; REG_R_ME_FLOW_CTRL ME_FLOW_CTRL; REG_R_ME_DCM_CTRL ME_DCM_CTRL; REG_R_ME_SA_CTRL ME_SA_CTRL; REG_R_ME_DMA_CTRL0 ME_DMA_CTRL0; REG_R_ME_DMA_CTRL1 ME_DMA_CTRL1; REG_R_ME_DMA_CTRL2 ME_DMA_CTRL2; REG_R_ME_CONF_CTRL ME_CONF_CTRL; REG_R_ME_PITCH ME_PITCH; REG_R_ME_FRAME_SIZE ME_FRAME_SIZE; REG_R_ME_BASE_ADDR0 ME_BASE_ADDR0; REG_R_ME_BASE_ADDR1 ME_BASE_ADDR1; REG_R_ME_BASE_ADDR2 ME_BASE_ADDR2; REG_R_ME_BASE_ADDR3 ME_BASE_ADDR3; REG_R_ME_BASE_ADDR4 ME_BASE_ADDR4; REG_R_ME_BASE_ADDR5 ME_BASE_ADDR5; REG_R_ME_BASE_ADDR6 ME_BASE_ADDR6; REG_R_ME_BASE_ADDR7 ME_BASE_ADDR7; REG_R_ME_BASE_ADDR8 ME_BASE_ADDR8; REG_R_ME_BASE_ADDR9 ME_BASE_ADDR9; REG_R_ME_BASE_ADDR10 ME_BASE_ADDR10; REG_R_ME_BASE_ADDR11 ME_BASE_ADDR11; REG_R_ME_BASE_ADDR12 ME_BASE_ADDR12; REG_R_ME_BASE_ADDR13 ME_BASE_ADDR13; REG_R_ME_BASE_ADDR14 ME_BASE_ADDR14; REG_R_ME_BASE_ADDR15 ME_BASE_ADDR15; REG_R_ME_BASE_ADDR16 ME_BASE_ADDR16; REG_R_ME_BASE_ADDR17 ME_BASE_ADDR17; REG_R_ME_BASE_ADDR18 ME_BASE_ADDR18; REG_R_ME_BASE_ADDR19 ME_BASE_ADDR19; REG_R_ME_BASE_ADDR20 ME_BASE_ADDR20; REG_R_ME_BASE_ADDR21 ME_BASE_ADDR21; REG_R_ME_BASE_ADDR22 ME_BASE_ADDR22; REG_R_ME_BASE_ADDR23 ME_BASE_ADDR23; REG_R_ME_BASE_ADDR24 ME_BASE_ADDR24; REG_R_ME_BASE_ADDR25 ME_BASE_ADDR25; REG_R_ME_BASE_ADDR26 ME_BASE_ADDR26; REG_R_ME_BASE_ADDR27 ME_BASE_ADDR27; REG_R_ME_BASE_ADDR28 ME_BASE_ADDR28; REG_R_ME_BASE_ADDR29 ME_BASE_ADDR29; REG_R_ME_BASE_ADDR30 ME_BASE_ADDR30; REG_R_ME_BASE_ADDR31 ME_BASE_ADDR31; REG_R_ME_BASE_ADDR32 ME_BASE_ADDR32; REG_R_ME_BASE_ADDR33 ME_BASE_ADDR33; REG_R_ME_BASE_ADDR34 ME_BASE_ADDR34; REG_R_ME_BASE_ADDR35 ME_BASE_ADDR35; REG_R_ME_BASE_ADDR36 ME_BASE_ADDR36; REG_R_ME_BASE_ADDR37 ME_BASE_ADDR37; REG_R_ME_BASE_ADDR38 ME_BASE_ADDR38; REG_R_ME_BASE_ADDR39 ME_BASE_ADDR39; REG_R_ME_BASE_ADDR40 ME_BASE_ADDR40; REG_R_ME_GROUP_OFFSET0 ME_GROUP_OFFSET0; REG_R_ME_GROUP_OFFSET1 ME_GROUP_OFFSET1; REG_R_ME_GROUP_OFFSET2 ME_GROUP_OFFSET2; REG_R_ME_TRIG ME_TRIG; REG_R_ME_INTR_EN ME_INTR_EN; REG_R_ME_INTR_STA ME_INTR_STA; REG_R_ME_ME_TCY_SLOPE_CTRL1 ME_ME_TCY_SLOPE_CTRL1; REG_R_ME_ME_TCY_SLOPE_CTRL2 ME_ME_TCY_SLOPE_CTRL2; REG_R_ME_ME_TCY_SLOPE_CTRL3 ME_ME_TCY_SLOPE_CTRL3; REG_R_ME_ME_TCY_SLOPE_CTRL4 ME_ME_TCY_SLOPE_CTRL4; REG_R_ME_FRAME_DRZ_APL ME_FRAME_DRZ_APL; REG_R_ME_HW2_APL_CTRL ME_HW2_APL_CTRL; REG_R_ME_INK_CTRL ME_INK_CTRL; REG_R_ME_INK_MASK ME_INK_MASK; REG_R_ME_INK_COLOR0 ME_INK_COLOR0; REG_R_ME_INK_COLOR1 ME_INK_COLOR1; REG_R_ME_INK_COLOR2 ME_INK_COLOR2; REG_R_ME_INK_COLOR3 ME_INK_COLOR3; REG_R_ME_INK_MV_0 ME_INK_MV_0; REG_R_ME_INK_MV_1 ME_INK_MV_1; REG_R_ME_ME_FORCE_MV_1 ME_ME_FORCE_MV_1; REG_R_ME_ME_FORCE_MV_2 ME_ME_FORCE_MV_2; REG_R_ME_CRC_CTRL ME_CRC_CTRL; REG_R_ME_DBG_CTRL ME_DBG_CTRL; REG_R_ME_RESERVE0 ME_RESERVE0; REG_R_ME_RESERVE1 ME_RESERVE1; REG_R_ME_DFTC ME_DFTC; UINT32 rsv_0138[18]; REG_R_ME_DMA_SEC_CTRL_0 ME_DMA_SEC_CTRL_0; REG_R_ME_DMA_SEC_CTRL_1 ME_DMA_SEC_CTRL_1; REG_R_ME_DMA_SEC_CTRL_2 ME_DMA_SEC_CTRL_2; UINT32 rsv_018C[29]; REG_R_ME_ME_LUMA_CMPS_CTRL ME_ME_LUMA_CMPS_CTRL; REG_R_ME_ME_CURR_BLK_CTRL_1 ME_ME_CURR_BLK_CTRL_1; REG_R_ME_ME_CURR_BLK_CTRL_2 ME_ME_CURR_BLK_CTRL_2; REG_R_ME_ME_CURR_BLK_CANDIDATE_CTRL ME_ME_CURR_BLK_CANDIDATE_CTRL; REG_R_ME_ME_CURR_BLK_COST_CTRL_1 ME_ME_CURR_BLK_COST_CTRL_1; REG_R_ME_ME_L0_CURR_BLK_COST_CTRL ME_ME_L0_CURR_BLK_COST_CTRL; REG_R_ME_ME_L0_RAND_HORZ_LUT_1 ME_ME_L0_RAND_HORZ_LUT_1; REG_R_ME_ME_L0_RAND_HORZ_LUT_2 ME_ME_L0_RAND_HORZ_LUT_2; REG_R_ME_ME_L0_RAND_VERT_LUT_1 ME_ME_L0_RAND_VERT_LUT_1; REG_R_ME_ME_L0_RAND_VERT_LUT_2 ME_ME_L0_RAND_VERT_LUT_2; REG_R_ME_ME_L0_VAR_TO_CORNER_LEVEL_CTRL1 ME_ME_L0_VAR_TO_CORNER_LEVEL_CTRL1; REG_R_ME_ME_L0_VAR_TO_CORNER_LEVEL_CTRL2 ME_ME_L0_VAR_TO_CORNER_LEVEL_CTRL2; REG_R_ME_ME_L0_HARRIS_TO_CORNER_LEVEL_CTRL1 ME_ME_L0_HARRIS_TO_CORNER_LEVEL_CTRL1; REG_R_ME_ME_L0_HARRIS_TO_CORNER_LEVEL_CTRL2 ME_ME_L0_HARRIS_TO_CORNER_LEVEL_CTRL2; REG_R_ME_ME_L0_HARRIS_TO_CORNER_LEVEL_CTRL3 ME_ME_L0_HARRIS_TO_CORNER_LEVEL_CTRL3; REG_R_ME_ME_L0_HARRIS_TO_CORNER_LEVEL_CTRL4 ME_ME_L0_HARRIS_TO_CORNER_LEVEL_CTRL4; REG_R_ME_ME_L0_HARRIS_TO_CORNER_LEVEL_CTRL5 ME_ME_L0_HARRIS_TO_CORNER_LEVEL_CTRL5; REG_R_ME_ME_L0_HARRIS_TO_CORNER_LEVEL_CTRL6 ME_ME_L0_HARRIS_TO_CORNER_LEVEL_CTRL6; REG_R_ME_ME_L1_CURR_BLK_COST_CTRL ME_ME_L1_CURR_BLK_COST_CTRL; REG_R_ME_ME_L1_RAND_HORZ_LUT_1 ME_ME_L1_RAND_HORZ_LUT_1; REG_R_ME_ME_L1_RAND_HORZ_LUT_2 ME_ME_L1_RAND_HORZ_LUT_2; REG_R_ME_ME_L1_RAND_VERT_LUT_1 ME_ME_L1_RAND_VERT_LUT_1; REG_R_ME_ME_L1_RAND_VERT_LUT_2 ME_ME_L1_RAND_VERT_LUT_2; REG_R_ME_ME_L1_VAR_TO_CORNER_LEVEL_CTRL1 ME_ME_L1_VAR_TO_CORNER_LEVEL_CTRL1; REG_R_ME_ME_L1_VAR_TO_CORNER_LEVEL_CTRL2 ME_ME_L1_VAR_TO_CORNER_LEVEL_CTRL2; REG_R_ME_ME_L1_HARRIS_TO_CORNER_LEVEL_CTRL1 ME_ME_L1_HARRIS_TO_CORNER_LEVEL_CTRL1; REG_R_ME_ME_L1_HARRIS_TO_CORNER_LEVEL_CTRL2 ME_ME_L1_HARRIS_TO_CORNER_LEVEL_CTRL2; REG_R_ME_ME_L1_HARRIS_TO_CORNER_LEVEL_CTRL3 ME_ME_L1_HARRIS_TO_CORNER_LEVEL_CTRL3; REG_R_ME_ME_L1_HARRIS_TO_CORNER_LEVEL_CTRL4 ME_ME_L1_HARRIS_TO_CORNER_LEVEL_CTRL4; REG_R_ME_ME_L1_HARRIS_TO_CORNER_LEVEL_CTRL5 ME_ME_L1_HARRIS_TO_CORNER_LEVEL_CTRL5; REG_R_ME_ME_L1_HARRIS_TO_CORNER_LEVEL_CTRL6 ME_ME_L1_HARRIS_TO_CORNER_LEVEL_CTRL6; REG_R_ME_ME_FRM_STAT_CTRL ME_ME_FRM_STAT_CTRL; REG_R_ME_ME_SEARCH_RANGE ME_ME_SEARCH_RANGE; REG_R_ME_MVP_SEARCH_RANGE ME_MVP_SEARCH_RANGE; REG_R_ME_ME_L0_HISTOGRAM_MV_1 ME_ME_L0_HISTOGRAM_MV_1; REG_R_ME_ME_L0_HISTOGRAM_MV_2 ME_ME_L0_HISTOGRAM_MV_2; REG_R_ME_ME_L0_HISTOGRAM_MV_3 ME_ME_L0_HISTOGRAM_MV_3; REG_R_ME_ME_L0_HISTOGRAM_MV_4 ME_ME_L0_HISTOGRAM_MV_4; REG_R_ME_ME_L1_HISTOGRAM_MV_1 ME_ME_L1_HISTOGRAM_MV_1; REG_R_ME_ME_L1_HISTOGRAM_MV_2 ME_ME_L1_HISTOGRAM_MV_2; REG_R_ME_ME_L1_HISTOGRAM_MV_3 ME_ME_L1_HISTOGRAM_MV_3; REG_R_ME_ME_L1_HISTOGRAM_MV_4 ME_ME_L1_HISTOGRAM_MV_4; REG_R_ME_CONF_HARRIS_1 ME_CONF_HARRIS_1; REG_R_ME_CONF_HARRIS_2 ME_CONF_HARRIS_2; REG_R_ME_CONF_HARRIS_3 ME_CONF_HARRIS_3; REG_R_ME_CONF_MV_BLK_EDGE_1 ME_CONF_MV_BLK_EDGE_1; REG_R_ME_CONF_MV_BLK_EDGE_2 ME_CONF_MV_BLK_EDGE_2; REG_R_ME_CONF_MV_BLK_EDGE_3 ME_CONF_MV_BLK_EDGE_3; REG_R_ME_CONF_MV_FIL ME_CONF_MV_FIL; REG_R_ME_CONF_PARAM1 ME_CONF_PARAM1; REG_R_ME_CONF_PARAM2 ME_CONF_PARAM2; REG_R_ME_MV_FIL ME_MV_FIL; REG_R_ME_MV_BLD_SLF_WT_0 ME_MV_BLD_SLF_WT_0; REG_R_ME_MV_BLD_SLF_WT_1 ME_MV_BLD_SLF_WT_1; REG_R_ME_MV_BLD_SLF_WT_2 ME_MV_BLD_SLF_WT_2; REG_R_ME_MV2MAP_HORI_STEP ME_MV2MAP_HORI_STEP; REG_R_ME_MV2MAP_VERT_STEP ME_MV2MAP_VERT_STEP; REG_R_ME_MV2MAP_HORI_INT_OFST ME_MV2MAP_HORI_INT_OFST; REG_R_ME_MV2MAP_HORI_SUB_OFST ME_MV2MAP_HORI_SUB_OFST; REG_R_ME_MV2MAP_VERT_INT_OFST ME_MV2MAP_VERT_INT_OFST; REG_R_ME_MV2MAP_VERT_SUB_OFST ME_MV2MAP_VERT_SUB_OFST; UINT32 rsv_02F4[3]; REG_R_ME_CONF_MV ME_CONF_MV; REG_R_ME_CONF_SAD ME_CONF_SAD; REG_R_ME_CONF_SLK_SAD_1 ME_CONF_SLK_SAD_1; REG_R_ME_CONF_SLK_SAD_2 ME_CONF_SLK_SAD_2; REG_R_ME_CONF_SLK_SAD_3 ME_CONF_SLK_SAD_3; REG_R_ME_CONF_FRM_STAT1 ME_CONF_FRM_STAT1; REG_R_ME_CONF_FRM_STAT2 ME_CONF_FRM_STAT2; REG_R_ME_ME_CURR_BLK_CTRL_3 ME_ME_CURR_BLK_CTRL_3; REG_R_ME_ME_CURR_BLK_CTRL_4 ME_ME_CURR_BLK_CTRL_4; REG_R_ME_ME_CURR_BLK_COST_CTRL_2 ME_ME_CURR_BLK_COST_CTRL_2; REG_R_ME_ME_L0_CURR_BLK_CTRL_1 ME_ME_L0_CURR_BLK_CTRL_1; REG_R_ME_ME_L0_CURR_BLK_CTRL_2 ME_ME_L0_CURR_BLK_CTRL_2; REG_R_ME_ME_L0_RAND_PNLTY_CTRL ME_ME_L0_RAND_PNLTY_CTRL; REG_R_ME_ME_L0_AVG_PNLTY_CTRL_1 ME_ME_L0_AVG_PNLTY_CTRL_1; REG_R_ME_ME_L0_TMPR_PNLTY_CTRL_1 ME_ME_L0_TMPR_PNLTY_CTRL_1; REG_R_ME_ME_L0_HIER_PNLTY_CTRL ME_ME_L0_HIER_PNLTY_CTRL; REG_R_ME_ME_L0_MV_PNLTY_CTRL ME_ME_L0_MV_PNLTY_CTRL; REG_R_ME_ME_L0_STILL_STRIP_CTRL_1 ME_ME_L0_STILL_STRIP_CTRL_1; REG_R_ME_ME_L0_STILL_STRIP_CTRL_2 ME_ME_L0_STILL_STRIP_CTRL_2; REG_R_ME_ME_L0_STILL_STRIP_CTRL_3 ME_ME_L0_STILL_STRIP_CTRL_3; REG_R_ME_ME_L0_DENOISE_CTRL1 ME_ME_L0_DENOISE_CTRL1; REG_R_ME_ME_L0_DENOISE_CTRL2 ME_ME_L0_DENOISE_CTRL2; REG_R_ME_ME_L0_DENOISE_CTRL3 ME_ME_L0_DENOISE_CTRL3; REG_R_ME_ME_L0_DENOISE_CTRL4 ME_ME_L0_DENOISE_CTRL4; REG_R_ME_ME_L0_DENOISE_CTRL5 ME_ME_L0_DENOISE_CTRL5; REG_R_ME_ME_L0_DENOISE_CTRL6 ME_ME_L0_DENOISE_CTRL6; REG_R_ME_ME_L0_DENOISE_CTRL7 ME_ME_L0_DENOISE_CTRL7; REG_R_ME_ME_L0_DENOISE_CTRL8 ME_ME_L0_DENOISE_CTRL8; REG_R_ME_ME_L0_PREPARE_MV_CTRL ME_ME_L0_PREPARE_MV_CTRL; REG_R_ME_ME_L1_CURR_BLK_CTRL_1 ME_ME_L1_CURR_BLK_CTRL_1; REG_R_ME_ME_L1_CURR_BLK_CTRL_2 ME_ME_L1_CURR_BLK_CTRL_2; REG_R_ME_ME_L1_RAND_PNLTY_CTRL ME_ME_L1_RAND_PNLTY_CTRL; REG_R_ME_ME_L1_AVG_PNLTY_CTRL_1 ME_ME_L1_AVG_PNLTY_CTRL_1; REG_R_ME_ME_L1_TMPR_PNLTY_CTRL_1 ME_ME_L1_TMPR_PNLTY_CTRL_1; REG_R_ME_ME_L1_MV_PNLTY_CTRL ME_ME_L1_MV_PNLTY_CTRL; REG_R_ME_ME_L1_STILL_STRIP_CTRL_1 ME_ME_L1_STILL_STRIP_CTRL_1; REG_R_ME_ME_L1_STILL_STRIP_CTRL_2 ME_ME_L1_STILL_STRIP_CTRL_2; REG_R_ME_ME_L1_STILL_STRIP_CTRL_3 ME_ME_L1_STILL_STRIP_CTRL_3; REG_R_ME_ME_L1_DENOISE_CTRL1 ME_ME_L1_DENOISE_CTRL1; REG_R_ME_ME_L1_DENOISE_CTRL2 ME_ME_L1_DENOISE_CTRL2; REG_R_ME_ME_L1_DENOISE_CTRL3 ME_ME_L1_DENOISE_CTRL3; REG_R_ME_ME_L1_DENOISE_CTRL4 ME_ME_L1_DENOISE_CTRL4; REG_R_ME_ME_L1_DENOISE_CTRL5 ME_ME_L1_DENOISE_CTRL5; REG_R_ME_ME_L1_DENOISE_CTRL6 ME_ME_L1_DENOISE_CTRL6; REG_R_ME_ME_L1_DENOISE_CTRL7 ME_ME_L1_DENOISE_CTRL7; REG_R_ME_ME_L1_DENOISE_CTRL8 ME_ME_L1_DENOISE_CTRL8; REG_R_ME_ME_L1_PREPARE_MV_CTRL ME_ME_L1_PREPARE_MV_CTRL; REG_R_ME_ME_FMB_PARAM0 ME_ME_FMB_PARAM0; REG_R_ME_ME_FMB_PARAM1 ME_ME_FMB_PARAM1; REG_R_ME_ME_MMG_MVCLUSTER_PARAM0 ME_ME_MMG_MVCLUSTER_PARAM0; REG_R_ME_ME_MMG_MVCLUSTER_PARAM1 ME_ME_MMG_MVCLUSTER_PARAM1; REG_R_ME_ME_MMG_PARAM0 ME_ME_MMG_PARAM0; REG_R_ME_ME_MMG_PARAM1 ME_ME_MMG_PARAM1; REG_R_ME_ME_MMG_PARAM2 ME_ME_MMG_PARAM2; REG_R_ME_ME_MMG_PARAM3 ME_ME_MMG_PARAM3; REG_R_ME_ME_GMM_PARAM0 ME_ME_GMM_PARAM0; REG_R_ME_ME_GMM_PARAM1 ME_ME_GMM_PARAM1; REG_R_ME_ME_GMM_PARAM2 ME_ME_GMM_PARAM2; REG_R_ME_ME_MMG_LCNF_PARAM0 ME_ME_MMG_LCNF_PARAM0; REG_R_ME_ME_MMG_LCNF_PARAM1 ME_ME_MMG_LCNF_PARAM1; REG_R_ME_ME_MMG_LCNF_PARAM2 ME_ME_MMG_LCNF_PARAM2; REG_R_ME_ME_MMG_LCNF_PARAM3 ME_ME_MMG_LCNF_PARAM3; REG_R_ME_ME_MMG_LCNF_PARAM4 ME_ME_MMG_LCNF_PARAM4; REG_R_ME_ME_MMG_LCNF_PARAM5 ME_ME_MMG_LCNF_PARAM5; REG_R_ME_ME_MMG_LCNF_PARAM6 ME_ME_MMG_LCNF_PARAM6; REG_R_ME_ME_MMG_LCNF_PARAM7 ME_ME_MMG_LCNF_PARAM7; REG_R_ME_ME_MMG_MODEL0 ME_ME_MMG_MODEL0; REG_R_ME_ME_MMG_MODEL1 ME_ME_MMG_MODEL1; REG_R_ME_ME_MMG_MODEL2 ME_ME_MMG_MODEL2; REG_R_ME_ME_MMG_MODEL3 ME_ME_MMG_MODEL3; REG_R_ME_ME_MMG_MODEL4 ME_ME_MMG_MODEL4; REG_R_ME_ME_MMG_MODEL5 ME_ME_MMG_MODEL5; REG_R_ME_ME_MMG_MODEL6 ME_ME_MMG_MODEL6; REG_R_ME_ME_MMG_MODEL7 ME_ME_MMG_MODEL7; REG_R_ME_ME_MMG_RST0 ME_ME_MMG_RST0; REG_R_ME_ME_MMG_RST1 ME_ME_MMG_RST1; REG_R_ME_ME_MMG_LCNF_PARAM8 ME_ME_MMG_LCNF_PARAM8; REG_R_ME_ME_MMG_LCNF_PARAM9 ME_ME_MMG_LCNF_PARAM9; REG_R_ME_ME_MMG_LCNF_PARAM10 ME_ME_MMG_LCNF_PARAM10; REG_R_ME_ME_MMG_LCNF_PARAM11 ME_ME_MMG_LCNF_PARAM11; REG_R_ME_ME_MMG_LCNF_PARAM12 ME_ME_MMG_LCNF_PARAM12; REG_R_ME_ME_MMG_LCNF_PARAM13 ME_ME_MMG_LCNF_PARAM13; REG_R_ME_ME_MMG_RGN00 ME_ME_MMG_RGN00; REG_R_ME_ME_MMG_RGN04 ME_ME_MMG_RGN04; REG_R_ME_ME_MMG_RGN08 ME_ME_MMG_RGN08; REG_R_ME_ME_MMG_RGN0C ME_ME_MMG_RGN0C; REG_R_ME_ME_MMG_RGN10 ME_ME_MMG_RGN10; REG_R_ME_ME_MMG_RGN14 ME_ME_MMG_RGN14; REG_R_ME_ME_MMG_RGN18 ME_ME_MMG_RGN18; REG_R_ME_ME_MMG_RGN1C ME_ME_MMG_RGN1C; REG_R_ME_ME_MMG_RGN20 ME_ME_MMG_RGN20; REG_R_ME_ME_MMG_RGN24 ME_ME_MMG_RGN24; REG_R_ME_ME_MMG_RGN28 ME_ME_MMG_RGN28; REG_R_ME_ME_MMG_RGN2C ME_ME_MMG_RGN2C; REG_R_ME_ME_MMG_RGN30 ME_ME_MMG_RGN30; REG_R_ME_ME_MMG_RGN34 ME_ME_MMG_RGN34; REG_R_ME_ME_MMG_RGN38 ME_ME_MMG_RGN38; REG_R_ME_ME_MMG_RGN3C ME_ME_MMG_RGN3C; REG_R_ME_ME_MMG_RGN40 ME_ME_MMG_RGN40; REG_R_ME_ME_MMG_RGN44 ME_ME_MMG_RGN44; REG_R_ME_ME_MMG_RGN48 ME_ME_MMG_RGN48; REG_R_ME_ME_MMG_RGN4C ME_ME_MMG_RGN4C; REG_R_ME_ME_MMG_RGN50 ME_ME_MMG_RGN50; REG_R_ME_ME_MMG_RGN54 ME_ME_MMG_RGN54; REG_R_ME_ME_MMG_RGN58 ME_ME_MMG_RGN58; REG_R_ME_ME_MMG_RGN5C ME_ME_MMG_RGN5C; REG_R_ME_ME_HISTOGRAM_MV_1 ME_ME_HISTOGRAM_MV_1; REG_R_ME_ME_HISTOGRAM_MV_2 ME_ME_HISTOGRAM_MV_2; REG_R_ME_ME_HISTOGRAM_MV_3 ME_ME_HISTOGRAM_MV_3; REG_R_ME_ME_HISTOGRAM_MV_4 ME_ME_HISTOGRAM_MV_4; REG_R_ME_ME_HISTOGRAM_MV_5 ME_ME_HISTOGRAM_MV_5; REG_R_ME_ME_HISTOGRAM_MV_6 ME_ME_HISTOGRAM_MV_6; REG_R_ME_SLK_CEN ME_SLK_CEN; REG_R_ME_SLK_RR_CON0 ME_SLK_RR_CON0; REG_R_ME_SLK_RR_CON1 ME_SLK_RR_CON1; REG_R_ME_SLK_GAIN ME_SLK_GAIN; REG_R_ME_SLK_HRZ ME_SLK_HRZ; REG_R_ME_SLK_VRZ ME_SLK_VRZ; REG_R_ME_SLK_SLP_CON0 ME_SLK_SLP_CON0; REG_R_ME_SLK_SLP_CON1 ME_SLK_SLP_CON1; REG_R_ME_SLK_SLP_CON2 ME_SLK_SLP_CON2; REG_R_ME_SLK_SLP_CON3 ME_SLK_SLP_CON3; REG_R_ME_SLK_CROPX ME_SLK_CROPX; REG_R_ME_SLK_CROPY ME_SLK_CROPY; UINT32 rsv_04F0[68]; REG_R_ME_HW1_APL_STA ME_HW1_APL_STA; REG_R_ME_ME_MMG_MVCLUSTER0 ME_ME_MMG_MVCLUSTER0; REG_R_ME_ME_MMG_MVCLUSTER1 ME_ME_MMG_MVCLUSTER1; REG_R_ME_ME_MMG_MVCLUSTER2 ME_ME_MMG_MVCLUSTER2; REG_R_ME_ME_MMG_MVCLUSTER3 ME_ME_MMG_MVCLUSTER3; REG_R_ME_ME_MMG_MVCLUSTER4 ME_ME_MMG_MVCLUSTER4; REG_R_ME_ME_MMG_MVCLUSTER5 ME_ME_MMG_MVCLUSTER5; REG_R_ME_ME_MMG_MVCLUSTER6 ME_ME_MMG_MVCLUSTER6; REG_R_ME_ME_MMG_MVCLUSTER7 ME_ME_MMG_MVCLUSTER7; REG_R_ME_ME_MMG_MVCLUSTER_CNT0 ME_ME_MMG_MVCLUSTER_CNT0; REG_R_ME_ME_MMG_MVCLUSTER_CNT2 ME_ME_MMG_MVCLUSTER_CNT2; REG_R_ME_ME_MMG_MVCLUSTER_CNT4 ME_ME_MMG_MVCLUSTER_CNT4; REG_R_ME_ME_MMG_MVCLUSTER_CNT6 ME_ME_MMG_MVCLUSTER_CNT6; REG_R_ME_ME_FRM_STAT1 ME_ME_FRM_STAT1; REG_R_ME_ME_FRM_STAT2 ME_ME_FRM_STAT2; REG_R_ME_ME_FRM_STAT3 ME_ME_FRM_STAT3; REG_R_ME_ME_FRM_STAT4 ME_ME_FRM_STAT4; REG_R_ME_ME_FRM_STAT5 ME_ME_FRM_STAT5; REG_R_ME_ME_FRM_STAT6 ME_ME_FRM_STAT6; REG_R_ME_ME_FRM_STAT7 ME_ME_FRM_STAT7; REG_R_ME_ME_FRM_STAT8 ME_ME_FRM_STAT8; REG_R_ME_ME_FRM_STAT9 ME_ME_FRM_STAT9; REG_R_ME_ME_FRM_STAT10 ME_ME_FRM_STAT10; REG_R_ME_ME_FRM_STAT11 ME_ME_FRM_STAT11; REG_R_ME_ME_FRM_STAT12 ME_ME_FRM_STAT12; REG_R_ME_ME_FRM_STAT13 ME_ME_FRM_STAT13; REG_R_ME_ME_FRM_STAT14 ME_ME_FRM_STAT14; REG_R_ME_ME_FRM_STAT15 ME_ME_FRM_STAT15; REG_R_ME_ME_FRM_STAT16 ME_ME_FRM_STAT16; REG_R_ME_ME_FRM_STAT17 ME_ME_FRM_STAT17; REG_R_ME_ME_FRM_STAT18 ME_ME_FRM_STAT18; REG_R_ME_ME_FRM_STAT19 ME_ME_FRM_STAT19; REG_R_ME_ME_FRM_STAT20 ME_ME_FRM_STAT20; REG_R_ME_ME_FRM_STAT21 ME_ME_FRM_STAT21; REG_R_ME_ME_FRM_STAT22 ME_ME_FRM_STAT22; REG_R_ME_ME_FRM_STAT23 ME_ME_FRM_STAT23; REG_R_ME_ME_FRM_STAT24 ME_ME_FRM_STAT24; REG_R_ME_ME_FRM_STAT25 ME_ME_FRM_STAT25; REG_R_ME_ME_FRM_STAT26 ME_ME_FRM_STAT26; REG_R_ME_ME_FRM_STAT27 ME_ME_FRM_STAT27; REG_R_ME_ME_FRM_STAT28 ME_ME_FRM_STAT28; REG_R_ME_ME_FRM_STAT29 ME_ME_FRM_STAT29; REG_R_ME_ME_FRM_STAT30 ME_ME_FRM_STAT30; REG_R_ME_ME_FRM_STAT31 ME_ME_FRM_STAT31; REG_R_ME_ME_FRM_STAT32 ME_ME_FRM_STAT32; REG_R_ME_ME_FRM_STAT33 ME_ME_FRM_STAT33; REG_R_ME_ME_FRM_STAT34 ME_ME_FRM_STAT34; REG_R_ME_ME_FRM_STAT35 ME_ME_FRM_STAT35; REG_R_ME_ME_FRM_STAT36 ME_ME_FRM_STAT36; REG_R_ME_ME_FRM_STAT37 ME_ME_FRM_STAT37; REG_R_ME_ME_FRM_STAT38 ME_ME_FRM_STAT38; REG_R_ME_ME_FRM_STAT39 ME_ME_FRM_STAT39; REG_R_ME_ME_FRM_STAT40 ME_ME_FRM_STAT40; REG_R_ME_ME_FRM_STAT41 ME_ME_FRM_STAT41; REG_R_ME_ME_FRM_STAT42 ME_ME_FRM_STAT42; REG_R_ME_ME_FRM_STAT43 ME_ME_FRM_STAT43; REG_R_ME_ME_FRM_STAT44 ME_ME_FRM_STAT44; REG_R_ME_ME_FRM_STAT45 ME_ME_FRM_STAT45; REG_R_ME_ME_FRM_STAT46 ME_ME_FRM_STAT46; REG_R_ME_ME_FRM_STAT47 ME_ME_FRM_STAT47; REG_R_ME_ME_FRM_STAT48 ME_ME_FRM_STAT48; REG_R_ME_ME_FRM_STAT49 ME_ME_FRM_STAT49; REG_R_ME_ME_FRM_STAT50 ME_ME_FRM_STAT50; REG_R_ME_ME_FRM_STAT51 ME_ME_FRM_STAT51; REG_R_ME_CONF_FRM_STAT3 ME_CONF_FRM_STAT3; REG_R_ME_CONF_FRM_STAT4 ME_CONF_FRM_STAT4; REG_R_ME_CONF_FRM_STAT5 ME_CONF_FRM_STAT5; REG_R_ME_CONF_FRM_STAT6 ME_CONF_FRM_STAT6; REG_R_ME_CONF_FRM_STAT7 ME_CONF_FRM_STAT7; REG_R_ME_CONF_FRM_STAT8 ME_CONF_FRM_STAT8; REG_R_ME_CONF_FRM_STAT9 ME_CONF_FRM_STAT9; REG_R_ME_CONF_FRM_STAT10 ME_CONF_FRM_STAT10; REG_R_ME_CONF_FRM_STAT11 ME_CONF_FRM_STAT11; REG_R_ME_CONF_FRM_STAT12 ME_CONF_FRM_STAT12; REG_R_ME_CONF_FRM_STAT13 ME_CONF_FRM_STAT13; REG_R_ME_CONF_FRM_STAT14 ME_CONF_FRM_STAT14; REG_R_ME_MV_VAL_HIST_X0 ME_MV_VAL_HIST_X0; REG_R_ME_MV_VAL_HIST_X1 ME_MV_VAL_HIST_X1; REG_R_ME_MV_VAL_HIST_X2 ME_MV_VAL_HIST_X2; REG_R_ME_MV_VAL_HIST_X3 ME_MV_VAL_HIST_X3; REG_R_ME_MV_VAL_HIST_X4 ME_MV_VAL_HIST_X4; REG_R_ME_MV_VAL_HIST_X5 ME_MV_VAL_HIST_X5; REG_R_ME_MV_VAL_HIST_X6 ME_MV_VAL_HIST_X6; REG_R_ME_MV_VAL_HIST_X7 ME_MV_VAL_HIST_X7; REG_R_ME_MV_VAL_HIST_X8 ME_MV_VAL_HIST_X8; REG_R_ME_MV_VAL_HIST_X9 ME_MV_VAL_HIST_X9; REG_R_ME_MV_VAL_HIST_X10 ME_MV_VAL_HIST_X10; REG_R_ME_MV_VAL_HIST_X11 ME_MV_VAL_HIST_X11; REG_R_ME_MV_VAL_HIST_Y0 ME_MV_VAL_HIST_Y0; REG_R_ME_MV_VAL_HIST_Y1 ME_MV_VAL_HIST_Y1; REG_R_ME_MV_VAL_HIST_Y2 ME_MV_VAL_HIST_Y2; REG_R_ME_MV_VAL_HIST_Y3 ME_MV_VAL_HIST_Y3; REG_R_ME_MV_VAL_HIST_Y4 ME_MV_VAL_HIST_Y4; REG_R_ME_MV_VAL_HIST_Y5 ME_MV_VAL_HIST_Y5; REG_R_ME_MV_VAL_HIST_Y6 ME_MV_VAL_HIST_Y6; REG_R_ME_MV_VAL_HIST_Y7 ME_MV_VAL_HIST_Y7; REG_R_ME_MV_EDGE_HIST_X0 ME_MV_EDGE_HIST_X0; REG_R_ME_MV_EDGE_HIST_X1 ME_MV_EDGE_HIST_X1; REG_R_ME_MV_EDGE_HIST_X2 ME_MV_EDGE_HIST_X2; REG_R_ME_MV_EDGE_HIST_X3 ME_MV_EDGE_HIST_X3; REG_R_ME_MV_EDGE_HIST_X4 ME_MV_EDGE_HIST_X4; REG_R_ME_MV_EDGE_HIST_X5 ME_MV_EDGE_HIST_X5; REG_R_ME_MV_EDGE_HIST_X6 ME_MV_EDGE_HIST_X6; REG_R_ME_MV_EDGE_HIST_X7 ME_MV_EDGE_HIST_X7; REG_R_ME_MV_EDGE_HIST_Y0 ME_MV_EDGE_HIST_Y0; REG_R_ME_MV_EDGE_HIST_Y1 ME_MV_EDGE_HIST_Y1; REG_R_ME_MV_EDGE_HIST_Y2 ME_MV_EDGE_HIST_Y2; REG_R_ME_MV_EDGE_HIST_Y3 ME_MV_EDGE_HIST_Y3; REG_R_ME_MV_EDGE_HIST_Y4 ME_MV_EDGE_HIST_Y4; REG_R_ME_MV_EDGE_HIST_Y5 ME_MV_EDGE_HIST_Y5; REG_R_ME_MV_EDGE_HIST_Y6 ME_MV_EDGE_HIST_Y6; REG_R_ME_MV_EDGE_HIST_Y7 ME_MV_EDGE_HIST_Y7; REG_R_ME_RDMA_APL_STA ME_RDMA_APL_STA; UINT32 rsv_07C4[15]; REG_R_ME_ME_RUN_STA ME_ME_RUN_STA; REG_R_ME_SMI_RD_CYC_STA ME_SMI_RD_CYC_STA; REG_R_ME_SMI_WT_CYC_STA ME_SMI_WT_CYC_STA; REG_R_ME_SMI_IF_STA ME_SMI_IF_STA; REG_R_ME_CTRL_DBG0 ME_CTRL_DBG0; REG_R_ME_CTRL_DBG1 ME_CTRL_DBG1; REG_R_ME_CTRL_DBG2 ME_CTRL_DBG2; REG_R_ME_MV_CLUS_DBG ME_MV_CLUS_DBG; REG_R_ME_MMG_CAND_DBG ME_MMG_CAND_DBG; REG_R_ME_RDMA_CRC ME_RDMA_CRC; REG_R_ME_WDMA_CRC ME_WDMA_CRC; REG_R_ME_MVS_CRC ME_MVS_CRC; REG_R_ME_MVP_CONF_DBG ME_MVP_CONF_DBG; REG_R_ME_MVP_URZ_DBG ME_MVP_URZ_DBG; REG_R_ME_MVP_SCAN_BUF_DBG ME_MVP_SCAN_BUF_DBG; REG_R_ME_SLK_DBG ME_SLK_DBG; }; /** * Mediatek camera ndg tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_ndg { REG_R_NDG_RAN_0 NDG_RAN_0; REG_R_NDG_RAN_1 NDG_RAN_1; REG_R_NDG_RAN_2 NDG_RAN_2; REG_R_NDG_RAN_3 NDG_RAN_3; REG_R_NDG_CROP_X NDG_CROP_X; REG_R_NDG_CROP_Y NDG_CROP_Y; }; /** * Mediatek camera obc tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_obc { REG_R_OBC_CTL OBC_CTL; REG_R_OBC_DBS OBC_DBS; REG_R_OBC_GRAY_BLD_0 OBC_GRAY_BLD_0; REG_R_OBC_GRAY_BLD_1 OBC_GRAY_BLD_1; REG_R_OBC_WBG_RB OBC_WBG_RB; REG_R_OBC_WBG_G OBC_WBG_G; REG_R_OBC_WBIG_RB OBC_WBIG_RB; REG_R_OBC_WBIG_G OBC_WBIG_G; REG_R_OBC_OBG_RB OBC_OBG_RB; REG_R_OBC_OBG_G OBC_OBG_G; REG_R_OBC_OFFSET_R OBC_OFFSET_R; REG_R_OBC_OFFSET_GR OBC_OFFSET_GR; REG_R_OBC_OFFSET_GB OBC_OFFSET_GB; REG_R_OBC_OFFSET_B OBC_OFFSET_B; REG_R_OBC_R_SUM_L OBC_R_SUM_L; REG_R_OBC_R_SUM_H OBC_R_SUM_H; REG_R_OBC_B_SUM_L OBC_B_SUM_L; REG_R_OBC_B_SUM_H OBC_B_SUM_H; REG_R_OBC_GR_SUM_L OBC_GR_SUM_L; REG_R_OBC_GR_SUM_H OBC_GR_SUM_H; REG_R_OBC_GB_SUM_L OBC_GB_SUM_L; REG_R_OBC_GB_SUM_H OBC_GB_SUM_H; REG_R_OBC_ACT_WIN_X OBC_ACT_WIN_X; REG_R_OBC_ACT_WIN_Y OBC_ACT_WIN_Y; REG_R_OBC_CMDL_ONLY_1 OBC_CMDL_ONLY_1; }; /** * Mediatek camera rec tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_rec { REG_R_REC_CTRL REC_CTRL; REG_R_REC_COR REC_COR; REG_R_REC_URZ_Y_ISIZE REC_URZ_Y_ISIZE; REG_R_REC_URZ_Y_OSIZE REC_URZ_Y_OSIZE; REG_R_REC_URZ_Y_HSTEP REC_URZ_Y_HSTEP; REG_R_REC_URZ_Y_VSTEP REC_URZ_Y_VSTEP; REG_R_REC_URZ_Y_HOFST REC_URZ_Y_HOFST; REG_R_REC_URZ_Y_VOFST REC_URZ_Y_VOFST; REG_R_REC_URZ_C_ISIZE REC_URZ_C_ISIZE; REG_R_REC_URZ_C_OSIZE REC_URZ_C_OSIZE; REG_R_REC_URZ_C_HSTEP REC_URZ_C_HSTEP; REG_R_REC_URZ_C_VSTEP REC_URZ_C_VSTEP; REG_R_REC_URZ_C_HOFST REC_URZ_C_HOFST; REG_R_REC_URZ_C_VOFST REC_URZ_C_VOFST; REG_R_REC_URZ_Y_XCROP REC_URZ_Y_XCROP; REG_R_REC_URZ_Y_YCROP REC_URZ_Y_YCROP; }; /** * Mediatek camera snrs tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_snrs { REG_R_SNRS_TBL SNRS_TBL[256]; REG_R_SNRS_CON1 SNRS_CON1; REG_R_SNRS_SM_EDGE SNRS_SM_EDGE; REG_R_SNRS_YNLM SNRS_YNLM; REG_R_SNRS_YIMP SNRS_YIMP; REG_R_SNRS_YAD1 SNRS_YAD1; REG_R_SNRS_YAD2 SNRS_YAD2; REG_R_SNRS_IPC_VAR SNRS_IPC_VAR; REG_R_SNRS_IPC_EDGE SNRS_IPC_EDGE; REG_R_SNRS_Y4LUT1 SNRS_Y4LUT1; REG_R_SNRS_Y4LUT2 SNRS_Y4LUT2; REG_R_SNRS_Y4LUT3 SNRS_Y4LUT3; REG_R_SNRS_Y4LUT4 SNRS_Y4LUT4; REG_R_SNRS_Y4LUT5 SNRS_Y4LUT5; REG_R_SNRS_Y4LUT6 SNRS_Y4LUT6; REG_R_SNRS_Y4LUT7 SNRS_Y4LUT7; REG_R_SNRS_SLK1 SNRS_SLK1; REG_R_SNRS_SLK2 SNRS_SLK2; REG_R_SNRS_SLK3 SNRS_SLK3; REG_R_SNRS_SLK4 SNRS_SLK4; REG_R_SNRS_STD1 SNRS_STD1; REG_R_SNRS_ACT1 SNRS_ACT1; REG_R_SNRS_ACT2 SNRS_ACT2; REG_R_SNRS_STDCON1 SNRS_STDCON1; REG_R_SNRS_STDCON3 SNRS_STDCON3; REG_R_SNRS_STDCON4 SNRS_STDCON4; REG_R_SNRS_STDCON5 SNRS_STDCON5; REG_R_SNRS_STDCON6 SNRS_STDCON6; REG_R_SNRS_YLVL0 SNRS_YLVL0; REG_R_SNRS_YLVL1 SNRS_YLVL1; REG_R_SNRS_HF_COR SNRS_HF_COR; REG_R_SNRS_HF_ACT4 SNRS_HF_ACT4; REG_R_SNRS_HF_ACT3 SNRS_HF_ACT3; REG_R_SNRS_HF_ACT2 SNRS_HF_ACT2; REG_R_SNRS_HF_ACT1 SNRS_HF_ACT1; REG_R_SNRS_HF_LUMA4 SNRS_HF_LUMA4; REG_R_SNRS_HF_LUMA3 SNRS_HF_LUMA3; REG_R_SNRS_HF_LUMA2 SNRS_HF_LUMA2; REG_R_SNRS_HF_LUMA1 SNRS_HF_LUMA1; REG_R_SNRS_ACTC SNRS_ACTC; REG_R_SNRS_TILE_SIZE SNRS_TILE_SIZE; REG_R_SNRS_RSV1 SNRS_RSV1; REG_R_SNRS_SLK_CEN SNRS_SLK_CEN; REG_R_SNRS_SLK_RR_CON0 SNRS_SLK_RR_CON0; REG_R_SNRS_SLK_RR_CON1 SNRS_SLK_RR_CON1; REG_R_SNRS_SLK_GAIN SNRS_SLK_GAIN; REG_R_SNRS_SLK_HRZ SNRS_SLK_HRZ; REG_R_SNRS_SLK_VRZ SNRS_SLK_VRZ; REG_R_SNRS_SLK_CROPX SNRS_SLK_CROPX; REG_R_SNRS_SLK_CROPY SNRS_SLK_CROPY; REG_R_SNRS_SLK_XOFF SNRS_SLK_XOFF; REG_R_SNRS_SLK_YOFF SNRS_SLK_YOFF; REG_R_SNRS_SLK_SLP_CON0 SNRS_SLK_SLP_CON0; REG_R_SNRS_SLK_SLP_CON1 SNRS_SLK_SLP_CON1; REG_R_SNRS_SLK_SLP_CON2 SNRS_SLK_SLP_CON2; REG_R_SNRS_SLK_SLP_CON3 SNRS_SLK_SLP_CON3; REG_R_SNRS_SLK_SIZE SNRS_SLK_SIZE; }; /** * Mediatek camera snr tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_snr { REG_R_SNR_TBL SNR_TBL[256]; REG_R_SNR_CON1 SNR_CON1; REG_R_SNR_SM_EDGE SNR_SM_EDGE; REG_R_SNR_YNLM SNR_YNLM; REG_R_SNR_YIMP SNR_YIMP; REG_R_SNR_YAD1 SNR_YAD1; REG_R_SNR_YAD2 SNR_YAD2; REG_R_SNR_IPC_VAR SNR_IPC_VAR; REG_R_SNR_IPC_EDGE SNR_IPC_EDGE; REG_R_SNR_Y4LUT1 SNR_Y4LUT1; REG_R_SNR_Y4LUT2 SNR_Y4LUT2; REG_R_SNR_Y4LUT3 SNR_Y4LUT3; REG_R_SNR_Y4LUT4 SNR_Y4LUT4; REG_R_SNR_Y4LUT5 SNR_Y4LUT5; REG_R_SNR_Y4LUT6 SNR_Y4LUT6; REG_R_SNR_Y4LUT7 SNR_Y4LUT7; REG_R_SNR_SLK1 SNR_SLK1; REG_R_SNR_SLK2 SNR_SLK2; REG_R_SNR_SLK3 SNR_SLK3; REG_R_SNR_SLK4 SNR_SLK4; REG_R_SNR_STD1 SNR_STD1; REG_R_SNR_STD2 SNR_STD2; REG_R_SNR_ACT1 SNR_ACT1; REG_R_SNR_ACT2 SNR_ACT2; REG_R_SNR_STDCON1 SNR_STDCON1; REG_R_SNR_STDCON2 SNR_STDCON2; REG_R_SNR_STDCON3 SNR_STDCON3; REG_R_SNR_STDCON4 SNR_STDCON4; REG_R_SNR_STDCON5 SNR_STDCON5; REG_R_SNR_STDCON6 SNR_STDCON6; REG_R_SNR_CATH SNR_CATH; REG_R_SNR_YLVL0 SNR_YLVL0; REG_R_SNR_YLVL1 SNR_YLVL1; REG_R_SNR_HF_COR SNR_HF_COR; REG_R_SNR_HF_ACT4 SNR_HF_ACT4; REG_R_SNR_HF_ACT3 SNR_HF_ACT3; REG_R_SNR_HF_ACT2 SNR_HF_ACT2; REG_R_SNR_HF_ACT1 SNR_HF_ACT1; REG_R_SNR_HF_LUMA4 SNR_HF_LUMA4; REG_R_SNR_HF_LUMA3 SNR_HF_LUMA3; REG_R_SNR_HF_LUMA2 SNR_HF_LUMA2; REG_R_SNR_HF_LUMA1 SNR_HF_LUMA1; REG_R_SNR_ACTC SNR_ACTC; REG_R_SNR_SKIN_CON SNR_SKIN_CON; REG_R_SNR_SKIN1_Y SNR_SKIN1_Y; REG_R_SNR_SKIN1_U SNR_SKIN1_U; REG_R_SNR_SKIN1_V SNR_SKIN1_V; REG_R_SNR_SKIN2_Y SNR_SKIN2_Y; REG_R_SNR_SKIN2_U SNR_SKIN2_U; REG_R_SNR_SKIN2_V SNR_SKIN2_V; REG_R_SNR_SKIN3_Y SNR_SKIN3_Y; REG_R_SNR_SKIN3_U SNR_SKIN3_U; REG_R_SNR_SKIN3_V SNR_SKIN3_V; REG_R_SNR_TNR_GAIN1 SNR_TNR_GAIN1; REG_R_SNR_TNR_GAIN2 SNR_TNR_GAIN2; REG_R_SNR_TNR_GAIN3 SNR_TNR_GAIN3; REG_R_SNR_TNR_GAIN4 SNR_TNR_GAIN4; REG_R_SNR_TNR_GAIN5 SNR_TNR_GAIN5; REG_R_SNR_TNR_GAIN6 SNR_TNR_GAIN6; REG_R_SNR_TILE_SIZE SNR_TILE_SIZE; REG_R_SNR_RSV1 SNR_RSV1; UINT32 rsv_94F0[4]; REG_R_SNR_SLK_CEN SNR_SLK_CEN; REG_R_SNR_SLK_RR_CON0 SNR_SLK_RR_CON0; REG_R_SNR_SLK_RR_CON1 SNR_SLK_RR_CON1; REG_R_SNR_SLK_GAIN SNR_SLK_GAIN; REG_R_SNR_SLK_HRZ SNR_SLK_HRZ; REG_R_SNR_SLK_VRZ SNR_SLK_VRZ; REG_R_SNR_SLK_CROPX SNR_SLK_CROPX; REG_R_SNR_SLK_CROPY SNR_SLK_CROPY; REG_R_SNR_SLK_XOFF SNR_SLK_XOFF; REG_R_SNR_SLK_YOFF SNR_SLK_YOFF; REG_R_SNR_SLK_SLP_CON0 SNR_SLK_SLP_CON0; REG_R_SNR_SLK_SLP_CON1 SNR_SLK_SLP_CON1; REG_R_SNR_SLK_SLP_CON2 SNR_SLK_SLP_CON2; REG_R_SNR_SLK_SLP_CON3 SNR_SLK_SLP_CON3; REG_R_SNR_SLK_SIZE SNR_SLK_SIZE; }; /** * Mediatek camera tcc tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_tcc { REG_R_TCC_LUT_0 TCC_LUT_0; REG_R_TCC_LUT_1 TCC_LUT_1; REG_R_TCC_LUT_2 TCC_LUT_2; REG_R_TCC_LUT_3 TCC_LUT_3; REG_R_TCC_LUT_4 TCC_LUT_4; REG_R_TCC_LUT_5 TCC_LUT_5; REG_R_TCC_LUT_6 TCC_LUT_6; REG_R_TCC_LUT_7 TCC_LUT_7; REG_R_TCC_LUT_8 TCC_LUT_8; REG_R_TCC_LUT_9 TCC_LUT_9; REG_R_TCC_LUT_10 TCC_LUT_10; REG_R_TCC_LUT_11 TCC_LUT_11; REG_R_TCC_LUT_12 TCC_LUT_12; REG_R_TCC_LUT_13 TCC_LUT_13; REG_R_TCC_LUT_14 TCC_LUT_14; REG_R_TCC_LUT_15 TCC_LUT_15; REG_R_TCC_LUT_16 TCC_LUT_16; REG_R_TCC_LUT_17 TCC_LUT_17; REG_R_TCC_LUT_18 TCC_LUT_18; REG_R_TCC_LUT_19 TCC_LUT_19; REG_R_TCC_LUT_20 TCC_LUT_20; REG_R_TCC_LUT_21 TCC_LUT_21; REG_R_TCC_LUT_22 TCC_LUT_22; REG_R_TCC_LUT_23 TCC_LUT_23; REG_R_TCC_LUT_24 TCC_LUT_24; REG_R_TCC_LUT_25 TCC_LUT_25; REG_R_TCC_LUT_26 TCC_LUT_26; REG_R_TCC_LUT_27 TCC_LUT_27; REG_R_TCC_LUT_28 TCC_LUT_28; REG_R_TCC_LUT_29 TCC_LUT_29; REG_R_TCC_LUT_30 TCC_LUT_30; REG_R_TCC_LUT_31 TCC_LUT_31; REG_R_TCC_LUT_32 TCC_LUT_32; REG_R_TCC_LUT_33 TCC_LUT_33; REG_R_TCC_LUT_34 TCC_LUT_34; REG_R_TCC_LUT_35 TCC_LUT_35; REG_R_TCC_LUT_36 TCC_LUT_36; REG_R_TCC_LUT_37 TCC_LUT_37; REG_R_TCC_LUT_38 TCC_LUT_38; REG_R_TCC_LUT_39 TCC_LUT_39; REG_R_TCC_LUT_40 TCC_LUT_40; REG_R_TCC_LUT_41 TCC_LUT_41; REG_R_TCC_LUT_42 TCC_LUT_42; REG_R_TCC_LUT_43 TCC_LUT_43; REG_R_TCC_LUT_44 TCC_LUT_44; REG_R_TCC_LUT_45 TCC_LUT_45; REG_R_TCC_LUT_46 TCC_LUT_46; REG_R_TCC_LUT_47 TCC_LUT_47; REG_R_TCC_LUT_48 TCC_LUT_48; REG_R_TCC_LUT_49 TCC_LUT_49; REG_R_TCC_LUT_50 TCC_LUT_50; REG_R_TCC_LUT_51 TCC_LUT_51; REG_R_TCC_LUT_52 TCC_LUT_52; REG_R_TCC_LUT_53 TCC_LUT_53; REG_R_TCC_LUT_54 TCC_LUT_54; REG_R_TCC_LUT_55 TCC_LUT_55; REG_R_TCC_LUT_56 TCC_LUT_56; REG_R_TCC_LUT_57 TCC_LUT_57; REG_R_TCC_LUT_58 TCC_LUT_58; REG_R_TCC_LUT_59 TCC_LUT_59; REG_R_TCC_LUT_60 TCC_LUT_60; REG_R_TCC_LUT_61 TCC_LUT_61; REG_R_TCC_LUT_62 TCC_LUT_62; REG_R_TCC_LUT_63 TCC_LUT_63; REG_R_TCC_LUT_64 TCC_LUT_64; REG_R_TCC_LUT_65 TCC_LUT_65; REG_R_TCC_LUT_66 TCC_LUT_66; REG_R_TCC_LUT_67 TCC_LUT_67; REG_R_TCC_LUT_68 TCC_LUT_68; REG_R_TCC_LUT_69 TCC_LUT_69; REG_R_TCC_LUT_70 TCC_LUT_70; REG_R_TCC_LUT_71 TCC_LUT_71; REG_R_TCC_LUT_72 TCC_LUT_72; REG_R_TCC_LUT_73 TCC_LUT_73; REG_R_TCC_LUT_74 TCC_LUT_74; REG_R_TCC_LUT_75 TCC_LUT_75; REG_R_TCC_LUT_76 TCC_LUT_76; REG_R_TCC_LUT_77 TCC_LUT_77; REG_R_TCC_LUT_78 TCC_LUT_78; REG_R_TCC_LUT_79 TCC_LUT_79; REG_R_TCC_LUT_80 TCC_LUT_80; REG_R_TCC_LUT_81 TCC_LUT_81; REG_R_TCC_LUT_82 TCC_LUT_82; REG_R_TCC_LUT_83 TCC_LUT_83; REG_R_TCC_LUT_84 TCC_LUT_84; REG_R_TCC_LUT_85 TCC_LUT_85; REG_R_TCC_LUT_86 TCC_LUT_86; REG_R_TCC_LUT_87 TCC_LUT_87; REG_R_TCC_LUT_88 TCC_LUT_88; REG_R_TCC_LUT_89 TCC_LUT_89; REG_R_TCC_LUT_90 TCC_LUT_90; REG_R_TCC_LUT_91 TCC_LUT_91; REG_R_TCC_LUT_92 TCC_LUT_92; REG_R_TCC_LUT_93 TCC_LUT_93; REG_R_TCC_LUT_94 TCC_LUT_94; REG_R_TCC_LUT_95 TCC_LUT_95; REG_R_TCC_LUT_96 TCC_LUT_96; REG_R_TCC_LUT_97 TCC_LUT_97; REG_R_TCC_LUT_98 TCC_LUT_98; REG_R_TCC_LUT_99 TCC_LUT_99; REG_R_TCC_LUT_100 TCC_LUT_100; REG_R_TCC_LUT_101 TCC_LUT_101; REG_R_TCC_LUT_102 TCC_LUT_102; REG_R_TCC_LUT_103 TCC_LUT_103; REG_R_TCC_LUT_104 TCC_LUT_104; REG_R_TCC_LUT_105 TCC_LUT_105; REG_R_TCC_LUT_106 TCC_LUT_106; REG_R_TCC_LUT_107 TCC_LUT_107; REG_R_TCC_LUT_108 TCC_LUT_108; REG_R_TCC_LUT_109 TCC_LUT_109; REG_R_TCC_LUT_110 TCC_LUT_110; REG_R_TCC_LUT_111 TCC_LUT_111; REG_R_TCC_LUT_112 TCC_LUT_112; REG_R_TCC_LUT_113 TCC_LUT_113; REG_R_TCC_LUT_114 TCC_LUT_114; REG_R_TCC_LUT_115 TCC_LUT_115; REG_R_TCC_LUT_116 TCC_LUT_116; REG_R_TCC_LUT_117 TCC_LUT_117; REG_R_TCC_LUT_118 TCC_LUT_118; REG_R_TCC_LUT_119 TCC_LUT_119; REG_R_TCC_LUT_120 TCC_LUT_120; REG_R_TCC_LUT_121 TCC_LUT_121; REG_R_TCC_LUT_122 TCC_LUT_122; REG_R_TCC_LUT_123 TCC_LUT_123; REG_R_TCC_LUT_124 TCC_LUT_124; REG_R_TCC_LUT_125 TCC_LUT_125; REG_R_TCC_LUT_126 TCC_LUT_126; REG_R_TCC_LUT_127 TCC_LUT_127; REG_R_TCC_LUT_128 TCC_LUT_128; REG_R_TCC_LUT_129 TCC_LUT_129; REG_R_TCC_LUT_130 TCC_LUT_130; REG_R_TCC_LUT_131 TCC_LUT_131; REG_R_TCC_LUT_132 TCC_LUT_132; REG_R_TCC_LUT_133 TCC_LUT_133; REG_R_TCC_LUT_134 TCC_LUT_134; REG_R_TCC_LUT_135 TCC_LUT_135; REG_R_TCC_LUT_136 TCC_LUT_136; REG_R_TCC_LUT_137 TCC_LUT_137; REG_R_TCC_LUT_138 TCC_LUT_138; REG_R_TCC_LUT_139 TCC_LUT_139; REG_R_TCC_LUT_140 TCC_LUT_140; REG_R_TCC_LUT_141 TCC_LUT_141; REG_R_TCC_LUT_142 TCC_LUT_142; REG_R_TCC_LUT_143 TCC_LUT_143; REG_R_TCC_LUT_144 TCC_LUT_144; REG_R_TCC_LUT_145 TCC_LUT_145; REG_R_TCC_LUT_146 TCC_LUT_146; REG_R_TCC_LUT_147 TCC_LUT_147; REG_R_TCC_LUT_148 TCC_LUT_148; REG_R_TCC_LUT_149 TCC_LUT_149; REG_R_TCC_LUT_150 TCC_LUT_150; REG_R_TCC_LUT_151 TCC_LUT_151; REG_R_TCC_LUT_152 TCC_LUT_152; REG_R_TCC_LUT_153 TCC_LUT_153; REG_R_TCC_LUT_154 TCC_LUT_154; REG_R_TCC_LUT_155 TCC_LUT_155; REG_R_TCC_LUT_156 TCC_LUT_156; REG_R_TCC_LUT_157 TCC_LUT_157; REG_R_TCC_LUT_158 TCC_LUT_158; REG_R_TCC_LUT_159 TCC_LUT_159; REG_R_TCC_LUT_160 TCC_LUT_160; REG_R_TCC_LUT_161 TCC_LUT_161; REG_R_TCC_LUT_162 TCC_LUT_162; REG_R_TCC_LUT_163 TCC_LUT_163; REG_R_TCC_LUT_164 TCC_LUT_164; REG_R_TCC_LUT_165 TCC_LUT_165; REG_R_TCC_LUT_166 TCC_LUT_166; REG_R_TCC_LUT_167 TCC_LUT_167; REG_R_TCC_LUT_168 TCC_LUT_168; REG_R_TCC_LUT_169 TCC_LUT_169; REG_R_TCC_LUT_170 TCC_LUT_170; REG_R_TCC_LUT_171 TCC_LUT_171; REG_R_TCC_LUT_172 TCC_LUT_172; REG_R_TCC_LUT_173 TCC_LUT_173; REG_R_TCC_LUT_174 TCC_LUT_174; REG_R_TCC_LUT_175 TCC_LUT_175; REG_R_TCC_LUT_176 TCC_LUT_176; REG_R_TCC_LUT_177 TCC_LUT_177; REG_R_TCC_LUT_178 TCC_LUT_178; REG_R_TCC_LUT_179 TCC_LUT_179; REG_R_TCC_LUT_180 TCC_LUT_180; REG_R_TCC_LUT_181 TCC_LUT_181; REG_R_TCC_LUT_182 TCC_LUT_182; REG_R_TCC_LUT_183 TCC_LUT_183; REG_R_TCC_LUT_184 TCC_LUT_184; REG_R_TCC_LUT_185 TCC_LUT_185; REG_R_TCC_LUT_186 TCC_LUT_186; REG_R_TCC_LUT_187 TCC_LUT_187; REG_R_TCC_LUT_188 TCC_LUT_188; REG_R_TCC_LUT_189 TCC_LUT_189; REG_R_TCC_LUT_190 TCC_LUT_190; REG_R_TCC_LUT_191 TCC_LUT_191; REG_R_TCC_LUT_192 TCC_LUT_192; REG_R_TCC_LUT_193 TCC_LUT_193; REG_R_TCC_LUT_194 TCC_LUT_194; REG_R_TCC_LUT_195 TCC_LUT_195; REG_R_TCC_LUT_196 TCC_LUT_196; REG_R_TCC_LUT_197 TCC_LUT_197; REG_R_TCC_LUT_198 TCC_LUT_198; REG_R_TCC_LUT_199 TCC_LUT_199; REG_R_TCC_LUT_200 TCC_LUT_200; REG_R_TCC_LUT_201 TCC_LUT_201; REG_R_TCC_LUT_202 TCC_LUT_202; REG_R_TCC_LUT_203 TCC_LUT_203; REG_R_TCC_LUT_204 TCC_LUT_204; REG_R_TCC_LUT_205 TCC_LUT_205; REG_R_TCC_LUT_206 TCC_LUT_206; REG_R_TCC_LUT_207 TCC_LUT_207; REG_R_TCC_LUT_208 TCC_LUT_208; REG_R_TCC_LUT_209 TCC_LUT_209; REG_R_TCC_LUT_210 TCC_LUT_210; REG_R_TCC_LUT_211 TCC_LUT_211; REG_R_TCC_LUT_212 TCC_LUT_212; REG_R_TCC_LUT_213 TCC_LUT_213; REG_R_TCC_LUT_214 TCC_LUT_214; REG_R_TCC_LUT_215 TCC_LUT_215; REG_R_TCC_LUT_216 TCC_LUT_216; REG_R_TCC_LUT_217 TCC_LUT_217; REG_R_TCC_LUT_218 TCC_LUT_218; REG_R_TCC_LUT_219 TCC_LUT_219; REG_R_TCC_LUT_220 TCC_LUT_220; REG_R_TCC_LUT_221 TCC_LUT_221; REG_R_TCC_LUT_222 TCC_LUT_222; REG_R_TCC_LUT_223 TCC_LUT_223; REG_R_TCC_LUT_224 TCC_LUT_224; REG_R_TCC_LUT_225 TCC_LUT_225; REG_R_TCC_LUT_226 TCC_LUT_226; REG_R_TCC_LUT_227 TCC_LUT_227; REG_R_TCC_LUT_228 TCC_LUT_228; REG_R_TCC_LUT_229 TCC_LUT_229; REG_R_TCC_LUT_230 TCC_LUT_230; REG_R_TCC_LUT_231 TCC_LUT_231; REG_R_TCC_LUT_232 TCC_LUT_232; REG_R_TCC_LUT_233 TCC_LUT_233; REG_R_TCC_LUT_234 TCC_LUT_234; REG_R_TCC_LUT_235 TCC_LUT_235; REG_R_TCC_LUT_236 TCC_LUT_236; REG_R_TCC_LUT_237 TCC_LUT_237; REG_R_TCC_LUT_238 TCC_LUT_238; REG_R_TCC_LUT_239 TCC_LUT_239; REG_R_TCC_LUT_240 TCC_LUT_240; REG_R_TCC_LUT_241 TCC_LUT_241; REG_R_TCC_LUT_242 TCC_LUT_242; REG_R_TCC_LUT_243 TCC_LUT_243; REG_R_TCC_LUT_244 TCC_LUT_244; REG_R_TCC_LUT_245 TCC_LUT_245; REG_R_TCC_LUT_246 TCC_LUT_246; REG_R_TCC_LUT_247 TCC_LUT_247; REG_R_TCC_LUT_248 TCC_LUT_248; REG_R_TCC_LUT_249 TCC_LUT_249; REG_R_TCC_LUT_250 TCC_LUT_250; REG_R_TCC_LUT_251 TCC_LUT_251; REG_R_TCC_LUT_252 TCC_LUT_252; REG_R_TCC_LUT_253 TCC_LUT_253; REG_R_TCC_LUT_254 TCC_LUT_254; REG_R_TCC_LUT_255 TCC_LUT_255; REG_R_TCC_LUT_END TCC_LUT_END; REG_R_TCC_C2G_CNV_0 TCC_C2G_CNV_0; REG_R_TCC_C2G_CNV_1 TCC_C2G_CNV_1; REG_R_TCC_C2G_CNV_2 TCC_C2G_CNV_2; REG_R_TCC_C2G_CNV_3 TCC_C2G_CNV_3; REG_R_TCC_C2G_CNV_4 TCC_C2G_CNV_4; REG_R_TCC_C2G_CNV_5 TCC_C2G_CNV_5; REG_R_TCC_G2C_CNV_0 TCC_G2C_CNV_0; REG_R_TCC_G2C_CNV_1 TCC_G2C_CNV_1; REG_R_TCC_G2C_CNV_2 TCC_G2C_CNV_2; REG_R_TCC_G2C_CNV_3 TCC_G2C_CNV_3; REG_R_TCC_G2C_CNV_4 TCC_G2C_CNV_4; REG_R_TCC_G2C_CNV_5 TCC_G2C_CNV_5; UINT32 rsv_5834[109]; REG_R_TCC_CROP_X TCC_CROP_X; REG_R_TCC_CROP_Y TCC_CROP_Y; REG_R_TCC_CROP2_X TCC_CROP2_X; REG_R_TCC_CROP2_Y TCC_CROP2_Y; REG_R_TCC_TILE TCC_TILE; }; /** * Mediatek camera tcy tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_tcy { REG_R_TCY_TC_G1 TCY_TC_G1; REG_R_TCY_TC_G2 TCY_TC_G2; REG_R_TCY_TC_G3 TCY_TC_G3; REG_R_TCY_TC_G4 TCY_TC_G4; REG_R_TCY_TC_G5 TCY_TC_G5; REG_R_TCY_TC_G6 TCY_TC_G6; REG_R_TCY_TC_G7 TCY_TC_G7; REG_R_TCY_TC_G8 TCY_TC_G8; REG_R_TCY_TC_G9 TCY_TC_G9; REG_R_TCY_TC_G10 TCY_TC_G10; REG_R_TCY_TC_G11 TCY_TC_G11; REG_R_TCY_TC_G12 TCY_TC_G12; REG_R_TCY_TC_G13 TCY_TC_G13; REG_R_TCY_TC_G14 TCY_TC_G14; REG_R_TCY_TC_G15 TCY_TC_G15; REG_R_TCY_TC_G16 TCY_TC_G16; REG_R_TCY_TC_G17 TCY_TC_G17; REG_R_TCY_TC_G18 TCY_TC_G18; REG_R_TCY_TC_G19 TCY_TC_G19; REG_R_TCY_TC_G20 TCY_TC_G20; REG_R_TCY_TC_G21 TCY_TC_G21; REG_R_TCY_TC_G22 TCY_TC_G22; REG_R_TCY_TC_G23 TCY_TC_G23; REG_R_TCY_TC_G24 TCY_TC_G24; REG_R_TCY_TC_G25 TCY_TC_G25; REG_R_TCY_TC_G26 TCY_TC_G26; REG_R_TCY_TC_G27 TCY_TC_G27; REG_R_TCY_TC_G28 TCY_TC_G28; REG_R_TCY_TC_G29 TCY_TC_G29; REG_R_TCY_TC_G30 TCY_TC_G30; REG_R_TCY_TC_G31 TCY_TC_G31; REG_R_TCY_TC_G32 TCY_TC_G32; REG_R_TCY_GAIN TCY_GAIN; REG_R_TCY_TCY_RESET TCY_TCY_RESET; REG_R_TCY_TCY_CFG TCY_TCY_CFG; REG_R_TCY_TCY_STATUS TCY_TCY_STATUS; REG_R_TCY_TCY_STATUS_C TCY_TCY_STATUS_C; REG_R_TCY_TCY_INPUT_COUNT TCY_TCY_INPUT_COUNT; REG_R_TCY_TCY_INPUT_COUNT_C TCY_TCY_INPUT_COUNT_C; REG_R_TCY_TCY_OUTPUT_COUNT TCY_TCY_OUTPUT_COUNT; REG_R_TCY_TCY_OUTPUT_COUNT_C TCY_TCY_OUTPUT_COUNT_C; REG_R_TCY_TCY_DUMMY_REG TCY_TCY_DUMMY_REG; REG_R_TCY_SIZE TCY_SIZE; REG_R_TCY_SIZE_C_CUSTOM TCY_SIZE_C_CUSTOM; }; /** * Mediatek camera tdshp tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_tdshp { REG_R_TDSHP_TDSHP_TDSHP_00 TDSHP_TDSHP_TDSHP_00; REG_R_TDSHP_TDSHP_TDSHP_01 TDSHP_TDSHP_TDSHP_01; REG_R_TDSHP_TDSHP_TDSHP_02 TDSHP_TDSHP_TDSHP_02; REG_R_TDSHP_TDSHP_TDSHP_03 TDSHP_TDSHP_TDSHP_03; UINT32 rsv_4010; REG_R_TDSHP_TDSHP_TDSHP_05 TDSHP_TDSHP_TDSHP_05; REG_R_TDSHP_TDSHP_TDSHP_06 TDSHP_TDSHP_TDSHP_06; REG_R_TDSHP_TDSHP_TDSHP_07 TDSHP_TDSHP_TDSHP_07; REG_R_TDSHP_TDSHP_TDSHP_08 TDSHP_TDSHP_TDSHP_08; REG_R_TDSHP_TDSHP_TDSHP_09 TDSHP_TDSHP_TDSHP_09; UINT32 rsv_4028[6]; REG_R_TDSHP_TDSHP_PBC_00 TDSHP_TDSHP_PBC_00; REG_R_TDSHP_TDSHP_PBC_01 TDSHP_TDSHP_PBC_01; REG_R_TDSHP_TDSHP_PBC_02 TDSHP_TDSHP_PBC_02; REG_R_TDSHP_TDSHP_PBC_03 TDSHP_TDSHP_PBC_03; REG_R_TDSHP_TDSHP_PBC_04 TDSHP_TDSHP_PBC_04; REG_R_TDSHP_TDSHP_PBC_05 TDSHP_TDSHP_PBC_05; REG_R_TDSHP_TDSHP_PBC_06 TDSHP_TDSHP_PBC_06; REG_R_TDSHP_TDSHP_PBC_07 TDSHP_TDSHP_PBC_07; REG_R_TDSHP_TDSHP_PBC_08 TDSHP_TDSHP_PBC_08; UINT32 rsv_4064[31]; REG_R_TDSHP_TDSHP_C_BOOST_MAIN TDSHP_TDSHP_C_BOOST_MAIN; REG_R_TDSHP_TDSHP_C_BOOST_MAIN_2 TDSHP_TDSHP_C_BOOST_MAIN_2; UINT32 rsv_40E8[5]; REG_R_TDSHP_TDSHP_TDSHP_ATPG TDSHP_TDSHP_TDSHP_ATPG; REG_R_TDSHP_TDSHP_TDSHP_CTRL TDSHP_TDSHP_TDSHP_CTRL; REG_R_TDSHP_TDSHP_TDSHP_INTEN TDSHP_TDSHP_TDSHP_INTEN; REG_R_TDSHP_TDSHP_TDSHP_INTSTA TDSHP_TDSHP_TDSHP_INTSTA; REG_R_TDSHP_TDSHP_TDSHP_STATUS TDSHP_TDSHP_TDSHP_STATUS; REG_R_TDSHP_TDSHP_TDSHP_CFG TDSHP_TDSHP_TDSHP_CFG; REG_R_TDSHP_TDSHP_TDSHP_INPUT_COUNT TDSHP_TDSHP_TDSHP_INPUT_COUNT; REG_R_TDSHP_TDSHP_TDSHP_CHKSUM TDSHP_TDSHP_TDSHP_CHKSUM; REG_R_TDSHP_TDSHP_TDSHP_OUTPUT_COUNT TDSHP_TDSHP_TDSHP_OUTPUT_COUNT; REG_R_TDSHP_TDSHP_TDSHP_INPUT_SIZE TDSHP_TDSHP_TDSHP_INPUT_SIZE; REG_R_TDSHP_TDSHP_TDSHP_OUTPUT_OFFSET TDSHP_TDSHP_TDSHP_OUTPUT_OFFSET; REG_R_TDSHP_TDSHP_TDSHP_OUTPUT_SIZE TDSHP_TDSHP_TDSHP_OUTPUT_SIZE; REG_R_TDSHP_TDSHP_TDSHP_BLANK_WIDTH TDSHP_TDSHP_TDSHP_BLANK_WIDTH; REG_R_TDSHP_TDSHP_TDSHP_DEMO_HMASK TDSHP_TDSHP_TDSHP_DEMO_HMASK; REG_R_TDSHP_TDSHP_TDSHP_DEMO_VMASK TDSHP_TDSHP_TDSHP_DEMO_VMASK; UINT32 rsv_4138[5]; REG_R_TDSHP_TDSHP_TDSHP_DUMMY_REG TDSHP_TDSHP_TDSHP_DUMMY_REG; UINT32 rsv_4150[108]; REG_R_TDSHP_TDSHP_EDF_GAIN_00 TDSHP_TDSHP_EDF_GAIN_00; REG_R_TDSHP_TDSHP_EDF_GAIN_01 TDSHP_TDSHP_EDF_GAIN_01; REG_R_TDSHP_TDSHP_EDF_GAIN_02 TDSHP_TDSHP_EDF_GAIN_02; REG_R_TDSHP_TDSHP_EDF_GAIN_03 TDSHP_TDSHP_EDF_GAIN_03; UINT32 rsv_4310; REG_R_TDSHP_TDSHP_EDF_GAIN_05 TDSHP_TDSHP_EDF_GAIN_05; UINT32 rsv_4318[2]; REG_R_TDSHP_TDSHP_TDSHP_10 TDSHP_TDSHP_TDSHP_10; REG_R_TDSHP_TDSHP_TDSHP_11 TDSHP_TDSHP_TDSHP_11; REG_R_TDSHP_TDSHP_TDSHP_12 TDSHP_TDSHP_TDSHP_12; REG_R_TDSHP_TDSHP_TDSHP_13 TDSHP_TDSHP_TDSHP_13; REG_R_TDSHP_TDSHP_TDSHP_PAT1_GEN_SET TDSHP_TDSHP_TDSHP_PAT1_GEN_SET; REG_R_TDSHP_TDSHP_TDSHP_PAT1_GEN_FRM_SIZE TDSHP_TDSHP_TDSHP_PAT1_GEN_FRM_SIZE; REG_R_TDSHP_TDSHP_TDSHP_PAT1_GEN_COLOR0 TDSHP_TDSHP_TDSHP_PAT1_GEN_COLOR0; REG_R_TDSHP_TDSHP_TDSHP_PAT1_GEN_COLOR1 TDSHP_TDSHP_TDSHP_PAT1_GEN_COLOR1; REG_R_TDSHP_TDSHP_TDSHP_PAT1_GEN_COLOR2 TDSHP_TDSHP_TDSHP_PAT1_GEN_COLOR2; REG_R_TDSHP_TDSHP_TDSHP_PAT1_GEN_POS TDSHP_TDSHP_TDSHP_PAT1_GEN_POS; UINT32 rsv_4348[3]; REG_R_TDSHP_TDSHP_TDSHP_PAT1_GEN_TILE_POS TDSHP_TDSHP_TDSHP_PAT1_GEN_TILE_POS; REG_R_TDSHP_TDSHP_TDSHP_PAT1_GEN_TILE_OV TDSHP_TDSHP_TDSHP_PAT1_GEN_TILE_OV; UINT32 rsv_435C; REG_R_TDSHP_TDSHP_TDSHP_PAT2_GEN_SET TDSHP_TDSHP_TDSHP_PAT2_GEN_SET; UINT32 rsv_4364; REG_R_TDSHP_TDSHP_TDSHP_PAT2_GEN_COLOR0 TDSHP_TDSHP_TDSHP_PAT2_GEN_COLOR0; REG_R_TDSHP_TDSHP_TDSHP_PAT2_GEN_COLOR1 TDSHP_TDSHP_TDSHP_PAT2_GEN_COLOR1; UINT32 rsv_4370; REG_R_TDSHP_TDSHP_TDSHP_PAT2_GEN_POS TDSHP_TDSHP_TDSHP_PAT2_GEN_POS; REG_R_TDSHP_TDSHP_TDSHP_PAT2_GEN_CURSOR_RB0 TDSHP_TDSHP_TDSHP_PAT2_GEN_CURSOR_RB0; REG_R_TDSHP_TDSHP_TDSHP_PAT2_GEN_CURSOR_RB1 TDSHP_TDSHP_TDSHP_PAT2_GEN_CURSOR_RB1; UINT32 rsv_4380; REG_R_TDSHP_TDSHP_TDSHP_PAT2_GEN_TILE_POS TDSHP_TDSHP_TDSHP_PAT2_GEN_TILE_POS; REG_R_TDSHP_TDSHP_TDSHP_PAT2_GEN_TILE_OV TDSHP_TDSHP_TDSHP_PAT2_GEN_TILE_OV; UINT32 rsv_438C[61]; REG_R_TDSHP_TDSHP_POST_YLEV_00 TDSHP_TDSHP_POST_YLEV_00; REG_R_TDSHP_TDSHP_POST_YLEV_01 TDSHP_TDSHP_POST_YLEV_01; REG_R_TDSHP_TDSHP_POST_YLEV_02 TDSHP_TDSHP_POST_YLEV_02; REG_R_TDSHP_TDSHP_POST_YLEV_03 TDSHP_TDSHP_POST_YLEV_03; REG_R_TDSHP_TDSHP_POST_YLEV_04 TDSHP_TDSHP_POST_YLEV_04; UINT32 rsv_4494[27]; REG_R_TDSHP_TDSHP_HFG_CTRL TDSHP_TDSHP_HFG_CTRL; REG_R_TDSHP_TDSHP_HFG_RAN_0 TDSHP_TDSHP_HFG_RAN_0; REG_R_TDSHP_TDSHP_HFG_RAN_1 TDSHP_TDSHP_HFG_RAN_1; REG_R_TDSHP_TDSHP_HFG_RAN_2 TDSHP_TDSHP_HFG_RAN_2; REG_R_TDSHP_TDSHP_HFG_RAN_3 TDSHP_TDSHP_HFG_RAN_3; REG_R_TDSHP_TDSHP_HFG_RAN_4 TDSHP_TDSHP_HFG_RAN_4; REG_R_TDSHP_TDSHP_HFG_CROP_X TDSHP_TDSHP_HFG_CROP_X; REG_R_TDSHP_TDSHP_HFG_CROP_Y TDSHP_TDSHP_HFG_CROP_Y; UINT32 rsv_4520; REG_R_TDSHP_TDSHP_HFC_CON_0 TDSHP_TDSHP_HFC_CON_0; REG_R_TDSHP_TDSHP_HFC_LUMA_0 TDSHP_TDSHP_HFC_LUMA_0; REG_R_TDSHP_TDSHP_HFC_LUMA_1 TDSHP_TDSHP_HFC_LUMA_1; REG_R_TDSHP_TDSHP_HFC_LUMA_2 TDSHP_TDSHP_HFC_LUMA_2; REG_R_TDSHP_TDSHP_HFC_SLK_0 TDSHP_TDSHP_HFC_SLK_0; REG_R_TDSHP_TDSHP_HFC_SLK_1 TDSHP_TDSHP_HFC_SLK_1; REG_R_TDSHP_TDSHP_HFC_SLK_2 TDSHP_TDSHP_HFC_SLK_2; UINT32 rsv_4540; REG_R_TDSHP_TDSHP_SLK_CEN TDSHP_TDSHP_SLK_CEN; REG_R_TDSHP_TDSHP_SLK_RR_CON0 TDSHP_TDSHP_SLK_RR_CON0; REG_R_TDSHP_TDSHP_SLK_RR_CON1 TDSHP_TDSHP_SLK_RR_CON1; REG_R_TDSHP_TDSHP_SLK_GAIN TDSHP_TDSHP_SLK_GAIN; REG_R_TDSHP_TDSHP_SLK_HRZ TDSHP_TDSHP_SLK_HRZ; REG_R_TDSHP_TDSHP_SLK_VRZ TDSHP_TDSHP_SLK_VRZ; REG_R_TDSHP_TDSHP_SLK_CROPX TDSHP_TDSHP_SLK_CROPX; REG_R_TDSHP_TDSHP_SLK_CROPY TDSHP_TDSHP_SLK_CROPY; REG_R_TDSHP_TDSHP_SLK_XOFF TDSHP_TDSHP_SLK_XOFF; REG_R_TDSHP_TDSHP_SLK_YOFF TDSHP_TDSHP_SLK_YOFF; REG_R_TDSHP_TDSHP_SLK_SLP_CON0 TDSHP_TDSHP_SLK_SLP_CON0; REG_R_TDSHP_TDSHP_SLK_SLP_CON1 TDSHP_TDSHP_SLK_SLP_CON1; REG_R_TDSHP_TDSHP_SLK_SLP_CON2 TDSHP_TDSHP_SLK_SLP_CON2; REG_R_TDSHP_TDSHP_SLK_SLP_CON3 TDSHP_TDSHP_SLK_SLP_CON3; REG_R_TDSHP_TDSHP_SLK_SIZE TDSHP_TDSHP_SLK_SIZE; UINT32 rsv_4580[33]; REG_R_TDSHP_TDSHP_HFG_ROUGHNESS TDSHP_TDSHP_HFG_ROUGHNESS; REG_R_TDSHP_TDSHP_RESERVE TDSHP_TDSHP_RESERVE; REG_R_TDSHP_TDSHP_SPEC_CTRL TDSHP_TDSHP_SPEC_CTRL; }; /** * Mediatek camera tncsc tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_tncsc { REG_R_TNCSC_PCRP_D13_X_POS TNCSC_PCRP_D13_X_POS; REG_R_TNCSC_PCRP_D13_Y_POS TNCSC_PCRP_D13_Y_POS; UINT32 rsv_A008; REG_R_TNCSC_C02_D3_CON1 TNCSC_C02_D3_CON1; REG_R_TNCSC_C02_D3_CON2 TNCSC_C02_D3_CON2; REG_R_TNCSC_C02_D3_CROP_CON1 TNCSC_C02_D3_CROP_CON1; REG_R_TNCSC_C02_D3_CROP_CON2 TNCSC_C02_D3_CROP_CON2; REG_R_TNCSC_C02_D3_IMG_SIZE TNCSC_C02_D3_IMG_SIZE; REG_R_TNCSC_C24_D2_TILE_EDGE TNCSC_C24_D2_TILE_EDGE; REG_R_TNCSC_C2G_D1_CONV_0A TNCSC_C2G_D1_CONV_0A; REG_R_TNCSC_C2G_D1_CONV_0B TNCSC_C2G_D1_CONV_0B; REG_R_TNCSC_C2G_D1_CONV_1A TNCSC_C2G_D1_CONV_1A; REG_R_TNCSC_C2G_D1_CONV_1B TNCSC_C2G_D1_CONV_1B; REG_R_TNCSC_C2G_D1_CONV_2A TNCSC_C2G_D1_CONV_2A; REG_R_TNCSC_C2G_D1_CONV_2B TNCSC_C2G_D1_CONV_2B; REG_R_TNCSC_IGGM_D1_LUT TNCSC_IGGM_D1_LUT[256]; REG_R_TNCSC_IGGM_D1_CTRL TNCSC_IGGM_D1_CTRL; REG_R_TNCSC_PCRP_D14_X_POS TNCSC_PCRP_D14_X_POS; REG_R_TNCSC_PCRP_D14_Y_POS TNCSC_PCRP_D14_Y_POS; REG_R_TNCSC_CMODEL_ONLY_1 TNCSC_CMODEL_ONLY_1; REG_R_TNCSC_CON1 TNCSC_CON1; REG_R_TNCSC_CON2 TNCSC_CON2; REG_R_TNCSC_MODULE_SEL TNCSC_MODULE_SEL; }; /** * Mediatek camera tncs tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_tncs { REG_R_TNCS_GTMS_DRZS1N_OUT TNCS_GTMS_DRZS1N_OUT; REG_R_TNCS_GTMS_SLM_DRZS1N_OUT TNCS_GTMS_SLM_DRZS1N_OUT; REG_R_TNCS_GTMS_HIST TNCS_GTMS_HIST; REG_R_TNCS_BCES_DRZS1N_OUT TNCS_BCES_DRZS1N_OUT; REG_R_TNCS_BCES_HIST TNCS_BCES_HIST; REG_R_TNCS_BCES_DETAIL_CTRL TNCS_BCES_DETAIL_CTRL; REG_R_TNCS_BCES_DETAIL_PXL TNCS_BCES_DETAIL_PXL; REG_R_TNCS_BCES_DETAIL_RANGE TNCS_BCES_DETAIL_RANGE; REG_R_TNCS_BCES_FLAT_HOR_VAR_1 TNCS_BCES_FLAT_HOR_VAR_1; REG_R_TNCS_BCES_FLAT_HOR_VAR_2 TNCS_BCES_FLAT_HOR_VAR_2; REG_R_TNCS_BCES_FLAT_HOR_VAR_3 TNCS_BCES_FLAT_HOR_VAR_3; REG_R_TNCS_BCES_FLAT_APL_DIFF TNCS_BCES_FLAT_APL_DIFF; REG_R_TNCS_BCES_FLAT_APL_LINE TNCS_BCES_FLAT_APL_LINE; REG_R_TNCS_BCES_COLOR_SKIN_RG TNCS_BCES_COLOR_SKIN_RG; REG_R_TNCS_BCES_COLOR_SKIN_BG TNCS_BCES_COLOR_SKIN_BG; REG_R_TNCS_BCES_COLOR_SKIN_RB TNCS_BCES_COLOR_SKIN_RB; REG_R_TNCS_BCES_COLOR_SKIN_G TNCS_BCES_COLOR_SKIN_G; REG_R_TNCS_BCES_COLOR_GREEN_RG TNCS_BCES_COLOR_GREEN_RG; REG_R_TNCS_BCES_COLOR_GREEN_BG TNCS_BCES_COLOR_GREEN_BG; REG_R_TNCS_BCES_COLOR_GREEN_RB TNCS_BCES_COLOR_GREEN_RB; REG_R_TNCS_BCES_COLOR_GREEN_G TNCS_BCES_COLOR_GREEN_G; REG_R_TNCS_GGM_LUT TNCS_GGM_LUT[256]; REG_R_TNCS_GGM_CTRL TNCS_GGM_CTRL; REG_R_TNCS_GTMS_DRZS1N_IN_SW TNCS_GTMS_DRZS1N_IN_SW; REG_R_TNCS_GTMS_DRZS1N_CONTROL TNCS_GTMS_DRZS1N_CONTROL; REG_R_TNCS_GTMS_DRZS1N_HORI_STEP TNCS_GTMS_DRZS1N_HORI_STEP; REG_R_TNCS_GTMS_DRZS1N_VERT_STEP TNCS_GTMS_DRZS1N_VERT_STEP; REG_R_TNCS_GTMS_DRZS1N_HORI_INT_OFST TNCS_GTMS_DRZS1N_HORI_INT_OFST; REG_R_TNCS_GTMS_DRZS1N_HORI_SUB_OFST TNCS_GTMS_DRZS1N_HORI_SUB_OFST; REG_R_TNCS_GTMS_DRZS1N_VERT_INT_OFST TNCS_GTMS_DRZS1N_VERT_INT_OFST; REG_R_TNCS_GTMS_DRZS1N_VERT_SUB_OFST TNCS_GTMS_DRZS1N_VERT_SUB_OFST; REG_R_TNCS_GTMS_SLM_DRZS1N_IN_SW TNCS_GTMS_SLM_DRZS1N_IN_SW; REG_R_TNCS_GTMS_SLM_DRZS1N_CONTROL TNCS_GTMS_SLM_DRZS1N_CONTROL; REG_R_TNCS_GTMS_SLM_DRZS1N_HORI_STEP TNCS_GTMS_SLM_DRZS1N_HORI_STEP; REG_R_TNCS_GTMS_SLM_DRZS1N_VERT_STEP TNCS_GTMS_SLM_DRZS1N_VERT_STEP; REG_R_TNCS_GTMS_SLM_DRZS1N_HORI_INT_OFST TNCS_GTMS_SLM_DRZS1N_HORI_INT_OFST; REG_R_TNCS_GTMS_SLM_DRZS1N_HORI_SUB_OFST TNCS_GTMS_SLM_DRZS1N_HORI_SUB_OFST; REG_R_TNCS_GTMS_SLM_DRZS1N_VERT_INT_OFST TNCS_GTMS_SLM_DRZS1N_VERT_INT_OFST; REG_R_TNCS_GTMS_SLM_DRZS1N_VERT_SUB_OFST TNCS_GTMS_SLM_DRZS1N_VERT_SUB_OFST; REG_R_TNCS_GTMS_FD_START_SW TNCS_GTMS_FD_START_SW; REG_R_TNCS_GTMS_FD_END_SW TNCS_GTMS_FD_END_SW; REG_R_TNCS_BCES_DRZS1N_IN_SW TNCS_BCES_DRZS1N_IN_SW; REG_R_TNCS_BCES_DRZS1N_CONTROL TNCS_BCES_DRZS1N_CONTROL; REG_R_TNCS_BCES_DRZS1N_HORI_STEP TNCS_BCES_DRZS1N_HORI_STEP; REG_R_TNCS_BCES_DRZS1N_VERT_STEP TNCS_BCES_DRZS1N_VERT_STEP; REG_R_TNCS_BCES_DRZS1N_HORI_INT_OFST TNCS_BCES_DRZS1N_HORI_INT_OFST; REG_R_TNCS_BCES_DRZS1N_HORI_SUB_OFST TNCS_BCES_DRZS1N_HORI_SUB_OFST; REG_R_TNCS_BCES_DRZS1N_VERT_INT_OFST TNCS_BCES_DRZS1N_VERT_INT_OFST; REG_R_TNCS_BCES_DRZS1N_VERT_SUB_OFST TNCS_BCES_DRZS1N_VERT_SUB_OFST; REG_R_TNCS_BCES_BLK_NUM_SW TNCS_BCES_BLK_NUM_SW; REG_R_TNCS_BCES_BLK_SIZE_SW TNCS_BCES_BLK_SIZE_SW; REG_R_TNCS_BCES_BLK_SIZE_2_SW TNCS_BCES_BLK_SIZE_2_SW; REG_R_TNCS_BCES_BLK_LOG2_SIZE_SW TNCS_BCES_BLK_LOG2_SIZE_SW; REG_R_TNCS_BCES_BLK_BDY_SIZE_SW TNCS_BCES_BLK_BDY_SIZE_SW; REG_R_TNCS_BCES_BLK_AREA TNCS_BCES_BLK_AREA; REG_R_TNCS_BCES_BLK_AREA_R TNCS_BCES_BLK_AREA_R; REG_R_TNCS_BCES_BLK_AREA_B TNCS_BCES_BLK_AREA_B; REG_R_TNCS_BCES_BLK_AREA_C TNCS_BCES_BLK_AREA_C; REG_R_TNCS_BCES_BLK_AREA_MIN TNCS_BCES_BLK_AREA_MIN; REG_R_TNCS_BCES_BLK_AREA_MIN_R TNCS_BCES_BLK_AREA_MIN_R; REG_R_TNCS_BCES_BLK_AREA_MIN_B TNCS_BCES_BLK_AREA_MIN_B; REG_R_TNCS_BCES_BLK_AREA_MIN_C TNCS_BCES_BLK_AREA_MIN_C; REG_R_TNCS_CTRL TNCS_CTRL; REG_R_TNCS_GTMS_ACT_WIN_START_TILE TNCS_GTMS_ACT_WIN_START_TILE; REG_R_TNCS_GTMS_ACT_WIN_END_TILE TNCS_GTMS_ACT_WIN_END_TILE; REG_R_TNCS_BCES_ACT_WIN_START_TILE TNCS_BCES_ACT_WIN_START_TILE; REG_R_TNCS_BCES_ACT_WIN_END_TILE TNCS_BCES_ACT_WIN_END_TILE; REG_R_TNCS_BCES_BLK_NUM_TILE TNCS_BCES_BLK_NUM_TILE; REG_R_TNCS_BCES_BLK_CNT_TILE TNCS_BCES_BLK_CNT_TILE; UINT32 rsv_AE10[2]; REG_R_TNCS_DFTC TNCS_DFTC; REG_R_TNCS_SPARE0 TNCS_SPARE0; REG_R_TNCS_SPARE1 TNCS_SPARE1; REG_R_TNCS_GTMS_SLM_ACT_WIN_START_TILE TNCS_GTMS_SLM_ACT_WIN_START_TILE; REG_R_TNCS_GTMS_SLM_ACT_WIN_END_TILE TNCS_GTMS_SLM_ACT_WIN_END_TILE; REG_R_TNCS_BCES_BLK_NBDY_SIZE_SW TNCS_BCES_BLK_NBDY_SIZE_SW; REG_R_TNCS_BCES_BLK_AREA_L TNCS_BCES_BLK_AREA_L; REG_R_TNCS_BCES_BLK_AREA_T TNCS_BCES_BLK_AREA_T; REG_R_TNCS_BCES_BLK_AREA_TL TNCS_BCES_BLK_AREA_TL; REG_R_TNCS_BCES_BLK_AREA_TR TNCS_BCES_BLK_AREA_TR; REG_R_TNCS_BCES_BLK_AREA_BL TNCS_BCES_BLK_AREA_BL; REG_R_TNCS_BCES_BLK_AREA_MIN_L TNCS_BCES_BLK_AREA_MIN_L; REG_R_TNCS_BCES_BLK_AREA_MIN_T TNCS_BCES_BLK_AREA_MIN_T; REG_R_TNCS_BCES_BLK_AREA_MIN_TL TNCS_BCES_BLK_AREA_MIN_TL; REG_R_TNCS_BCES_BLK_AREA_MIN_TR TNCS_BCES_BLK_AREA_MIN_TR; REG_R_TNCS_BCES_BLK_AREA_MIN_BL TNCS_BCES_BLK_AREA_MIN_BL; }; /** * Mediatek camera tnc tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_tnc { REG_R_TNC_DIP_COLOR_CFG_MAIN TNC_DIP_COLOR_CFG_MAIN; REG_R_TNC_DIP_COLOR_PXL_CNT_MAIN TNC_DIP_COLOR_PXL_CNT_MAIN; REG_R_TNC_DIP_COLOR_LINE_CNT_MAIN TNC_DIP_COLOR_LINE_CNT_MAIN; REG_R_TNC_DIP_COLOR_WIN_X_MAIN TNC_DIP_COLOR_WIN_X_MAIN; REG_R_TNC_DIP_COLOR_WIN_Y_MAIN TNC_DIP_COLOR_WIN_Y_MAIN; REG_R_TNC_DIP_COLOR_TIMING_DETECTION_0 TNC_DIP_COLOR_TIMING_DETECTION_0; REG_R_TNC_DIP_COLOR_TIMING_DETECTION_1 TNC_DIP_COLOR_TIMING_DETECTION_1; REG_R_TNC_DIP_COLOR_DBG_CFG_MAIN TNC_DIP_COLOR_DBG_CFG_MAIN; REG_R_TNC_DIP_COLOR_C_BOOST_MAIN TNC_DIP_COLOR_C_BOOST_MAIN; REG_R_TNC_DIP_COLOR_C_BOOST_MAIN_2 TNC_DIP_COLOR_C_BOOST_MAIN_2; REG_R_TNC_DIP_COLOR_LUMA_ADJ TNC_DIP_COLOR_LUMA_ADJ; REG_R_TNC_DIP_COLOR_G_PIC_ADJ_MAIN_1 TNC_DIP_COLOR_G_PIC_ADJ_MAIN_1; REG_R_TNC_DIP_COLOR_G_PIC_ADJ_MAIN_2 TNC_DIP_COLOR_G_PIC_ADJ_MAIN_2; REG_R_TNC_DIP_COLOR_POS_MAIN TNC_DIP_COLOR_POS_MAIN; REG_R_TNC_DIP_COLOR_INK_DATA_MAIN TNC_DIP_COLOR_INK_DATA_MAIN; REG_R_TNC_DIP_COLOR_INK_DATA_MAIN_CR TNC_DIP_COLOR_INK_DATA_MAIN_CR; REG_R_TNC_DIP_COLOR_CAP_IN_DATA_MAIN TNC_DIP_COLOR_CAP_IN_DATA_MAIN; REG_R_TNC_DIP_COLOR_CAP_IN_DATA_MAIN_CR TNC_DIP_COLOR_CAP_IN_DATA_MAIN_CR; REG_R_TNC_DIP_COLOR_CAP_OUT_DATA_MAIN TNC_DIP_COLOR_CAP_OUT_DATA_MAIN; REG_R_TNC_DIP_COLOR_CAP_OUT_DATA_MAIN_CR TNC_DIP_COLOR_CAP_OUT_DATA_MAIN_CR; REG_R_TNC_DIP_COLOR_Y_SLOPE_1_0_MAIN TNC_DIP_COLOR_Y_SLOPE_1_0_MAIN; REG_R_TNC_DIP_COLOR_Y_SLOPE_3_2_MAIN TNC_DIP_COLOR_Y_SLOPE_3_2_MAIN; REG_R_TNC_DIP_COLOR_Y_SLOPE_5_4_MAIN TNC_DIP_COLOR_Y_SLOPE_5_4_MAIN; REG_R_TNC_DIP_COLOR_Y_SLOPE_7_6_MAIN TNC_DIP_COLOR_Y_SLOPE_7_6_MAIN; REG_R_TNC_DIP_COLOR_Y_SLOPE_9_8_MAIN TNC_DIP_COLOR_Y_SLOPE_9_8_MAIN; REG_R_TNC_DIP_COLOR_Y_SLOPE_11_10_MAIN TNC_DIP_COLOR_Y_SLOPE_11_10_MAIN; REG_R_TNC_DIP_COLOR_Y_SLOPE_13_12_MAIN TNC_DIP_COLOR_Y_SLOPE_13_12_MAIN; REG_R_TNC_DIP_COLOR_Y_SLOPE_15_14_MAIN TNC_DIP_COLOR_Y_SLOPE_15_14_MAIN; REG_R_TNC_DIP_COLOR_LOCAL_HUE_CD_0 TNC_DIP_COLOR_LOCAL_HUE_CD_0; REG_R_TNC_DIP_COLOR_LOCAL_HUE_CD_1 TNC_DIP_COLOR_LOCAL_HUE_CD_1; REG_R_TNC_DIP_COLOR_LOCAL_HUE_CD_2 TNC_DIP_COLOR_LOCAL_HUE_CD_2; REG_R_TNC_DIP_COLOR_LOCAL_HUE_CD_3 TNC_DIP_COLOR_LOCAL_HUE_CD_3; REG_R_TNC_DIP_COLOR_LOCAL_HUE_CD_4 TNC_DIP_COLOR_LOCAL_HUE_CD_4; REG_R_TNC_DIP_COLOR_TWO_D_WINDOW_1 TNC_DIP_COLOR_TWO_D_WINDOW_1; REG_R_TNC_DIP_COLOR_TWO_D_W1_RESULT TNC_DIP_COLOR_TWO_D_W1_RESULT; REG_R_TNC_DIP_COLOR_SAT_HIST_X_CFG_MAIN TNC_DIP_COLOR_SAT_HIST_X_CFG_MAIN; REG_R_TNC_DIP_COLOR_SAT_HIST_Y_CFG_MAIN TNC_DIP_COLOR_SAT_HIST_Y_CFG_MAIN; REG_R_TNC_DIP_COLOR_BWS_2 TNC_DIP_COLOR_BWS_2; REG_R_TNC_DIP_COLOR_CRC_0 TNC_DIP_COLOR_CRC_0; REG_R_TNC_DIP_COLOR_CRC_1 TNC_DIP_COLOR_CRC_1; REG_R_TNC_DIP_COLOR_CRC_2 TNC_DIP_COLOR_CRC_2; REG_R_TNC_DIP_COLOR_CRC_3 TNC_DIP_COLOR_CRC_3; REG_R_TNC_DIP_COLOR_CRC_4 TNC_DIP_COLOR_CRC_4; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_GAIN1_0 TNC_DIP_COLOR_PARTIAL_SAT_GAIN1_0; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_GAIN1_1 TNC_DIP_COLOR_PARTIAL_SAT_GAIN1_1; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_GAIN1_2 TNC_DIP_COLOR_PARTIAL_SAT_GAIN1_2; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_GAIN1_3 TNC_DIP_COLOR_PARTIAL_SAT_GAIN1_3; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_GAIN1_4 TNC_DIP_COLOR_PARTIAL_SAT_GAIN1_4; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_GAIN2_0 TNC_DIP_COLOR_PARTIAL_SAT_GAIN2_0; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_GAIN2_1 TNC_DIP_COLOR_PARTIAL_SAT_GAIN2_1; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_GAIN2_2 TNC_DIP_COLOR_PARTIAL_SAT_GAIN2_2; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_GAIN2_3 TNC_DIP_COLOR_PARTIAL_SAT_GAIN2_3; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_GAIN2_4 TNC_DIP_COLOR_PARTIAL_SAT_GAIN2_4; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_GAIN3_0 TNC_DIP_COLOR_PARTIAL_SAT_GAIN3_0; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_GAIN3_1 TNC_DIP_COLOR_PARTIAL_SAT_GAIN3_1; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_GAIN3_2 TNC_DIP_COLOR_PARTIAL_SAT_GAIN3_2; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_GAIN3_3 TNC_DIP_COLOR_PARTIAL_SAT_GAIN3_3; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_GAIN3_4 TNC_DIP_COLOR_PARTIAL_SAT_GAIN3_4; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_POINT1_0 TNC_DIP_COLOR_PARTIAL_SAT_POINT1_0; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_POINT1_1 TNC_DIP_COLOR_PARTIAL_SAT_POINT1_1; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_POINT1_2 TNC_DIP_COLOR_PARTIAL_SAT_POINT1_2; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_POINT1_3 TNC_DIP_COLOR_PARTIAL_SAT_POINT1_3; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_POINT1_4 TNC_DIP_COLOR_PARTIAL_SAT_POINT1_4; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_POINT2_0 TNC_DIP_COLOR_PARTIAL_SAT_POINT2_0; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_POINT2_1 TNC_DIP_COLOR_PARTIAL_SAT_POINT2_1; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_POINT2_2 TNC_DIP_COLOR_PARTIAL_SAT_POINT2_2; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_POINT2_3 TNC_DIP_COLOR_PARTIAL_SAT_POINT2_3; REG_R_TNC_DIP_COLOR_PARTIAL_SAT_POINT2_4 TNC_DIP_COLOR_PARTIAL_SAT_POINT2_4; REG_R_TNC_DIP_COLOR_START TNC_DIP_COLOR_START; REG_R_TNC_DIP_COLOR_INTEN TNC_DIP_COLOR_INTEN; REG_R_TNC_DIP_COLOR_INTSTA TNC_DIP_COLOR_INTSTA; REG_R_TNC_DIP_COLOR_OUT_SEL TNC_DIP_COLOR_OUT_SEL; REG_R_TNC_DIP_COLOR_FRAME_DONE_DEL TNC_DIP_COLOR_FRAME_DONE_DEL; REG_R_TNC_DIP_COLOR_CRC TNC_DIP_COLOR_CRC; REG_R_TNC_DIP_COLOR_SW_SCRATCH TNC_DIP_COLOR_SW_SCRATCH; REG_R_TNC_DIP_COLOR_CK_ON TNC_DIP_COLOR_CK_ON; REG_R_TNC_DIP_COLOR_INTERNAL_IP_WIDTH TNC_DIP_COLOR_INTERNAL_IP_WIDTH; REG_R_TNC_DIP_COLOR_INTERNAL_IP_HEIGHT TNC_DIP_COLOR_INTERNAL_IP_HEIGHT; REG_R_TNC_DIP_COLOR_CM1_EN TNC_DIP_COLOR_CM1_EN; REG_R_TNC_DIP_COLOR_CM2_EN TNC_DIP_COLOR_CM2_EN; REG_R_TNC_DIP_COLOR_SHADOW_CTRL TNC_DIP_COLOR_SHADOW_CTRL; REG_R_TNC_DIP_COLOR_R0_CRC TNC_DIP_COLOR_R0_CRC; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y0_0 TNC_DIP_COLOR_S_GAIN_BY_Y0_0; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y0_1 TNC_DIP_COLOR_S_GAIN_BY_Y0_1; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y0_2 TNC_DIP_COLOR_S_GAIN_BY_Y0_2; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y0_3 TNC_DIP_COLOR_S_GAIN_BY_Y0_3; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y0_4 TNC_DIP_COLOR_S_GAIN_BY_Y0_4; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y64_0 TNC_DIP_COLOR_S_GAIN_BY_Y64_0; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y64_1 TNC_DIP_COLOR_S_GAIN_BY_Y64_1; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y64_2 TNC_DIP_COLOR_S_GAIN_BY_Y64_2; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y64_3 TNC_DIP_COLOR_S_GAIN_BY_Y64_3; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y64_4 TNC_DIP_COLOR_S_GAIN_BY_Y64_4; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y128_0 TNC_DIP_COLOR_S_GAIN_BY_Y128_0; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y128_1 TNC_DIP_COLOR_S_GAIN_BY_Y128_1; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y128_2 TNC_DIP_COLOR_S_GAIN_BY_Y128_2; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y128_3 TNC_DIP_COLOR_S_GAIN_BY_Y128_3; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y128_4 TNC_DIP_COLOR_S_GAIN_BY_Y128_4; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y192_0 TNC_DIP_COLOR_S_GAIN_BY_Y192_0; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y192_1 TNC_DIP_COLOR_S_GAIN_BY_Y192_1; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y192_2 TNC_DIP_COLOR_S_GAIN_BY_Y192_2; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y192_3 TNC_DIP_COLOR_S_GAIN_BY_Y192_3; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y192_4 TNC_DIP_COLOR_S_GAIN_BY_Y192_4; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y256_0 TNC_DIP_COLOR_S_GAIN_BY_Y256_0; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y256_1 TNC_DIP_COLOR_S_GAIN_BY_Y256_1; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y256_2 TNC_DIP_COLOR_S_GAIN_BY_Y256_2; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y256_3 TNC_DIP_COLOR_S_GAIN_BY_Y256_3; REG_R_TNC_DIP_COLOR_S_GAIN_BY_Y256_4 TNC_DIP_COLOR_S_GAIN_BY_Y256_4; REG_R_TNC_DIP_COLOR_LSP_1 TNC_DIP_COLOR_LSP_1; REG_R_TNC_DIP_COLOR_LSP_2 TNC_DIP_COLOR_LSP_2; REG_R_TNC_DIP_COLOR_CM_CONTROL TNC_DIP_COLOR_CM_CONTROL; REG_R_TNC_DIP_COLOR_CM_W1_HUE_0 TNC_DIP_COLOR_CM_W1_HUE_0; REG_R_TNC_DIP_COLOR_CM_W1_HUE_1 TNC_DIP_COLOR_CM_W1_HUE_1; REG_R_TNC_DIP_COLOR_CM_W1_HUE_2 TNC_DIP_COLOR_CM_W1_HUE_2; REG_R_TNC_DIP_COLOR_CM_W1_HUE_3 TNC_DIP_COLOR_CM_W1_HUE_3; REG_R_TNC_DIP_COLOR_CM_W1_HUE_4 TNC_DIP_COLOR_CM_W1_HUE_4; REG_R_TNC_DIP_COLOR_CM_W1_LUMA_0 TNC_DIP_COLOR_CM_W1_LUMA_0; REG_R_TNC_DIP_COLOR_CM_W1_LUMA_1 TNC_DIP_COLOR_CM_W1_LUMA_1; REG_R_TNC_DIP_COLOR_CM_W1_LUMA_2 TNC_DIP_COLOR_CM_W1_LUMA_2; REG_R_TNC_DIP_COLOR_CM_W1_LUMA_3 TNC_DIP_COLOR_CM_W1_LUMA_3; REG_R_TNC_DIP_COLOR_CM_W1_LUMA_4 TNC_DIP_COLOR_CM_W1_LUMA_4; REG_R_TNC_DIP_COLOR_CM_W1_SAT_0 TNC_DIP_COLOR_CM_W1_SAT_0; REG_R_TNC_DIP_COLOR_CM_W1_SAT_1 TNC_DIP_COLOR_CM_W1_SAT_1; REG_R_TNC_DIP_COLOR_CM_W1_SAT_2 TNC_DIP_COLOR_CM_W1_SAT_2; REG_R_TNC_DIP_COLOR_CM_W1_SAT_3 TNC_DIP_COLOR_CM_W1_SAT_3; REG_R_TNC_DIP_COLOR_CM_W1_SAT_4 TNC_DIP_COLOR_CM_W1_SAT_4; REG_R_TNC_DIP_COLOR_CM_W2_HUE_0 TNC_DIP_COLOR_CM_W2_HUE_0; REG_R_TNC_DIP_COLOR_CM_W2_HUE_1 TNC_DIP_COLOR_CM_W2_HUE_1; REG_R_TNC_DIP_COLOR_CM_W2_HUE_2 TNC_DIP_COLOR_CM_W2_HUE_2; REG_R_TNC_DIP_COLOR_CM_W2_HUE_3 TNC_DIP_COLOR_CM_W2_HUE_3; REG_R_TNC_DIP_COLOR_CM_W2_HUE_4 TNC_DIP_COLOR_CM_W2_HUE_4; REG_R_TNC_DIP_COLOR_CM_W2_LUMA_0 TNC_DIP_COLOR_CM_W2_LUMA_0; REG_R_TNC_DIP_COLOR_CM_W2_LUMA_1 TNC_DIP_COLOR_CM_W2_LUMA_1; REG_R_TNC_DIP_COLOR_CM_W2_LUMA_2 TNC_DIP_COLOR_CM_W2_LUMA_2; REG_R_TNC_DIP_COLOR_CM_W2_LUMA_3 TNC_DIP_COLOR_CM_W2_LUMA_3; REG_R_TNC_DIP_COLOR_CM_W2_LUMA_4 TNC_DIP_COLOR_CM_W2_LUMA_4; REG_R_TNC_DIP_COLOR_CM_W2_SAT_0 TNC_DIP_COLOR_CM_W2_SAT_0; REG_R_TNC_DIP_COLOR_CM_W2_SAT_1 TNC_DIP_COLOR_CM_W2_SAT_1; REG_R_TNC_DIP_COLOR_CM_W2_SAT_2 TNC_DIP_COLOR_CM_W2_SAT_2; REG_R_TNC_DIP_COLOR_CM_W2_SAT_3 TNC_DIP_COLOR_CM_W2_SAT_3; REG_R_TNC_DIP_COLOR_CM_W2_SAT_4 TNC_DIP_COLOR_CM_W2_SAT_4; REG_R_TNC_DIP_COLOR_CM_W3_HUE_0 TNC_DIP_COLOR_CM_W3_HUE_0; REG_R_TNC_DIP_COLOR_CM_W3_HUE_1 TNC_DIP_COLOR_CM_W3_HUE_1; REG_R_TNC_DIP_COLOR_CM_W3_HUE_2 TNC_DIP_COLOR_CM_W3_HUE_2; REG_R_TNC_DIP_COLOR_CM_W3_HUE_3 TNC_DIP_COLOR_CM_W3_HUE_3; REG_R_TNC_DIP_COLOR_CM_W3_HUE_4 TNC_DIP_COLOR_CM_W3_HUE_4; REG_R_TNC_DIP_COLOR_CM_W3_LUMA_0 TNC_DIP_COLOR_CM_W3_LUMA_0; REG_R_TNC_DIP_COLOR_CM_W3_LUMA_1 TNC_DIP_COLOR_CM_W3_LUMA_1; REG_R_TNC_DIP_COLOR_CM_W3_LUMA_2 TNC_DIP_COLOR_CM_W3_LUMA_2; REG_R_TNC_DIP_COLOR_CM_W3_LUMA_3 TNC_DIP_COLOR_CM_W3_LUMA_3; REG_R_TNC_DIP_COLOR_CM_W3_LUMA_4 TNC_DIP_COLOR_CM_W3_LUMA_4; REG_R_TNC_DIP_COLOR_CM_W3_SAT_0 TNC_DIP_COLOR_CM_W3_SAT_0; REG_R_TNC_DIP_COLOR_CM_W3_SAT_1 TNC_DIP_COLOR_CM_W3_SAT_1; REG_R_TNC_DIP_COLOR_CM_W3_SAT_2 TNC_DIP_COLOR_CM_W3_SAT_2; REG_R_TNC_DIP_COLOR_CM_W3_SAT_3 TNC_DIP_COLOR_CM_W3_SAT_3; REG_R_TNC_DIP_COLOR_CM_W3_SAT_4 TNC_DIP_COLOR_CM_W3_SAT_4; UINT32 rsv_326C; REG_R_TNC_C3D_CFG TNC_C3D_CFG; REG_R_TNC_C3D_RESET TNC_C3D_RESET; REG_R_TNC_C3D_INTEN TNC_C3D_INTEN; REG_R_TNC_C3D_INTSTA TNC_C3D_INTSTA; REG_R_TNC_C3D_STATUS TNC_C3D_STATUS; REG_R_TNC_C3D_INPUT_COUNT TNC_C3D_INPUT_COUNT; REG_R_TNC_C3D_OUTPUT_COUNT TNC_C3D_OUTPUT_COUNT; REG_R_TNC_C3D_CHKSUM TNC_C3D_CHKSUM; REG_R_TNC_C3D_TILE_SIZE TNC_C3D_TILE_SIZE; REG_R_TNC_C3D_SRAM_CFG TNC_C3D_SRAM_CFG; REG_R_TNC_C3D_SRAM_STATUS TNC_C3D_SRAM_STATUS; REG_R_TNC_C3D_DUMMY_REG TNC_C3D_DUMMY_REG; REG_R_TNC_C3D_ATPG TNC_C3D_ATPG; REG_R_TNC_C3D_SHADOW_CTRL TNC_C3D_SHADOW_CTRL; REG_R_TNC_C3D_C1D_000_001 TNC_C3D_C1D_000_001; REG_R_TNC_C3D_C1D_002_003 TNC_C3D_C1D_002_003; REG_R_TNC_C3D_C1D_004_005 TNC_C3D_C1D_004_005; REG_R_TNC_C3D_C1D_006_007 TNC_C3D_C1D_006_007; REG_R_TNC_C3D_C1D_008_009 TNC_C3D_C1D_008_009; REG_R_TNC_C3D_C1D_010_011 TNC_C3D_C1D_010_011; REG_R_TNC_C3D_C1D_012_013 TNC_C3D_C1D_012_013; REG_R_TNC_C3D_C1D_014_015 TNC_C3D_C1D_014_015; REG_R_TNC_C3D_C1D_016_017 TNC_C3D_C1D_016_017; REG_R_TNC_C3D_C1D_018_019 TNC_C3D_C1D_018_019; REG_R_TNC_C3D_C1D_020_021 TNC_C3D_C1D_020_021; REG_R_TNC_C3D_C1D_022_023 TNC_C3D_C1D_022_023; REG_R_TNC_C3D_C1D_024_025 TNC_C3D_C1D_024_025; REG_R_TNC_C3D_C1D_026_027 TNC_C3D_C1D_026_027; REG_R_TNC_C3D_C1D_028_029 TNC_C3D_C1D_028_029; REG_R_TNC_C3D_C1D_030_031 TNC_C3D_C1D_030_031; UINT32 rsv_32E8; REG_R_TNC_C3D_LFSR_CFG TNC_C3D_LFSR_CFG; REG_R_TNC_C3D_LFSR_SEED TNC_C3D_LFSR_SEED; UINT32 rsv_32F4[3]; REG_R_TNC_C3D_LUT TNC_C3D_LUT[4913]; UINT32 rsv_7FC4[4111]; REG_R_TNC_BCE_FORMAT TNC_BCE_FORMAT; REG_R_TNC_BCE_BLK_NUM TNC_BCE_BLK_NUM; REG_R_TNC_BCE_BLK_ALPHA TNC_BCE_BLK_ALPHA; REG_R_TNC_BCE_BLK_SIZE TNC_BCE_BLK_SIZE; REG_R_TNC_BCE_CURVE_LUT TNC_BCE_CURVE_LUT[864]; REG_R_TNC_TILE_BLK_NUM TNC_TILE_BLK_NUM; REG_R_TNC_TILE_BLK_X_CNT TNC_TILE_BLK_X_CNT; REG_R_TNC_TILE_BLK_Y_CNT TNC_TILE_BLK_Y_CNT; UINT32 rsv_CD9C[153]; REG_R_TNC_DEBUG_REG TNC_DEBUG_REG; REG_R_TNC_C2G_CONV_0A TNC_C2G_CONV_0A; REG_R_TNC_C2G_CONV_0B TNC_C2G_CONV_0B; REG_R_TNC_C2G_CONV_1A TNC_C2G_CONV_1A; REG_R_TNC_C2G_CONV_1B TNC_C2G_CONV_1B; REG_R_TNC_C2G_CONV_2A TNC_C2G_CONV_2A; REG_R_TNC_C2G_CONV_2B TNC_C2G_CONV_2B; REG_R_TNC_G2C_CONV_0A TNC_G2C_CONV_0A; REG_R_TNC_G2C_CONV_0B TNC_G2C_CONV_0B; REG_R_TNC_G2C_CONV_1A TNC_G2C_CONV_1A; REG_R_TNC_G2C_CONV_1B TNC_G2C_CONV_1B; REG_R_TNC_G2C_CONV_2A TNC_G2C_CONV_2A; REG_R_TNC_G2C_CONV_2B TNC_G2C_CONV_2B; REG_R_TNC_CURVE_GGM_LUT TNC_CURVE_GGM_LUT[256]; REG_R_TNC_CURVE_GGM_CTRL TNC_CURVE_GGM_CTRL; REG_R_TNC_HFE_V_RNG_A TNC_HFE_V_RNG_A; REG_R_TNC_HFE_V_RNG_B TNC_HFE_V_RNG_B; REG_R_TNC_HFE_H_RNG_A TNC_HFE_H_RNG_A; REG_R_TNC_HFE_H_RNG_B TNC_HFE_H_RNG_B; REG_R_TNC_HFE_Y_CPX TNC_HFE_Y_CPX; REG_R_TNC_HFE_Y_CPY TNC_HFE_Y_CPY; REG_R_TNC_HFE_Y_SP TNC_HFE_Y_SP; REG_R_TNC_HFE_BLD_CPY TNC_HFE_BLD_CPY; REG_R_TNC_HFE_BLD_SP TNC_HFE_BLD_SP; REG_R_TNC_HFE_PARA TNC_HFE_PARA; REG_R_TNC_HFR_PARA TNC_HFR_PARA; REG_R_TNC_GTM_FORMAT TNC_GTM_FORMAT; REG_R_TNC_GTM_LFTC_Y00 TNC_GTM_LFTC_Y00; REG_R_TNC_GTM_LFTC_Y02 TNC_GTM_LFTC_Y02; REG_R_TNC_GTM_LFTC_Y04 TNC_GTM_LFTC_Y04; REG_R_TNC_GTM_LFTC_Y06 TNC_GTM_LFTC_Y06; REG_R_TNC_GTM_LFTC_Y08 TNC_GTM_LFTC_Y08; REG_R_TNC_GTM_LFTC_Y10 TNC_GTM_LFTC_Y10; REG_R_TNC_GTM_LFTC_Y12 TNC_GTM_LFTC_Y12; REG_R_TNC_GTM_LFTC_Y14 TNC_GTM_LFTC_Y14; REG_R_TNC_GTM_LFTC_Y16 TNC_GTM_LFTC_Y16; REG_R_TNC_LME_V_RNG TNC_LME_V_RNG; REG_R_TNC_LME_H_RNG TNC_LME_H_RNG; REG_R_TNC_LME_V_CPX TNC_LME_V_CPX; REG_R_TNC_LME_DBLD_CPY TNC_LME_DBLD_CPY; REG_R_TNC_LME_DBLD_SP TNC_LME_DBLD_SP; REG_R_TNC_LME_PARA TNC_LME_PARA; REG_R_TNC_TILE_SIZE TNC_TILE_SIZE; REG_R_TNC_TILE_CTL TNC_TILE_CTL; REG_R_TNC_MODULE_EN TNC_MODULE_EN; REG_R_TNC_MOD_DCM_DIS TNC_MOD_DCM_DIS; REG_R_TNC_MOD_DCM_STATUS TNC_MOD_DCM_STATUS; REG_R_TNC_MOD2_DCM_STATUS TNC_MOD2_DCM_STATUS; REG_R_TNC_MOD_REQ_STATUS TNC_MOD_REQ_STATUS; REG_R_TNC_MOD2_REQ_STATUS TNC_MOD2_REQ_STATUS; REG_R_TNC_MOD_RDY_STATUS TNC_MOD_RDY_STATUS; REG_R_TNC_MOD2_RDY_STATUS TNC_MOD2_RDY_STATUS; REG_R_TNC_DEBUG_SET TNC_DEBUG_SET; REG_R_TNC_TNC_CTL TNC_TNC_CTL; REG_R_TNC_HFR_SAT_CTL TNC_HFR_SAT_CTL; REG_R_TNC_HFR_SAT_GAIN_R TNC_HFR_SAT_GAIN_R; REG_R_TNC_HFR_SAT_GAIN_G TNC_HFR_SAT_GAIN_G; REG_R_TNC_HFR_SAT_GAIN_B TNC_HFR_SAT_GAIN_B; REG_R_TNC_HFR_SAT_GAIN_LO_RG TNC_HFR_SAT_GAIN_LO_RG; REG_R_TNC_HFR_SAT_GAIN_LO_B TNC_HFR_SAT_GAIN_LO_B; UINT32 rsv_D4EC[453]; REG_R_TNC_LMC_CFG TNC_LMC_CFG; REG_R_TNC_LMC_W1_R_0 TNC_LMC_W1_R_0; REG_R_TNC_LMC_W1_R_1 TNC_LMC_W1_R_1; REG_R_TNC_LMC_W1_R_2 TNC_LMC_W1_R_2; REG_R_TNC_LMC_W1_R_3 TNC_LMC_W1_R_3; REG_R_TNC_LMC_W1_R_4 TNC_LMC_W1_R_4; REG_R_TNC_LMC_W1_G_0 TNC_LMC_W1_G_0; REG_R_TNC_LMC_W1_G_1 TNC_LMC_W1_G_1; REG_R_TNC_LMC_W1_G_2 TNC_LMC_W1_G_2; REG_R_TNC_LMC_W1_G_3 TNC_LMC_W1_G_3; REG_R_TNC_LMC_W1_G_4 TNC_LMC_W1_G_4; REG_R_TNC_LMC_W1_B_0 TNC_LMC_W1_B_0; REG_R_TNC_LMC_W1_B_1 TNC_LMC_W1_B_1; REG_R_TNC_LMC_W1_B_2 TNC_LMC_W1_B_2; REG_R_TNC_LMC_W1_B_3 TNC_LMC_W1_B_3; REG_R_TNC_LMC_W1_B_4 TNC_LMC_W1_B_4; REG_R_TNC_LMC_W2_R_0 TNC_LMC_W2_R_0; REG_R_TNC_LMC_W2_R_1 TNC_LMC_W2_R_1; REG_R_TNC_LMC_W2_R_2 TNC_LMC_W2_R_2; REG_R_TNC_LMC_W2_R_3 TNC_LMC_W2_R_3; REG_R_TNC_LMC_W2_R_4 TNC_LMC_W2_R_4; REG_R_TNC_LMC_W2_G_0 TNC_LMC_W2_G_0; REG_R_TNC_LMC_W2_G_1 TNC_LMC_W2_G_1; REG_R_TNC_LMC_W2_G_2 TNC_LMC_W2_G_2; REG_R_TNC_LMC_W2_G_3 TNC_LMC_W2_G_3; REG_R_TNC_LMC_W2_G_4 TNC_LMC_W2_G_4; REG_R_TNC_LMC_W2_B_0 TNC_LMC_W2_B_0; REG_R_TNC_LMC_W2_B_1 TNC_LMC_W2_B_1; REG_R_TNC_LMC_W2_B_2 TNC_LMC_W2_B_2; REG_R_TNC_LMC_W2_B_3 TNC_LMC_W2_B_3; REG_R_TNC_LMC_W2_B_4 TNC_LMC_W2_B_4; REG_R_TNC_LMC_W3_R_0 TNC_LMC_W3_R_0; REG_R_TNC_LMC_W3_R_1 TNC_LMC_W3_R_1; REG_R_TNC_LMC_W3_R_2 TNC_LMC_W3_R_2; REG_R_TNC_LMC_W3_R_3 TNC_LMC_W3_R_3; REG_R_TNC_LMC_W3_R_4 TNC_LMC_W3_R_4; REG_R_TNC_LMC_W3_G_0 TNC_LMC_W3_G_0; REG_R_TNC_LMC_W3_G_1 TNC_LMC_W3_G_1; REG_R_TNC_LMC_W3_G_2 TNC_LMC_W3_G_2; REG_R_TNC_LMC_W3_G_3 TNC_LMC_W3_G_3; REG_R_TNC_LMC_W3_G_4 TNC_LMC_W3_G_4; REG_R_TNC_LMC_W3_B_0 TNC_LMC_W3_B_0; REG_R_TNC_LMC_W3_B_1 TNC_LMC_W3_B_1; REG_R_TNC_LMC_W3_B_2 TNC_LMC_W3_B_2; REG_R_TNC_LMC_W3_B_3 TNC_LMC_W3_B_3; REG_R_TNC_LMC_W3_B_4 TNC_LMC_W3_B_4; REG_R_TNC_LMC_RESET TNC_LMC_RESET; REG_R_TNC_LMC_INTEN TNC_LMC_INTEN; REG_R_TNC_LMC_INTSTA TNC_LMC_INTSTA; REG_R_TNC_LMC_STATUS TNC_LMC_STATUS; REG_R_TNC_LMC_INPUT_COUNT TNC_LMC_INPUT_COUNT; REG_R_TNC_LMC_OUTPUT_COUNT TNC_LMC_OUTPUT_COUNT; REG_R_TNC_LMC_CHKSUM TNC_LMC_CHKSUM; REG_R_TNC_LMC_TILE_SIZE TNC_LMC_TILE_SIZE; REG_R_TNC_LMC_DUMMY_REG TNC_LMC_DUMMY_REG; REG_R_TNC_LMC_ATPG TNC_LMC_ATPG; REG_R_TNC_LMC_SHADOW_CTRL TNC_LMC_SHADOW_CTRL; UINT32 rsv_DCE4[199]; REG_R_TNC_TGGM_LUT TNC_TGGM_LUT[256]; REG_R_TNC_TGGM_CTRL TNC_TGGM_CTRL; REG_R_TNC_TIGGM_LUT TNC_TIGGM_LUT[256]; REG_R_TNC_TIGGM_CTRL TNC_TIGGM_CTRL; }; /** * Mediatek camera tnr tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_tnr { REG_R_TNR_TOP_CTRL TNR_TOP_CTRL; REG_R_TNR_TOP_CTRL2 TNR_TOP_CTRL2; UINT32 rsv_6008; REG_R_TNR_TOP_RST TNR_TOP_RST; REG_R_TNR_SIZE TNR_SIZE; REG_R_TNR_ATPG TNR_ATPG; REG_R_TNR_MULTISCALE_ROLLING TNR_MULTISCALE_ROLLING; REG_R_TNR_MULTISCALE_ROLLING2 TNR_MULTISCALE_ROLLING2; REG_R_TNR_TNR_STR_Y TNR_TNR_STR_Y; REG_R_TNR_TNR_STR_UV TNR_TNR_STR_UV; REG_R_TNR_FREQUENCY_DIFFERENCE TNR_FREQUENCY_DIFFERENCE; REG_R_TNR_FREQUENCY_NES TNR_FREQUENCY_NES; REG_R_TNR_FREQUENCY_BANDPASS_FILTER0 TNR_FREQUENCY_BANDPASS_FILTER0; REG_R_TNR_FREQUENCY_BANDPASS_FILTER1 TNR_FREQUENCY_BANDPASS_FILTER1; REG_R_TNR_GRADIENT_DIFFERENCE0 TNR_GRADIENT_DIFFERENCE0; REG_R_TNR_GRADIENT_DIFFERENCE1 TNR_GRADIENT_DIFFERENCE1; REG_R_TNR_GRADIENT_NES TNR_GRADIENT_NES; REG_R_TNR_MEAN_SMOOTH_THD0 TNR_MEAN_SMOOTH_THD0; REG_R_TNR_MEAN_SMOOTH_THD1 TNR_MEAN_SMOOTH_THD1; REG_R_TNR_MEAN_SMOOTH_WGT0 TNR_MEAN_SMOOTH_WGT0; REG_R_TNR_MEAN_SMOOTH_SLP0 TNR_MEAN_SMOOTH_SLP0; REG_R_TNR_MEAN_DIFFERENCE0 TNR_MEAN_DIFFERENCE0; REG_R_TNR_MEAN_DIFFERENCE1 TNR_MEAN_DIFFERENCE1; REG_R_TNR_MEAN_DIFFERENCE2 TNR_MEAN_DIFFERENCE2; REG_R_TNR_MEAN_NES TNR_MEAN_NES; REG_R_TNR_GRADIENT_SMOOTH_THD0 TNR_GRADIENT_SMOOTH_THD0; REG_R_TNR_GRADIENT_SMOOTH_THD1 TNR_GRADIENT_SMOOTH_THD1; REG_R_TNR_GRADIENT_SMOOTH_WGT0 TNR_GRADIENT_SMOOTH_WGT0; REG_R_TNR_GRADIENT_SMOOTH_SLP0 TNR_GRADIENT_SMOOTH_SLP0; REG_R_TNR_RESIDUE_DIFFERENCE0 TNR_RESIDUE_DIFFERENCE0; REG_R_TNR_RESIDUE_DIFFERENCE1 TNR_RESIDUE_DIFFERENCE1; REG_R_TNR_RESI_Y_SMOOTH_THD0 TNR_RESI_Y_SMOOTH_THD0; REG_R_TNR_RESI_Y_SMOOTH_THD1 TNR_RESI_Y_SMOOTH_THD1; REG_R_TNR_RESI_Y_SMOOTH_WGT0 TNR_RESI_Y_SMOOTH_WGT0; REG_R_TNR_RESI_Y_SMOOTH_SLP0 TNR_RESI_Y_SMOOTH_SLP0; REG_R_TNR_RESI_UV_SMOOTH_THD0 TNR_RESI_UV_SMOOTH_THD0; REG_R_TNR_RESI_UV_SMOOTH_THD1 TNR_RESI_UV_SMOOTH_THD1; REG_R_TNR_RESI_UV_SMOOTH_WGT0 TNR_RESI_UV_SMOOTH_WGT0; REG_R_TNR_RESI_UV_SMOOTH_SLP0 TNR_RESI_UV_SMOOTH_SLP0; REG_R_TNR_GLOBAL_FREQUENCY_ANALYSIS0 TNR_GLOBAL_FREQUENCY_ANALYSIS0; REG_R_TNR_GLOBAL_FREQUENCY_ANALYSIS1 TNR_GLOBAL_FREQUENCY_ANALYSIS1; REG_R_TNR_GLOBAL_FREQUENCY_ANALYSIS2 TNR_GLOBAL_FREQUENCY_ANALYSIS2; REG_R_TNR_GLOBAL_FREQUENCY_ANALYSIS3 TNR_GLOBAL_FREQUENCY_ANALYSIS3; REG_R_TNR_GLOBAL_FREQUENCY_COEFFICIENT0 TNR_GLOBAL_FREQUENCY_COEFFICIENT0; REG_R_TNR_GLOBAL_FREQUENCY_COEFFICIENT1 TNR_GLOBAL_FREQUENCY_COEFFICIENT1; REG_R_TNR_GLOBAL_FREQUENCY_COEFFICIENT2 TNR_GLOBAL_FREQUENCY_COEFFICIENT2; REG_R_TNR_GLOBAL_FREQUENCY_COEFFICIENT3 TNR_GLOBAL_FREQUENCY_COEFFICIENT3; REG_R_TNR_GLOBAL_FREQUENCY_COEFFICIENT4 TNR_GLOBAL_FREQUENCY_COEFFICIENT4; REG_R_TNR_GLOBAL_FREQUENCY_COEFFICIENT5 TNR_GLOBAL_FREQUENCY_COEFFICIENT5; REG_R_TNR_GLOBAL_FREQUENCY_STATISTICS0 TNR_GLOBAL_FREQUENCY_STATISTICS0; UINT32 rsv_60C8; REG_R_TNR_EDGE_CONFIDENCE0 TNR_EDGE_CONFIDENCE0; REG_R_TNR_EDGE_CONFIDENCE1 TNR_EDGE_CONFIDENCE1; REG_R_TNR_EDGE_CONFIDENCE2 TNR_EDGE_CONFIDENCE2; REG_R_TNR_BLENDING_CONTROL0 TNR_BLENDING_CONTROL0; REG_R_TNR_BLENDING_CONTROL1 TNR_BLENDING_CONTROL1; REG_R_TNR_BLENDING_CONTROL2 TNR_BLENDING_CONTROL2; REG_R_TNR_BLENDING_CONTROL3 TNR_BLENDING_CONTROL3; REG_R_TNR_BLENDING_CONTROL4 TNR_BLENDING_CONTROL4; REG_R_TNR_BLENDING_CONTROL5 TNR_BLENDING_CONTROL5; REG_R_TNR_BLENDING_CONTROL6 TNR_BLENDING_CONTROL6; REG_R_TNR_BLENDING_CONTROL7 TNR_BLENDING_CONTROL7; REG_R_TNR_CONFIDENCE_ACCUMULATION TNR_CONFIDENCE_ACCUMULATION; REG_R_TNR_AGGRESSIVE_BLENDING0 TNR_AGGRESSIVE_BLENDING0; REG_R_TNR_AGGRESSIVE_BLENDING1 TNR_AGGRESSIVE_BLENDING1; REG_R_TNR_LUMINANCE_CONTROL0 TNR_LUMINANCE_CONTROL0; REG_R_TNR_LUMINANCE_CONTROL1 TNR_LUMINANCE_CONTROL1; REG_R_TNR_LUMINANCE_CONTROL2 TNR_LUMINANCE_CONTROL2; REG_R_TNR_LUMINANCE_CONTROL3 TNR_LUMINANCE_CONTROL3; REG_R_TNR_SHADING_LINK0 TNR_SHADING_LINK0; REG_R_TNR_SHADING_LINK1 TNR_SHADING_LINK1; REG_R_TNR_NOISE_LEVEL_STATISTICS0 TNR_NOISE_LEVEL_STATISTICS0; REG_R_TNR_NOISE_LEVEL_STATISTICS1 TNR_NOISE_LEVEL_STATISTICS1; REG_R_TNR_TILE_STATISTICS0 TNR_TILE_STATISTICS0; REG_R_TNR_TILE_STATISTICS1 TNR_TILE_STATISTICS1; REG_R_TNR_BACKGROUND_PROTECTION0 TNR_BACKGROUND_PROTECTION0; REG_R_TNR_BACKGROUND_PROTECTION1 TNR_BACKGROUND_PROTECTION1; REG_R_TNR_VALID_BIT_ADJUSTMENT TNR_VALID_BIT_ADJUSTMENT; REG_R_TNR_NON_LOCAL_MEANS_FILTERING0 TNR_NON_LOCAL_MEANS_FILTERING0; REG_R_TNR_NON_LOCAL_MEANS_FILTERING1 TNR_NON_LOCAL_MEANS_FILTERING1; REG_R_TNR_NON_LOCAL_MEANS_FILTERING2 TNR_NON_LOCAL_MEANS_FILTERING2; REG_R_TNR_NON_LOCAL_MEANS_FILTERING3 TNR_NON_LOCAL_MEANS_FILTERING3; UINT32 rsv_6148; REG_R_TNR_HIGH_FREQUENCY_ENHANCEMENT0 TNR_HIGH_FREQUENCY_ENHANCEMENT0; REG_R_TNR_HIGH_FREQUENCY_ENHANCEMENT1 TNR_HIGH_FREQUENCY_ENHANCEMENT1; REG_R_TNR_HIGH_FREQUENCY_ENHANCEMENT2 TNR_HIGH_FREQUENCY_ENHANCEMENT2; REG_R_TNR_HFE_NES0 TNR_HFE_NES0; REG_R_TNR_HFE_NES1 TNR_HFE_NES1; UINT32 rsv_6160; REG_R_TNR_TEMPORAL TNR_TEMPORAL; REG_R_TNR_SPATIAL TNR_SPATIAL; UINT32 rsv_616C[18]; REG_R_TNR_GF_REG TNR_GF_REG; REG_R_TNR_IN1_CNT TNR_IN1_CNT; REG_R_TNR_IN2_CNT TNR_IN2_CNT; REG_R_TNR_IN3_CNT TNR_IN3_CNT; REG_R_TNR_IN4_CNT TNR_IN4_CNT; REG_R_TNR_IN5_CNT TNR_IN5_CNT; REG_R_TNR_IN6_CNT TNR_IN6_CNT; REG_R_TNR_IN7_CNT TNR_IN7_CNT; REG_R_TNR_IN8_CNT TNR_IN8_CNT; REG_R_TNR_IN9_CNT TNR_IN9_CNT; REG_R_TNR_IN10_CNT TNR_IN10_CNT; REG_R_TNR_IN11_CNT TNR_IN11_CNT; UINT32 rsv_61E4; REG_R_TNR_OUT1_CNT TNR_OUT1_CNT; REG_R_TNR_OUT2_CNT TNR_OUT2_CNT; REG_R_TNR_OUT3_CNT TNR_OUT3_CNT; REG_R_TNR_OUT4_CNT TNR_OUT4_CNT; REG_R_TNR_IN1_STATUS TNR_IN1_STATUS; REG_R_TNR_IN2_STATUS TNR_IN2_STATUS; REG_R_TNR_IN3_STATUS TNR_IN3_STATUS; REG_R_TNR_IN4_STATUS TNR_IN4_STATUS; REG_R_TNR_IN5_STATUS TNR_IN5_STATUS; REG_R_TNR_IN6_STATUS TNR_IN6_STATUS; REG_R_TNR_IN7_STATUS TNR_IN7_STATUS; REG_R_TNR_IN8_STATUS TNR_IN8_STATUS; REG_R_TNR_IN9_STATUS TNR_IN9_STATUS; REG_R_TNR_IN10_STATUS TNR_IN10_STATUS; REG_R_TNR_IN11_STATUS TNR_IN11_STATUS; UINT32 rsv_6224; REG_R_TNR_OUT1_STATUS TNR_OUT1_STATUS; REG_R_TNR_OUT2_STATUS TNR_OUT2_STATUS; REG_R_TNR_OUT3_STATUS TNR_OUT3_STATUS; REG_R_TNR_OUT4_STATUS TNR_OUT4_STATUS; UINT32 rsv_6238[9]; REG_R_TNR_STAT_INIT_PHASE0 TNR_STAT_INIT_PHASE0; REG_R_TNR_STAT_INIT_PHASE1 TNR_STAT_INIT_PHASE1; UINT32 rsv_6264[7]; REG_R_TNR_DUMMY0 TNR_DUMMY0; REG_R_TNR_DUMMY1 TNR_DUMMY1; REG_R_TNR_DUMMY2 TNR_DUMMY2; UINT32 rsv_628C[5]; REG_R_TNR_YCNR_FLT_CONFIG TNR_YCNR_FLT_CONFIG; UINT32 rsv_62A4; REG_R_TNR_YCNR_THR_1 TNR_YCNR_THR_1; REG_R_TNR_YCNR_CURVE_1 TNR_YCNR_CURVE_1; REG_R_TNR_YCNR_CURVE_2 TNR_YCNR_CURVE_2; REG_R_TNR_YCNR_CURVE_3 TNR_YCNR_CURVE_3; REG_R_TNR_YCNR_CURVE_4 TNR_YCNR_CURVE_4; REG_R_TNR_YCNR_CURVE_5 TNR_YCNR_CURVE_5; REG_R_TNR_YCNR_CURVE_6 TNR_YCNR_CURVE_6; REG_R_TNR_YCNR_CURVE_7 TNR_YCNR_CURVE_7; REG_R_TNR_YCNR_CURVE_8 TNR_YCNR_CURVE_8; REG_R_TNR_YCNR_CURVE_9 TNR_YCNR_CURVE_9; REG_R_TNR_YCNR_CURVE_10 TNR_YCNR_CURVE_10; REG_R_TNR_YCNR_CURVE_11 TNR_YCNR_CURVE_11; REG_R_TNR_YCNR_CURVE_12 TNR_YCNR_CURVE_12; REG_R_TNR_YCNR_CURVE_13 TNR_YCNR_CURVE_13; REG_R_TNR_YCNR_CURVE_14 TNR_YCNR_CURVE_14; REG_R_TNR_YCNR_CURVE_15 TNR_YCNR_CURVE_15; REG_R_TNR_YCNR_DBG_6 TNR_YCNR_DBG_6; REG_R_TNR_YCNR_DMY_0 TNR_YCNR_DMY_0; REG_R_TNR_YCNR_DBG_9 TNR_YCNR_DBG_9; REG_R_TNR_YCNR_DBG_10 TNR_YCNR_DBG_10; REG_R_TNR_YCNR_DBG_11 TNR_YCNR_DBG_11; REG_R_TNR_YCNR_DBG_12 TNR_YCNR_DBG_12; REG_R_TNR_YCNR_DMY_1 TNR_YCNR_DMY_1; REG_R_TNR_YCNR_DMY_2 TNR_YCNR_DMY_2; REG_R_TNR_YCNR_WGT_CTRL TNR_YCNR_WGT_CTRL; REG_R_TNR_NOISE_TABLE TNR_NOISE_TABLE; REG_R_TNR_MVP_0 TNR_MVP_0; REG_R_TNR_MVP_1 TNR_MVP_1; REG_R_TNR_MVP_2 TNR_MVP_2; REG_R_TNR_MVP_3 TNR_MVP_3; REG_R_TNR_MEMA TNR_MEMA; REG_R_TNR_BLENDING_PRIOR_0 TNR_BLENDING_PRIOR_0; REG_R_TNR_BLENDING_PRIOR_1 TNR_BLENDING_PRIOR_1; REG_R_TNR_EXPOSURE TNR_EXPOSURE; REG_R_TNR_LUMA_ENHANCEMENT TNR_LUMA_ENHANCEMENT; REG_R_TNR_LUMA_EE_CURVE_0 TNR_LUMA_EE_CURVE_0; REG_R_TNR_LUMA_EE_CURVE_1 TNR_LUMA_EE_CURVE_1; REG_R_TNR_LUMA_EE_CURVE_2 TNR_LUMA_EE_CURVE_2; REG_R_TNR_LUMA_EE_CURVE_3 TNR_LUMA_EE_CURVE_3; REG_R_TNR_LUMA_EE_CURVE_4 TNR_LUMA_EE_CURVE_4; REG_R_TNR_LUMA_EE_CURVE_5 TNR_LUMA_EE_CURVE_5; REG_R_TNR_LUMA_EE_CURVE_6 TNR_LUMA_EE_CURVE_6; REG_R_TNR_LUMA_EE_CURVE_7 TNR_LUMA_EE_CURVE_7; REG_R_TNR_LUMA_EE_CURVE_8 TNR_LUMA_EE_CURVE_8; REG_R_TNR_LUMA_EE_CURVE_9 TNR_LUMA_EE_CURVE_9; REG_R_TNR_LUMA_EE_CURVE_10 TNR_LUMA_EE_CURVE_10; REG_R_TNR_LUMA_EE_CURVE_11 TNR_LUMA_EE_CURVE_11; REG_R_TNR_LUMA_EE_CURVE_12 TNR_LUMA_EE_CURVE_12; REG_R_TNR_LUMA_EE_CURVE_13 TNR_LUMA_EE_CURVE_13; REG_R_TNR_LUMA_EE_CURVE_14 TNR_LUMA_EE_CURVE_14; REG_R_TNR_LUMA_EE_CURVE_15 TNR_LUMA_EE_CURVE_15; REG_R_TNR_LUMA_EE_CURVE_16 TNR_LUMA_EE_CURVE_16; REG_R_TNR_LUMA_EE_CURVE_17 TNR_LUMA_EE_CURVE_17; REG_R_TNR_LUMA_EE_CURVE_18 TNR_LUMA_EE_CURVE_18; REG_R_TNR_LUMA_EE_CURVE_19 TNR_LUMA_EE_CURVE_19; REG_R_TNR_LUMA_EE_CURVE_20 TNR_LUMA_EE_CURVE_20; REG_R_TNR_LUMA_EE_CURVE_21 TNR_LUMA_EE_CURVE_21; REG_R_TNR_LUMA_EE_CURVE_22 TNR_LUMA_EE_CURVE_22; REG_R_TNR_LUMA_EE_CURVE_23 TNR_LUMA_EE_CURVE_23; REG_R_TNR_LUMA_EE_CURVE_24 TNR_LUMA_EE_CURVE_24; REG_R_TNR_LUMA_EE_CURVE_25 TNR_LUMA_EE_CURVE_25; REG_R_TNR_LUMA_EE_CURVE_26 TNR_LUMA_EE_CURVE_26; REG_R_TNR_LUMA_EE_CURVE_27 TNR_LUMA_EE_CURVE_27; REG_R_TNR_LUMA_EE_CURVE_28 TNR_LUMA_EE_CURVE_28; REG_R_TNR_LUMA_EE_CURVE_29 TNR_LUMA_EE_CURVE_29; REG_R_TNR_LUMA_EE_CURVE_30 TNR_LUMA_EE_CURVE_30; REG_R_TNR_LUMA_EE_CURVE_31 TNR_LUMA_EE_CURVE_31; REG_R_TNR_NEW_EDGE_CONF_0 TNR_NEW_EDGE_CONF_0; REG_R_TNR_NEW_EDGE_CONF_1 TNR_NEW_EDGE_CONF_1; REG_R_TNR_MOTION_DETECTION_0 TNR_MOTION_DETECTION_0; REG_R_TNR_MOTION_DETECTION_1 TNR_MOTION_DETECTION_1; REG_R_TNR_MOTION_DETECTION_2 TNR_MOTION_DETECTION_2; REG_R_TNR_FD_ADAPTIVE_ADJUSTMENT_0 TNR_FD_ADAPTIVE_ADJUSTMENT_0; REG_R_TNR_FD_ADAPTIVE_ADJUSTMENT_1 TNR_FD_ADAPTIVE_ADJUSTMENT_1; REG_R_TNR_GD_ADAPTIVE_ADJUSTMENT_0 TNR_GD_ADAPTIVE_ADJUSTMENT_0; REG_R_TNR_GD_ADAPTIVE_ADJUSTMENT_1 TNR_GD_ADAPTIVE_ADJUSTMENT_1; REG_R_TNR_MD_ADAPTIVE_ADJUSTMENT_0 TNR_MD_ADAPTIVE_ADJUSTMENT_0; REG_R_TNR_MD_ADAPTIVE_ADJUSTMENT_1 TNR_MD_ADAPTIVE_ADJUSTMENT_1; REG_R_TNR_MD_ADAPTIVE_ADJUSTMENT_2 TNR_MD_ADAPTIVE_ADJUSTMENT_2; REG_R_TNR_MD_ADAPTIVE_ADJUSTMENT_3 TNR_MD_ADAPTIVE_ADJUSTMENT_3; REG_R_TNR_RD_ADAPTIVE_ADJUSTMENT_0 TNR_RD_ADAPTIVE_ADJUSTMENT_0; REG_R_TNR_RESIDUE_DIFFERENCE2 TNR_RESIDUE_DIFFERENCE2; REG_R_TNR_ACCUMULATION TNR_ACCUMULATION; REG_R_TNR_BACKGROUND_PROTECTION3 TNR_BACKGROUND_PROTECTION3; REG_R_TNR_SINGLE_SCALE_ALPHA TNR_SINGLE_SCALE_ALPHA; REG_R_TNR_STNLM_0 TNR_STNLM_0; REG_R_TNR_STNLM_1 TNR_STNLM_1; REG_R_TNR_STNLM_2 TNR_STNLM_2; REG_R_TNR_STNLM_3 TNR_STNLM_3; REG_R_TNR_STNLM_4 TNR_STNLM_4; REG_R_TNR_STNLM_5 TNR_STNLM_5; REG_R_TNR_STNLM_6 TNR_STNLM_6; REG_R_TNR_DYNAMIC_MAX_ALPHA_0 TNR_DYNAMIC_MAX_ALPHA_0; REG_R_TNR_DYNAMIC_MAX_ALPHA_1 TNR_DYNAMIC_MAX_ALPHA_1; REG_R_TNR_DYNAMIC_MAX_ALPHA_2 TNR_DYNAMIC_MAX_ALPHA_2; REG_R_TNR_DYNAMIC_MAX_ALPHA_3 TNR_DYNAMIC_MAX_ALPHA_3; REG_R_TNR_DYNAMIC_MAX_ALPHA_4 TNR_DYNAMIC_MAX_ALPHA_4; REG_R_TNR_DYNAMIC_MAX_ALPHA_5 TNR_DYNAMIC_MAX_ALPHA_5; REG_R_TNR_FREQ_NR_0 TNR_FREQ_NR_0; REG_R_TNR_FREQ_NR_1 TNR_FREQ_NR_1; REG_R_TNR_FREQ_NR_2 TNR_FREQ_NR_2; REG_R_TNR_FALLBACK TNR_FALLBACK; REG_R_TNR_DIFF_MAP_GEN TNR_DIFF_MAP_GEN; REG_R_TNR_MULTISCALE_ACCUMULATION TNR_MULTISCALE_ACCUMULATION; REG_R_TNR_NLM_THR_1 TNR_NLM_THR_1; REG_R_TNR_NLM_THR_2 TNR_NLM_THR_2; REG_R_TNR_GF_EXP_CURVE_0 TNR_GF_EXP_CURVE_0; REG_R_TNR_GF_EXP_CURVE_1 TNR_GF_EXP_CURVE_1; REG_R_TNR_GF_EXP_CURVE_2 TNR_GF_EXP_CURVE_2; REG_R_TNR_GF_EXP_CURVE_3 TNR_GF_EXP_CURVE_3; REG_R_TNR_GF_EXP_CURVE_4 TNR_GF_EXP_CURVE_4; REG_R_TNR_GF_EXP_CURVE_5 TNR_GF_EXP_CURVE_5; REG_R_TNR_GF_EXP_CURVE_6 TNR_GF_EXP_CURVE_6; REG_R_TNR_GF_EXP_CURVE_7 TNR_GF_EXP_CURVE_7; REG_R_TNR_GF_EXP_CURVE_8 TNR_GF_EXP_CURVE_8; REG_R_TNR_GF_EXP_CURVE_9 TNR_GF_EXP_CURVE_9; REG_R_TNR_GF_EXP_CURVE_10 TNR_GF_EXP_CURVE_10; REG_R_TNR_GF_EXP_CURVE_11 TNR_GF_EXP_CURVE_11; REG_R_TNR_GF_EXP_CURVE_12 TNR_GF_EXP_CURVE_12; REG_R_TNR_GF_EXP_CURVE_13 TNR_GF_EXP_CURVE_13; REG_R_TNR_GF_EXP_CURVE_14 TNR_GF_EXP_CURVE_14; REG_R_TNR_GF_EXP_CURVE_15 TNR_GF_EXP_CURVE_15; REG_R_TNR_GF_EXP_CURVE_16 TNR_GF_EXP_CURVE_16; REG_R_TNR_GF_EXP_CURVE_17 TNR_GF_EXP_CURVE_17; REG_R_TNR_GF_EXP_CURVE_18 TNR_GF_EXP_CURVE_18; REG_R_TNR_GF_EXP_CURVE_19 TNR_GF_EXP_CURVE_19; REG_R_TNR_GF_EXP_CURVE_20 TNR_GF_EXP_CURVE_20; REG_R_TNR_GF_EXP_CURVE_21 TNR_GF_EXP_CURVE_21; REG_R_TNR_GF_EXP_CURVE_22 TNR_GF_EXP_CURVE_22; REG_R_TNR_GF_EXP_CURVE_23 TNR_GF_EXP_CURVE_23; REG_R_TNR_GF_EXP_CURVE_24 TNR_GF_EXP_CURVE_24; REG_R_TNR_GF_EXP_CURVE_25 TNR_GF_EXP_CURVE_25; REG_R_TNR_GF_EXP_CURVE_26 TNR_GF_EXP_CURVE_26; REG_R_TNR_GF_EXP_CURVE_27 TNR_GF_EXP_CURVE_27; REG_R_TNR_GF_EXP_CURVE_28 TNR_GF_EXP_CURVE_28; REG_R_TNR_GF_EXP_CURVE_29 TNR_GF_EXP_CURVE_29; REG_R_TNR_GF_EXP_CURVE_30 TNR_GF_EXP_CURVE_30; REG_R_TNR_GF_EXP_CURVE_31 TNR_GF_EXP_CURVE_31; REG_R_TNR_GF_EXP_CURVE_32 TNR_GF_EXP_CURVE_32; REG_R_TNR_GF_EXP_CURVE_33 TNR_GF_EXP_CURVE_33; REG_R_TNR_GF_EXP_CURVE_34 TNR_GF_EXP_CURVE_34; REG_R_TNR_GF_EXP_CURVE_35 TNR_GF_EXP_CURVE_35; REG_R_TNR_GF_EXP_CURVE_36 TNR_GF_EXP_CURVE_36; REG_R_TNR_GF_EXP_CURVE_37 TNR_GF_EXP_CURVE_37; REG_R_TNR_GF_EXP_CURVE_38 TNR_GF_EXP_CURVE_38; REG_R_TNR_GF_EXP_CURVE_39 TNR_GF_EXP_CURVE_39; REG_R_TNR_GF_EXP_CURVE_40 TNR_GF_EXP_CURVE_40; REG_R_TNR_GF_EXP_CURVE_41 TNR_GF_EXP_CURVE_41; REG_R_TNR_GF_EXP_CURVE_42 TNR_GF_EXP_CURVE_42; REG_R_TNR_GF_EXP_CURVE_43 TNR_GF_EXP_CURVE_43; REG_R_TNR_GF_EXP_CURVE_44 TNR_GF_EXP_CURVE_44; REG_R_TNR_GF_EXP_CURVE_45 TNR_GF_EXP_CURVE_45; REG_R_TNR_GF_EXP_CURVE_46 TNR_GF_EXP_CURVE_46; REG_R_TNR_GF_EXP_CURVE_47 TNR_GF_EXP_CURVE_47; REG_R_TNR_GF_EXP_CURVE_48 TNR_GF_EXP_CURVE_48; REG_R_TNR_GF_EXP_CURVE_49 TNR_GF_EXP_CURVE_49; REG_R_TNR_GF_EXP_CURVE_50 TNR_GF_EXP_CURVE_50; REG_R_TNR_GF_EXP_CURVE_51 TNR_GF_EXP_CURVE_51; REG_R_TNR_GF_EXP_CURVE_52 TNR_GF_EXP_CURVE_52; REG_R_TNR_GF_EXP_CURVE_53 TNR_GF_EXP_CURVE_53; REG_R_TNR_GF_EXP_CURVE_54 TNR_GF_EXP_CURVE_54; REG_R_TNR_GF_EXP_CURVE_55 TNR_GF_EXP_CURVE_55; REG_R_TNR_GF_EXP_CURVE_56 TNR_GF_EXP_CURVE_56; REG_R_TNR_GF_EXP_CURVE_57 TNR_GF_EXP_CURVE_57; REG_R_TNR_GF_EXP_CURVE_58 TNR_GF_EXP_CURVE_58; REG_R_TNR_GF_EXP_CURVE_59 TNR_GF_EXP_CURVE_59; REG_R_TNR_GF_EXP_CURVE_60 TNR_GF_EXP_CURVE_60; REG_R_TNR_GF_EXP_CURVE_61 TNR_GF_EXP_CURVE_61; REG_R_TNR_GF_EXP_CURVE_62 TNR_GF_EXP_CURVE_62; REG_R_TNR_GF_EXP_CURVE_63 TNR_GF_EXP_CURVE_63; REG_R_TNR_GF_EXP_CURVE_64 TNR_GF_EXP_CURVE_64; REG_R_TNR_GF_EXP_CURVE_65 TNR_GF_EXP_CURVE_65; REG_R_TNR_GF_EXP_CURVE_66 TNR_GF_EXP_CURVE_66; REG_R_TNR_GF_EXP_CURVE_67 TNR_GF_EXP_CURVE_67; REG_R_TNR_GF_EXP_CURVE_68 TNR_GF_EXP_CURVE_68; REG_R_TNR_GF_EXP_CURVE_69 TNR_GF_EXP_CURVE_69; REG_R_TNR_GF_EXP_CURVE_70 TNR_GF_EXP_CURVE_70; REG_R_TNR_GF_EXP_CURVE_71 TNR_GF_EXP_CURVE_71; REG_R_TNR_GF_EXP_CURVE_72 TNR_GF_EXP_CURVE_72; REG_R_TNR_GF_EXP_CURVE_73 TNR_GF_EXP_CURVE_73; REG_R_TNR_GF_EXP_CURVE_74 TNR_GF_EXP_CURVE_74; REG_R_TNR_GF_EXP_CURVE_75 TNR_GF_EXP_CURVE_75; REG_R_TNR_GF_EXP_CURVE_76 TNR_GF_EXP_CURVE_76; REG_R_TNR_GF_EXP_CURVE_77 TNR_GF_EXP_CURVE_77; REG_R_TNR_GF_EXP_CURVE_78 TNR_GF_EXP_CURVE_78; REG_R_TNR_GF_EXP_CURVE_79 TNR_GF_EXP_CURVE_79; REG_R_TNR_GF_EXP_CURVE_80 TNR_GF_EXP_CURVE_80; REG_R_TNR_GF_EXP_CURVE_81 TNR_GF_EXP_CURVE_81; REG_R_TNR_GF_EXP_CURVE_82 TNR_GF_EXP_CURVE_82; REG_R_TNR_GF_EXP_CURVE_83 TNR_GF_EXP_CURVE_83; REG_R_TNR_GF_EXP_CURVE_84 TNR_GF_EXP_CURVE_84; REG_R_TNR_GF_EXP_CURVE_85 TNR_GF_EXP_CURVE_85; REG_R_TNR_GF_EXP_CURVE_86 TNR_GF_EXP_CURVE_86; REG_R_TNR_GF_EXP_CURVE_87 TNR_GF_EXP_CURVE_87; REG_R_TNR_GF_EXP_CURVE_88 TNR_GF_EXP_CURVE_88; REG_R_TNR_GF_EXP_CURVE_89 TNR_GF_EXP_CURVE_89; REG_R_TNR_GF_EXP_CURVE_90 TNR_GF_EXP_CURVE_90; REG_R_TNR_GF_EXP_CURVE_91 TNR_GF_EXP_CURVE_91; REG_R_TNR_GF_EXP_CURVE_92 TNR_GF_EXP_CURVE_92; REG_R_TNR_GF_EXP_CURVE_93 TNR_GF_EXP_CURVE_93; REG_R_TNR_GF_EXP_CURVE_94 TNR_GF_EXP_CURVE_94; REG_R_TNR_GF_EXP_CURVE_95 TNR_GF_EXP_CURVE_95; REG_R_TNR_GF_EXP_CURVE_96 TNR_GF_EXP_CURVE_96; REG_R_TNR_GF_EXP_CURVE_97 TNR_GF_EXP_CURVE_97; REG_R_TNR_GF_EXP_CURVE_98 TNR_GF_EXP_CURVE_98; REG_R_TNR_GF_EXP_CURVE_99 TNR_GF_EXP_CURVE_99; REG_R_TNR_GF_EXP_CURVE_100 TNR_GF_EXP_CURVE_100; REG_R_TNR_GF_EXP_CURVE_101 TNR_GF_EXP_CURVE_101; REG_R_TNR_GF_EXP_CURVE_102 TNR_GF_EXP_CURVE_102; REG_R_TNR_GF_EXP_CURVE_103 TNR_GF_EXP_CURVE_103; REG_R_TNR_GF_EXP_CURVE_104 TNR_GF_EXP_CURVE_104; REG_R_TNR_GF_EXP_CURVE_105 TNR_GF_EXP_CURVE_105; REG_R_TNR_GF_EXP_CURVE_106 TNR_GF_EXP_CURVE_106; REG_R_TNR_GF_EXP_CURVE_107 TNR_GF_EXP_CURVE_107; REG_R_TNR_GF_EXP_CURVE_108 TNR_GF_EXP_CURVE_108; REG_R_TNR_GF_EXP_CURVE_109 TNR_GF_EXP_CURVE_109; REG_R_TNR_GF_EXP_CURVE_110 TNR_GF_EXP_CURVE_110; REG_R_TNR_GF_EXP_CURVE_111 TNR_GF_EXP_CURVE_111; REG_R_TNR_GF_EXP_CURVE_112 TNR_GF_EXP_CURVE_112; REG_R_TNR_GF_EXP_CURVE_113 TNR_GF_EXP_CURVE_113; REG_R_TNR_GF_EXP_CURVE_114 TNR_GF_EXP_CURVE_114; REG_R_TNR_GF_EXP_CURVE_115 TNR_GF_EXP_CURVE_115; REG_R_TNR_GF_EXP_CURVE_116 TNR_GF_EXP_CURVE_116; REG_R_TNR_GF_EXP_CURVE_117 TNR_GF_EXP_CURVE_117; REG_R_TNR_GF_EXP_CURVE_118 TNR_GF_EXP_CURVE_118; REG_R_TNR_GF_EXP_CURVE_119 TNR_GF_EXP_CURVE_119; REG_R_TNR_GF_EXP_CURVE_120 TNR_GF_EXP_CURVE_120; REG_R_TNR_GF_EXP_CURVE_121 TNR_GF_EXP_CURVE_121; REG_R_TNR_GF_EXP_CURVE_122 TNR_GF_EXP_CURVE_122; REG_R_TNR_GF_EXP_CURVE_123 TNR_GF_EXP_CURVE_123; REG_R_TNR_GF_EXP_CURVE_124 TNR_GF_EXP_CURVE_124; REG_R_TNR_GF_EXP_CURVE_125 TNR_GF_EXP_CURVE_125; REG_R_TNR_GF_EXP_CURVE_126 TNR_GF_EXP_CURVE_126; REG_R_TNR_GF_EXP_CURVE_127 TNR_GF_EXP_CURVE_127; REG_R_TNR_GF_EXP_CURVE_128 TNR_GF_EXP_CURVE_128; REG_R_TNR_GF_EXP_CURVE_129 TNR_GF_EXP_CURVE_129; REG_R_TNR_GF_EXP_CURVE_130 TNR_GF_EXP_CURVE_130; REG_R_TNR_GF_EXP_CURVE_131 TNR_GF_EXP_CURVE_131; REG_R_TNR_GF_EXP_CURVE_132 TNR_GF_EXP_CURVE_132; REG_R_TNR_GF_EXP_CURVE_133 TNR_GF_EXP_CURVE_133; REG_R_TNR_GF_EXP_CURVE_134 TNR_GF_EXP_CURVE_134; REG_R_TNR_GF_EXP_CURVE_135 TNR_GF_EXP_CURVE_135; REG_R_TNR_GF_EXP_CURVE_136 TNR_GF_EXP_CURVE_136; REG_R_TNR_GF_EXP_CURVE_137 TNR_GF_EXP_CURVE_137; REG_R_TNR_GF_EXP_CURVE_138 TNR_GF_EXP_CURVE_138; REG_R_TNR_GF_EXP_CURVE_139 TNR_GF_EXP_CURVE_139; REG_R_TNR_GF_EXP_CURVE_140 TNR_GF_EXP_CURVE_140; REG_R_TNR_GF_EXP_CURVE_141 TNR_GF_EXP_CURVE_141; REG_R_TNR_GF_EXP_CURVE_142 TNR_GF_EXP_CURVE_142; REG_R_TNR_GF_EXP_CURVE_143 TNR_GF_EXP_CURVE_143; REG_R_TNR_GF_EXP_CURVE_144 TNR_GF_EXP_CURVE_144; REG_R_TNR_GF_EXP_CURVE_145 TNR_GF_EXP_CURVE_145; REG_R_TNR_GF_EXP_CURVE_146 TNR_GF_EXP_CURVE_146; REG_R_TNR_GF_EXP_CURVE_147 TNR_GF_EXP_CURVE_147; REG_R_TNR_GF_EXP_CURVE_148 TNR_GF_EXP_CURVE_148; REG_R_TNR_GF_EXP_CURVE_149 TNR_GF_EXP_CURVE_149; REG_R_TNR_GF_EXP_CURVE_150 TNR_GF_EXP_CURVE_150; REG_R_TNR_GF_EXP_CURVE_151 TNR_GF_EXP_CURVE_151; REG_R_TNR_GF_EXP_CURVE_152 TNR_GF_EXP_CURVE_152; REG_R_TNR_GF_EXP_CURVE_153 TNR_GF_EXP_CURVE_153; REG_R_TNR_GF_EXP_CURVE_154 TNR_GF_EXP_CURVE_154; REG_R_TNR_GF_EXP_CURVE_155 TNR_GF_EXP_CURVE_155; REG_R_TNR_GF_EXP_CURVE_156 TNR_GF_EXP_CURVE_156; REG_R_TNR_GF_EXP_CURVE_157 TNR_GF_EXP_CURVE_157; REG_R_TNR_GF_EXP_CURVE_158 TNR_GF_EXP_CURVE_158; REG_R_TNR_GF_EXP_CURVE_159 TNR_GF_EXP_CURVE_159; REG_R_TNR_GF_EXP_CURVE_160 TNR_GF_EXP_CURVE_160; REG_R_TNR_GF_EXP_CURVE_161 TNR_GF_EXP_CURVE_161; REG_R_TNR_GF_EXP_CURVE_162 TNR_GF_EXP_CURVE_162; REG_R_TNR_GF_EXP_CURVE_163 TNR_GF_EXP_CURVE_163; REG_R_TNR_GF_EXP_CURVE_164 TNR_GF_EXP_CURVE_164; REG_R_TNR_GF_EXP_CURVE_165 TNR_GF_EXP_CURVE_165; REG_R_TNR_GF_EXP_CURVE_166 TNR_GF_EXP_CURVE_166; REG_R_TNR_GF_EXP_CURVE_167 TNR_GF_EXP_CURVE_167; REG_R_TNR_GF_EXP_CURVE_168 TNR_GF_EXP_CURVE_168; REG_R_TNR_GF_EXP_CURVE_169 TNR_GF_EXP_CURVE_169; REG_R_TNR_GF_EXP_CURVE_170 TNR_GF_EXP_CURVE_170; REG_R_TNR_GF_EXP_CURVE_171 TNR_GF_EXP_CURVE_171; REG_R_TNR_GF_EXP_CURVE_172 TNR_GF_EXP_CURVE_172; REG_R_TNR_GF_EXP_CURVE_173 TNR_GF_EXP_CURVE_173; REG_R_TNR_GF_EXP_CURVE_174 TNR_GF_EXP_CURVE_174; REG_R_TNR_GF_EXP_CURVE_175 TNR_GF_EXP_CURVE_175; REG_R_TNR_GF_EXP_CURVE_176 TNR_GF_EXP_CURVE_176; REG_R_TNR_GF_EXP_CURVE_177 TNR_GF_EXP_CURVE_177; REG_R_TNR_GF_EXP_CURVE_178 TNR_GF_EXP_CURVE_178; REG_R_TNR_GF_EXP_CURVE_179 TNR_GF_EXP_CURVE_179; REG_R_TNR_GF_EXP_CURVE_180 TNR_GF_EXP_CURVE_180; REG_R_TNR_GF_EXP_CURVE_181 TNR_GF_EXP_CURVE_181; REG_R_TNR_GF_EXP_CURVE_182 TNR_GF_EXP_CURVE_182; REG_R_TNR_GF_EXP_CURVE_183 TNR_GF_EXP_CURVE_183; REG_R_TNR_GF_EXP_CURVE_184 TNR_GF_EXP_CURVE_184; REG_R_TNR_GF_EXP_CURVE_185 TNR_GF_EXP_CURVE_185; REG_R_TNR_GF_EXP_CURVE_186 TNR_GF_EXP_CURVE_186; REG_R_TNR_GF_EXP_CURVE_187 TNR_GF_EXP_CURVE_187; REG_R_TNR_GF_EXP_CURVE_188 TNR_GF_EXP_CURVE_188; REG_R_TNR_GF_EXP_CURVE_189 TNR_GF_EXP_CURVE_189; REG_R_TNR_GF_EXP_CURVE_190 TNR_GF_EXP_CURVE_190; REG_R_TNR_GF_EXP_CURVE_191 TNR_GF_EXP_CURVE_191; REG_R_TNR_GF_EXP_CURVE_192 TNR_GF_EXP_CURVE_192; REG_R_TNR_GF_EXP_CURVE_193 TNR_GF_EXP_CURVE_193; REG_R_TNR_GF_EXP_CURVE_194 TNR_GF_EXP_CURVE_194; REG_R_TNR_GF_EXP_CURVE_195 TNR_GF_EXP_CURVE_195; REG_R_TNR_GF_EXP_CURVE_196 TNR_GF_EXP_CURVE_196; REG_R_TNR_GF_EXP_CURVE_197 TNR_GF_EXP_CURVE_197; REG_R_TNR_GF_EXP_CURVE_198 TNR_GF_EXP_CURVE_198; REG_R_TNR_GF_EXP_CURVE_199 TNR_GF_EXP_CURVE_199; REG_R_TNR_GF_EXP_CURVE_200 TNR_GF_EXP_CURVE_200; REG_R_TNR_GF_EXP_CURVE_201 TNR_GF_EXP_CURVE_201; REG_R_TNR_GF_EXP_CURVE_202 TNR_GF_EXP_CURVE_202; REG_R_TNR_GF_EXP_CURVE_203 TNR_GF_EXP_CURVE_203; REG_R_TNR_GF_EXP_CURVE_204 TNR_GF_EXP_CURVE_204; REG_R_TNR_GF_EXP_CURVE_205 TNR_GF_EXP_CURVE_205; REG_R_TNR_GF_EXP_CURVE_206 TNR_GF_EXP_CURVE_206; REG_R_TNR_GF_EXP_CURVE_207 TNR_GF_EXP_CURVE_207; REG_R_TNR_GF_EXP_CURVE_208 TNR_GF_EXP_CURVE_208; REG_R_TNR_GF_EXP_CURVE_209 TNR_GF_EXP_CURVE_209; REG_R_TNR_GF_EXP_CURVE_210 TNR_GF_EXP_CURVE_210; REG_R_TNR_GF_EXP_CURVE_211 TNR_GF_EXP_CURVE_211; REG_R_TNR_GF_EXP_CURVE_212 TNR_GF_EXP_CURVE_212; REG_R_TNR_GF_EXP_CURVE_213 TNR_GF_EXP_CURVE_213; REG_R_TNR_GF_EXP_CURVE_214 TNR_GF_EXP_CURVE_214; REG_R_TNR_GF_EXP_CURVE_215 TNR_GF_EXP_CURVE_215; REG_R_TNR_GF_EXP_CURVE_216 TNR_GF_EXP_CURVE_216; REG_R_TNR_GF_EXP_CURVE_217 TNR_GF_EXP_CURVE_217; REG_R_TNR_GF_EXP_CURVE_218 TNR_GF_EXP_CURVE_218; REG_R_TNR_GF_EXP_CURVE_219 TNR_GF_EXP_CURVE_219; REG_R_TNR_GF_EXP_CURVE_220 TNR_GF_EXP_CURVE_220; REG_R_TNR_GF_EXP_CURVE_221 TNR_GF_EXP_CURVE_221; REG_R_TNR_GF_EXP_CURVE_222 TNR_GF_EXP_CURVE_222; REG_R_TNR_GF_EXP_CURVE_223 TNR_GF_EXP_CURVE_223; REG_R_TNR_GF_EXP_CURVE_224 TNR_GF_EXP_CURVE_224; REG_R_TNR_GF_EXP_CURVE_225 TNR_GF_EXP_CURVE_225; REG_R_TNR_GF_EXP_CURVE_226 TNR_GF_EXP_CURVE_226; REG_R_TNR_GF_EXP_CURVE_227 TNR_GF_EXP_CURVE_227; REG_R_TNR_GF_EXP_CURVE_228 TNR_GF_EXP_CURVE_228; REG_R_TNR_GF_EXP_CURVE_229 TNR_GF_EXP_CURVE_229; REG_R_TNR_GF_EXP_CURVE_230 TNR_GF_EXP_CURVE_230; REG_R_TNR_GF_EXP_CURVE_231 TNR_GF_EXP_CURVE_231; REG_R_TNR_GF_EXP_CURVE_232 TNR_GF_EXP_CURVE_232; REG_R_TNR_GF_EXP_CURVE_233 TNR_GF_EXP_CURVE_233; REG_R_TNR_GF_EXP_CURVE_234 TNR_GF_EXP_CURVE_234; REG_R_TNR_GF_EXP_CURVE_235 TNR_GF_EXP_CURVE_235; REG_R_TNR_GF_EXP_CURVE_236 TNR_GF_EXP_CURVE_236; REG_R_TNR_GF_EXP_CURVE_237 TNR_GF_EXP_CURVE_237; REG_R_TNR_GF_EXP_CURVE_238 TNR_GF_EXP_CURVE_238; REG_R_TNR_GF_EXP_CURVE_239 TNR_GF_EXP_CURVE_239; REG_R_TNR_GF_EXP_CURVE_240 TNR_GF_EXP_CURVE_240; REG_R_TNR_GF_EXP_CURVE_241 TNR_GF_EXP_CURVE_241; REG_R_TNR_GF_EXP_CURVE_242 TNR_GF_EXP_CURVE_242; REG_R_TNR_GF_EXP_CURVE_243 TNR_GF_EXP_CURVE_243; REG_R_TNR_GF_EXP_CURVE_244 TNR_GF_EXP_CURVE_244; REG_R_TNR_GF_EXP_CURVE_245 TNR_GF_EXP_CURVE_245; REG_R_TNR_GF_EXP_CURVE_246 TNR_GF_EXP_CURVE_246; REG_R_TNR_GF_EXP_CURVE_247 TNR_GF_EXP_CURVE_247; REG_R_TNR_GF_EXP_CURVE_248 TNR_GF_EXP_CURVE_248; REG_R_TNR_GF_EXP_CURVE_249 TNR_GF_EXP_CURVE_249; REG_R_TNR_GF_EXP_CURVE_250 TNR_GF_EXP_CURVE_250; REG_R_TNR_GF_EXP_CURVE_251 TNR_GF_EXP_CURVE_251; REG_R_TNR_GF_EXP_CURVE_252 TNR_GF_EXP_CURVE_252; REG_R_TNR_GF_EXP_CURVE_253 TNR_GF_EXP_CURVE_253; REG_R_TNR_GF_EXP_CURVE_254 TNR_GF_EXP_CURVE_254; REG_R_TNR_GF_EXP_CURVE_255 TNR_GF_EXP_CURVE_255; REG_R_TNR_SLK_CEN TNR_SLK_CEN; REG_R_TNR_SLK_RR_CON0 TNR_SLK_RR_CON0; REG_R_TNR_SLK_RR_CON1 TNR_SLK_RR_CON1; REG_R_TNR_SLK_GAIN TNR_SLK_GAIN; REG_R_TNR_SLK_HRZ TNR_SLK_HRZ; REG_R_TNR_SLK_VRZ TNR_SLK_VRZ; REG_R_TNR_SLK_CROPX TNR_SLK_CROPX; REG_R_TNR_SLK_CROPY TNR_SLK_CROPY; REG_R_TNR_SLK_XOFF TNR_SLK_XOFF; REG_R_TNR_SLK_YOFF TNR_SLK_YOFF; REG_R_TNR_SLK_SLP_CON0 TNR_SLK_SLP_CON0; REG_R_TNR_SLK_SLP_CON1 TNR_SLK_SLP_CON1; REG_R_TNR_SLK_SLP_CON2 TNR_SLK_SLP_CON2; REG_R_TNR_SLK_SLP_CON3 TNR_SLK_SLP_CON3; REG_R_TNR_SLK_SIZE TNR_SLK_SIZE; UINT32 rsv_688C[2]; REG_R_TNR_DIV_INV1 TNR_DIV_INV1; REG_R_TNR_DIV_INV2 TNR_DIV_INV2; REG_R_TNR_DIV_INV3 TNR_DIV_INV3; REG_R_TNR_DIV_INV4 TNR_DIV_INV4; REG_R_TNR_DIV_INV5 TNR_DIV_INV5; REG_R_TNR_DE_CONF TNR_DE_CONF; REG_R_TNR_DE_NES0 TNR_DE_NES0; REG_R_TNR_DE_NES1 TNR_DE_NES1; REG_R_TNR_DE_NES2 TNR_DE_NES2; REG_R_TNR_DE_NES3 TNR_DE_NES3; REG_R_TNR_TILE TNR_TILE; REG_R_TNR_ENHANCEMENT_RATE TNR_ENHANCEMENT_RATE; REG_R_TNR_COMPENSATION TNR_COMPENSATION; REG_R_TNR_GD_ADAPTIVE_ADJUSTMENT_2 TNR_GD_ADAPTIVE_ADJUSTMENT_2; REG_R_TNR_NEW_EDGE_CONF_2 TNR_NEW_EDGE_CONF_2; REG_R_TNR_VARIANCE TNR_VARIANCE; REG_R_TNR_YCNR_DBG_13 TNR_YCNR_DBG_13; REG_R_TNR_PADDING_1 TNR_PADDING_1; REG_R_TNR_PADDING_2 TNR_PADDING_2; REG_R_TNR_PADDING_3 TNR_PADDING_3; REG_R_TNR_ME_INK TNR_ME_INK; }; /** * Mediatek camera urz6t tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_urz6t { REG_R_URZ6T_RSZ_ENABLE URZ6T_RSZ_ENABLE; REG_R_URZ6T_RSZ_CONTROL_1 URZ6T_RSZ_CONTROL_1; REG_R_URZ6T_RSZ_CONTROL_2 URZ6T_RSZ_CONTROL_2; REG_R_URZ6T_RSZ_INT_FLAG URZ6T_RSZ_INT_FLAG; REG_R_URZ6T_RSZ_INPUT_IMAGE URZ6T_RSZ_INPUT_IMAGE; REG_R_URZ6T_RSZ_OUTPUT_IMAGE URZ6T_RSZ_OUTPUT_IMAGE; REG_R_URZ6T_RSZ_HORIZONTAL_COEFF_STEP URZ6T_RSZ_HORIZONTAL_COEFF_STEP; REG_R_URZ6T_RSZ_VERTICAL_COEFF_STEP URZ6T_RSZ_VERTICAL_COEFF_STEP; REG_R_URZ6T_RSZ_LUMA_HORIZONTAL_INTEGER_OFFSET URZ6T_RSZ_LUMA_HORIZONTAL_INTEGER_OFFSET; REG_R_URZ6T_RSZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET URZ6T_RSZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET; REG_R_URZ6T_RSZ_LUMA_VERTICAL_INTEGER_OFFSET URZ6T_RSZ_LUMA_VERTICAL_INTEGER_OFFSET; REG_R_URZ6T_RSZ_LUMA_VERTICAL_SUBPIXEL_OFFSET URZ6T_RSZ_LUMA_VERTICAL_SUBPIXEL_OFFSET; REG_R_URZ6T_RSZ_CHROMA_HORIZONTAL_INTEGER_OFFSET URZ6T_RSZ_CHROMA_HORIZONTAL_INTEGER_OFFSET; REG_R_URZ6T_RSZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET URZ6T_RSZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET; UINT32 rsv_3038[2]; REG_R_URZ6T_RSZ_RSV URZ6T_RSZ_RSV; REG_R_URZ6T_RSZ_DEBUG_SEL URZ6T_RSZ_DEBUG_SEL; REG_R_URZ6T_RSZ_DEBUG URZ6T_RSZ_DEBUG; REG_R_URZ6T_RSZ_TAP_ADAPT URZ6T_RSZ_TAP_ADAPT; UINT32 rsv_3050[40]; REG_R_URZ6T_RSZ_SHADOW_CTRL URZ6T_RSZ_SHADOW_CTRL; UINT32 rsv_30F4[2]; REG_R_URZ6T_RSZ_ATPG URZ6T_RSZ_ATPG; REG_R_URZ6T_PAT1_GEN_SET URZ6T_PAT1_GEN_SET; REG_R_URZ6T_PAT1_GEN_FRM_SIZE URZ6T_PAT1_GEN_FRM_SIZE; REG_R_URZ6T_PAT1_GEN_COLOR0 URZ6T_PAT1_GEN_COLOR0; REG_R_URZ6T_PAT1_GEN_COLOR1 URZ6T_PAT1_GEN_COLOR1; REG_R_URZ6T_PAT1_GEN_COLOR2 URZ6T_PAT1_GEN_COLOR2; REG_R_URZ6T_PAT1_GEN_POS URZ6T_PAT1_GEN_POS; UINT32 rsv_3118[3]; REG_R_URZ6T_PAT1_GEN_TILE_POS URZ6T_PAT1_GEN_TILE_POS; REG_R_URZ6T_PAT1_GEN_TILE_OV URZ6T_PAT1_GEN_TILE_OV; UINT32 rsv_312C[53]; REG_R_URZ6T_PAT2_GEN_SET URZ6T_PAT2_GEN_SET; UINT32 rsv_3204; REG_R_URZ6T_PAT2_GEN_COLOR0 URZ6T_PAT2_GEN_COLOR0; REG_R_URZ6T_PAT2_GEN_COLOR1 URZ6T_PAT2_GEN_COLOR1; UINT32 rsv_3210; REG_R_URZ6T_PAT2_GEN_POS URZ6T_PAT2_GEN_POS; REG_R_URZ6T_PAT2_GEN_CURSOR_RB0 URZ6T_PAT2_GEN_CURSOR_RB0; REG_R_URZ6T_PAT2_GEN_CURSOR_RB1 URZ6T_PAT2_GEN_CURSOR_RB1; UINT32 rsv_3220; REG_R_URZ6T_PAT2_GEN_TILE_POS URZ6T_PAT2_GEN_TILE_POS; REG_R_URZ6T_PAT2_GEN_TILE_OV URZ6T_PAT2_GEN_TILE_OV; REG_R_URZ6T_RSZ_ETC_CONTROL URZ6T_RSZ_ETC_CONTROL; REG_R_URZ6T_RSZ_ETC_SWITCH_MAX_MIN_1 URZ6T_RSZ_ETC_SWITCH_MAX_MIN_1; REG_R_URZ6T_RSZ_ETC_SWITCH_MAX_MIN_2 URZ6T_RSZ_ETC_SWITCH_MAX_MIN_2; REG_R_URZ6T_RSZ_ETC_RING_CONTROL URZ6T_RSZ_ETC_RING_CONTROL; REG_R_URZ6T_RSZ_ETC_RING_CONTROL_GAINCONTROL_1 URZ6T_RSZ_ETC_RING_CONTROL_GAINCONTROL_1; REG_R_URZ6T_RSZ_ETC_RING_CONTROL_GAINCONTROL_2 URZ6T_RSZ_ETC_RING_CONTROL_GAINCONTROL_2; REG_R_URZ6T_RSZ_ETC_RING_CONTROL_GAINCONTROL_3 URZ6T_RSZ_ETC_RING_CONTROL_GAINCONTROL_3; REG_R_URZ6T_RSZ_ETC_SIMILARITY_PROTECTION_GAINCONTROL_1 URZ6T_RSZ_ETC_SIMILARITY_PROTECTION_GAINCONTROL_1; REG_R_URZ6T_RSZ_ETC_SIMILARITY_PROTECTION_GAINCONTROL_2 URZ6T_RSZ_ETC_SIMILARITY_PROTECTION_GAINCONTROL_2; REG_R_URZ6T_RSZ_ETC_SIMILARITY_PROTECTION_GAINCONTROL_3 URZ6T_RSZ_ETC_SIMILARITY_PROTECTION_GAINCONTROL_3; REG_R_URZ6T_RSZ_ETC_BLEND URZ6T_RSZ_ETC_BLEND; REG_R_URZ6T_RSZ_RESERVE URZ6T_RSZ_RESERVE; }; /** * Mediatek camera wb tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_wb { REG_R_WB_GAIN_1 WB_GAIN_1; REG_R_WB_GAIN_2 WB_GAIN_2; REG_R_WB_HLC WB_HLC; REG_R_WB_MULTI_EN WB_MULTI_EN; REG_R_WB_MULTI_MODE WB_MULTI_MODE; REG_R_WB_MULTI_GAIN0_1 WB_MULTI_GAIN0_1; REG_R_WB_MULTI_GAIN0_2 WB_MULTI_GAIN0_2; REG_R_WB_MULTI_GAIN1_1 WB_MULTI_GAIN1_1; REG_R_WB_MULTI_GAIN1_2 WB_MULTI_GAIN1_2; REG_R_WB_MULTI_GAIN2_1 WB_MULTI_GAIN2_1; REG_R_WB_MULTI_GAIN2_2 WB_MULTI_GAIN2_2; REG_R_WB_MULTI_GAIN3_1 WB_MULTI_GAIN3_1; REG_R_WB_MULTI_GAIN3_2 WB_MULTI_GAIN3_2; REG_R_WB_MULTI_GAIN4_1 WB_MULTI_GAIN4_1; REG_R_WB_MULTI_GAIN4_2 WB_MULTI_GAIN4_2; REG_R_WB_MULTI_GAIN5_1 WB_MULTI_GAIN5_1; REG_R_WB_MULTI_GAIN5_2 WB_MULTI_GAIN5_2; REG_R_WB_MULTI_NODE1 WB_MULTI_NODE1; REG_R_WB_MULTI_NODE2 WB_MULTI_NODE2; REG_R_WB_MULTI_NODE3 WB_MULTI_NODE3; REG_R_WB_MULTI_NODE4 WB_MULTI_NODE4; REG_R_WB_MULTI_SLOPE0_0 WB_MULTI_SLOPE0_0; REG_R_WB_MULTI_SLOPE0_1 WB_MULTI_SLOPE0_1; REG_R_WB_MULTI_SLOPE0_2 WB_MULTI_SLOPE0_2; REG_R_WB_MULTI_SLOPE0_3 WB_MULTI_SLOPE0_3; REG_R_WB_MULTI_SLOPE1_0 WB_MULTI_SLOPE1_0; REG_R_WB_MULTI_SLOPE1_1 WB_MULTI_SLOPE1_1; REG_R_WB_MULTI_SLOPE1_2 WB_MULTI_SLOPE1_2; REG_R_WB_MULTI_SLOPE1_3 WB_MULTI_SLOPE1_3; REG_R_WB_MULTI_SLOPE2_0 WB_MULTI_SLOPE2_0; REG_R_WB_MULTI_SLOPE2_1 WB_MULTI_SLOPE2_1; REG_R_WB_MULTI_SLOPE2_2 WB_MULTI_SLOPE2_2; REG_R_WB_MULTI_SLOPE2_3 WB_MULTI_SLOPE2_3; REG_R_WB_MULTI_SLOPE3_0 WB_MULTI_SLOPE3_0; REG_R_WB_MULTI_SLOPE3_1 WB_MULTI_SLOPE3_1; REG_R_WB_MULTI_SLOPE3_2 WB_MULTI_SLOPE3_2; REG_R_WB_MULTI_SLOPE3_3 WB_MULTI_SLOPE3_3; REG_R_WB_MULTI_SLOPE4_0 WB_MULTI_SLOPE4_0; REG_R_WB_MULTI_SLOPE4_1 WB_MULTI_SLOPE4_1; REG_R_WB_MULTI_SLOPE4_2 WB_MULTI_SLOPE4_2; REG_R_WB_MULTI_SLOPE4_3 WB_MULTI_SLOPE4_3; REG_R_WB_CTL WB_CTL; REG_R_WB_CTL2 WB_CTL2; }; /** * Mediatek camera wpe tuning setting * All the member of this structure are confidential */ struct mtk_img_uapi_regmap_raw_wpe { REG_R_WPE_START WPE_START; REG_R_CTL_MOD_EN CTL_MOD_EN; UINT32 rsv_0008[3]; REG_R_CTL_FMT CTL_FMT; UINT32 rsv_0018[4]; REG_R_CTL_TDR_TILE CTL_TDR_TILE; UINT32 rsv_002C[146]; REG_R_ROI_CTL ROI_CTL; REG_R_ROI_X ROI_X; REG_R_ROI_Y ROI_Y; UINT32 rsv_0280[146]; REG_R_VGEN_OUT_IMG VGEN_OUT_IMG; REG_R_VGEN_HORI_STEP VGEN_HORI_STEP; REG_R_VGEN_VERT_STEP VGEN_VERT_STEP; UINT32 rsv_04D4[9]; REG_R_V2M_STEP_W V2M_STEP_W; REG_R_V2M_STEP_H V2M_STEP_H; REG_R_V2M_RT V2M_RT; UINT32 rsv_0504[17]; REG_R_PSP_BORDER PSP_BORDER; REG_R_PSP_BORDER2 PSP_BORDER2; REG_R_PSP_OPT PSP_OPT; REG_R_PSP_COEF0 PSP_COEF0; REG_R_PSP_COEF2 PSP_COEF2; REG_R_PSP_COEF4 PSP_COEF4; REG_R_PSP_COEF6 PSP_COEF6; REG_R_PSP_COEF8 PSP_COEF8; REG_R_PSP_COEF10 PSP_COEF10; REG_R_PSP_COEF12 PSP_COEF12; REG_R_PSP_COEF14 PSP_COEF14; REG_R_PSP_COEF16 PSP_COEF16; REG_R_PSP_COEF18 PSP_COEF18; REG_R_PSP_COEF20 PSP_COEF20; REG_R_PSP_COEF22 PSP_COEF22; REG_R_PSP_COEF24 PSP_COEF24; REG_R_PSP_COEF26 PSP_COEF26; REG_R_PSP_COEF28 PSP_COEF28; REG_R_PSP_COEF30 PSP_COEF30; REG_R_PSP_COEF32 PSP_COEF32; REG_R_PSP_COEF34 PSP_COEF34; REG_R_PSP_COEF36 PSP_COEF36; REG_R_PSP_COEF38 PSP_COEF38; REG_R_PSP_COEF40 PSP_COEF40; REG_R_PSP_COEF42 PSP_COEF42; REG_R_PSP_COEF44 PSP_COEF44; REG_R_PSP_COEF46 PSP_COEF46; REG_R_PSP_COEF48 PSP_COEF48; REG_R_PSP_COEF50 PSP_COEF50; REG_R_PSP_COEF52 PSP_COEF52; REG_R_PSP_COEF54 PSP_COEF54; REG_R_PSP_COEF56 PSP_COEF56; REG_R_PSP_COEF58 PSP_COEF58; REG_R_PSP_COEF60 PSP_COEF60; REG_R_PSP_COEF62 PSP_COEF62; REG_R_PSP_COEF64 PSP_COEF64; }; /** * This regmap is for the following version * * MTK_IMG_META_VERSION_MAJOR: 2 * MTK_IMG_META_VERSION_MINOR: 0 * MTK_IMG_META_PLATFORM_NAME: isp71 * MTK_IMG_META_CHIP_NAME: mt8188 */ #endif /* HW_IMGSTREAM_INC_DRV_COMMON_7_1_MT8188_MTK_IMG_REG_USER_H_ */