/******************************************************************************* Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. *******************************************************************************/ /* AUTO GENERATED FILE -- DO NOT EDIT */ #ifndef __CLCBC0QMD_H__ #define __CLCBC0QMD_H__ /* ** Queue Meta Data, Version 03_00 */ #define NVCBC0_QMDV03_00_OUTER_PUT MW(30:0) #define NVCBC0_QMDV03_00_OUTER_OVERFLOW MW(31:31) #define NVCBC0_QMDV03_00_OUTER_GET MW(62:32) #define NVCBC0_QMDV03_00_OUTER_STICKY_OVERFLOW MW(63:63) #define NVCBC0_QMDV03_00_INNER_GET MW(94:64) #define NVCBC0_QMDV03_00_INNER_OVERFLOW MW(95:95) #define NVCBC0_QMDV03_00_INNER_PUT MW(126:96) #define NVCBC0_QMDV03_00_INNER_STICKY_OVERFLOW MW(127:127) #define NVCBC0_QMDV03_00_QMD_GROUP_ID MW(133:128) #define NVCBC0_QMDV03_00_SM_GLOBAL_CACHING_ENABLE MW(134:134) #define NVCBC0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) #define NVCBC0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 #define NVCBC0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 #define NVCBC0_QMDV03_00_IS_QUEUE MW(136:136) #define NVCBC0_QMDV03_00_IS_QUEUE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_IS_QUEUE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) #define NVCBC0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 #define NVCBC0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 #define NVCBC0_QMDV03_00_REQUIRE_SCHEDULING_PCAS MW(140:140) #define NVCBC0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 #define NVCBC0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 #define NVCBC0_QMDV03_00_DEPENDENCE_COUNTER MW(157:142) #define NVCBC0_QMDV03_00_SELF_COPY_ON_COMPLETION MW(158:158) #define NVCBC0_QMDV03_00_SELF_COPY_ON_COMPLETION_FALSE 0x00000000 #define NVCBC0_QMDV03_00_SELF_COPY_ON_COMPLETION_TRUE 0x00000001 #define NVCBC0_QMDV03_00_CIRCULAR_QUEUE_SIZE MW(184:160) #define NVCBC0_QMDV03_00_DEMOTE_L2_EVICT_LAST MW(185:185) #define NVCBC0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) #define NVCBC0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) #define NVCBC0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) #define NVCBC0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE MW(189:189) #define NVCBC0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE MW(190:190) #define NVCBC0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) #define NVCBC0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_CTA_RASTER_WIDTH_RESUME MW(223:192) #define NVCBC0_QMDV03_00_CTA_RASTER_HEIGHT_RESUME MW(239:224) #define NVCBC0_QMDV03_00_CTA_RASTER_DEPTH_RESUME MW(255:240) #define NVCBC0_QMDV03_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) #define NVCBC0_QMDV03_00_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) #define NVCBC0_QMDV03_00_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) #define NVCBC0_QMDV03_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) #define NVCBC0_QMDV03_00_CWD_REFERENCE_COUNT_ID MW(357:352) #define NVCBC0_QMDV03_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) #define NVCBC0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) #define NVCBC0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_CWD_MEMBAR_TYPE MW(369:368) #define NVCBC0_QMDV03_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 #define NVCBC0_QMDV03_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 #define NVCBC0_QMDV03_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 #define NVCBC0_QMDV03_00_SEQUENTIALLY_RUN_CTAS MW(370:370) #define NVCBC0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 #define NVCBC0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 #define NVCBC0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) #define NVCBC0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_API_VISIBLE_CALL_LIMIT MW(378:378) #define NVCBC0_QMDV03_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 #define NVCBC0_QMDV03_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 #define NVCBC0_QMDV03_00_SAMPLER_INDEX MW(382:382) #define NVCBC0_QMDV03_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 #define NVCBC0_QMDV03_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 #define NVCBC0_QMDV03_00_DISABLE_AUTO_INVALIDATE MW(383:383) #define NVCBC0_QMDV03_00_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_CTA_RASTER_WIDTH MW(415:384) #define NVCBC0_QMDV03_00_CTA_RASTER_HEIGHT MW(431:416) #define NVCBC0_QMDV03_00_CTA_RASTER_DEPTH MW(463:448) #define NVCBC0_QMDV03_00_DEPENDENT_QMD0_POINTER MW(511:480) #define NVCBC0_QMDV03_00_DEPENDENT_QMD0_ENABLE MW(512:512) #define NVCBC0_QMDV03_00_DEPENDENT_QMD0_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_DEPENDENT_QMD0_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_DEPENDENT_QMD0_ACTION MW(515:513) #define NVCBC0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT 0x00000000 #define NVCBC0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE 0x00000001 #define NVCBC0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 #define NVCBC0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 #define NVCBC0_QMDV03_00_DEPENDENT_QMD0_PREFETCH MW(516:516) #define NVCBC0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_FALSE 0x00000000 #define NVCBC0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_TRUE 0x00000001 #define NVCBC0_QMDV03_00_DEPENDENT_QMD1_ENABLE MW(517:517) #define NVCBC0_QMDV03_00_DEPENDENT_QMD1_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_DEPENDENT_QMD1_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_DEPENDENT_QMD1_ACTION MW(520:518) #define NVCBC0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT 0x00000000 #define NVCBC0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE 0x00000001 #define NVCBC0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 #define NVCBC0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 #define NVCBC0_QMDV03_00_DEPENDENT_QMD1_PREFETCH MW(521:521) #define NVCBC0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_FALSE 0x00000000 #define NVCBC0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_TRUE 0x00000001 #define NVCBC0_QMDV03_00_COALESCE_WAITING_PERIOD MW(529:522) #define NVCBC0_QMDV03_00_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) #define NVCBC0_QMDV03_00_OCCUPANCY_THRESHOLD_SHARED_MEM MW(542:535) #define NVCBC0_QMDV03_00_CTA_LAUNCH_QUEUE MW(543:543) #define NVCBC0_QMDV03_00_SHARED_MEMORY_SIZE MW(561:544) #define NVCBC0_QMDV03_00_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(567:562) #define NVCBC0_QMDV03_00_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(574:569) #define NVCBC0_QMDV03_00_QMD_VERSION MW(579:576) #define NVCBC0_QMDV03_00_QMD_MAJOR_VERSION MW(583:580) #define NVCBC0_QMDV03_00_OCCUPANCY_MAX_SHARED_MEM MW(591:584) #define NVCBC0_QMDV03_00_CTA_THREAD_DIMENSION0 MW(607:592) #define NVCBC0_QMDV03_00_CTA_THREAD_DIMENSION1 MW(623:608) #define NVCBC0_QMDV03_00_CTA_THREAD_DIMENSION2 MW(639:624) #define NVCBC0_QMDV03_00_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) #define NVCBC0_QMDV03_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 #define NVCBC0_QMDV03_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 #define NVCBC0_QMDV03_00_REGISTER_COUNT_V MW(656:648) #define NVCBC0_QMDV03_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(662:657) #define NVCBC0_QMDV03_00_SHARED_ALLOCATION_ENABLE MW(663:663) #define NVCBC0_QMDV03_00_SHARED_ALLOCATION_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_SHARED_ALLOCATION_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) #define NVCBC0_QMDV03_00_SM_DISABLE_MASK_LOWER MW(703:672) #define NVCBC0_QMDV03_00_SM_DISABLE_MASK_UPPER MW(735:704) #define NVCBC0_QMDV03_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(759:736) #define NVCBC0_QMDV03_00_BARRIER_COUNT MW(767:763) #define NVCBC0_QMDV03_00_RELEASE0_ADDRESS_LOWER MW(799:768) #define NVCBC0_QMDV03_00_RELEASE0_ADDRESS_UPPER MW(807:800) #define NVCBC0_QMDV03_00_RELEASE0_MEMBAR_TYPE MW(819:819) #define NVCBC0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_NONE 0x00000000 #define NVCBC0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 #define NVCBC0_QMDV03_00_RELEASE0_REDUCTION_OP MW(822:820) #define NVCBC0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 #define NVCBC0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 #define NVCBC0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 #define NVCBC0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 #define NVCBC0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 #define NVCBC0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 #define NVCBC0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 #define NVCBC0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 #define NVCBC0_QMDV03_00_RELEASE0_ENABLE MW(823:823) #define NVCBC0_QMDV03_00_RELEASE0_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_RELEASE0_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_RELEASE0_REDUCTION_FORMAT MW(825:824) #define NVCBC0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED 0x00000000 #define NVCBC0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_SIGNED 0x00000001 #define NVCBC0_QMDV03_00_RELEASE0_REDUCTION_ENABLE MW(826:826) #define NVCBC0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_RELEASE0_TRAP_TYPE MW(828:827) #define NVCBC0_QMDV03_00_RELEASE0_TRAP_TYPE_TRAP_NONE 0x00000000 #define NVCBC0_QMDV03_00_RELEASE0_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 #define NVCBC0_QMDV03_00_RELEASE0_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 #define NVCBC0_QMDV03_00_RELEASE0_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 #define NVCBC0_QMDV03_00_RELEASE0_PAYLOAD64B MW(829:829) #define NVCBC0_QMDV03_00_RELEASE0_PAYLOAD64B_FALSE 0x00000000 #define NVCBC0_QMDV03_00_RELEASE0_PAYLOAD64B_TRUE 0x00000001 #define NVCBC0_QMDV03_00_RELEASE0_STRUCTURE_SIZE MW(831:830) #define NVCBC0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 #define NVCBC0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 #define NVCBC0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 #define NVCBC0_QMDV03_00_RELEASE0_PAYLOAD_LOWER MW(863:832) #define NVCBC0_QMDV03_00_RELEASE0_PAYLOAD_UPPER MW(895:864) #define NVCBC0_QMDV03_00_RELEASE1_ADDRESS_LOWER MW(927:896) #define NVCBC0_QMDV03_00_RELEASE1_ADDRESS_UPPER MW(935:928) #define NVCBC0_QMDV03_00_RELEASE1_MEMBAR_TYPE MW(947:947) #define NVCBC0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_NONE 0x00000000 #define NVCBC0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 #define NVCBC0_QMDV03_00_RELEASE1_REDUCTION_OP MW(950:948) #define NVCBC0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 #define NVCBC0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 #define NVCBC0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 #define NVCBC0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 #define NVCBC0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 #define NVCBC0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 #define NVCBC0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 #define NVCBC0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 #define NVCBC0_QMDV03_00_RELEASE1_ENABLE MW(951:951) #define NVCBC0_QMDV03_00_RELEASE1_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_RELEASE1_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_RELEASE1_REDUCTION_FORMAT MW(953:952) #define NVCBC0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED 0x00000000 #define NVCBC0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_SIGNED 0x00000001 #define NVCBC0_QMDV03_00_RELEASE1_REDUCTION_ENABLE MW(954:954) #define NVCBC0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_RELEASE1_TRAP_TYPE MW(956:955) #define NVCBC0_QMDV03_00_RELEASE1_TRAP_TYPE_TRAP_NONE 0x00000000 #define NVCBC0_QMDV03_00_RELEASE1_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 #define NVCBC0_QMDV03_00_RELEASE1_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 #define NVCBC0_QMDV03_00_RELEASE1_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 #define NVCBC0_QMDV03_00_RELEASE1_PAYLOAD64B MW(957:957) #define NVCBC0_QMDV03_00_RELEASE1_PAYLOAD64B_FALSE 0x00000000 #define NVCBC0_QMDV03_00_RELEASE1_PAYLOAD64B_TRUE 0x00000001 #define NVCBC0_QMDV03_00_RELEASE1_STRUCTURE_SIZE MW(959:958) #define NVCBC0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 #define NVCBC0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 #define NVCBC0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 #define NVCBC0_QMDV03_00_RELEASE1_PAYLOAD_LOWER MW(991:960) #define NVCBC0_QMDV03_00_RELEASE1_PAYLOAD_UPPER MW(1023:992) #define NVCBC0_QMDV03_00_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) #define NVCBC0_QMDV03_00_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) #define NVCBC0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64)) #define NVCBC0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000 #define NVCBC0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001 #define NVCBC0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) #define NVCBC0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) #define NVCBC0_QMDV03_00_PROGRAM_ADDRESS_LOWER MW(1567:1536) #define NVCBC0_QMDV03_00_PROGRAM_ADDRESS_UPPER MW(1584:1568) #define NVCBC0_QMDV03_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1623:1600) #define NVCBC0_QMDV03_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1640:1632) #define NVCBC0_QMDV03_00_PROGRAM_PREFETCH_SIZE MW(1649:1641) #define NVCBC0_QMDV03_00_PROGRAM_PREFETCH_TYPE MW(1651:1650) #define NVCBC0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000 #define NVCBC0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001 #define NVCBC0_QMDV03_00_SASS_VERSION MW(1663:1656) #define NVCBC0_QMDV03_00_RELEASE2_ADDRESS_LOWER MW(1695:1664) #define NVCBC0_QMDV03_00_RELEASE2_ADDRESS_UPPER MW(1703:1696) #define NVCBC0_QMDV03_00_RELEASE2_MEMBAR_TYPE MW(1715:1715) #define NVCBC0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_NONE 0x00000000 #define NVCBC0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 #define NVCBC0_QMDV03_00_RELEASE2_REDUCTION_OP MW(1718:1716) #define NVCBC0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_ADD 0x00000000 #define NVCBC0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MIN 0x00000001 #define NVCBC0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MAX 0x00000002 #define NVCBC0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_INC 0x00000003 #define NVCBC0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_DEC 0x00000004 #define NVCBC0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_AND 0x00000005 #define NVCBC0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_OR 0x00000006 #define NVCBC0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_XOR 0x00000007 #define NVCBC0_QMDV03_00_RELEASE2_ENABLE MW(1719:1719) #define NVCBC0_QMDV03_00_RELEASE2_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_RELEASE2_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_RELEASE2_REDUCTION_FORMAT MW(1721:1720) #define NVCBC0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_UNSIGNED 0x00000000 #define NVCBC0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_SIGNED 0x00000001 #define NVCBC0_QMDV03_00_RELEASE2_REDUCTION_ENABLE MW(1722:1722) #define NVCBC0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV03_00_RELEASE2_TRAP_TYPE MW(1724:1723) #define NVCBC0_QMDV03_00_RELEASE2_TRAP_TYPE_TRAP_NONE 0x00000000 #define NVCBC0_QMDV03_00_RELEASE2_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 #define NVCBC0_QMDV03_00_RELEASE2_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 #define NVCBC0_QMDV03_00_RELEASE2_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 #define NVCBC0_QMDV03_00_RELEASE2_PAYLOAD64B MW(1725:1725) #define NVCBC0_QMDV03_00_RELEASE2_PAYLOAD64B_FALSE 0x00000000 #define NVCBC0_QMDV03_00_RELEASE2_PAYLOAD64B_TRUE 0x00000001 #define NVCBC0_QMDV03_00_RELEASE2_STRUCTURE_SIZE MW(1727:1726) #define NVCBC0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 #define NVCBC0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 #define NVCBC0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 #define NVCBC0_QMDV03_00_RELEASE2_PAYLOAD_LOWER MW(1759:1728) #define NVCBC0_QMDV03_00_RELEASE2_PAYLOAD_UPPER MW(1791:1760) #define NVCBC0_QMDV03_00_OCCUPANCY_THRESHOLD_WARP MW(1799:1792) #define NVCBC0_QMDV03_00_OCCUPANCY_MAX_WARP MW(1807:1800) #define NVCBC0_QMDV03_00_OCCUPANCY_THRESHOLD_REGISTER MW(1815:1808) #define NVCBC0_QMDV03_00_OCCUPANCY_MAX_REGISTER MW(1823:1816) #define NVCBC0_QMDV03_00_HW_ONLY_INNER_GET MW(1854:1824) #define NVCBC0_QMDV03_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1855:1855) #define NVCBC0_QMDV03_00_HW_ONLY_INNER_PUT MW(1886:1856) #define NVCBC0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1917:1888) #define NVCBC0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1919:1919) #define NVCBC0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 #define NVCBC0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 #define NVCBC0_QMDV03_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1951:1920) #define NVCBC0_QMDV03_00_HW_ONLY_DEPENDENCE_COUNTER MW(1967:1952) #define NVCBC0_QMDV03_00_DEBUG_ID_UPPER MW(2015:1984) #define NVCBC0_QMDV03_00_DEBUG_ID_LOWER MW(2047:2016) /* ** Queue Meta Data, Version 04_00 */ #define NVCBC0_QMDV04_00_DEPENDENCE_COUNTER MW(15:0) #define NVCBC0_QMDV04_00_QMD_GROUP_ID MW(21:16) #define NVCBC0_QMDV04_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(22:22) #define NVCBC0_QMDV04_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 #define NVCBC0_QMDV04_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 #define NVCBC0_QMDV04_00_QMD_TYPE MW(25:23) #define NVCBC0_QMDV04_00_QMD_TYPE_QUEUE 0x00000000 #define NVCBC0_QMDV04_00_QMD_TYPE_GRID_NULL 0x00000001 #define NVCBC0_QMDV04_00_QMD_TYPE_GRID_CTA 0x00000002 #define NVCBC0_QMDV04_00_QMD_TYPE_GRID_GPC_CGA 0x00000003 #define NVCBC0_QMDV04_00_QMD_TYPE_GRID_GPU_CGA 0x00000004 #define NVCBC0_QMDV04_00_QMD_TYPE_GRID_GPU_GPC_CGA 0x00000005 #define NVCBC0_QMDV04_00_ARRIVE_AT_LATCH_VALID MW(28:28) #define NVCBC0_QMDV04_00_WAIT_ON_LATCH_VALID MW(29:29) #define NVCBC0_QMDV04_00_REQUIRE_SCHEDULING_PCAS MW(30:30) #define NVCBC0_QMDV04_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 #define NVCBC0_QMDV04_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 #define NVCBC0_QMDV04_00_TPC_DISABLE_MASK_VALID MW(31:31) #define NVCBC0_QMDV04_00_TPC_DISABLE_MASK_VALID_FALSE 0x00000000 #define NVCBC0_QMDV04_00_TPC_DISABLE_MASK_VALID_TRUE 0x00000001 #define NVCBC0_QMDV04_00_CIRCULAR_QUEUE_SIZE MW(56:32) #define NVCBC0_QMDV04_00_INNER_GET MW(94:64) #define NVCBC0_QMDV04_00_INNER_OVERFLOW MW(95:95) #define NVCBC0_QMDV04_00_INNER_PUT MW(126:96) #define NVCBC0_QMDV04_00_INNER_STICKY_OVERFLOW MW(127:127) #define NVCBC0_QMDV04_00_HW_ONLY_INNER_GET MW(190:160) #define NVCBC0_QMDV04_00_HW_ONLY_INNER_PUT MW(222:192) #define NVCBC0_QMDV04_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(253:224) #define NVCBC0_QMDV04_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(254:254) #define NVCBC0_QMDV04_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 #define NVCBC0_QMDV04_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 #define NVCBC0_QMDV04_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(287:256) #define NVCBC0_QMDV04_00_HW_ONLY_DEPENDENCE_COUNTER MW(303:288) #define NVCBC0_QMDV04_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(304:304) #define NVCBC0_QMDV04_00_RELEASE_ENABLE(i) MW((320+(i)*16):(320+(i)*16)) #define NVCBC0_QMDV04_00_RELEASE_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_RELEASE_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_RELEASE_STRUCTURE_SIZE(i) MW((322+(i)*16):(321+(i)*16)) #define NVCBC0_QMDV04_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 #define NVCBC0_QMDV04_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 #define NVCBC0_QMDV04_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 #define NVCBC0_QMDV04_00_RELEASE_MEMBAR_TYPE(i) MW((323+(i)*16):(323+(i)*16)) #define NVCBC0_QMDV04_00_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 #define NVCBC0_QMDV04_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 #define NVCBC0_QMDV04_00_RELEASE_REDUCTION_ENABLE(i) MW((324+(i)*16):(324+(i)*16)) #define NVCBC0_QMDV04_00_RELEASE_REDUCTION_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_RELEASE_REDUCTION_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_RELEASE_REDUCTION_OP(i) MW((327+(i)*16):(325+(i)*16)) #define NVCBC0_QMDV04_00_RELEASE_REDUCTION_OP_RED_ADD 0x00000000 #define NVCBC0_QMDV04_00_RELEASE_REDUCTION_OP_RED_MIN 0x00000001 #define NVCBC0_QMDV04_00_RELEASE_REDUCTION_OP_RED_MAX 0x00000002 #define NVCBC0_QMDV04_00_RELEASE_REDUCTION_OP_RED_INC 0x00000003 #define NVCBC0_QMDV04_00_RELEASE_REDUCTION_OP_RED_DEC 0x00000004 #define NVCBC0_QMDV04_00_RELEASE_REDUCTION_OP_RED_AND 0x00000005 #define NVCBC0_QMDV04_00_RELEASE_REDUCTION_OP_RED_OR 0x00000006 #define NVCBC0_QMDV04_00_RELEASE_REDUCTION_OP_RED_XOR 0x00000007 #define NVCBC0_QMDV04_00_RELEASE_REDUCTION_FORMAT(i) MW((329+(i)*16):(328+(i)*16)) #define NVCBC0_QMDV04_00_RELEASE_REDUCTION_FORMAT_UNSIGNED 0x00000000 #define NVCBC0_QMDV04_00_RELEASE_REDUCTION_FORMAT_SIGNED 0x00000001 #define NVCBC0_QMDV04_00_RELEASE_TRAP_TYPE(i) MW((331+(i)*16):(330+(i)*16)) #define NVCBC0_QMDV04_00_RELEASE_TRAP_TYPE_TRAP_NONE 0x00000000 #define NVCBC0_QMDV04_00_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 #define NVCBC0_QMDV04_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 #define NVCBC0_QMDV04_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 #define NVCBC0_QMDV04_00_RELEASE_PAYLOAD64B(i) MW((332+(i)*16):(332+(i)*16)) #define NVCBC0_QMDV04_00_RELEASE_PAYLOAD64B_FALSE 0x00000000 #define NVCBC0_QMDV04_00_RELEASE_PAYLOAD64B_TRUE 0x00000001 #define NVCBC0_QMDV04_00_RELEASE_RESERVED_INFO(i) MW((335+(i)*16):(333+(i)*16)) #define NVCBC0_QMDV04_00_DEPENDENT_QMD_ENABLE(i) MW((368+(i)*5):(368+(i)*5)) #define NVCBC0_QMDV04_00_DEPENDENT_QMD_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_DEPENDENT_QMD_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_DEPENDENT_QMD_ACTION(i) MW((371+(i)*5):(369+(i)*5)) #define NVCBC0_QMDV04_00_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT 0x00000000 #define NVCBC0_QMDV04_00_DEPENDENT_QMD_ACTION_QMD_SCHEDULE 0x00000001 #define NVCBC0_QMDV04_00_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 #define NVCBC0_QMDV04_00_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 #define NVCBC0_QMDV04_00_DEPENDENT_QMD_PREFETCH(i) MW((372+(i)*5):(372+(i)*5)) #define NVCBC0_QMDV04_00_DEPENDENT_QMD_PREFETCH_FALSE 0x00000000 #define NVCBC0_QMDV04_00_DEPENDENT_QMD_PREFETCH_TRUE 0x00000001 #define NVCBC0_QMDV04_00_SELF_COPY_ON_COMPLETION MW(378:378) #define NVCBC0_QMDV04_00_SELF_COPY_ON_COMPLETION_FALSE 0x00000000 #define NVCBC0_QMDV04_00_SELF_COPY_ON_COMPLETION_TRUE 0x00000001 #define NVCBC0_QMDV04_00_DEMOTE_L2_EVICT_LAST MW(379:379) #define NVCBC0_QMDV04_00_DEMOTE_L2_EVICT_LAST_FALSE 0x00000000 #define NVCBC0_QMDV04_00_DEMOTE_L2_EVICT_LAST_TRUE 0x00000001 #define NVCBC0_QMDV04_00_DISABLE_AUTO_INVALIDATE MW(380:380) #define NVCBC0_QMDV04_00_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_CORRELATION_ID_INTERNAL MW(381:381) #define NVCBC0_QMDV04_00_CORRELATION_ID_INTERNAL_FALSE 0x00000000 #define NVCBC0_QMDV04_00_CORRELATION_ID_INTERNAL_TRUE 0x00000001 #define NVCBC0_QMDV04_00_CWD_MEMBAR_TASK_CHASING_ENABLE MW(382:382) #define NVCBC0_QMDV04_00_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_CORRELATION_ID MW(415:384) #define NVCBC0_QMDV04_00_CONSTANT_BUFFER_VALID(i) MW((416+(i)*4):(416+(i)*4)) #define NVCBC0_QMDV04_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 #define NVCBC0_QMDV04_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 #define NVCBC0_QMDV04_00_CONSTANT_BUFFER_PREFETCH(i) MW((418+(i)*4):(417+(i)*4)) #define NVCBC0_QMDV04_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE 0x00000000 #define NVCBC0_QMDV04_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE 0x00000001 #define NVCBC0_QMDV04_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST 0x00000002 #define NVCBC0_QMDV04_00_CONSTANT_BUFFER_INVALIDATE(i) MW((419+(i)*4):(419+(i)*4)) #define NVCBC0_QMDV04_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_DEPENDENT_QMD0_POINTER MW(479:448) #define NVCBC0_QMDV04_00_DEPENDENT_QMD1_POINTER MW(511:480) #define NVCBC0_QMDV04_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(535:512) #define NVCBC0_QMDV04_00_SASS_VERSION MW(543:536) #define NVCBC0_QMDV04_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(567:544) #define NVCBC0_QMDV04_00_API_VISIBLE_CALL_LIMIT MW(568:568) #define NVCBC0_QMDV04_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 #define NVCBC0_QMDV04_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 #define NVCBC0_QMDV04_00_SAMPLER_INDEX MW(569:569) #define NVCBC0_QMDV04_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 #define NVCBC0_QMDV04_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 #define NVCBC0_QMDV04_00_CONSTANT_BUFFER_PREFETCH_PRE_MAX_SIZE_SHIFTED8 MW(575:570) #define NVCBC0_QMDV04_00_QMD_MINOR_VERSION MW(579:576) #define NVCBC0_QMDV04_00_QMD_MAJOR_VERSION MW(583:580) #define NVCBC0_QMDV04_00_SHARED_MEMORY_SIZE MW(601:584) #define NVCBC0_QMDV04_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(602:602) #define NVCBC0_QMDV04_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(603:603) #define NVCBC0_QMDV04_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_INVALIDATE_TEXTURE_DATA_CACHE MW(604:604) #define NVCBC0_QMDV04_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_INVALIDATE_SHADER_DATA_CACHE MW(605:605) #define NVCBC0_QMDV04_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_INVALIDATE_INSTRUCTION_CACHE MW(606:606) #define NVCBC0_QMDV04_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(607:607) #define NVCBC0_QMDV04_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(613:608) #define NVCBC0_QMDV04_00_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(619:614) #define NVCBC0_QMDV04_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(625:620) #define NVCBC0_QMDV04_00_SHARED_ALLOCATION_ENABLE MW(626:626) #define NVCBC0_QMDV04_00_SHARED_ALLOCATION_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_SHARED_ALLOCATION_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_RELEASE_SEMAPHORE0_ADDR_LOWER MW(671:640) #define NVCBC0_QMDV04_00_RELEASE_SEMAPHORE0_ADDR_UPPER MW(696:672) #define NVCBC0_QMDV04_00_RELEASE_SEMAPHORE0_PAYLOAD_LOWER MW(735:704) #define NVCBC0_QMDV04_00_RELEASE_SEMAPHORE0_PAYLOAD_UPPER MW(767:736) #define NVCBC0_QMDV04_00_RELEASE_SEMAPHORE1_ADDR_LOWER MW(799:768) #define NVCBC0_QMDV04_00_RELEASE_SEMAPHORE1_ADDR_UPPER MW(824:800) #define NVCBC0_QMDV04_00_RELEASE_SEMAPHORE1_PAYLOAD_LOWER MW(863:832) #define NVCBC0_QMDV04_00_RELEASE_SEMAPHORE1_PAYLOAD_UPPER MW(895:864) #define NVCBC0_QMDV04_00_RELEASE_SEMAPHORE2_ADDR_LOWER MW(927:896) #define NVCBC0_QMDV04_00_RELEASE_SEMAPHORE2_ADDR_UPPER MW(952:928) #define NVCBC0_QMDV04_00_RELEASE_SEMAPHORE2_PAYLOAD_LOWER MW(991:960) #define NVCBC0_QMDV04_00_RELEASE_SEMAPHORE2_PAYLOAD_UPPER MW(1023:992) #define NVCBC0_QMDV04_00_GRID_WIDTH MW(1055:1024) #define NVCBC0_QMDV04_00_GRID_HEIGHT MW(1071:1056) #define NVCBC0_QMDV04_00_GRID_DEPTH MW(1103:1088) #define NVCBC0_QMDV04_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(1127:1120) #define NVCBC0_QMDV04_00_CWD_REFERENCE_COUNT_ID MW(1133:1128) #define NVCBC0_QMDV04_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(1134:1134) #define NVCBC0_QMDV04_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(1135:1135) #define NVCBC0_QMDV04_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_CWD_MEMBAR_TYPE MW(1137:1136) #define NVCBC0_QMDV04_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 #define NVCBC0_QMDV04_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 #define NVCBC0_QMDV04_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 #define NVCBC0_QMDV04_00_SEQUENTIALLY_RUN_CTAS MW(1138:1138) #define NVCBC0_QMDV04_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 #define NVCBC0_QMDV04_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 #define NVCBC0_QMDV04_00_CTA_LAUNCH_QUEUE MW(1139:1139) #define NVCBC0_QMDV04_00_FREE_CTA_SLOTS_EMPTY_SM MW(1147:1140) #define NVCBC0_QMDV04_00_SYNC_DOMAIN_ID MW(1149:1148) #define NVCBC0_QMDV04_00_PRE_EXIT_AT_LAST_CTA_LAUNCH MW(1150:1150) #define NVCBC0_QMDV04_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE 0x00000000 #define NVCBC0_QMDV04_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE 0x00000001 #define NVCBC0_QMDV04_00_ENABLE_PROGRAM_PRE_EXIT MW(1151:1151) #define NVCBC0_QMDV04_00_ENABLE_PROGRAM_PRE_EXIT_FALSE 0x00000000 #define NVCBC0_QMDV04_00_ENABLE_PROGRAM_PRE_EXIT_TRUE 0x00000001 #define NVCBC0_QMDV04_00_CTA_THREAD_DIMENSION0 MW(1167:1152) #define NVCBC0_QMDV04_00_CTA_THREAD_DIMENSION1 MW(1183:1168) #define NVCBC0_QMDV04_00_CTA_THREAD_DIMENSION2 MW(1199:1184) #define NVCBC0_QMDV04_00_REGISTER_COUNT MW(1208:1200) #define NVCBC0_QMDV04_00_BARRIER_COUNT MW(1215:1211) #define NVCBC0_QMDV04_00_PROGRAM_ADDRESS_LOWER MW(1247:1216) #define NVCBC0_QMDV04_00_PROGRAM_ADDRESS_UPPER MW(1272:1248) #define NVCBC0_QMDV04_00_OCCUPANCY_THRESHOLD_WARP MW(1287:1280) #define NVCBC0_QMDV04_00_OCCUPANCY_MAX_WARP MW(1295:1288) #define NVCBC0_QMDV04_00_OCCUPANCY_THRESHOLD_REGISTER MW(1303:1296) #define NVCBC0_QMDV04_00_OCCUPANCY_MAX_REGISTER MW(1311:1304) #define NVCBC0_QMDV04_00_OCCUPANCY_THRESHOLD_SHARED_MEM MW(1319:1312) #define NVCBC0_QMDV04_00_OCCUPANCY_MAX_SHARED_MEM MW(1327:1320) #define NVCBC0_QMDV04_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(1375:1344) #define NVCBC0_QMDV04_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1392:1376) #define NVCBC0_QMDV04_00_PROGRAM_PREFETCH_SIZE MW(1401:1393) #define NVCBC0_QMDV04_00_PROGRAM_PREFETCH_TYPE MW(1403:1402) #define NVCBC0_QMDV04_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000 #define NVCBC0_QMDV04_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001 #define NVCBC0_QMDV04_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE MW(1406:1406) #define NVCBC0_QMDV04_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE MW(1407:1407) #define NVCBC0_QMDV04_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 #define NVCBC0_QMDV04_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 #define NVCBC0_QMDV04_00_GRID_WIDTH_RESUME MW(1439:1408) #define NVCBC0_QMDV04_00_GRID_HEIGHT_RESUME MW(1455:1440) #define NVCBC0_QMDV04_00_GRID_DEPTH_RESUME MW(1471:1456) #define NVCBC0_QMDV04_00_ARRIVE_AT_LATCH_ID MW(1503:1472) #define NVCBC0_QMDV04_00_WAIT_ON_LATCH_ID MW(1535:1504) #define NVCBC0_QMDV04_00_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6(i) MW((1567+(i)*64):(1536+(i)*64)) #define NVCBC0_QMDV04_00_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6(i) MW((1586+(i)*64):(1568+(i)*64)) #define NVCBC0_QMDV04_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1599+(i)*64):(1587+(i)*64)) #define NVCBC0_QMDV04_00_CIRCULAR_QUEUE_ADDR_LOWER MW(2079:2048) #define NVCBC0_QMDV04_00_CIRCULAR_QUEUE_ADDR_UPPER MW(2087:2080) #define NVCBC0_QMDV04_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(2127:2112) #define NVCBC0_QMDV04_00_COALESCE_WAITING_PERIOD MW(2135:2128) #define NVCBC0_QMDV04_00_QUEUE_ENTRIES_PER_CTA_LOG2 MW(2140:2136) #define NVCBC0_QMDV04_00_GPC_CGA_WIDTH MW(2149:2144) #define NVCBC0_QMDV04_00_GPC_CGA_HEIGHT MW(2157:2152) #define NVCBC0_QMDV04_00_GPC_CGA_DEPTH MW(2165:2160) #define NVCBC0_QMDV04_00_CGA_CTA_DISTRIBUTION_MODE MW(2207:2207) #define NVCBC0_QMDV04_00_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING 0x00000000 #define NVCBC0_QMDV04_00_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST 0x00000001 #define NVCBC0_QMDV04_00_GPU_CGA_WIDTH MW(2223:2208) #define NVCBC0_QMDV04_00_GPU_CGA_HEIGHT MW(2239:2224) #define NVCBC0_QMDV04_00_GPU_CGA_DEPTH MW(2255:2240) #define NVCBC0_QMDV04_00_DEBUG_ID_LOWER MW(2399:2368) #define NVCBC0_QMDV04_00_DEBUG_ID_UPPER MW(2431:2400) #define NVCBC0_QMDV04_00_TPC_DISABLE_MASK(i) MW((2463+(i)*32):(2432+(i)*32)) #define NVCBC0_QMDV04_00_OUTER_PUT MW(3038:3008) #define NVCBC0_QMDV04_00_OUTER_OVERFLOW MW(3039:3039) #define NVCBC0_QMDV04_00_OUTER_GET MW(3070:3040) #define NVCBC0_QMDV04_00_OUTER_STICKY_OVERFLOW MW(3071:3071) #endif // #ifndef __CLCBC0QMD_H__