/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Global Instruction Selector for the AArch64 target *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_GLOBALISEL_PREDICATE_BITSET const unsigned MAX_SUBTARGET_PREDICATES = 57; using PredicateBitset = llvm::PredicateBitsetImpl; #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET #ifdef GET_GLOBALISEL_TEMPORARIES_DECL mutable MatcherState State; typedef ComplexRendererFns(AArch64InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; typedef void(AArch64InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; const ISelInfoTy ISelInfo; static AArch64InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; static AArch64InstructionSelector::CustomRendererFn CustomRenderers[]; bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; const int64_t *getMatchTable() const override; bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const std::array &Operands) const override; #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL #ifdef GET_GLOBALISEL_TEMPORARIES_INIT , State(1), ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT #ifdef GET_GLOBALISEL_IMPL // Bits for subtarget features that participate in instruction matching. enum SubtargetFeatureBits : uint8_t { Feature_HasPAuthBit = 7, Feature_HasJSBit = 9, Feature_HasComplxNumBit = 44, Feature_HasFPARMv8Bit = 8, Feature_HasNEONBit = 3, Feature_HasSM4Bit = 43, Feature_HasSHA3Bit = 42, Feature_HasSHA2Bit = 18, Feature_HasAESBit = 17, Feature_HasDotProdBit = 1, Feature_HasCRCBit = 11, Feature_HasCSSCBit = 19, Feature_HasNoCSSCBit = 39, Feature_HasLSEBit = 40, Feature_HasNoLSEBit = 38, Feature_HasRDMBit = 16, Feature_HasFullFP16Bit = 14, Feature_HasFP16FMLBit = 6, Feature_HasFuseAESBit = 51, Feature_HasSVEBit = 20, Feature_HasSVE2Bit = 21, Feature_HasSVE2AESBit = 28, Feature_HasSVE2SM4Bit = 29, Feature_HasSVE2SHA3Bit = 30, Feature_HasSVE2BitPermBit = 31, Feature_HasSMEBit = 34, Feature_HasSMEF64F64Bit = 36, Feature_HasSMEI16I64Bit = 35, Feature_HasSME2Bit = 37, Feature_HasSVEorSMEBit = 0, Feature_HasSVE2orSMEBit = 27, Feature_HasSVE2p1_or_HasSMEBit = 32, Feature_HasSVE2p1_or_HasSME2Bit = 33, Feature_HasNEONorSMEBit = 4, Feature_HasRCPCBit = 56, Feature_HasFRInt3264Bit = 15, Feature_HasMTEBit = 12, Feature_HasTMEBit = 10, Feature_HasBF16Bit = 2, Feature_HasMatMulInt8Bit = 5, Feature_HasMatMulFP32Bit = 41, Feature_HasMatMulFP64Bit = 26, Feature_HasLS64Bit = 55, Feature_HasHBCBit = 13, Feature_IsLEBit = 24, Feature_IsBEBit = 52, Feature_UseExperimentalZeroingPseudosBit = 22, Feature_UseAlternateSExtLoadCVTF32Bit = 50, Feature_UseScalarIncVLBit = 23, Feature_NotInStreamingSVEModeBit = 25, Feature_NotForCodeSizeBit = 49, Feature_UseSTRQroBit = 48, Feature_UseBTIBit = 54, Feature_NotUseBTIBit = 53, Feature_SLSBLRMitigationBit = 47, Feature_NoSLSBLRMitigationBit = 46, Feature_OptimizedGISelOrOtherSelectorBit = 45, }; PredicateBitset AArch64InstructionSelector:: computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const { PredicateBitset Features; if (Subtarget->hasPAuth()) Features.set(Feature_HasPAuthBit); if (Subtarget->hasJS()) Features.set(Feature_HasJSBit); if (Subtarget->hasComplxNum()) Features.set(Feature_HasComplxNumBit); if (Subtarget->hasFPARMv8()) Features.set(Feature_HasFPARMv8Bit); if (Subtarget->hasNEON()) Features.set(Feature_HasNEONBit); if (Subtarget->hasSM4()) Features.set(Feature_HasSM4Bit); if (Subtarget->hasSHA3()) Features.set(Feature_HasSHA3Bit); if (Subtarget->hasSHA2()) Features.set(Feature_HasSHA2Bit); if (Subtarget->hasAES()) Features.set(Feature_HasAESBit); if (Subtarget->hasDotProd()) Features.set(Feature_HasDotProdBit); if (Subtarget->hasCRC()) Features.set(Feature_HasCRCBit); if (Subtarget->hasCSSC()) Features.set(Feature_HasCSSCBit); if (!Subtarget->hasCSSC()) Features.set(Feature_HasNoCSSCBit); if (Subtarget->hasLSE()) Features.set(Feature_HasLSEBit); if (!Subtarget->hasLSE()) Features.set(Feature_HasNoLSEBit); if (Subtarget->hasRDM()) Features.set(Feature_HasRDMBit); if (Subtarget->hasFullFP16()) Features.set(Feature_HasFullFP16Bit); if (Subtarget->hasFP16FML()) Features.set(Feature_HasFP16FMLBit); if (Subtarget->hasFuseAES()) Features.set(Feature_HasFuseAESBit); if (Subtarget->hasSVE()) Features.set(Feature_HasSVEBit); if (Subtarget->hasSVE2()) Features.set(Feature_HasSVE2Bit); if (Subtarget->hasSVE2AES()) Features.set(Feature_HasSVE2AESBit); if (Subtarget->hasSVE2SM4()) Features.set(Feature_HasSVE2SM4Bit); if (Subtarget->hasSVE2SHA3()) Features.set(Feature_HasSVE2SHA3Bit); if (Subtarget->hasSVE2BitPerm()) Features.set(Feature_HasSVE2BitPermBit); if (Subtarget->hasSME()) Features.set(Feature_HasSMEBit); if (Subtarget->hasSMEF64F64()) Features.set(Feature_HasSMEF64F64Bit); if (Subtarget->hasSMEI16I64()) Features.set(Feature_HasSMEI16I64Bit); if (Subtarget->hasSME2()) Features.set(Feature_HasSME2Bit); if (Subtarget->hasSVEorSME()) Features.set(Feature_HasSVEorSMEBit); if (Subtarget->hasSVE2() || Subtarget->hasSME()) Features.set(Feature_HasSVE2orSMEBit); if (Subtarget->hasSVE2p1() || Subtarget->hasSME()) Features.set(Feature_HasSVE2p1_or_HasSMEBit); if (Subtarget->hasSVE2p1() || Subtarget->hasSME2()) Features.set(Feature_HasSVE2p1_or_HasSME2Bit); if (Subtarget->hasNEON() || Subtarget->hasSME()) Features.set(Feature_HasNEONorSMEBit); if (Subtarget->hasRCPC()) Features.set(Feature_HasRCPCBit); if (Subtarget->hasFRInt3264()) Features.set(Feature_HasFRInt3264Bit); if (Subtarget->hasMTE()) Features.set(Feature_HasMTEBit); if (Subtarget->hasTME()) Features.set(Feature_HasTMEBit); if (Subtarget->hasBF16()) Features.set(Feature_HasBF16Bit); if (Subtarget->hasMatMulInt8()) Features.set(Feature_HasMatMulInt8Bit); if (Subtarget->hasMatMulFP32()) Features.set(Feature_HasMatMulFP32Bit); if (Subtarget->hasMatMulFP64()) Features.set(Feature_HasMatMulFP64Bit); if (Subtarget->hasLS64()) Features.set(Feature_HasLS64Bit); if (Subtarget->hasHBC()) Features.set(Feature_HasHBCBit); if (Subtarget->isLittleEndian()) Features.set(Feature_IsLEBit); if (!Subtarget->isLittleEndian()) Features.set(Feature_IsBEBit); if (Subtarget->useExperimentalZeroingPseudos()) Features.set(Feature_UseExperimentalZeroingPseudosBit); if (Subtarget->useAlternateSExtLoadCVTF32Pattern()) Features.set(Feature_UseAlternateSExtLoadCVTF32Bit); if (Subtarget->useScalarIncVL()) Features.set(Feature_UseScalarIncVLBit); if (!Subtarget->forceStreamingCompatibleSVE()) Features.set(Feature_NotInStreamingSVEModeBit); return Features; } void AArch64InstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { AvailableFunctionFeatures = computeAvailableFunctionFeatures((const AArch64Subtarget *)&MF.getSubtarget(), &MF); } PredicateBitset AArch64InstructionSelector:: computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, const MachineFunction *MF) const { PredicateBitset Features; if (!shouldOptForSize(MF)) Features.set(Feature_NotForCodeSizeBit); if (!Subtarget->isSTRQroSlow() || shouldOptForSize(MF)) Features.set(Feature_UseSTRQroBit); if ( MF->getInfo()->branchTargetEnforcement() ) Features.set(Feature_UseBTIBit); if ( !MF->getInfo()->branchTargetEnforcement() ) Features.set(Feature_NotUseBTIBit); if ( MF->getSubtarget().hardenSlsBlr() ) Features.set(Feature_SLSBLRMitigationBit); if ( !MF->getSubtarget().hardenSlsBlr() ) Features.set(Feature_NoSLSBLRMitigationBit); if (!MF->getFunction().hasOptNone() || MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) || !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized)) Features.set(Feature_OptimizedGISelOrOtherSelectorBit); return Features; } // LLT Objects. enum { GILLT_s16, GILLT_s32, GILLT_s64, GILLT_s128, GILLT_v2s32, GILLT_v2s64, GILLT_v4s16, GILLT_v4s32, GILLT_v8s8, GILLT_v8s16, GILLT_v16s8, GILLT_nxv1s1, GILLT_nxv2s1, GILLT_nxv2s16, GILLT_nxv2s32, GILLT_nxv2s64, GILLT_nxv4s1, GILLT_nxv4s16, GILLT_nxv4s32, GILLT_nxv8s1, GILLT_nxv8s16, GILLT_nxv16s1, GILLT_nxv16s8, }; const static size_t NumTypeObjects = 23; const static LLT TypeObjects[] = { LLT::scalar(16), LLT::scalar(32), LLT::scalar(64), LLT::scalar(128), LLT::vector(ElementCount::getFixed(2), 32), LLT::vector(ElementCount::getFixed(2), 64), LLT::vector(ElementCount::getFixed(4), 16), LLT::vector(ElementCount::getFixed(4), 32), LLT::vector(ElementCount::getFixed(8), 8), LLT::vector(ElementCount::getFixed(8), 16), LLT::vector(ElementCount::getFixed(16), 8), LLT::vector(ElementCount::getScalable(1), 1), LLT::vector(ElementCount::getScalable(2), 1), LLT::vector(ElementCount::getScalable(2), 16), LLT::vector(ElementCount::getScalable(2), 32), LLT::vector(ElementCount::getScalable(2), 64), LLT::vector(ElementCount::getScalable(4), 1), LLT::vector(ElementCount::getScalable(4), 16), LLT::vector(ElementCount::getScalable(4), 32), LLT::vector(ElementCount::getScalable(8), 1), LLT::vector(ElementCount::getScalable(8), 16), LLT::vector(ElementCount::getScalable(16), 1), LLT::vector(ElementCount::getScalable(16), 8), }; // Feature bitsets. enum { GIFBS_Invalid, GIFBS_HasAES, GIFBS_HasCRC, GIFBS_HasCSSC, GIFBS_HasFPARMv8, GIFBS_HasFRInt3264, GIFBS_HasFullFP16, GIFBS_HasFuseAES, GIFBS_HasLSE, GIFBS_HasMTE, GIFBS_HasMatMulInt8, GIFBS_HasNEON, GIFBS_HasNEONorSME, GIFBS_HasNoCSSC, GIFBS_HasNoLSE, GIFBS_HasPAuth, GIFBS_HasRCPC, GIFBS_HasRDM, GIFBS_HasSHA2, GIFBS_HasSHA3, GIFBS_HasSM4, GIFBS_HasSME, GIFBS_HasSVE, GIFBS_HasSVE2, GIFBS_HasSVEorSME, GIFBS_HasTME, GIFBS_IsBE, GIFBS_IsLE, GIFBS_NotInStreamingSVEMode, GIFBS_OptimizedGISelOrOtherSelector, GIFBS_UseSTRQro, GIFBS_HasBF16_HasNEON, GIFBS_HasBF16_HasNEONorSME, GIFBS_HasComplxNum_HasNEON, GIFBS_HasFP16FML_HasNEON, GIFBS_HasFPARMv8_HasJS, GIFBS_HasFullFP16_HasNEON, GIFBS_HasFullFP16_HasNEONorSME, GIFBS_HasNEON_HasRDM, GIFBS_HasSVEorSME_UseScalarIncVL, GIFBS_IsLE_UseSTRQro, GIFBS_HasComplxNum_HasFullFP16_HasNEON, GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32, }; const static PredicateBitset FeatureBitsets[] { {}, // GIFBS_Invalid {Feature_HasAESBit, }, {Feature_HasCRCBit, }, {Feature_HasCSSCBit, }, {Feature_HasFPARMv8Bit, }, {Feature_HasFRInt3264Bit, }, {Feature_HasFullFP16Bit, }, {Feature_HasFuseAESBit, }, {Feature_HasLSEBit, }, {Feature_HasMTEBit, }, {Feature_HasMatMulInt8Bit, }, {Feature_HasNEONBit, }, {Feature_HasNEONorSMEBit, }, {Feature_HasNoCSSCBit, }, {Feature_HasNoLSEBit, }, {Feature_HasPAuthBit, }, {Feature_HasRCPCBit, }, {Feature_HasRDMBit, }, {Feature_HasSHA2Bit, }, {Feature_HasSHA3Bit, }, {Feature_HasSM4Bit, }, {Feature_HasSMEBit, }, {Feature_HasSVEBit, }, {Feature_HasSVE2Bit, }, {Feature_HasSVEorSMEBit, }, {Feature_HasTMEBit, }, {Feature_IsBEBit, }, {Feature_IsLEBit, }, {Feature_NotInStreamingSVEModeBit, }, {Feature_OptimizedGISelOrOtherSelectorBit, }, {Feature_UseSTRQroBit, }, {Feature_HasBF16Bit, Feature_HasNEONBit, }, {Feature_HasBF16Bit, Feature_HasNEONorSMEBit, }, {Feature_HasComplxNumBit, Feature_HasNEONBit, }, {Feature_HasFP16FMLBit, Feature_HasNEONBit, }, {Feature_HasFPARMv8Bit, Feature_HasJSBit, }, {Feature_HasFullFP16Bit, Feature_HasNEONBit, }, {Feature_HasFullFP16Bit, Feature_HasNEONorSMEBit, }, {Feature_HasNEONBit, Feature_HasRDMBit, }, {Feature_HasSVEorSMEBit, Feature_UseScalarIncVLBit, }, {Feature_IsLEBit, Feature_UseSTRQroBit, }, {Feature_HasComplxNumBit, Feature_HasFullFP16Bit, Feature_HasNEONBit, }, {Feature_HasNEONBit, Feature_NotForCodeSizeBit, Feature_UseAlternateSExtLoadCVTF32Bit, }, }; // ComplexPattern predicates. enum { GICP_Invalid, GICP_gi_addsub_shifted_imm32, GICP_gi_addsub_shifted_imm64, GICP_gi_am_indexed128, GICP_gi_am_indexed16, GICP_gi_am_indexed32, GICP_gi_am_indexed64, GICP_gi_am_indexed8, GICP_gi_am_unscaled128, GICP_gi_am_unscaled16, GICP_gi_am_unscaled32, GICP_gi_am_unscaled64, GICP_gi_am_unscaled8, GICP_gi_arith_extended_reg32_i32, GICP_gi_arith_extended_reg32_i64, GICP_gi_arith_extended_reg32to64_i64, GICP_gi_arith_shifted_reg32, GICP_gi_arith_shifted_reg64, GICP_gi_logical_shifted_reg32, GICP_gi_logical_shifted_reg64, GICP_gi_neg_addsub_shifted_imm32, GICP_gi_neg_addsub_shifted_imm64, GICP_gi_ro_Windexed128, GICP_gi_ro_Windexed16, GICP_gi_ro_Windexed32, GICP_gi_ro_Windexed64, GICP_gi_ro_Windexed8, GICP_gi_ro_Xindexed128, GICP_gi_ro_Xindexed16, GICP_gi_ro_Xindexed32, GICP_gi_ro_Xindexed64, GICP_gi_ro_Xindexed8, }; // See constructor for table contents // PatFrag predicates. enum { GIPFP_I64_Predicate_VectorIndex0 = GIPFP_I64_Invalid + 1, GIPFP_I64_Predicate_VectorIndex0_timm, GIPFP_I64_Predicate_VectorIndex1, GIPFP_I64_Predicate_VectorIndex132b, GIPFP_I64_Predicate_VectorIndex132b_timm, GIPFP_I64_Predicate_VectorIndex1_timm, GIPFP_I64_Predicate_VectorIndexB, GIPFP_I64_Predicate_VectorIndexB32b, GIPFP_I64_Predicate_VectorIndexB32b_timm, GIPFP_I64_Predicate_VectorIndexB_timm, GIPFP_I64_Predicate_VectorIndexD, GIPFP_I64_Predicate_VectorIndexD32b, GIPFP_I64_Predicate_VectorIndexD32b_timm, GIPFP_I64_Predicate_VectorIndexD_timm, GIPFP_I64_Predicate_VectorIndexH, GIPFP_I64_Predicate_VectorIndexH32b, GIPFP_I64_Predicate_VectorIndexH32b_timm, GIPFP_I64_Predicate_VectorIndexH_timm, GIPFP_I64_Predicate_VectorIndexS, GIPFP_I64_Predicate_VectorIndexS32b, GIPFP_I64_Predicate_VectorIndexS32b_timm, GIPFP_I64_Predicate_VectorIndexS_timm, GIPFP_I64_Predicate_complexrotateop, GIPFP_I64_Predicate_complexrotateopodd, GIPFP_I64_Predicate_i64imm_32bit, GIPFP_I64_Predicate_i64imm_32bit_tgt, GIPFP_I64_Predicate_imm0_1, GIPFP_I64_Predicate_imm0_127, GIPFP_I64_Predicate_imm0_127_64b, GIPFP_I64_Predicate_imm0_15, GIPFP_I64_Predicate_imm0_255, GIPFP_I64_Predicate_imm0_3, GIPFP_I64_Predicate_imm0_31, GIPFP_I64_Predicate_imm0_63, GIPFP_I64_Predicate_imm0_7, GIPFP_I64_Predicate_imm32_0_15, GIPFP_I64_Predicate_imm32_0_31, GIPFP_I64_Predicate_maski16_or_more, GIPFP_I64_Predicate_maski8_or_more, GIPFP_I64_Predicate_rprfop, GIPFP_I64_Predicate_s64imm_32bit, GIPFP_I64_Predicate_simm4s1, GIPFP_I64_Predicate_simm4s16, GIPFP_I64_Predicate_simm4s2, GIPFP_I64_Predicate_simm4s3, GIPFP_I64_Predicate_simm4s32, GIPFP_I64_Predicate_simm4s4, GIPFP_I64_Predicate_simm5_16b, GIPFP_I64_Predicate_simm5_16b_tgt, GIPFP_I64_Predicate_simm5_32b, GIPFP_I64_Predicate_simm5_32b_tgt, GIPFP_I64_Predicate_simm5_64b, GIPFP_I64_Predicate_simm5_64b_tgt, GIPFP_I64_Predicate_simm5_8b, GIPFP_I64_Predicate_simm5_8b_tgt, GIPFP_I64_Predicate_simm6_32b, GIPFP_I64_Predicate_simm6s1, GIPFP_I64_Predicate_simm8_32b, GIPFP_I64_Predicate_simm8_64b, GIPFP_I64_Predicate_simm9, GIPFP_I64_Predicate_sme_elm_idx0_0, GIPFP_I64_Predicate_sme_elm_idx0_1, GIPFP_I64_Predicate_sme_elm_idx0_15, GIPFP_I64_Predicate_sme_elm_idx0_3, GIPFP_I64_Predicate_sme_elm_idx0_7, GIPFP_I64_Predicate_svcr_op, GIPFP_I64_Predicate_sve_elm_idx_extdup_b, GIPFP_I64_Predicate_sve_elm_idx_extdup_b_timm, GIPFP_I64_Predicate_sve_elm_idx_extdup_d, GIPFP_I64_Predicate_sve_elm_idx_extdup_d_timm, GIPFP_I64_Predicate_sve_elm_idx_extdup_h, GIPFP_I64_Predicate_sve_elm_idx_extdup_h_timm, GIPFP_I64_Predicate_sve_elm_idx_extdup_q, GIPFP_I64_Predicate_sve_elm_idx_extdup_q_timm, GIPFP_I64_Predicate_sve_elm_idx_extdup_s, GIPFP_I64_Predicate_sve_elm_idx_extdup_s_timm, GIPFP_I64_Predicate_sve_incdec_imm, GIPFP_I64_Predicate_sve_pred_enum, GIPFP_I64_Predicate_sve_prfop, GIPFP_I64_Predicate_sve_vec_len_specifier_enum, GIPFP_I64_Predicate_tbz_imm0_31_diag, GIPFP_I64_Predicate_tbz_imm0_31_nodiag, GIPFP_I64_Predicate_tbz_imm32_63, GIPFP_I64_Predicate_timm0_1, GIPFP_I64_Predicate_timm0_31, GIPFP_I64_Predicate_timm0_63, GIPFP_I64_Predicate_timm32_0_1, GIPFP_I64_Predicate_timm32_0_15, GIPFP_I64_Predicate_timm32_0_255, GIPFP_I64_Predicate_timm32_0_3, GIPFP_I64_Predicate_timm32_0_31, GIPFP_I64_Predicate_timm32_0_65535, GIPFP_I64_Predicate_timm32_0_7, GIPFP_I64_Predicate_timm64_0_65535, GIPFP_I64_Predicate_tuimm5s2, GIPFP_I64_Predicate_tuimm5s4, GIPFP_I64_Predicate_tuimm5s8, GIPFP_I64_Predicate_tvecshiftL16, GIPFP_I64_Predicate_tvecshiftL32, GIPFP_I64_Predicate_tvecshiftL64, GIPFP_I64_Predicate_tvecshiftL8, GIPFP_I64_Predicate_tvecshiftR16, GIPFP_I64_Predicate_tvecshiftR32, GIPFP_I64_Predicate_tvecshiftR64, GIPFP_I64_Predicate_tvecshiftR8, GIPFP_I64_Predicate_ubsan_trap_imm, GIPFP_I64_Predicate_uimm0s2range, GIPFP_I64_Predicate_uimm0s4range, GIPFP_I64_Predicate_uimm16, GIPFP_I64_Predicate_uimm1s2range, GIPFP_I64_Predicate_uimm1s4range, GIPFP_I64_Predicate_uimm2s2range, GIPFP_I64_Predicate_uimm2s4range, GIPFP_I64_Predicate_uimm3s2range, GIPFP_I64_Predicate_uimm3s8, GIPFP_I64_Predicate_uimm5s2, GIPFP_I64_Predicate_uimm5s4, GIPFP_I64_Predicate_uimm5s8, GIPFP_I64_Predicate_uimm6, GIPFP_I64_Predicate_uimm6s1, GIPFP_I64_Predicate_uimm6s16, GIPFP_I64_Predicate_uimm6s2, GIPFP_I64_Predicate_uimm6s4, GIPFP_I64_Predicate_uimm6s8, GIPFP_I64_Predicate_uimm8_32b, GIPFP_I64_Predicate_uimm8_64b, GIPFP_I64_Predicate_vecshiftL16, GIPFP_I64_Predicate_vecshiftL32, GIPFP_I64_Predicate_vecshiftL64, GIPFP_I64_Predicate_vecshiftL8, GIPFP_I64_Predicate_vecshiftR16, GIPFP_I64_Predicate_vecshiftR16Narrow, GIPFP_I64_Predicate_vecshiftR32, GIPFP_I64_Predicate_vecshiftR32Narrow, GIPFP_I64_Predicate_vecshiftR64, GIPFP_I64_Predicate_vecshiftR64Narrow, GIPFP_I64_Predicate_vecshiftR8, }; bool AArch64InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { switch (PredicateID) { case GIPFP_I64_Predicate_VectorIndex0: { return ((uint64_t)Imm) == 0; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndex0_timm: { return ((uint64_t)Imm) == 0; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndex1: { return ((uint64_t)Imm) == 1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndex132b: { return ((uint64_t)Imm) == 1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndex132b_timm: { return ((uint64_t)Imm) == 1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndex1_timm: { return ((uint64_t)Imm) == 1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexB: { return ((uint64_t)Imm) < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexB32b: { return ((uint64_t)Imm) < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexB32b_timm: { return ((uint64_t)Imm) < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexB_timm: { return ((uint64_t)Imm) < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexD: { return ((uint64_t)Imm) < 2; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexD32b: { return ((uint64_t)Imm) < 2; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexD32b_timm: { return ((uint64_t)Imm) < 2; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexD_timm: { return ((uint64_t)Imm) < 2; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexH: { return ((uint64_t)Imm) < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexH32b: { return ((uint64_t)Imm) < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexH32b_timm: { return ((uint64_t)Imm) < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexH_timm: { return ((uint64_t)Imm) < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexS: { return ((uint64_t)Imm) < 4; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexS32b: { return ((uint64_t)Imm) < 4; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexS32b_timm: { return ((uint64_t)Imm) < 4; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexS_timm: { return ((uint64_t)Imm) < 4; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_complexrotateop: { return Imm >= 0 && Imm <= 270; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_complexrotateopodd: { return Imm >= 0 && Imm <= 270; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_i64imm_32bit: { return (Imm & 0xffffffffULL) == static_cast(Imm); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_i64imm_32bit_tgt: { return (Imm & 0xffffffffULL) == static_cast(Imm); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_1: { return ((uint64_t)Imm) < 2; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_127: { return ((uint32_t)Imm) < 128; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_127_64b: { return ((uint64_t)Imm) < 128; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_15: { return ((uint64_t)Imm) < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_255: { return ((uint32_t)Imm) < 256; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_3: { return ((uint64_t)Imm) < 4; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_31: { return ((uint64_t)Imm) < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_63: { return ((uint64_t)Imm) < 64; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_7: { return ((uint64_t)Imm) < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm32_0_15: { return ((uint32_t)Imm) < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm32_0_31: { return ((uint64_t)Imm) < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_maski16_or_more: { return (Imm & 0xffff) == 0xffff; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_maski8_or_more: { return (Imm & 0xff) == 0xff; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_rprfop: { return (((uint32_t)Imm) <= 63); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_s64imm_32bit: { int64_t Imm64 = static_cast(Imm); return Imm64 >= std::numeric_limits::min() && Imm64 <= std::numeric_limits::max(); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm4s1: { return Imm >=-8 && Imm <= 7; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm4s16: { return Imm >=-128 && Imm <= 112 && (Imm % 16) == 0x0; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm4s2: { return Imm >=-16 && Imm <= 14 && (Imm % 2) == 0x0; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm4s3: { return Imm >=-24 && Imm <= 21 && (Imm % 3) == 0x0; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm4s32: { return Imm >=-256 && Imm <= 224 && (Imm % 32) == 0x0; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm4s4: { return Imm >=-32 && Imm <= 28 && (Imm % 4) == 0x0; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm5_16b: { return (int16_t)Imm >= -16 && (int16_t)Imm < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm5_16b_tgt: { return (int16_t)Imm >= -16 && (int16_t)Imm < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm5_32b: { return Imm >= -16 && Imm < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm5_32b_tgt: { return (int32_t)Imm >= -16 && (int32_t)Imm < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm5_64b: { return Imm >= -16 && Imm < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm5_64b_tgt: { return (int64_t)Imm >= -16 && (int64_t)Imm < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm5_8b: { return (int8_t)Imm >= -16 && (int8_t)Imm < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm5_8b_tgt: { return (int8_t)Imm >= -16 && (int8_t)Imm < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm6_32b: { return Imm >= -32 && Imm < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm6s1: { return Imm >= -32 && Imm < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm8_32b: { return Imm >= -128 && Imm < 128; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm8_64b: { return Imm >= -128 && Imm < 128; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm9: { return Imm >= -256 && Imm < 256; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sme_elm_idx0_0: { return ((uint32_t)Imm) == 0; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sme_elm_idx0_1: { return ((uint32_t)Imm) <= 1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sme_elm_idx0_15: { return ((uint32_t)Imm) <= 15; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sme_elm_idx0_3: { return ((uint32_t)Imm) <= 3; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sme_elm_idx0_7: { return ((uint32_t)Imm) <= 7; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_svcr_op: { return AArch64SVCR::lookupSVCRByEncoding(Imm) != nullptr; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_elm_idx_extdup_b: { return ((uint64_t)Imm) < 64; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_elm_idx_extdup_b_timm: { return ((uint64_t)Imm) < 64; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_elm_idx_extdup_d: { return ((uint64_t)Imm) < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_elm_idx_extdup_d_timm: { return ((uint64_t)Imm) < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_elm_idx_extdup_h: { return ((uint64_t)Imm) < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_elm_idx_extdup_h_timm: { return ((uint64_t)Imm) < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_elm_idx_extdup_q: { return ((uint64_t)Imm) < 4; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_elm_idx_extdup_q_timm: { return ((uint64_t)Imm) < 4; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_elm_idx_extdup_s: { return ((uint64_t)Imm) < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_elm_idx_extdup_s_timm: { return ((uint64_t)Imm) < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_incdec_imm: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_pred_enum: { return (((uint32_t)Imm) < 32); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_prfop: { return (((uint32_t)Imm) <= 15); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_vec_len_specifier_enum: { return (((uint32_t)Imm) < 2); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tbz_imm0_31_diag: { return (((uint32_t)Imm) < 32); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tbz_imm0_31_nodiag: { return (((uint32_t)Imm) < 32); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tbz_imm32_63: { return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_timm0_1: { return ((uint64_t)Imm) < 2; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_timm0_31: { return ((uint64_t)Imm) < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_timm0_63: { return ((uint64_t)Imm) < 64; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_timm32_0_1: { return ((uint32_t)Imm) < 2; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_timm32_0_15: { return ((uint32_t)Imm) < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_timm32_0_255: { return ((uint32_t)Imm) < 256; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_timm32_0_3: { return ((uint32_t)Imm) < 4; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_timm32_0_31: { return ((uint32_t)Imm) < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_timm32_0_65535: { return ((uint32_t)Imm) < 65536; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_timm32_0_7: { return ((uint32_t)Imm) < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_timm64_0_65535: { return ((uint64_t)Imm) < 65536; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tuimm5s2: { return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tuimm5s4: { return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tuimm5s8: { return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tvecshiftL16: { return (((uint32_t)Imm) < 16); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tvecshiftL32: { return (((uint32_t)Imm) < 32); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tvecshiftL64: { return (((uint32_t)Imm) < 64); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tvecshiftL8: { return (((uint32_t)Imm) < 8); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tvecshiftR16: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tvecshiftR32: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tvecshiftR64: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tvecshiftR8: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_ubsan_trap_imm: { return isUInt<8>(Imm); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm0s2range: { return Imm == 0; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm0s4range: { return Imm == 0; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm16: { return Imm >= 0 && Imm < 65536; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm1s2range: { return Imm >= 0 && Imm <= 2 && ((Imm % 2) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm1s4range: { return Imm >= 0 && Imm <= 4 && ((Imm % 4) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm2s2range: { return Imm >= 0 && Imm <= 6 && ((Imm % 2) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm2s4range: { return Imm >= 0 && Imm <= 12 && ((Imm % 4) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm3s2range: { return Imm >= 0 && Imm <= 14 && ((Imm % 2) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm3s8: { return Imm >= 0 && Imm <= 56 && ((Imm % 8) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm5s2: { return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm5s4: { return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm5s8: { return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm6: { return Imm >= 0 && Imm < 64; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm6s1: { return Imm >= 0 && Imm < 64; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm6s16: { return Imm >= 0 && Imm < (64*16) && ((Imm % 16) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm6s2: { return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm6s4: { return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm6s8: { return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm8_32b: { return Imm >= 0 && Imm < 256; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm8_64b: { return Imm >= 0 && Imm < 256; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftL16: { return (((uint32_t)Imm) < 16); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftL32: { return (((uint32_t)Imm) < 32); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftL64: { return (((uint32_t)Imm) < 64); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftL8: { return (((uint32_t)Imm) < 8); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftR16: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftR16Narrow: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftR32: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftR32Narrow: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftR64: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftR64Narrow: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftR8: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9); llvm_unreachable("ImmediateCode should have returned"); return false; } } llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. enum { GIPFP_APFloat_Predicate_fpimm0 = GIPFP_APFloat_Invalid + 1, GIPFP_APFloat_Predicate_fpimm16, GIPFP_APFloat_Predicate_fpimm32, GIPFP_APFloat_Predicate_fpimm32SIMDModImmType4, GIPFP_APFloat_Predicate_fpimm64, GIPFP_APFloat_Predicate_fpimm_half, GIPFP_APFloat_Predicate_fpimm_minus0, GIPFP_APFloat_Predicate_fpimm_one, GIPFP_APFloat_Predicate_fpimm_two, GIPFP_APFloat_Predicate_simdimmtype10, }; bool AArch64InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { switch (PredicateID) { case GIPFP_APFloat_Predicate_fpimm0: { return Imm.isExactlyValue(+0.0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_APFloat_Predicate_fpimm16: { return AArch64_AM::getFP16Imm(Imm) != -1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_APFloat_Predicate_fpimm32: { return AArch64_AM::getFP32Imm(Imm) != -1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_APFloat_Predicate_fpimm32SIMDModImmType4: { uint64_t Enc = Imm.bitcastToAPInt().getZExtValue(); return Enc != 0 && AArch64_AM::isAdvSIMDModImmType4(Enc << 32 | Enc); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_APFloat_Predicate_fpimm64: { return AArch64_AM::getFP64Imm(Imm) != -1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_APFloat_Predicate_fpimm_half: { return Imm.isExactlyValue(+0.5); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_APFloat_Predicate_fpimm_minus0: { return Imm.isExactlyValue(-0.0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_APFloat_Predicate_fpimm_one: { return Imm.isExactlyValue(+1.0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_APFloat_Predicate_fpimm_two: { return Imm.isExactlyValue(+2.0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_APFloat_Predicate_simdimmtype10: { return AArch64_AM::isAdvSIMDModImmType10( Imm.bitcastToAPInt().getZExtValue()); llvm_unreachable("ImmediateCode should have returned"); return false; } } llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. enum { GIPFP_APInt_Predicate_logical_imm32 = GIPFP_APInt_Invalid + 1, GIPFP_APInt_Predicate_logical_imm64, }; bool AArch64InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { switch (PredicateID) { case GIPFP_APInt_Predicate_logical_imm32: { return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 32); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_APInt_Predicate_logical_imm64: { return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 64); llvm_unreachable("ImmediateCode should have returned"); return false; } } llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. enum { GIPFP_MI_Predicate_add_and_or_is_add = GIPFP_MI_Invalid + 1, GIPFP_MI_Predicate_ldaxr_1, GIPFP_MI_Predicate_ldaxr_2, GIPFP_MI_Predicate_ldaxr_4, GIPFP_MI_Predicate_ldaxr_8, GIPFP_MI_Predicate_ldxr_1, GIPFP_MI_Predicate_ldxr_2, GIPFP_MI_Predicate_ldxr_4, GIPFP_MI_Predicate_ldxr_8, GIPFP_MI_Predicate_stlxr_1, GIPFP_MI_Predicate_stlxr_2, GIPFP_MI_Predicate_stlxr_4, GIPFP_MI_Predicate_stlxr_8, GIPFP_MI_Predicate_stxr_1, GIPFP_MI_Predicate_stxr_2, GIPFP_MI_Predicate_stxr_4, GIPFP_MI_Predicate_stxr_8, }; bool AArch64InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const std::array &Operands) const { const MachineFunction &MF = *MI.getParent()->getParent(); const MachineRegisterInfo &MRI = MF.getRegInfo(); (void)MRI; switch (PredicateID) { case GIPFP_MI_Predicate_add_and_or_is_add: { // Only handle G_ADD for now. FIXME. build capability to compute whether // operands of G_OR have common bits set or not. return MI.getOpcode() == TargetOpcode::G_ADD; llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_ldaxr_1: { return isLoadStoreOfNumBytes(MI, 1); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_ldaxr_2: { return isLoadStoreOfNumBytes(MI, 2); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_ldaxr_4: { return isLoadStoreOfNumBytes(MI, 4); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_ldaxr_8: { return isLoadStoreOfNumBytes(MI, 8); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_ldxr_1: { return isLoadStoreOfNumBytes(MI, 1); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_ldxr_2: { return isLoadStoreOfNumBytes(MI, 2); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_ldxr_4: { return isLoadStoreOfNumBytes(MI, 4); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_ldxr_8: { return isLoadStoreOfNumBytes(MI, 8); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stlxr_1: { return isLoadStoreOfNumBytes(MI, 1); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stlxr_2: { return isLoadStoreOfNumBytes(MI, 2); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stlxr_4: { return isLoadStoreOfNumBytes(MI, 4); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stlxr_8: { return isLoadStoreOfNumBytes(MI, 8); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stxr_1: { return isLoadStoreOfNumBytes(MI, 1); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stxr_2: { return isLoadStoreOfNumBytes(MI, 2); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stxr_4: { return isLoadStoreOfNumBytes(MI, 4); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stxr_8: { return isLoadStoreOfNumBytes(MI, 8); llvm_unreachable("GISelPredicateCode should have returned"); return false; } } llvm_unreachable("Unknown predicate"); return false; } AArch64InstructionSelector::ComplexMatcherMemFn AArch64InstructionSelector::ComplexPredicateFns[] = { nullptr, // GICP_Invalid &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm32 &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm64 &AArch64InstructionSelector::selectAddrModeIndexed<128>, // gi_am_indexed128 &AArch64InstructionSelector::selectAddrModeIndexed<16>, // gi_am_indexed16 &AArch64InstructionSelector::selectAddrModeIndexed<32>, // gi_am_indexed32 &AArch64InstructionSelector::selectAddrModeIndexed<64>, // gi_am_indexed64 &AArch64InstructionSelector::selectAddrModeIndexed<8>, // gi_am_indexed8 &AArch64InstructionSelector::selectAddrModeUnscaled128, // gi_am_unscaled128 &AArch64InstructionSelector::selectAddrModeUnscaled16, // gi_am_unscaled16 &AArch64InstructionSelector::selectAddrModeUnscaled32, // gi_am_unscaled32 &AArch64InstructionSelector::selectAddrModeUnscaled64, // gi_am_unscaled64 &AArch64InstructionSelector::selectAddrModeUnscaled8, // gi_am_unscaled8 &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32_i32 &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32_i64 &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32to64_i64 &AArch64InstructionSelector::selectArithShiftedRegister, // gi_arith_shifted_reg32 &AArch64InstructionSelector::selectArithShiftedRegister, // gi_arith_shifted_reg64 &AArch64InstructionSelector::selectLogicalShiftedRegister, // gi_logical_shifted_reg32 &AArch64InstructionSelector::selectLogicalShiftedRegister, // gi_logical_shifted_reg64 &AArch64InstructionSelector::selectNegArithImmed, // gi_neg_addsub_shifted_imm32 &AArch64InstructionSelector::selectNegArithImmed, // gi_neg_addsub_shifted_imm64 &AArch64InstructionSelector::selectAddrModeWRO<128>, // gi_ro_Windexed128 &AArch64InstructionSelector::selectAddrModeWRO<16>, // gi_ro_Windexed16 &AArch64InstructionSelector::selectAddrModeWRO<32>, // gi_ro_Windexed32 &AArch64InstructionSelector::selectAddrModeWRO<64>, // gi_ro_Windexed64 &AArch64InstructionSelector::selectAddrModeWRO<8>, // gi_ro_Windexed8 &AArch64InstructionSelector::selectAddrModeXRO<128>, // gi_ro_Xindexed128 &AArch64InstructionSelector::selectAddrModeXRO<16>, // gi_ro_Xindexed16 &AArch64InstructionSelector::selectAddrModeXRO<32>, // gi_ro_Xindexed32 &AArch64InstructionSelector::selectAddrModeXRO<64>, // gi_ro_Xindexed64 &AArch64InstructionSelector::selectAddrModeXRO<8>, // gi_ro_Xindexed8 }; // Custom renderers. enum { GICR_Invalid, GICR_renderFPImm16, GICR_renderFPImm32, GICR_renderFPImm32SIMDModImmType4, GICR_renderFPImm64, GICR_renderLogicalImm32, GICR_renderLogicalImm64, GICR_renderTruncImm, }; AArch64InstructionSelector::CustomRendererFn AArch64InstructionSelector::CustomRenderers[] = { nullptr, // GICR_Invalid &AArch64InstructionSelector::renderFPImm16, &AArch64InstructionSelector::renderFPImm32, &AArch64InstructionSelector::renderFPImm32SIMDModImmType4, &AArch64InstructionSelector::renderFPImm64, &AArch64InstructionSelector::renderLogicalImm32, &AArch64InstructionSelector::renderLogicalImm64, &AArch64InstructionSelector::renderTruncImm, }; bool AArch64InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { MachineFunction &MF = *I.getParent()->getParent(); MachineRegisterInfo &MRI = MF.getRegInfo(); const PredicateBitset AvailableFeatures = getAvailableFeatures(); NewMIVector OutMIs; State.MIs.clear(); State.MIs.push_back(&I); if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) { return true; } return false; } const int64_t *AArch64InstructionSelector::getMatchTable() const { constexpr static int64_t MatchTable0[] = { GIM_SwitchOpcode, /*MI*/0, /*[*/46, 773, /*)*//*default:*//*Label 119*/ 199135, /*TargetOpcode::G_ADD*//*Label 0*/ 732, /*TargetOpcode::G_SUB*//*Label 1*/ 12245, /*TargetOpcode::G_MUL*//*Label 2*/ 16113, /*TargetOpcode::G_SDIV*//*Label 3*/ 17428, /*TargetOpcode::G_UDIV*//*Label 4*/ 17497, 0, 0, 0, 0, /*TargetOpcode::G_AND*//*Label 5*/ 17566, /*TargetOpcode::G_OR*//*Label 6*/ 20738, /*TargetOpcode::G_XOR*//*Label 7*/ 32335, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*TargetOpcode::G_CONCAT_VECTORS*//*Label 8*/ 36564, 0, 0, /*TargetOpcode::G_BITCAST*//*Label 9*/ 44956, 0, 0, /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 10*/ 56739, /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 11*/ 56972, /*TargetOpcode::G_INTRINSIC_LRINT*//*Label 12*/ 57205, 0, /*TargetOpcode::G_READCYCLECOUNTER*//*Label 13*/ 57472, /*TargetOpcode::G_LOAD*//*Label 14*/ 57498, /*TargetOpcode::G_SEXTLOAD*//*Label 15*/ 65308, /*TargetOpcode::G_ZEXTLOAD*//*Label 16*/ 66279, 0, 0, 0, /*TargetOpcode::G_STORE*//*Label 17*/ 68854, 0, 0, /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 18*/ 77897, /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 19*/ 79342, /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 20*/ 80371, /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 21*/ 81400, /*TargetOpcode::G_ATOMICRMW_AND*//*Label 22*/ 82829, 0, /*TargetOpcode::G_ATOMICRMW_OR*//*Label 23*/ 84258, /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 24*/ 85287, /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 25*/ 86316, /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 26*/ 87345, /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 27*/ 88374, /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 28*/ 89403, 0, 0, 0, 0, 0, 0, /*TargetOpcode::G_FENCE*//*Label 29*/ 90432, 0, 0, 0, /*TargetOpcode::G_INTRINSIC*//*Label 30*/ 90484, /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 31*/ 135866, /*TargetOpcode::G_ANYEXT*//*Label 32*/ 140836, /*TargetOpcode::G_TRUNC*//*Label 33*/ 141013, /*TargetOpcode::G_CONSTANT*//*Label 34*/ 142021, /*TargetOpcode::G_FCONSTANT*//*Label 35*/ 142129, 0, 0, /*TargetOpcode::G_SEXT*//*Label 36*/ 142341, 0, /*TargetOpcode::G_ZEXT*//*Label 37*/ 142676, /*TargetOpcode::G_SHL*//*Label 38*/ 143135, /*TargetOpcode::G_LSHR*//*Label 39*/ 143448, /*TargetOpcode::G_ASHR*//*Label 40*/ 143833, 0, 0, /*TargetOpcode::G_ROTR*//*Label 41*/ 144328, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*TargetOpcode::G_UMULH*//*Label 42*/ 144817, /*TargetOpcode::G_SMULH*//*Label 43*/ 145250, /*TargetOpcode::G_UADDSAT*//*Label 44*/ 145683, /*TargetOpcode::G_SADDSAT*//*Label 45*/ 145921, /*TargetOpcode::G_USUBSAT*//*Label 46*/ 146159, /*TargetOpcode::G_SSUBSAT*//*Label 47*/ 146397, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*TargetOpcode::G_FADD*//*Label 48*/ 146635, /*TargetOpcode::G_FSUB*//*Label 49*/ 147553, /*TargetOpcode::G_FMUL*//*Label 50*/ 147850, /*TargetOpcode::G_FMA*//*Label 51*/ 150003, 0, /*TargetOpcode::G_FDIV*//*Label 52*/ 160215, 0, 0, 0, 0, 0, 0, 0, 0, /*TargetOpcode::G_FNEG*//*Label 53*/ 160512, /*TargetOpcode::G_FPEXT*//*Label 54*/ 161390, /*TargetOpcode::G_FPTRUNC*//*Label 55*/ 161534, /*TargetOpcode::G_FPTOSI*//*Label 56*/ 161678, /*TargetOpcode::G_FPTOUI*//*Label 57*/ 162699, /*TargetOpcode::G_SITOFP*//*Label 58*/ 163720, /*TargetOpcode::G_UITOFP*//*Label 59*/ 166465, /*TargetOpcode::G_FABS*//*Label 60*/ 168538, 0, 0, 0, /*TargetOpcode::G_FMINNUM*//*Label 61*/ 169099, /*TargetOpcode::G_FMAXNUM*//*Label 62*/ 169411, 0, 0, /*TargetOpcode::G_FMINIMUM*//*Label 63*/ 169723, /*TargetOpcode::G_FMAXIMUM*//*Label 64*/ 170035, 0, 0, /*TargetOpcode::G_SMIN*//*Label 65*/ 170347, /*TargetOpcode::G_SMAX*//*Label 66*/ 170696, /*TargetOpcode::G_UMIN*//*Label 67*/ 171045, /*TargetOpcode::G_UMAX*//*Label 68*/ 171394, /*TargetOpcode::G_ABS*//*Label 69*/ 171743, /*TargetOpcode::G_LROUND*//*Label 70*/ 172245, /*TargetOpcode::G_LLROUND*//*Label 71*/ 172380, /*TargetOpcode::G_BR*//*Label 72*/ 172450, 0, 0, /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 73*/ 172463, 0, /*TargetOpcode::G_CTTZ*//*Label 74*/ 174721, 0, /*TargetOpcode::G_CTLZ*//*Label 75*/ 174852, 0, /*TargetOpcode::G_CTPOP*//*Label 76*/ 175475, /*TargetOpcode::G_BSWAP*//*Label 77*/ 175588, /*TargetOpcode::G_BITREVERSE*//*Label 78*/ 175733, /*TargetOpcode::G_FCEIL*//*Label 79*/ 175842, 0, 0, /*TargetOpcode::G_FSQRT*//*Label 80*/ 176075, /*TargetOpcode::G_FFLOOR*//*Label 81*/ 176308, /*TargetOpcode::G_FRINT*//*Label 82*/ 176541, /*TargetOpcode::G_FNEARBYINT*//*Label 83*/ 176774, 0, 0, 0, 0, /*TargetOpcode::G_STRICT_FADD*//*Label 84*/ 177007, /*TargetOpcode::G_STRICT_FSUB*//*Label 85*/ 177795, /*TargetOpcode::G_STRICT_FMUL*//*Label 86*/ 178092, /*TargetOpcode::G_STRICT_FDIV*//*Label 87*/ 179983, 0, /*TargetOpcode::G_STRICT_FMA*//*Label 88*/ 180280, /*TargetOpcode::G_STRICT_FSQRT*//*Label 89*/ 189794, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*AArch64::G_BIT*//*Label 90*/ 190027, /*AArch64::G_DUP*//*Label 91*/ 190363, /*AArch64::G_DUPLANE16*//*Label 92*/ 191942, /*AArch64::G_DUPLANE32*//*Label 93*/ 192195, /*AArch64::G_DUPLANE64*//*Label 94*/ 192382, /*AArch64::G_DUPLANE8*//*Label 95*/ 192474, /*AArch64::G_EXT*//*Label 96*/ 192588, /*AArch64::G_FCMEQ*//*Label 97*/ 193412, /*AArch64::G_FCMEQZ*//*Label 98*/ 193690, /*AArch64::G_FCMGE*//*Label 99*/ 193867, /*AArch64::G_FCMGEZ*//*Label 100*/ 194145, /*AArch64::G_FCMGT*//*Label 101*/ 194322, /*AArch64::G_FCMGTZ*//*Label 102*/ 194600, /*AArch64::G_FCMLEZ*//*Label 103*/ 194777, /*AArch64::G_FCMLTZ*//*Label 104*/ 194954, /*AArch64::G_PREFETCH*//*Label 105*/ 195131, /*AArch64::G_REV16*//*Label 106*/ 195258, /*AArch64::G_REV32*//*Label 107*/ 195316, /*AArch64::G_REV64*//*Label 108*/ 195466, /*AArch64::G_SITOF*//*Label 109*/ 195690, /*AArch64::G_TRN1*//*Label 110*/ 195781, /*AArch64::G_TRN2*//*Label 111*/ 196146, /*AArch64::G_UITOF*//*Label 112*/ 196511, /*AArch64::G_UZP1*//*Label 113*/ 196602, /*AArch64::G_UZP2*//*Label 114*/ 196967, /*AArch64::G_VASHR*//*Label 115*/ 197332, /*AArch64::G_VLSHR*//*Label 116*/ 197967, /*AArch64::G_ZIP1*//*Label 117*/ 198405, /*AArch64::G_ZIP2*//*Label 118*/ 198770, // Label 0: @732 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 129*/ 12244, /*GILLT_s32*//*Label 120*/ 748, /*GILLT_s64*//*Label 121*/ 2165, 0, /*GILLT_v2s32*//*Label 122*/ 4587, /*GILLT_v2s64*//*Label 123*/ 5386, /*GILLT_v4s16*//*Label 124*/ 6841, /*GILLT_v4s32*//*Label 125*/ 7640, /*GILLT_v8s8*//*Label 126*/ 9367, /*GILLT_v8s16*//*Label 127*/ 9942, /*GILLT_v16s8*//*Label 128*/ 11669, // Label 120: @748 GIM_Try, /*On fail goto*//*Label 130*/ 2164, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 131*/ 792, // Rule ID 10620 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32, // (add:{ *:[i32] } addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32sp:{ *:[i32] }:$Rn) => (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10620, GIR_Done, // Label 131: @792 GIM_Try, /*On fail goto*//*Label 132*/ 931, // Rule ID 11401 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_sve_cnth, // MIs[2] pattern GIM_CheckIsImm, /*MI*/2, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 889:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern)), GPR32:{ *:[i32] }:$Rdn) => (EXTRACT_SUBREG:{ *:[i32] } (INCH_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn GIR_AddImm, /*InsnID*/2, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::INCH_XPiI, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::sub_32, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64RegClassID, // GIR_Coverage, 11401, GIR_Done, // Label 132: @931 GIM_Try, /*On fail goto*//*Label 133*/ 1070, // Rule ID 11413 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_sve_cntw, // MIs[2] pattern GIM_CheckIsImm, /*MI*/2, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 891:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern)), GPR32:{ *:[i32] }:$Rdn) => (EXTRACT_SUBREG:{ *:[i32] } (INCW_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn GIR_AddImm, /*InsnID*/2, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::INCW_XPiI, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::sub_32, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64RegClassID, // GIR_Coverage, 11413, GIR_Done, // Label 133: @1070 GIM_Try, /*On fail goto*//*Label 134*/ 1209, // Rule ID 11425 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_sve_cntd, // MIs[2] pattern GIM_CheckIsImm, /*MI*/2, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 888:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern)), GPR32:{ *:[i32] }:$Rdn) => (EXTRACT_SUBREG:{ *:[i32] } (INCD_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn GIR_AddImm, /*InsnID*/2, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::INCD_XPiI, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::sub_32, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64RegClassID, // GIR_Coverage, 11425, GIR_Done, // Label 134: @1209 GIM_Try, /*On fail goto*//*Label 135*/ 1348, // Rule ID 11535 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_sve_cntb, // MIs[2] pattern GIM_CheckIsImm, /*MI*/2, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 887:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern)), GPR32:{ *:[i32] }:$Rdn) => (EXTRACT_SUBREG:{ *:[i32] } (INCB_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn GIR_AddImm, /*InsnID*/2, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::INCB_XPiI, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::sub_32, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64RegClassID, // GIR_Coverage, 11535, GIR_Done, // Label 135: @1348 GIM_Try, /*On fail goto*//*Label 136*/ 1382, // Rule ID 93 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32, // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) => (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 93, GIR_Done, // Label 136: @1382 GIM_Try, /*On fail goto*//*Label 137*/ 1521, // Rule ID 4540 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_sve_cnth, // MIs[2] pattern GIM_CheckIsImm, /*MI*/2, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 889:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (INCH_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_AddImm, /*InsnID*/2, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::INCH_XPiI, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::sub_32, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64RegClassID, // GIR_Coverage, 4540, GIR_Done, // Label 137: @1521 GIM_Try, /*On fail goto*//*Label 138*/ 1660, // Rule ID 4552 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_sve_cntw, // MIs[2] pattern GIM_CheckIsImm, /*MI*/2, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 891:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (INCW_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_AddImm, /*InsnID*/2, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::INCW_XPiI, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::sub_32, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64RegClassID, // GIR_Coverage, 4552, GIR_Done, // Label 138: @1660 GIM_Try, /*On fail goto*//*Label 139*/ 1799, // Rule ID 4564 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_sve_cntd, // MIs[2] pattern GIM_CheckIsImm, /*MI*/2, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 888:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (INCD_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_AddImm, /*InsnID*/2, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::INCD_XPiI, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::sub_32, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64RegClassID, // GIR_Coverage, 4564, GIR_Done, // Label 139: @1799 GIM_Try, /*On fail goto*//*Label 140*/ 1938, // Rule ID 6935 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_sve_cntb, // MIs[2] pattern GIM_CheckIsImm, /*MI*/2, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 887:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (INCB_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_AddImm, /*InsnID*/2, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::INCB_XPiI, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::sub_32, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64RegClassID, // GIR_Coverage, 6935, GIR_Done, // Label 140: @1938 GIM_Try, /*On fail goto*//*Label 141*/ 1972, // Rule ID 10624 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_arith_extended_reg32_i32, // (add:{ *:[i32] } arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend, GPR32sp:{ *:[i32] }:$Rn) => (ADDWrx:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrx, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_extend GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10624, GIR_Done, // Label 141: @1972 GIM_Try, /*On fail goto*//*Label 142*/ 2006, // Rule ID 11656 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm32, // (add:{ *:[i32] } neg_addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32:{ *:[i32] }:$Rn) => (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11656, GIR_Done, // Label 142: @2006 GIM_Try, /*On fail goto*//*Label 143*/ 2040, // Rule ID 99 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_extended_reg32_i32, // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend) => (ADDWrx:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrx, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_extend GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 99, GIR_Done, // Label 143: @2040 GIM_Try, /*On fail goto*//*Label 144*/ 2074, // Rule ID 7883 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm32, // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) => (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7883, GIR_Done, // Label 144: @2074 GIM_Try, /*On fail goto*//*Label 145*/ 2108, // Rule ID 10622 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_arith_shifted_reg32, // (add:{ *:[i32] } arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn) => (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10622, GIR_Done, // Label 145: @2108 GIM_Try, /*On fail goto*//*Label 146*/ 2142, // Rule ID 97 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_shifted_reg32, // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift) => (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 97, GIR_Done, // Label 146: @2142 GIM_Try, /*On fail goto*//*Label 147*/ 2163, // Rule ID 95 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ADDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDWrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 95, GIR_Done, // Label 147: @2163 GIM_Reject, // Label 130: @2164 GIM_Reject, // Label 121: @2165 GIM_Try, /*On fail goto*//*Label 148*/ 4586, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 149*/ 2244, // Rule ID 10117 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] })) => (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10117, GIR_Done, // Label 149: @2244 GIM_Try, /*On fail goto*//*Label 150*/ 2313, // Rule ID 11793 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] })) => (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11793, GIR_Done, // Label 150: @2313 GIM_Try, /*On fail goto*//*Label 151*/ 2347, // Rule ID 10621 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm64, // (add:{ *:[i64] } addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64sp:{ *:[i64] }:$Rn) => (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10621, GIR_Done, // Label 151: @2347 GIM_Try, /*On fail goto*//*Label 152*/ 2443, // Rule ID 7933 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C), GPR64:{ *:[i64] }:$Ra) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7933, GIR_Done, // Label 152: @2443 GIM_Try, /*On fail goto*//*Label 153*/ 2539, // Rule ID 7934 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C), GPR64:{ *:[i64] }:$Ra) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7934, GIR_Done, // Label 153: @2539 GIM_Try, /*On fail goto*//*Label 154*/ 2573, // Rule ID 94 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64, // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) => (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 94, GIR_Done, // Label 154: @2573 GIM_Try, /*On fail goto*//*Label 155*/ 2669, // Rule ID 11664 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C)) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11664, GIR_Done, // Label 155: @2669 GIM_Try, /*On fail goto*//*Label 156*/ 2765, // Rule ID 11665 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C)) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11665, GIR_Done, // Label 156: @2765 GIM_Try, /*On fail goto*//*Label 157*/ 2850, // Rule ID 10632 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10632, GIR_Done, // Label 157: @2850 GIM_Try, /*On fail goto*//*Label 158*/ 2935, // Rule ID 10633 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10633, GIR_Done, // Label 158: @2935 GIM_Try, /*On fail goto*//*Label 159*/ 3020, // Rule ID 125 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 125, GIR_Done, // Label 159: @3020 GIM_Try, /*On fail goto*//*Label 160*/ 3105, // Rule ID 127 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 127, GIR_Done, // Label 160: @3105 GIM_Try, /*On fail goto*//*Label 161*/ 3164, // Rule ID 11396 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_sve_cnth, // MIs[1] pattern GIM_CheckIsImm, /*MI*/1, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 889:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern), GPR64:{ *:[i64] }:$Rdn) => (INCH_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INCH_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11396, GIR_Done, // Label 161: @3164 GIM_Try, /*On fail goto*//*Label 162*/ 3223, // Rule ID 11408 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_sve_cntw, // MIs[1] pattern GIM_CheckIsImm, /*MI*/1, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 891:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern), GPR64:{ *:[i64] }:$Rdn) => (INCW_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INCW_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11408, GIR_Done, // Label 162: @3223 GIM_Try, /*On fail goto*//*Label 163*/ 3282, // Rule ID 11420 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_sve_cntd, // MIs[1] pattern GIM_CheckIsImm, /*MI*/1, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 888:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern), GPR64:{ *:[i64] }:$Rdn) => (INCD_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INCD_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11420, GIR_Done, // Label 163: @3282 GIM_Try, /*On fail goto*//*Label 164*/ 3341, // Rule ID 11530 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_sve_cntb, // MIs[1] pattern GIM_CheckIsImm, /*MI*/1, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 887:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern), GPR64:{ *:[i64] }:$Rdn) => (INCB_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INCB_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11530, GIR_Done, // Label 164: @3341 GIM_Try, /*On fail goto*//*Label 165*/ 3400, // Rule ID 4537 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_sve_cnth, // MIs[1] pattern GIM_CheckIsImm, /*MI*/1, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 889:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern)) => (INCH_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INCH_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4537, GIR_Done, // Label 165: @3400 GIM_Try, /*On fail goto*//*Label 166*/ 3459, // Rule ID 4549 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_sve_cntw, // MIs[1] pattern GIM_CheckIsImm, /*MI*/1, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 891:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern)) => (INCW_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INCW_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4549, GIR_Done, // Label 166: @3459 GIM_Try, /*On fail goto*//*Label 167*/ 3518, // Rule ID 4561 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_sve_cntd, // MIs[1] pattern GIM_CheckIsImm, /*MI*/1, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 888:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern)) => (INCD_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INCD_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4561, GIR_Done, // Label 167: @3518 GIM_Try, /*On fail goto*//*Label 168*/ 3577, // Rule ID 6932 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_sve_cntb, // MIs[1] pattern GIM_CheckIsImm, /*MI*/1, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 887:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern)) => (INCB_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INCB_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6932, GIR_Done, // Label 168: @3577 GIM_Try, /*On fail goto*//*Label 169*/ 3611, // Rule ID 10625 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_arith_extended_reg32to64_i64, // (add:{ *:[i64] } arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend, GPR64sp:{ *:[i64] }:$Rn) => (ADDXrx:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrx, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_extend GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10625, GIR_Done, // Label 169: @3611 GIM_Try, /*On fail goto*//*Label 170*/ 3645, // Rule ID 11657 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm64, // (add:{ *:[i64] } neg_addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64:{ *:[i64] }:$Rn) => (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11657, GIR_Done, // Label 170: @3645 GIM_Try, /*On fail goto*//*Label 171*/ 3679, // Rule ID 100 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_extended_reg32to64_i64, // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend) => (ADDXrx:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrx, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_extend GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 100, GIR_Done, // Label 171: @3679 GIM_Try, /*On fail goto*//*Label 172*/ 3713, // Rule ID 7884 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm64, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) => (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7884, GIR_Done, // Label 172: @3713 GIM_Try, /*On fail goto*//*Label 173*/ 3747, // Rule ID 10623 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_arith_shifted_reg64, // (add:{ *:[i64] } arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn) => (ADDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10623, GIR_Done, // Label 173: @3747 GIM_Try, /*On fail goto*//*Label 174*/ 3781, // Rule ID 98 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_shifted_reg64, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift) => (ADDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 98, GIR_Done, // Label 174: @3781 GIM_Try, /*On fail goto*//*Label 175*/ 3837, // Rule ID 10707 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 550:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd) => (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10707, GIR_Done, // Label 175: @3837 GIM_Try, /*On fail goto*//*Label 176*/ 3893, // Rule ID 10719 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 615:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd) => (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10719, GIR_Done, // Label 176: @3893 GIM_Try, /*On fail goto*//*Label 177*/ 3960, // Rule ID 10897 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i64] } (AArch64vashr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm), FPR64:{ *:[i64] }:$Rd)<> => (SSRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10897, GIR_Done, // Label 177: @3960 GIM_Try, /*On fail goto*//*Label 178*/ 4027, // Rule ID 11782 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v1i64] } (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm), FPR64:{ *:[v1i64] }:$Rd)<> => (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11782, GIR_Done, // Label 178: @4027 GIM_Try, /*On fail goto*//*Label 179*/ 4094, // Rule ID 10900 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i64] } (AArch64vlshr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm), FPR64:{ *:[i64] }:$Rd)<> => (USRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10900, GIR_Done, // Label 179: @4094 GIM_Try, /*On fail goto*//*Label 180*/ 4161, // Rule ID 11785 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v1i64] } (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm), FPR64:{ *:[v1i64] }:$Rd)<> => (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11785, GIR_Done, // Label 180: @4161 GIM_Try, /*On fail goto*//*Label 181*/ 4217, // Rule ID 970 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 550:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)) => (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 970, GIR_Done, // Label 181: @4217 GIM_Try, /*On fail goto*//*Label 182*/ 4273, // Rule ID 1031 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 615:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)) => (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1031, GIR_Done, // Label 182: @4273 GIM_Try, /*On fail goto*//*Label 183*/ 4340, // Rule ID 2037 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, (AArch64vashr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2037, GIR_Done, // Label 183: @4340 GIM_Try, /*On fail goto*//*Label 184*/ 4407, // Rule ID 9438 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9438, GIR_Done, // Label 184: @4407 GIM_Try, /*On fail goto*//*Label 185*/ 4474, // Rule ID 2046 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, (AArch64vlshr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2046, GIR_Done, // Label 185: @4474 GIM_Try, /*On fail goto*//*Label 186*/ 4541, // Rule ID 9444 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9444, GIR_Done, // Label 186: @4541 GIM_Try, /*On fail goto*//*Label 187*/ 4562, // Rule ID 96 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ADDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDXrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 96, GIR_Done, // Label 187: @4562 GIM_Try, /*On fail goto*//*Label 188*/ 4585, // Rule ID 1572 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (ADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv1i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1572, GIR_Done, // Label 188: @4585 GIM_Reject, // Label 148: @4586 GIM_Reject, // Label 122: @4587 GIM_Try, /*On fail goto*//*Label 189*/ 5385, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_Try, /*On fail goto*//*Label 190*/ 4665, // Rule ID 10741 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 549:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd) => (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10741, GIR_Done, // Label 190: @4665 GIM_Try, /*On fail goto*//*Label 191*/ 4733, // Rule ID 10753 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 614:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd) => (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10753, GIR_Done, // Label 191: @4733 GIM_Try, /*On fail goto*//*Label 192*/ 4789, // Rule ID 10703 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 550:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd) => (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10703, GIR_Done, // Label 192: @4789 GIM_Try, /*On fail goto*//*Label 193*/ 4845, // Rule ID 10715 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 615:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd) => (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10715, GIR_Done, // Label 193: @4845 GIM_Try, /*On fail goto*//*Label 194*/ 4912, // Rule ID 10917 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i32] } (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<>:$imm), V64:{ *:[v2i32] }:$Rd)<> => (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10917, GIR_Done, // Label 194: @4912 GIM_Try, /*On fail goto*//*Label 195*/ 4979, // Rule ID 10938 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<>:$imm), V64:{ *:[v2i32] }:$Rd)<> => (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10938, GIR_Done, // Label 195: @4979 GIM_Try, /*On fail goto*//*Label 196*/ 5047, // Rule ID 1328 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 549:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1328, GIR_Done, // Label 196: @5047 GIM_Try, /*On fail goto*//*Label 197*/ 5115, // Rule ID 1451 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 614:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1451, GIR_Done, // Label 197: @5115 GIM_Try, /*On fail goto*//*Label 198*/ 5171, // Rule ID 966 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 550:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 966, GIR_Done, // Label 198: @5171 GIM_Try, /*On fail goto*//*Label 199*/ 5227, // Rule ID 1027 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 615:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1027, GIR_Done, // Label 199: @5227 GIM_Try, /*On fail goto*//*Label 200*/ 5294, // Rule ID 2151 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2151, GIR_Done, // Label 200: @5294 GIM_Try, /*On fail goto*//*Label 201*/ 5361, // Rule ID 2210 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2210, GIR_Done, // Label 201: @5361 GIM_Try, /*On fail goto*//*Label 202*/ 5384, // Rule ID 1077 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1077, GIR_Done, // Label 202: @5384 GIM_Reject, // Label 189: @5385 GIM_Reject, // Label 123: @5386 GIM_Try, /*On fail goto*//*Label 203*/ 6840, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_Try, /*On fail goto*//*Label 204*/ 5477, // Rule ID 10783 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 549:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd) => (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10783, GIR_Done, // Label 204: @5477 GIM_Try, /*On fail goto*//*Label 205*/ 5558, // Rule ID 10807 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 614:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd) => (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10807, GIR_Done, // Label 205: @5558 GIM_Try, /*On fail goto*//*Label 206*/ 5639, // Rule ID 1661 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 549:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))) => (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1661, GIR_Done, // Label 206: @5639 GIM_Try, /*On fail goto*//*Label 207*/ 5720, // Rule ID 1739 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 614:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))) => (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1739, GIR_Done, // Label 207: @5720 GIM_Try, /*On fail goto*//*Label 208*/ 5776, // Rule ID 10709 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 550:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10709, GIR_Done, // Label 208: @5776 GIM_Try, /*On fail goto*//*Label 209*/ 5832, // Rule ID 10721 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 615:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10721, GIR_Done, // Label 209: @5832 GIM_Try, /*On fail goto*//*Label 210*/ 5899, // Rule ID 10921 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v2i64] }:$Rd)<> => (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10921, GIR_Done, // Label 210: @5899 GIM_Try, /*On fail goto*//*Label 211*/ 5966, // Rule ID 10942 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v2i64] }:$Rd)<> => (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10942, GIR_Done, // Label 211: @5966 GIM_Try, /*On fail goto*//*Label 212*/ 6022, // Rule ID 972 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 550:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 972, GIR_Done, // Label 212: @6022 GIM_Try, /*On fail goto*//*Label 213*/ 6078, // Rule ID 1033 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 615:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1033, GIR_Done, // Label 213: @6078 GIM_Try, /*On fail goto*//*Label 214*/ 6145, // Rule ID 2155 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2155, GIR_Done, // Label 214: @6145 GIM_Try, /*On fail goto*//*Label 215*/ 6212, // Rule ID 2214 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2214, GIR_Done, // Label 215: @6212 GIM_Try, /*On fail goto*//*Label 216*/ 6274, // Rule ID 1761 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1761, GIR_Done, // Label 216: @6274 GIM_Try, /*On fail goto*//*Label 217*/ 6336, // Rule ID 1760 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1760, GIR_Done, // Label 217: @6336 GIM_Try, /*On fail goto*//*Label 218*/ 6398, // Rule ID 1680 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1680, GIR_Done, // Label 218: @6398 GIM_Try, /*On fail goto*//*Label 219*/ 6460, // Rule ID 1759 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1759, GIR_Done, // Label 219: @6460 GIM_Try, /*On fail goto*//*Label 220*/ 6522, // Rule ID 1758 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1758, GIR_Done, // Label 220: @6522 GIM_Try, /*On fail goto*//*Label 221*/ 6571, // Rule ID 10819 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10819, GIR_Done, // Label 221: @6571 GIM_Try, /*On fail goto*//*Label 222*/ 6620, // Rule ID 10790 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn) => (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10790, GIR_Done, // Label 222: @6620 GIM_Try, /*On fail goto*//*Label 223*/ 6669, // Rule ID 10818 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10818, GIR_Done, // Label 223: @6669 GIM_Try, /*On fail goto*//*Label 224*/ 6718, // Rule ID 1775 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1775, GIR_Done, // Label 224: @6718 GIM_Try, /*On fail goto*//*Label 225*/ 6767, // Rule ID 1686 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1686, GIR_Done, // Label 225: @6767 GIM_Try, /*On fail goto*//*Label 226*/ 6816, // Rule ID 1774 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1774, GIR_Done, // Label 226: @6816 GIM_Try, /*On fail goto*//*Label 227*/ 6839, // Rule ID 1079 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1079, GIR_Done, // Label 227: @6839 GIM_Reject, // Label 203: @6840 GIM_Reject, // Label 124: @6841 GIM_Try, /*On fail goto*//*Label 228*/ 7639, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_Try, /*On fail goto*//*Label 229*/ 6919, // Rule ID 10737 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 549:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd) => (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10737, GIR_Done, // Label 229: @6919 GIM_Try, /*On fail goto*//*Label 230*/ 6987, // Rule ID 10749 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 614:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd) => (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10749, GIR_Done, // Label 230: @6987 GIM_Try, /*On fail goto*//*Label 231*/ 7043, // Rule ID 10699 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 550:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd) => (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10699, GIR_Done, // Label 231: @7043 GIM_Try, /*On fail goto*//*Label 232*/ 7099, // Rule ID 10711 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 615:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd) => (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10711, GIR_Done, // Label 232: @7099 GIM_Try, /*On fail goto*//*Label 233*/ 7166, // Rule ID 10913 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i16] } (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<>:$imm), V64:{ *:[v4i16] }:$Rd)<> => (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10913, GIR_Done, // Label 233: @7166 GIM_Try, /*On fail goto*//*Label 234*/ 7233, // Rule ID 10934 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<>:$imm), V64:{ *:[v4i16] }:$Rd)<> => (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10934, GIR_Done, // Label 234: @7233 GIM_Try, /*On fail goto*//*Label 235*/ 7301, // Rule ID 1324 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 549:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1324, GIR_Done, // Label 235: @7301 GIM_Try, /*On fail goto*//*Label 236*/ 7369, // Rule ID 1447 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 614:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1447, GIR_Done, // Label 236: @7369 GIM_Try, /*On fail goto*//*Label 237*/ 7425, // Rule ID 962 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 550:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 962, GIR_Done, // Label 237: @7425 GIM_Try, /*On fail goto*//*Label 238*/ 7481, // Rule ID 1023 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 615:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1023, GIR_Done, // Label 238: @7481 GIM_Try, /*On fail goto*//*Label 239*/ 7548, // Rule ID 2147 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2147, GIR_Done, // Label 239: @7548 GIM_Try, /*On fail goto*//*Label 240*/ 7615, // Rule ID 2206 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2206, GIR_Done, // Label 240: @7615 GIM_Try, /*On fail goto*//*Label 241*/ 7638, // Rule ID 1075 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1075, GIR_Done, // Label 241: @7638 GIM_Reject, // Label 228: @7639 GIM_Reject, // Label 125: @7640 GIM_Try, /*On fail goto*//*Label 242*/ 9366, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 243*/ 7731, // Rule ID 10779 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 549:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd) => (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10779, GIR_Done, // Label 243: @7731 GIM_Try, /*On fail goto*//*Label 244*/ 7812, // Rule ID 10803 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 614:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd) => (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10803, GIR_Done, // Label 244: @7812 GIM_Try, /*On fail goto*//*Label 245*/ 7893, // Rule ID 1657 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 549:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))) => (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1657, GIR_Done, // Label 245: @7893 GIM_Try, /*On fail goto*//*Label 246*/ 7974, // Rule ID 1735 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 614:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))) => (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1735, GIR_Done, // Label 246: @7974 GIM_Try, /*On fail goto*//*Label 247*/ 8042, // Rule ID 10743 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 549:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10743, GIR_Done, // Label 247: @8042 GIM_Try, /*On fail goto*//*Label 248*/ 8110, // Rule ID 10755 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 614:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10755, GIR_Done, // Label 248: @8110 GIM_Try, /*On fail goto*//*Label 249*/ 8166, // Rule ID 10705 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 550:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd) => (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10705, GIR_Done, // Label 249: @8166 GIM_Try, /*On fail goto*//*Label 250*/ 8222, // Rule ID 10717 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 615:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd) => (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10717, GIR_Done, // Label 250: @8222 GIM_Try, /*On fail goto*//*Label 251*/ 8289, // Rule ID 10919 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v4i32] }:$Rd)<> => (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10919, GIR_Done, // Label 251: @8289 GIM_Try, /*On fail goto*//*Label 252*/ 8356, // Rule ID 10940 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v4i32] }:$Rd)<> => (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10940, GIR_Done, // Label 252: @8356 GIM_Try, /*On fail goto*//*Label 253*/ 8424, // Rule ID 1330 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 549:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1330, GIR_Done, // Label 253: @8424 GIM_Try, /*On fail goto*//*Label 254*/ 8492, // Rule ID 1453 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 614:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1453, GIR_Done, // Label 254: @8492 GIM_Try, /*On fail goto*//*Label 255*/ 8548, // Rule ID 968 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 550:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 968, GIR_Done, // Label 255: @8548 GIM_Try, /*On fail goto*//*Label 256*/ 8604, // Rule ID 1029 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 615:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1029, GIR_Done, // Label 256: @8604 GIM_Try, /*On fail goto*//*Label 257*/ 8671, // Rule ID 2153 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2153, GIR_Done, // Label 257: @8671 GIM_Try, /*On fail goto*//*Label 258*/ 8738, // Rule ID 2212 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2212, GIR_Done, // Label 258: @8738 GIM_Try, /*On fail goto*//*Label 259*/ 8800, // Rule ID 1753 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1753, GIR_Done, // Label 259: @8800 GIM_Try, /*On fail goto*//*Label 260*/ 8862, // Rule ID 1752 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1752, GIR_Done, // Label 260: @8862 GIM_Try, /*On fail goto*//*Label 261*/ 8924, // Rule ID 1678 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1678, GIR_Done, // Label 261: @8924 GIM_Try, /*On fail goto*//*Label 262*/ 8986, // Rule ID 1751 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1751, GIR_Done, // Label 262: @8986 GIM_Try, /*On fail goto*//*Label 263*/ 9048, // Rule ID 1750 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1750, GIR_Done, // Label 263: @9048 GIM_Try, /*On fail goto*//*Label 264*/ 9097, // Rule ID 10815 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10815, GIR_Done, // Label 264: @9097 GIM_Try, /*On fail goto*//*Label 265*/ 9146, // Rule ID 10788 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn) => (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10788, GIR_Done, // Label 265: @9146 GIM_Try, /*On fail goto*//*Label 266*/ 9195, // Rule ID 10814 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10814, GIR_Done, // Label 266: @9195 GIM_Try, /*On fail goto*//*Label 267*/ 9244, // Rule ID 1771 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1771, GIR_Done, // Label 267: @9244 GIM_Try, /*On fail goto*//*Label 268*/ 9293, // Rule ID 1684 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1684, GIR_Done, // Label 268: @9293 GIM_Try, /*On fail goto*//*Label 269*/ 9342, // Rule ID 1770 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1770, GIR_Done, // Label 269: @9342 GIM_Try, /*On fail goto*//*Label 270*/ 9365, // Rule ID 1078 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1078, GIR_Done, // Label 270: @9365 GIM_Reject, // Label 242: @9366 GIM_Reject, // Label 126: @9367 GIM_Try, /*On fail goto*//*Label 271*/ 9941, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_Try, /*On fail goto*//*Label 272*/ 9445, // Rule ID 10733 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 549:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd) => (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10733, GIR_Done, // Label 272: @9445 GIM_Try, /*On fail goto*//*Label 273*/ 9513, // Rule ID 10745 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 614:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd) => (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10745, GIR_Done, // Label 273: @9513 GIM_Try, /*On fail goto*//*Label 274*/ 9580, // Rule ID 10909 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i8] } (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<>:$imm), V64:{ *:[v8i8] }:$Rd)<> => (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10909, GIR_Done, // Label 274: @9580 GIM_Try, /*On fail goto*//*Label 275*/ 9647, // Rule ID 10930 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<>:$imm), V64:{ *:[v8i8] }:$Rd)<> => (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10930, GIR_Done, // Label 275: @9647 GIM_Try, /*On fail goto*//*Label 276*/ 9715, // Rule ID 1320 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 549:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1320, GIR_Done, // Label 276: @9715 GIM_Try, /*On fail goto*//*Label 277*/ 9783, // Rule ID 1443 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 614:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1443, GIR_Done, // Label 277: @9783 GIM_Try, /*On fail goto*//*Label 278*/ 9850, // Rule ID 2143 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2143, GIR_Done, // Label 278: @9850 GIM_Try, /*On fail goto*//*Label 279*/ 9917, // Rule ID 2202 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2202, GIR_Done, // Label 279: @9917 GIM_Try, /*On fail goto*//*Label 280*/ 9940, // Rule ID 1073 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1073, GIR_Done, // Label 280: @9940 GIM_Reject, // Label 271: @9941 GIM_Reject, // Label 127: @9942 GIM_Try, /*On fail goto*//*Label 281*/ 11668, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 282*/ 10033, // Rule ID 10775 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 549:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd) => (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10775, GIR_Done, // Label 282: @10033 GIM_Try, /*On fail goto*//*Label 283*/ 10114, // Rule ID 10799 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 614:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd) => (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10799, GIR_Done, // Label 283: @10114 GIM_Try, /*On fail goto*//*Label 284*/ 10195, // Rule ID 1653 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 549:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))) => (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1653, GIR_Done, // Label 284: @10195 GIM_Try, /*On fail goto*//*Label 285*/ 10276, // Rule ID 1731 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 614:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))) => (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1731, GIR_Done, // Label 285: @10276 GIM_Try, /*On fail goto*//*Label 286*/ 10344, // Rule ID 10739 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 549:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10739, GIR_Done, // Label 286: @10344 GIM_Try, /*On fail goto*//*Label 287*/ 10412, // Rule ID 10751 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 614:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10751, GIR_Done, // Label 287: @10412 GIM_Try, /*On fail goto*//*Label 288*/ 10468, // Rule ID 10701 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 550:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd) => (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10701, GIR_Done, // Label 288: @10468 GIM_Try, /*On fail goto*//*Label 289*/ 10524, // Rule ID 10713 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 615:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd) => (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10713, GIR_Done, // Label 289: @10524 GIM_Try, /*On fail goto*//*Label 290*/ 10591, // Rule ID 10915 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v8i16] }:$Rd)<> => (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10915, GIR_Done, // Label 290: @10591 GIM_Try, /*On fail goto*//*Label 291*/ 10658, // Rule ID 10936 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v8i16] }:$Rd)<> => (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10936, GIR_Done, // Label 291: @10658 GIM_Try, /*On fail goto*//*Label 292*/ 10726, // Rule ID 1326 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 549:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1326, GIR_Done, // Label 292: @10726 GIM_Try, /*On fail goto*//*Label 293*/ 10794, // Rule ID 1449 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 614:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1449, GIR_Done, // Label 293: @10794 GIM_Try, /*On fail goto*//*Label 294*/ 10850, // Rule ID 964 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 550:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 964, GIR_Done, // Label 294: @10850 GIM_Try, /*On fail goto*//*Label 295*/ 10906, // Rule ID 1025 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 615:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1025, GIR_Done, // Label 295: @10906 GIM_Try, /*On fail goto*//*Label 296*/ 10973, // Rule ID 2149 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2149, GIR_Done, // Label 296: @10973 GIM_Try, /*On fail goto*//*Label 297*/ 11040, // Rule ID 2208 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2208, GIR_Done, // Label 297: @11040 GIM_Try, /*On fail goto*//*Label 298*/ 11102, // Rule ID 1745 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1745, GIR_Done, // Label 298: @11102 GIM_Try, /*On fail goto*//*Label 299*/ 11164, // Rule ID 1744 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1744, GIR_Done, // Label 299: @11164 GIM_Try, /*On fail goto*//*Label 300*/ 11226, // Rule ID 1676 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1676, GIR_Done, // Label 300: @11226 GIM_Try, /*On fail goto*//*Label 301*/ 11288, // Rule ID 1743 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1743, GIR_Done, // Label 301: @11288 GIM_Try, /*On fail goto*//*Label 302*/ 11350, // Rule ID 1742 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1742, GIR_Done, // Label 302: @11350 GIM_Try, /*On fail goto*//*Label 303*/ 11399, // Rule ID 10811 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10811, GIR_Done, // Label 303: @11399 GIM_Try, /*On fail goto*//*Label 304*/ 11448, // Rule ID 10786 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn) => (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10786, GIR_Done, // Label 304: @11448 GIM_Try, /*On fail goto*//*Label 305*/ 11497, // Rule ID 10810 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10810, GIR_Done, // Label 305: @11497 GIM_Try, /*On fail goto*//*Label 306*/ 11546, // Rule ID 1767 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1767, GIR_Done, // Label 306: @11546 GIM_Try, /*On fail goto*//*Label 307*/ 11595, // Rule ID 1682 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1682, GIR_Done, // Label 307: @11595 GIM_Try, /*On fail goto*//*Label 308*/ 11644, // Rule ID 1766 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1766, GIR_Done, // Label 308: @11644 GIM_Try, /*On fail goto*//*Label 309*/ 11667, // Rule ID 1076 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1076, GIR_Done, // Label 309: @11667 GIM_Reject, // Label 281: @11668 GIM_Reject, // Label 128: @11669 GIM_Try, /*On fail goto*//*Label 310*/ 12243, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 311*/ 11747, // Rule ID 10735 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 549:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd) => (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10735, GIR_Done, // Label 311: @11747 GIM_Try, /*On fail goto*//*Label 312*/ 11815, // Rule ID 10747 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 614:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd) => (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10747, GIR_Done, // Label 312: @11815 GIM_Try, /*On fail goto*//*Label 313*/ 11882, // Rule ID 10911 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v16i8] } (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v16i8] }:$Rd)<> => (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10911, GIR_Done, // Label 313: @11882 GIM_Try, /*On fail goto*//*Label 314*/ 11949, // Rule ID 10932 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v16i8] } (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v16i8] }:$Rd)<> => (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10932, GIR_Done, // Label 314: @11949 GIM_Try, /*On fail goto*//*Label 315*/ 12017, // Rule ID 1322 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 549:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) => (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1322, GIR_Done, // Label 315: @12017 GIM_Try, /*On fail goto*//*Label 316*/ 12085, // Rule ID 1445 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 614:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) => (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1445, GIR_Done, // Label 316: @12085 GIM_Try, /*On fail goto*//*Label 317*/ 12152, // Rule ID 2145 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2145, GIR_Done, // Label 317: @12152 GIM_Try, /*On fail goto*//*Label 318*/ 12219, // Rule ID 2204 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2204, GIR_Done, // Label 318: @12219 GIM_Try, /*On fail goto*//*Label 319*/ 12242, // Rule ID 1074 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1074, GIR_Done, // Label 319: @12242 GIM_Reject, // Label 310: @12243 GIM_Reject, // Label 129: @12244 GIM_Reject, // Label 1: @12245 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 329*/ 16112, /*GILLT_s32*//*Label 320*/ 12261, /*GILLT_s64*//*Label 321*/ 13048, 0, /*GILLT_v2s32*//*Label 322*/ 14340, /*GILLT_v2s64*//*Label 323*/ 14411, /*GILLT_v4s16*//*Label 324*/ 14907, /*GILLT_v4s32*//*Label 325*/ 14978, /*GILLT_v8s8*//*Label 326*/ 15474, /*GILLT_v8s16*//*Label 327*/ 15545, /*GILLT_v16s8*//*Label 328*/ 16041, // Label 320: @12261 GIM_Try, /*On fail goto*//*Label 330*/ 13047, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 331*/ 12410, // Rule ID 4534 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_sve_cntb, // MIs[2] pattern GIM_CheckIsImm, /*MI*/2, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 887:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (DECB_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_AddImm, /*InsnID*/2, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::DECB_XPiI, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::sub_32, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64RegClassID, // GIR_Coverage, 4534, GIR_Done, // Label 331: @12410 GIM_Try, /*On fail goto*//*Label 332*/ 12549, // Rule ID 4546 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_sve_cnth, // MIs[2] pattern GIM_CheckIsImm, /*MI*/2, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 889:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (DECH_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_AddImm, /*InsnID*/2, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::DECH_XPiI, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::sub_32, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64RegClassID, // GIR_Coverage, 4546, GIR_Done, // Label 332: @12549 GIM_Try, /*On fail goto*//*Label 333*/ 12688, // Rule ID 4558 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_sve_cntw, // MIs[2] pattern GIM_CheckIsImm, /*MI*/2, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 891:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (DECW_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_AddImm, /*InsnID*/2, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::DECW_XPiI, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::sub_32, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64RegClassID, // GIR_Coverage, 4558, GIR_Done, // Label 333: @12688 GIM_Try, /*On fail goto*//*Label 334*/ 12827, // Rule ID 4570 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_sve_cntd, // MIs[2] pattern GIM_CheckIsImm, /*MI*/2, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 888:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (DECD_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_AddImm, /*InsnID*/2, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::DECD_XPiI, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::sub_32, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64RegClassID, // GIR_Coverage, 4570, GIR_Done, // Label 334: @12827 GIM_Try, /*On fail goto*//*Label 335*/ 12886, // Rule ID 7915 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i32] } 0:{ *:[i32] }, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)) => (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7915, GIR_Done, // Label 335: @12886 GIM_Try, /*On fail goto*//*Label 336*/ 12920, // Rule ID 7880 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_extended_reg32_i32, // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3) => (SUBSWrx:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWrx, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // R2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // R3 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7880, GIR_Done, // Label 336: @12920 GIM_Try, /*On fail goto*//*Label 337*/ 12954, // Rule ID 7885 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm32, // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) => (ADDWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7885, GIR_Done, // Label 337: @12954 GIM_Try, /*On fail goto*//*Label 338*/ 12988, // Rule ID 7874 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32, // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) => (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7874, GIR_Done, // Label 338: @12988 GIM_Try, /*On fail goto*//*Label 339*/ 13022, // Rule ID 7878 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_shifted_reg32, // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm) => (SUBSWrs:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7878, GIR_Done, // Label 339: @13022 GIM_Try, /*On fail goto*//*Label 340*/ 13046, // Rule ID 7876 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SUBSWrr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSWrr, GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7876, GIR_Done, // Label 340: @13046 GIM_Reject, // Label 330: @13047 GIM_Reject, // Label 321: @13048 GIM_Try, /*On fail goto*//*Label 341*/ 14339, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 342*/ 13154, // Rule ID 7930 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C)) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7930, GIR_Done, // Label 342: @13154 GIM_Try, /*On fail goto*//*Label 343*/ 13250, // Rule ID 7931 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C)) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7931, GIR_Done, // Label 343: @13250 GIM_Try, /*On fail goto*//*Label 344*/ 13335, // Rule ID 7925 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7925, GIR_Done, // Label 344: @13335 GIM_Try, /*On fail goto*//*Label 345*/ 13420, // Rule ID 7926 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7926, GIR_Done, // Label 345: @13420 GIM_Try, /*On fail goto*//*Label 346*/ 13516, // Rule ID 7936 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C)) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7936, GIR_Done, // Label 346: @13516 GIM_Try, /*On fail goto*//*Label 347*/ 13612, // Rule ID 7937 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C)) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7937, GIR_Done, // Label 347: @13612 GIM_Try, /*On fail goto*//*Label 348*/ 13697, // Rule ID 126 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 126, GIR_Done, // Label 348: @13697 GIM_Try, /*On fail goto*//*Label 349*/ 13782, // Rule ID 128 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 128, GIR_Done, // Label 349: @13782 GIM_Try, /*On fail goto*//*Label 350*/ 13841, // Rule ID 7916 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)) => (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7916, GIR_Done, // Label 350: @13841 GIM_Try, /*On fail goto*//*Label 351*/ 13900, // Rule ID 4531 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_sve_cntb, // MIs[1] pattern GIM_CheckIsImm, /*MI*/1, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 887:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern)) => (DECB_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DECB_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4531, GIR_Done, // Label 351: @13900 GIM_Try, /*On fail goto*//*Label 352*/ 13959, // Rule ID 4543 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_sve_cnth, // MIs[1] pattern GIM_CheckIsImm, /*MI*/1, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 889:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern)) => (DECH_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DECH_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4543, GIR_Done, // Label 352: @13959 GIM_Try, /*On fail goto*//*Label 353*/ 14018, // Rule ID 4555 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_sve_cntw, // MIs[1] pattern GIM_CheckIsImm, /*MI*/1, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 891:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern)) => (DECW_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DECW_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4555, GIR_Done, // Label 353: @14018 GIM_Try, /*On fail goto*//*Label 354*/ 14077, // Rule ID 4567 // GIM_CheckFeatures, GIFBS_HasSVEorSME_UseScalarIncVL, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_sve_cntd, // MIs[1] pattern GIM_CheckIsImm, /*MI*/1, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 888:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern)) => (DECD_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DECD_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4567, GIR_Done, // Label 354: @14077 GIM_Try, /*On fail goto*//*Label 355*/ 14111, // Rule ID 7881 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_extended_reg32to64_i64, // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3) => (SUBSXrx:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXrx, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // R2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // R3 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7881, GIR_Done, // Label 355: @14111 GIM_Try, /*On fail goto*//*Label 356*/ 14145, // Rule ID 7886 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm64, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) => (ADDXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7886, GIR_Done, // Label 356: @14145 GIM_Try, /*On fail goto*//*Label 357*/ 14179, // Rule ID 7875 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64, // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) => (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7875, GIR_Done, // Label 357: @14179 GIM_Try, /*On fail goto*//*Label 358*/ 14213, // Rule ID 7879 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_shifted_reg64, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm) => (SUBSXrs:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7879, GIR_Done, // Label 358: @14213 GIM_Try, /*On fail goto*//*Label 359*/ 14253, // Rule ID 1619 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllZeros, /*MI*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v1i64] } immAllZerosV:{ *:[v1i64] }, FPR64:{ *:[v1i64] }:$Rn) => (NEGv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1619, GIR_Done, // Label 359: @14253 GIM_Try, /*On fail goto*//*Label 360*/ 14291, // Rule ID 8716 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllZeros, /*MI*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i64] } immAllZerosV:{ *:[i64] }, FPR64:{ *:[i64] }:$Rn) => (NEGv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8716, GIR_Done, // Label 360: @14291 GIM_Try, /*On fail goto*//*Label 361*/ 14314, // Rule ID 1609 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (sub:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv1i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1609, GIR_Done, // Label 361: @14314 GIM_Try, /*On fail goto*//*Label 362*/ 14338, // Rule ID 7877 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SUBSXrr:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSXrr, GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7877, GIR_Done, // Label 362: @14338 GIM_Reject, // Label 341: @14339 GIM_Reject, // Label 322: @14340 GIM_Try, /*On fail goto*//*Label 363*/ 14410, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 364*/ 14390, // Rule ID 942 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllZeros, /*MI*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn) => (NEGv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 942, GIR_Done, // Label 364: @14390 GIM_Try, /*On fail goto*//*Label 365*/ 14409, // Rule ID 1439 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1439, GIR_Done, // Label 365: @14409 GIM_Reject, // Label 363: @14410 GIM_Reject, // Label 323: @14411 GIM_Try, /*On fail goto*//*Label 366*/ 14906, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 367*/ 14483, // Rule ID 1815 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1815, GIR_Done, // Label 367: @14483 GIM_Try, /*On fail goto*//*Label 368*/ 14541, // Rule ID 1814 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1814, GIR_Done, // Label 368: @14541 GIM_Try, /*On fail goto*//*Label 369*/ 14599, // Rule ID 1722 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SSUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1722, GIR_Done, // Label 369: @14599 GIM_Try, /*On fail goto*//*Label 370*/ 14657, // Rule ID 1813 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1813, GIR_Done, // Label 370: @14657 GIM_Try, /*On fail goto*//*Label 371*/ 14715, // Rule ID 1812 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1812, GIR_Done, // Label 371: @14715 GIM_Try, /*On fail goto*//*Label 372*/ 14751, // Rule ID 944 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllZeros, /*MI*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn) => (NEGv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 944, GIR_Done, // Label 372: @14751 GIM_Try, /*On fail goto*//*Label 373*/ 14796, // Rule ID 1829 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1829, GIR_Done, // Label 373: @14796 GIM_Try, /*On fail goto*//*Label 374*/ 14841, // Rule ID 1728 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SSUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1728, GIR_Done, // Label 374: @14841 GIM_Try, /*On fail goto*//*Label 375*/ 14886, // Rule ID 1828 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1828, GIR_Done, // Label 375: @14886 GIM_Try, /*On fail goto*//*Label 376*/ 14905, // Rule ID 1441 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1441, GIR_Done, // Label 376: @14905 GIM_Reject, // Label 366: @14906 GIM_Reject, // Label 324: @14907 GIM_Try, /*On fail goto*//*Label 377*/ 14977, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 378*/ 14957, // Rule ID 940 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllZeros, /*MI*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn) => (NEGv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 940, GIR_Done, // Label 378: @14957 GIM_Try, /*On fail goto*//*Label 379*/ 14976, // Rule ID 1437 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1437, GIR_Done, // Label 379: @14976 GIM_Reject, // Label 377: @14977 GIM_Reject, // Label 325: @14978 GIM_Try, /*On fail goto*//*Label 380*/ 15473, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 381*/ 15050, // Rule ID 1807 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1807, GIR_Done, // Label 381: @15050 GIM_Try, /*On fail goto*//*Label 382*/ 15108, // Rule ID 1806 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1806, GIR_Done, // Label 382: @15108 GIM_Try, /*On fail goto*//*Label 383*/ 15166, // Rule ID 1720 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SSUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1720, GIR_Done, // Label 383: @15166 GIM_Try, /*On fail goto*//*Label 384*/ 15224, // Rule ID 1805 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1805, GIR_Done, // Label 384: @15224 GIM_Try, /*On fail goto*//*Label 385*/ 15282, // Rule ID 1804 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1804, GIR_Done, // Label 385: @15282 GIM_Try, /*On fail goto*//*Label 386*/ 15318, // Rule ID 943 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllZeros, /*MI*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn) => (NEGv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 943, GIR_Done, // Label 386: @15318 GIM_Try, /*On fail goto*//*Label 387*/ 15363, // Rule ID 1825 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1825, GIR_Done, // Label 387: @15363 GIM_Try, /*On fail goto*//*Label 388*/ 15408, // Rule ID 1726 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SSUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1726, GIR_Done, // Label 388: @15408 GIM_Try, /*On fail goto*//*Label 389*/ 15453, // Rule ID 1824 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1824, GIR_Done, // Label 389: @15453 GIM_Try, /*On fail goto*//*Label 390*/ 15472, // Rule ID 1440 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1440, GIR_Done, // Label 390: @15472 GIM_Reject, // Label 380: @15473 GIM_Reject, // Label 326: @15474 GIM_Try, /*On fail goto*//*Label 391*/ 15544, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 392*/ 15524, // Rule ID 938 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllZeros, /*MI*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn) => (NEGv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 938, GIR_Done, // Label 392: @15524 GIM_Try, /*On fail goto*//*Label 393*/ 15543, // Rule ID 1435 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1435, GIR_Done, // Label 393: @15543 GIM_Reject, // Label 391: @15544 GIM_Reject, // Label 327: @15545 GIM_Try, /*On fail goto*//*Label 394*/ 16040, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 395*/ 15617, // Rule ID 1799 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1799, GIR_Done, // Label 395: @15617 GIM_Try, /*On fail goto*//*Label 396*/ 15675, // Rule ID 1798 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1798, GIR_Done, // Label 396: @15675 GIM_Try, /*On fail goto*//*Label 397*/ 15733, // Rule ID 1718 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SSUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1718, GIR_Done, // Label 397: @15733 GIM_Try, /*On fail goto*//*Label 398*/ 15791, // Rule ID 1797 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1797, GIR_Done, // Label 398: @15791 GIM_Try, /*On fail goto*//*Label 399*/ 15849, // Rule ID 1796 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1796, GIR_Done, // Label 399: @15849 GIM_Try, /*On fail goto*//*Label 400*/ 15885, // Rule ID 941 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllZeros, /*MI*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn) => (NEGv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 941, GIR_Done, // Label 400: @15885 GIM_Try, /*On fail goto*//*Label 401*/ 15930, // Rule ID 1821 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1821, GIR_Done, // Label 401: @15930 GIM_Try, /*On fail goto*//*Label 402*/ 15975, // Rule ID 1724 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SSUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1724, GIR_Done, // Label 402: @15975 GIM_Try, /*On fail goto*//*Label 403*/ 16020, // Rule ID 1820 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1820, GIR_Done, // Label 403: @16020 GIM_Try, /*On fail goto*//*Label 404*/ 16039, // Rule ID 1438 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1438, GIR_Done, // Label 404: @16039 GIM_Reject, // Label 394: @16040 GIM_Reject, // Label 328: @16041 GIM_Try, /*On fail goto*//*Label 405*/ 16111, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 406*/ 16091, // Rule ID 939 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllZeros, /*MI*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn) => (NEGv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 939, GIR_Done, // Label 406: @16091 GIM_Try, /*On fail goto*//*Label 407*/ 16110, // Rule ID 1436 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (sub:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1436, GIR_Done, // Label 407: @16110 GIM_Reject, // Label 405: @16111 GIM_Reject, // Label 329: @16112 GIM_Reject, // Label 2: @16113 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 416*/ 17427, /*GILLT_s32*//*Label 408*/ 16129, /*GILLT_s64*//*Label 409*/ 16289, 0, /*GILLT_v2s32*//*Label 410*/ 16711, 0, /*GILLT_v4s16*//*Label 411*/ 16874, /*GILLT_v4s32*//*Label 412*/ 17037, /*GILLT_v8s8*//*Label 413*/ 17200, /*GILLT_v8s16*//*Label 414*/ 17232, /*GILLT_v16s8*//*Label 415*/ 17395, // Label 408: @16129 GIM_Try, /*On fail goto*//*Label 417*/ 16288, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 418*/ 16198, // Rule ID 7917 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (mul:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn), GPR32:{ *:[i32] }:$Rm) => (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7917, GIR_Done, // Label 418: @16198 GIM_Try, /*On fail goto*//*Label 419*/ 16253, // Rule ID 11660 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn)) => (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11660, GIR_Done, // Label 419: @16253 GIM_Try, /*On fail goto*//*Label 420*/ 16287, // Rule ID 7913 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (MADDWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MADDWrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7913, GIR_Done, // Label 420: @16287 GIM_Reject, // Label 417: @16288 GIM_Reject, // Label 409: @16289 GIM_Try, /*On fail goto*//*Label 421*/ 16710, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 422*/ 16358, // Rule ID 7918 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (mul:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn), GPR64:{ *:[i64] }:$Rm) => (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7918, GIR_Done, // Label 422: @16358 GIM_Try, /*On fail goto*//*Label 423*/ 16413, // Rule ID 11661 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn)) => (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11661, GIR_Done, // Label 423: @16413 GIM_Try, /*On fail goto*//*Label 424*/ 16484, // Rule ID 7927 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7927, GIR_Done, // Label 424: @16484 GIM_Try, /*On fail goto*//*Label 425*/ 16555, // Rule ID 7928 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7928, GIR_Done, // Label 425: @16555 GIM_Try, /*On fail goto*//*Label 426*/ 16615, // Rule ID 7921 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7921, GIR_Done, // Label 426: @16615 GIM_Try, /*On fail goto*//*Label 427*/ 16675, // Rule ID 7924 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7924, GIR_Done, // Label 427: @16675 GIM_Try, /*On fail goto*//*Label 428*/ 16709, // Rule ID 7914 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (MADDXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MADDXrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7914, GIR_Done, // Label 428: @16709 GIM_Reject, // Label 421: @16710 GIM_Reject, // Label 410: @16711 GIM_Try, /*On fail goto*//*Label 429*/ 16873, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 430*/ 16789, // Rule ID 10854 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[v2i32] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v2i32] }:$Rn) => (MULv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10854, GIR_Done, // Label 430: @16789 GIM_Try, /*On fail goto*//*Label 431*/ 16853, // Rule ID 1975 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (MULv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1975, GIR_Done, // Label 431: @16853 GIM_Try, /*On fail goto*//*Label 432*/ 16872, // Rule ID 1315 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (MULv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1315, GIR_Done, // Label 432: @16872 GIM_Reject, // Label 429: @16873 GIM_Reject, // Label 411: @16874 GIM_Try, /*On fail goto*//*Label 433*/ 17036, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 434*/ 16952, // Rule ID 10852 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[v4i16] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v4i16] }:$Rn) => (MULv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10852, GIR_Done, // Label 434: @16952 GIM_Try, /*On fail goto*//*Label 435*/ 17016, // Rule ID 1973 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (MULv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1973, GIR_Done, // Label 435: @17016 GIM_Try, /*On fail goto*//*Label 436*/ 17035, // Rule ID 1313 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (MULv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1313, GIR_Done, // Label 436: @17035 GIM_Reject, // Label 433: @17036 GIM_Reject, // Label 412: @17037 GIM_Try, /*On fail goto*//*Label 437*/ 17199, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 438*/ 17115, // Rule ID 10855 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[v4i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v4i32] }:$Rn) => (MULv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10855, GIR_Done, // Label 438: @17115 GIM_Try, /*On fail goto*//*Label 439*/ 17179, // Rule ID 1976 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (MULv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1976, GIR_Done, // Label 439: @17179 GIM_Try, /*On fail goto*//*Label 440*/ 17198, // Rule ID 1316 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (MULv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1316, GIR_Done, // Label 440: @17198 GIM_Reject, // Label 437: @17199 GIM_Reject, // Label 413: @17200 GIM_Try, /*On fail goto*//*Label 441*/ 17231, // Rule ID 1311 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (MULv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1311, GIR_Done, // Label 441: @17231 GIM_Reject, // Label 414: @17232 GIM_Try, /*On fail goto*//*Label 442*/ 17394, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 443*/ 17310, // Rule ID 10853 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[v8i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v8i16] }:$Rn) => (MULv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10853, GIR_Done, // Label 443: @17310 GIM_Try, /*On fail goto*//*Label 444*/ 17374, // Rule ID 1974 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (MULv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1974, GIR_Done, // Label 444: @17374 GIM_Try, /*On fail goto*//*Label 445*/ 17393, // Rule ID 1314 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (MULv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1314, GIR_Done, // Label 445: @17393 GIM_Reject, // Label 442: @17394 GIM_Reject, // Label 415: @17395 GIM_Try, /*On fail goto*//*Label 446*/ 17426, // Rule ID 1312 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (MULv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1312, GIR_Done, // Label 446: @17426 GIM_Reject, // Label 416: @17427 GIM_Reject, // Label 3: @17428 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 449*/ 17496, /*GILLT_s32*//*Label 447*/ 17436, /*GILLT_s64*//*Label 448*/ 17466, // Label 447: @17436 GIM_Try, /*On fail goto*//*Label 450*/ 17465, // Rule ID 119 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SDIVWr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 119, GIR_Done, // Label 450: @17465 GIM_Reject, // Label 448: @17466 GIM_Try, /*On fail goto*//*Label 451*/ 17495, // Rule ID 120 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (sdiv:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SDIVXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 120, GIR_Done, // Label 451: @17495 GIM_Reject, // Label 449: @17496 GIM_Reject, // Label 4: @17497 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 454*/ 17565, /*GILLT_s32*//*Label 452*/ 17505, /*GILLT_s64*//*Label 453*/ 17535, // Label 452: @17505 GIM_Try, /*On fail goto*//*Label 455*/ 17534, // Rule ID 117 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (UDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UDIVWr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 117, GIR_Done, // Label 455: @17534 GIM_Reject, // Label 453: @17535 GIM_Try, /*On fail goto*//*Label 456*/ 17564, // Rule ID 118 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (udiv:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UDIVXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 118, GIR_Done, // Label 456: @17564 GIM_Reject, // Label 454: @17565 GIM_Reject, // Label 5: @17566 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 22, /*)*//*default:*//*Label 471*/ 20737, /*GILLT_s32*//*Label 457*/ 17593, /*GILLT_s64*//*Label 458*/ 18080, 0, /*GILLT_v2s32*//*Label 459*/ 19318, /*GILLT_v2s64*//*Label 460*/ 19475, /*GILLT_v4s16*//*Label 461*/ 19632, /*GILLT_v4s32*//*Label 462*/ 19789, /*GILLT_v8s8*//*Label 463*/ 19946, /*GILLT_v8s16*//*Label 464*/ 20103, /*GILLT_v16s8*//*Label 465*/ 20260, /*GILLT_nxv1s1*//*Label 466*/ 20417, /*GILLT_nxv2s1*//*Label 467*/ 20481, 0, 0, 0, /*GILLT_nxv4s1*//*Label 468*/ 20545, 0, 0, /*GILLT_nxv8s1*//*Label 469*/ 20609, 0, /*GILLT_nxv16s1*//*Label 470*/ 20673, // Label 457: @17593 GIM_Try, /*On fail goto*//*Label 472*/ 18079, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 473*/ 17658, // Rule ID 10644 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (and:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (BICWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10644, GIR_Done, // Label 473: @17658 GIM_Try, /*On fail goto*//*Label 474*/ 17713, // Rule ID 164 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] })) => (BICWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 164, GIR_Done, // Label 474: @17713 GIM_Try, /*On fail goto*//*Label 475*/ 17775, // Rule ID 8991 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<>:$idx), 255:{ *:[i32] }) => (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8991, GIR_Done, // Label 475: @17775 GIM_Try, /*On fail goto*//*Label 476*/ 17837, // Rule ID 8992 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<>:$idx), 65535:{ *:[i32] }) => (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8992, GIR_Done, // Label 476: @17837 GIM_Try, /*On fail goto*//*Label 477*/ 17892, // Rule ID 10642 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (BICWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10642, GIR_Done, // Label 477: @17892 GIM_Try, /*On fail goto*//*Label 478*/ 17947, // Rule ID 162 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 162, GIR_Done, // Label 478: @17947 GIM_Try, /*On fail goto*//*Label 479*/ 17989, // Rule ID 144 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<><>:$imm) => (ANDWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm32, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 144, GIR_Done, // Label 479: @17989 GIM_Try, /*On fail goto*//*Label 480*/ 18023, // Rule ID 10640 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (and:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn) => (ANDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10640, GIR_Done, // Label 480: @18023 GIM_Try, /*On fail goto*//*Label 481*/ 18057, // Rule ID 160 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) => (ANDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 160, GIR_Done, // Label 481: @18057 GIM_Try, /*On fail goto*//*Label 482*/ 18078, // Rule ID 158 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ANDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDWrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 158, GIR_Done, // Label 482: @18078 GIM_Reject, // Label 472: @18079 GIM_Reject, // Label 458: @18080 GIM_Try, /*On fail goto*//*Label 483*/ 19317, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 484*/ 18145, // Rule ID 10645 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (and:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (BICXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10645, GIR_Done, // Label 484: @18145 GIM_Try, /*On fail goto*//*Label 485*/ 18200, // Rule ID 165 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] })) => (BICXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 165, GIR_Done, // Label 485: @18200 GIM_Try, /*On fail goto*//*Label 486*/ 18303, // Rule ID 8993 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, // MIs[3] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (and:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<>:$idx)), 255:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<>:$idx), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::UMOVvi8, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // idx GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8993, GIR_Done, // Label 486: @18303 GIM_Try, /*On fail goto*//*Label 487*/ 18406, // Rule ID 8994 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (and:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<>:$idx)), 65535:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<>:$idx), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::UMOVvi16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // idx GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8994, GIR_Done, // Label 487: @18406 GIM_Try, /*On fail goto*//*Label 488*/ 18492, // Rule ID 10248 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldxr, // MIs[1] addr GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldxr_1, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 476:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<>, 255:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRB, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 10248, GIR_Done, // Label 488: @18492 GIM_Try, /*On fail goto*//*Label 489*/ 18578, // Rule ID 10249 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldxr, // MIs[1] addr GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldxr_2, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 476:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<>, 65535:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 10249, GIR_Done, // Label 489: @18578 GIM_Try, /*On fail goto*//*Label 490*/ 18664, // Rule ID 10250 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldxr, // MIs[1] addr GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldxr_4, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294967295, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 476:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<>, 4294967295:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 10250, GIR_Done, // Label 490: @18664 GIM_Try, /*On fail goto*//*Label 491*/ 18750, // Rule ID 10255 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldaxr, // MIs[1] addr GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldaxr_1, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 473:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<>, 255:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRB, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 10255, GIR_Done, // Label 491: @18750 GIM_Try, /*On fail goto*//*Label 492*/ 18836, // Rule ID 10256 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldaxr, // MIs[1] addr GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldaxr_2, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 473:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<>, 65535:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 10256, GIR_Done, // Label 492: @18836 GIM_Try, /*On fail goto*//*Label 493*/ 18922, // Rule ID 10257 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldaxr, // MIs[1] addr GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldaxr_4, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294967295, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 473:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<>, 4294967295:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 10257, GIR_Done, // Label 493: @18922 GIM_Try, /*On fail goto*//*Label 494*/ 18977, // Rule ID 10643 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (BICXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10643, GIR_Done, // Label 494: @18977 GIM_Try, /*On fail goto*//*Label 495*/ 19032, // Rule ID 163 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (BICXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 163, GIR_Done, // Label 495: @19032 GIM_Try, /*On fail goto*//*Label 496*/ 19074, // Rule ID 145 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<><>:$imm) => (ANDXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm64, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 145, GIR_Done, // Label 496: @19074 GIM_Try, /*On fail goto*//*Label 497*/ 19108, // Rule ID 10641 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (and:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn) => (ANDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10641, GIR_Done, // Label 497: @19108 GIM_Try, /*On fail goto*//*Label 498*/ 19142, // Rule ID 161 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) => (ANDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 161, GIR_Done, // Label 498: @19142 GIM_Try, /*On fail goto*//*Label 499*/ 19207, // Rule ID 11759 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$LHS) => (BICv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11759, GIR_Done, // Label 499: @19207 GIM_Try, /*On fail goto*//*Label 500*/ 19272, // Rule ID 8643 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] })) => (BICv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8643, GIR_Done, // Label 500: @19272 GIM_Try, /*On fail goto*//*Label 501*/ 19293, // Rule ID 159 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ANDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDXrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 159, GIR_Done, // Label 501: @19293 GIM_Try, /*On fail goto*//*Label 502*/ 19316, // Rule ID 6802 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (ANDv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6802, GIR_Done, // Label 502: @19316 GIM_Reject, // Label 483: @19317 GIM_Reject, // Label 459: @19318 GIM_Try, /*On fail goto*//*Label 503*/ 19474, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 504*/ 19393, // Rule ID 11758 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$LHS) => (BICv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11758, GIR_Done, // Label 504: @19393 GIM_Try, /*On fail goto*//*Label 505*/ 19454, // Rule ID 8642 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] })) => (BICv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8642, GIR_Done, // Label 505: @19454 GIM_Try, /*On fail goto*//*Label 506*/ 19473, // Rule ID 6801 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (ANDv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6801, GIR_Done, // Label 506: @19473 GIM_Reject, // Label 503: @19474 GIM_Reject, // Label 460: @19475 GIM_Try, /*On fail goto*//*Label 507*/ 19631, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 508*/ 19550, // Rule ID 11762 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$LHS) => (BICv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11762, GIR_Done, // Label 508: @19550 GIM_Try, /*On fail goto*//*Label 509*/ 19611, // Rule ID 8646 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] })) => (BICv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8646, GIR_Done, // Label 509: @19611 GIM_Try, /*On fail goto*//*Label 510*/ 19630, // Rule ID 6805 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (ANDv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6805, GIR_Done, // Label 510: @19630 GIM_Reject, // Label 507: @19631 GIM_Reject, // Label 461: @19632 GIM_Try, /*On fail goto*//*Label 511*/ 19788, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 512*/ 19707, // Rule ID 11757 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$LHS) => (BICv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11757, GIR_Done, // Label 512: @19707 GIM_Try, /*On fail goto*//*Label 513*/ 19768, // Rule ID 8641 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] })) => (BICv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8641, GIR_Done, // Label 513: @19768 GIM_Try, /*On fail goto*//*Label 514*/ 19787, // Rule ID 6800 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (ANDv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6800, GIR_Done, // Label 514: @19787 GIM_Reject, // Label 511: @19788 GIM_Reject, // Label 462: @19789 GIM_Try, /*On fail goto*//*Label 515*/ 19945, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 516*/ 19864, // Rule ID 11761 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$LHS) => (BICv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11761, GIR_Done, // Label 516: @19864 GIM_Try, /*On fail goto*//*Label 517*/ 19925, // Rule ID 8645 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] })) => (BICv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8645, GIR_Done, // Label 517: @19925 GIM_Try, /*On fail goto*//*Label 518*/ 19944, // Rule ID 6804 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (ANDv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6804, GIR_Done, // Label 518: @19944 GIM_Reject, // Label 515: @19945 GIM_Reject, // Label 463: @19946 GIM_Try, /*On fail goto*//*Label 519*/ 20102, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 520*/ 20021, // Rule ID 10756 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rn) => (BICv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10756, GIR_Done, // Label 520: @20021 GIM_Try, /*On fail goto*//*Label 521*/ 20082, // Rule ID 1560 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] })) => (BICv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1560, GIR_Done, // Label 521: @20082 GIM_Try, /*On fail goto*//*Label 522*/ 20101, // Rule ID 1558 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ANDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1558, GIR_Done, // Label 522: @20101 GIM_Reject, // Label 519: @20102 GIM_Reject, // Label 464: @20103 GIM_Try, /*On fail goto*//*Label 523*/ 20259, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 524*/ 20178, // Rule ID 11760 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$LHS) => (BICv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11760, GIR_Done, // Label 524: @20178 GIM_Try, /*On fail goto*//*Label 525*/ 20239, // Rule ID 8644 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] })) => (BICv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8644, GIR_Done, // Label 525: @20239 GIM_Try, /*On fail goto*//*Label 526*/ 20258, // Rule ID 6803 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (ANDv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6803, GIR_Done, // Label 526: @20258 GIM_Reject, // Label 523: @20259 GIM_Reject, // Label 465: @20260 GIM_Try, /*On fail goto*//*Label 527*/ 20416, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 528*/ 20335, // Rule ID 10757 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rn) => (BICv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10757, GIR_Done, // Label 528: @20335 GIM_Try, /*On fail goto*//*Label 529*/ 20396, // Rule ID 1561 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] })) => (BICv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1561, GIR_Done, // Label 529: @20396 GIM_Try, /*On fail goto*//*Label 530*/ 20415, // Rule ID 1559 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ANDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1559, GIR_Done, // Label 530: @20415 GIM_Reject, // Label 527: @20416 GIM_Reject, // Label 466: @20417 GIM_Try, /*On fail goto*//*Label 531*/ 20480, // Rule ID 5200 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::PPRRegClassID, // (and:{ *:[nxv1i1] } PPR:{ *:[nxv1i1] }:$Ps1, PPR:{ *:[nxv1i1] }:$Ps2) => (AND_PPzPP:{ *:[nxv1i1] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv1i1] }:$Ps1, PPR:{ *:[nxv1i1] }:$Ps2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AND_PPzPP, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ps1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ps2 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5200, GIR_Done, // Label 531: @20480 GIM_Reject, // Label 467: @20481 GIM_Try, /*On fail goto*//*Label 532*/ 20544, // Rule ID 5199 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::PPRRegClassID, // (and:{ *:[nxv2i1] } PPR:{ *:[nxv2i1] }:$Ps1, PPR:{ *:[nxv2i1] }:$Ps2) => (AND_PPzPP:{ *:[nxv2i1] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv2i1] }:$Ps1, PPR:{ *:[nxv2i1] }:$Ps2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AND_PPzPP, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ps1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ps2 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5199, GIR_Done, // Label 532: @20544 GIM_Reject, // Label 468: @20545 GIM_Try, /*On fail goto*//*Label 533*/ 20608, // Rule ID 5198 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::PPRRegClassID, // (and:{ *:[nxv4i1] } PPR:{ *:[nxv4i1] }:$Ps1, PPR:{ *:[nxv4i1] }:$Ps2) => (AND_PPzPP:{ *:[nxv4i1] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv4i1] }:$Ps1, PPR:{ *:[nxv4i1] }:$Ps2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_S, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AND_PPzPP, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ps1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ps2 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5198, GIR_Done, // Label 533: @20608 GIM_Reject, // Label 469: @20609 GIM_Try, /*On fail goto*//*Label 534*/ 20672, // Rule ID 5197 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::PPRRegClassID, // (and:{ *:[nxv8i1] } PPR:{ *:[nxv8i1] }:$Ps1, PPR:{ *:[nxv8i1] }:$Ps2) => (AND_PPzPP:{ *:[nxv8i1] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv8i1] }:$Ps1, PPR:{ *:[nxv8i1] }:$Ps2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_H, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AND_PPzPP, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ps1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ps2 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5197, GIR_Done, // Label 534: @20672 GIM_Reject, // Label 470: @20673 GIM_Try, /*On fail goto*//*Label 535*/ 20736, // Rule ID 5196 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::PPRRegClassID, // (and:{ *:[nxv16i1] } PPR:{ *:[nxv16i1] }:$Ps1, PPR:{ *:[nxv16i1] }:$Ps2) => (AND_PPzPP:{ *:[nxv16i1] } (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv16i1] }:$Ps1, PPR:{ *:[nxv16i1] }:$Ps2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_B, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AND_PPzPP, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ps1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ps2 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5196, GIR_Done, // Label 535: @20736 GIM_Reject, // Label 471: @20737 GIM_Reject, // Label 6: @20738 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 545*/ 32334, /*GILLT_s32*//*Label 536*/ 20754, /*GILLT_s64*//*Label 537*/ 21117, 0, /*GILLT_v2s32*//*Label 538*/ 23255, /*GILLT_v2s64*//*Label 539*/ 24552, /*GILLT_v4s16*//*Label 540*/ 25849, /*GILLT_v4s32*//*Label 541*/ 27146, /*GILLT_v8s8*//*Label 542*/ 28443, /*GILLT_v8s16*//*Label 543*/ 29740, /*GILLT_v16s8*//*Label 544*/ 31037, // Label 536: @20754 GIM_Try, /*On fail goto*//*Label 546*/ 21116, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 547*/ 20819, // Rule ID 10664 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (or:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (ORNWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10664, GIR_Done, // Label 547: @20819 GIM_Try, /*On fail goto*//*Label 548*/ 20874, // Rule ID 176 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] })) => (ORNWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 176, GIR_Done, // Label 548: @20874 GIM_Try, /*On fail goto*//*Label 549*/ 20916, // Rule ID 148 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<><>:$imm) => (ORRWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm32, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 148, GIR_Done, // Label 549: @20916 GIM_Try, /*On fail goto*//*Label 550*/ 20950, // Rule ID 10666 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (or:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn) => (ORRWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10666, GIR_Done, // Label 550: @20950 GIM_Try, /*On fail goto*//*Label 551*/ 20984, // Rule ID 180 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) => (ORRWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 180, GIR_Done, // Label 551: @20984 GIM_Try, /*On fail goto*//*Label 552*/ 21039, // Rule ID 10662 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (ORNWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10662, GIR_Done, // Label 552: @21039 GIM_Try, /*On fail goto*//*Label 553*/ 21094, // Rule ID 174 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (ORNWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 174, GIR_Done, // Label 553: @21094 GIM_Try, /*On fail goto*//*Label 554*/ 21115, // Rule ID 178 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ORRWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRWrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 178, GIR_Done, // Label 554: @21115 GIM_Reject, // Label 546: @21116 GIM_Reject, // Label 537: @21117 GIM_Try, /*On fail goto*//*Label 555*/ 23254, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 556*/ 21238, // Rule ID 7976 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 71777214294589695, GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, // MIs[4] Rn GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, -71777214294589696, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i64] } (and:{ *:[i64] } (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), 71777214294589695:{ *:[i64] }), (and:{ *:[i64] } (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), -71777214294589696:{ *:[i64] })) => (REV16Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV16Xr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7976, GIR_Done, // Label 556: @21238 GIM_Try, /*On fail goto*//*Label 557*/ 21349, // Rule ID 11683 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -71777214294589696, GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, // MIs[4] Rn GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 71777214294589695, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i64] } (and:{ *:[i64] } (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), -71777214294589696:{ *:[i64] }), (and:{ *:[i64] } (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), 71777214294589695:{ *:[i64] })) => (REV16Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV16Xr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11683, GIR_Done, // Label 557: @21349 GIM_Try, /*On fail goto*//*Label 558*/ 21404, // Rule ID 10665 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (or:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (ORNXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10665, GIR_Done, // Label 558: @21404 GIM_Try, /*On fail goto*//*Label 559*/ 21459, // Rule ID 177 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] })) => (ORNXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 177, GIR_Done, // Label 559: @21459 GIM_Try, /*On fail goto*//*Label 560*/ 21567, // Rule ID 11505 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v1i64] } (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11505, GIR_Done, // Label 560: @21567 GIM_Try, /*On fail goto*//*Label 561*/ 21675, // Rule ID 11504 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v1i64] } (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11504, GIR_Done, // Label 561: @21675 GIM_Try, /*On fail goto*//*Label 562*/ 21783, // Rule ID 11507 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] })), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11507, GIR_Done, // Label 562: @21783 GIM_Try, /*On fail goto*//*Label 563*/ 21891, // Rule ID 11506 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] })), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11506, GIR_Done, // Label 563: @21891 GIM_Try, /*On fail goto*//*Label 564*/ 21999, // Rule ID 6789 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS), (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6789, GIR_Done, // Label 564: @21999 GIM_Try, /*On fail goto*//*Label 565*/ 22107, // Rule ID 11502 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS), (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11502, GIR_Done, // Label 565: @22107 GIM_Try, /*On fail goto*//*Label 566*/ 22215, // Rule ID 11501 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }))) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11501, GIR_Done, // Label 566: @22215 GIM_Try, /*On fail goto*//*Label 567*/ 22323, // Rule ID 11503 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }))) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11503, GIR_Done, // Label 567: @22323 GIM_Try, /*On fail goto*//*Label 568*/ 22365, // Rule ID 149 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<><>:$imm) => (ORRXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm64, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 149, GIR_Done, // Label 568: @22365 GIM_Try, /*On fail goto*//*Label 569*/ 22399, // Rule ID 10667 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (or:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn) => (ORRXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10667, GIR_Done, // Label 569: @22399 GIM_Try, /*On fail goto*//*Label 570*/ 22433, // Rule ID 181 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) => (ORRXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 181, GIR_Done, // Label 570: @22433 GIM_Try, /*On fail goto*//*Label 571*/ 22500, // Rule ID 10898 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[i64] } (AArch64vashr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm), FPR64:{ *:[i64] }:$Rd)<> => (SSRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10898, GIR_Done, // Label 571: @22500 GIM_Try, /*On fail goto*//*Label 572*/ 22567, // Rule ID 11783 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v1i64] } (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm), FPR64:{ *:[v1i64] }:$Rd)<> => (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11783, GIR_Done, // Label 572: @22567 GIM_Try, /*On fail goto*//*Label 573*/ 22634, // Rule ID 10901 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[i64] } (AArch64vlshr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm), FPR64:{ *:[i64] }:$Rd)<> => (USRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10901, GIR_Done, // Label 573: @22634 GIM_Try, /*On fail goto*//*Label 574*/ 22701, // Rule ID 11786 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v1i64] } (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm), FPR64:{ *:[v1i64] }:$Rd)<> => (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11786, GIR_Done, // Label 574: @22701 GIM_Try, /*On fail goto*//*Label 575*/ 22756, // Rule ID 10663 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (ORNXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10663, GIR_Done, // Label 575: @22756 GIM_Try, /*On fail goto*//*Label 576*/ 22823, // Rule ID 2038 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, (AArch64vashr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2038, GIR_Done, // Label 576: @22823 GIM_Try, /*On fail goto*//*Label 577*/ 22890, // Rule ID 9439 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9439, GIR_Done, // Label 577: @22890 GIM_Try, /*On fail goto*//*Label 578*/ 22957, // Rule ID 2047 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, (AArch64vlshr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2047, GIR_Done, // Label 578: @22957 GIM_Try, /*On fail goto*//*Label 579*/ 23024, // Rule ID 9445 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9445, GIR_Done, // Label 579: @23024 GIM_Try, /*On fail goto*//*Label 580*/ 23079, // Rule ID 175 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (ORNXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 175, GIR_Done, // Label 580: @23079 GIM_Try, /*On fail goto*//*Label 581*/ 23144, // Rule ID 11765 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$LHS) => (ORNv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11765, GIR_Done, // Label 581: @23144 GIM_Try, /*On fail goto*//*Label 582*/ 23209, // Rule ID 8655 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] })) => (ORNv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8655, GIR_Done, // Label 582: @23209 GIM_Try, /*On fail goto*//*Label 583*/ 23230, // Rule ID 179 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ORRXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRXrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 179, GIR_Done, // Label 583: @23230 GIM_Try, /*On fail goto*//*Label 584*/ 23253, // Rule ID 8661 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (or:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (ORRv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8661, GIR_Done, // Label 584: @23253 GIM_Reject, // Label 555: @23254 GIM_Reject, // Label 538: @23255 GIM_Try, /*On fail goto*//*Label 585*/ 24551, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_Try, /*On fail goto*//*Label 586*/ 23373, // Rule ID 11498 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i32] } (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11498, GIR_Done, // Label 586: @23373 GIM_Try, /*On fail goto*//*Label 587*/ 23481, // Rule ID 11497 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i32] } (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11497, GIR_Done, // Label 587: @23481 GIM_Try, /*On fail goto*//*Label 588*/ 23589, // Rule ID 11500 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] })), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11500, GIR_Done, // Label 588: @23589 GIM_Try, /*On fail goto*//*Label 589*/ 23697, // Rule ID 11499 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] })), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11499, GIR_Done, // Label 589: @23697 GIM_Try, /*On fail goto*//*Label 590*/ 23805, // Rule ID 6788 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS), (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6788, GIR_Done, // Label 590: @23805 GIM_Try, /*On fail goto*//*Label 591*/ 23913, // Rule ID 11495 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS), (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11495, GIR_Done, // Label 591: @23913 GIM_Try, /*On fail goto*//*Label 592*/ 24021, // Rule ID 11494 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }))) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11494, GIR_Done, // Label 592: @24021 GIM_Try, /*On fail goto*//*Label 593*/ 24129, // Rule ID 11496 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }))) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11496, GIR_Done, // Label 593: @24129 GIM_Try, /*On fail goto*//*Label 594*/ 24196, // Rule ID 10918 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v2i32] } (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<>:$imm), V64:{ *:[v2i32] }:$Rd)<> => (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10918, GIR_Done, // Label 594: @24196 GIM_Try, /*On fail goto*//*Label 595*/ 24263, // Rule ID 10939 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<>:$imm), V64:{ *:[v2i32] }:$Rd)<> => (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10939, GIR_Done, // Label 595: @24263 GIM_Try, /*On fail goto*//*Label 596*/ 24330, // Rule ID 2152 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2152, GIR_Done, // Label 596: @24330 GIM_Try, /*On fail goto*//*Label 597*/ 24397, // Rule ID 2211 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2211, GIR_Done, // Label 597: @24397 GIM_Try, /*On fail goto*//*Label 598*/ 24462, // Rule ID 11764 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$LHS) => (ORNv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11764, GIR_Done, // Label 598: @24462 GIM_Try, /*On fail goto*//*Label 599*/ 24527, // Rule ID 8654 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] })) => (ORNv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8654, GIR_Done, // Label 599: @24527 GIM_Try, /*On fail goto*//*Label 600*/ 24550, // Rule ID 8660 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (ORRv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8660, GIR_Done, // Label 600: @24550 GIM_Reject, // Label 585: @24551 GIM_Reject, // Label 539: @24552 GIM_Try, /*On fail goto*//*Label 601*/ 25848, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_Try, /*On fail goto*//*Label 602*/ 24670, // Rule ID 11526 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11526, GIR_Done, // Label 602: @24670 GIM_Try, /*On fail goto*//*Label 603*/ 24778, // Rule ID 11525 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s64, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11525, GIR_Done, // Label 603: @24778 GIM_Try, /*On fail goto*//*Label 604*/ 24886, // Rule ID 11528 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] })), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11528, GIR_Done, // Label 604: @24886 GIM_Try, /*On fail goto*//*Label 605*/ 24994, // Rule ID 11527 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s64, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] })), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11527, GIR_Done, // Label 605: @24994 GIM_Try, /*On fail goto*//*Label 606*/ 25102, // Rule ID 6792 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS), (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6792, GIR_Done, // Label 606: @25102 GIM_Try, /*On fail goto*//*Label 607*/ 25210, // Rule ID 11523 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS), (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11523, GIR_Done, // Label 607: @25210 GIM_Try, /*On fail goto*//*Label 608*/ 25318, // Rule ID 11522 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }))) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11522, GIR_Done, // Label 608: @25318 GIM_Try, /*On fail goto*//*Label 609*/ 25426, // Rule ID 11524 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }))) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11524, GIR_Done, // Label 609: @25426 GIM_Try, /*On fail goto*//*Label 610*/ 25493, // Rule ID 10922 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v2i64] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v2i64] }:$Rd)<> => (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10922, GIR_Done, // Label 610: @25493 GIM_Try, /*On fail goto*//*Label 611*/ 25560, // Rule ID 10943 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v2i64] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v2i64] }:$Rd)<> => (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10943, GIR_Done, // Label 611: @25560 GIM_Try, /*On fail goto*//*Label 612*/ 25627, // Rule ID 2156 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2156, GIR_Done, // Label 612: @25627 GIM_Try, /*On fail goto*//*Label 613*/ 25694, // Rule ID 2215 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2215, GIR_Done, // Label 613: @25694 GIM_Try, /*On fail goto*//*Label 614*/ 25759, // Rule ID 11768 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$LHS) => (ORNv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11768, GIR_Done, // Label 614: @25759 GIM_Try, /*On fail goto*//*Label 615*/ 25824, // Rule ID 8658 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] })) => (ORNv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8658, GIR_Done, // Label 615: @25824 GIM_Try, /*On fail goto*//*Label 616*/ 25847, // Rule ID 8664 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (ORRv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8664, GIR_Done, // Label 616: @25847 GIM_Reject, // Label 601: @25848 GIM_Reject, // Label 540: @25849 GIM_Try, /*On fail goto*//*Label 617*/ 27145, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_Try, /*On fail goto*//*Label 618*/ 25967, // Rule ID 11491 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i16] } (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11491, GIR_Done, // Label 618: @25967 GIM_Try, /*On fail goto*//*Label 619*/ 26075, // Rule ID 11490 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s16, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i16] } (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11490, GIR_Done, // Label 619: @26075 GIM_Try, /*On fail goto*//*Label 620*/ 26183, // Rule ID 11493 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] })), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11493, GIR_Done, // Label 620: @26183 GIM_Try, /*On fail goto*//*Label 621*/ 26291, // Rule ID 11492 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s16, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] })), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11492, GIR_Done, // Label 621: @26291 GIM_Try, /*On fail goto*//*Label 622*/ 26399, // Rule ID 6787 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS), (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6787, GIR_Done, // Label 622: @26399 GIM_Try, /*On fail goto*//*Label 623*/ 26507, // Rule ID 11488 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS), (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11488, GIR_Done, // Label 623: @26507 GIM_Try, /*On fail goto*//*Label 624*/ 26615, // Rule ID 11487 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }))) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11487, GIR_Done, // Label 624: @26615 GIM_Try, /*On fail goto*//*Label 625*/ 26723, // Rule ID 11489 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }))) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11489, GIR_Done, // Label 625: @26723 GIM_Try, /*On fail goto*//*Label 626*/ 26790, // Rule ID 10914 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v4i16] } (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<>:$imm), V64:{ *:[v4i16] }:$Rd)<> => (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10914, GIR_Done, // Label 626: @26790 GIM_Try, /*On fail goto*//*Label 627*/ 26857, // Rule ID 10935 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<>:$imm), V64:{ *:[v4i16] }:$Rd)<> => (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10935, GIR_Done, // Label 627: @26857 GIM_Try, /*On fail goto*//*Label 628*/ 26924, // Rule ID 2148 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2148, GIR_Done, // Label 628: @26924 GIM_Try, /*On fail goto*//*Label 629*/ 26991, // Rule ID 2207 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2207, GIR_Done, // Label 629: @26991 GIM_Try, /*On fail goto*//*Label 630*/ 27056, // Rule ID 11763 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$LHS) => (ORNv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11763, GIR_Done, // Label 630: @27056 GIM_Try, /*On fail goto*//*Label 631*/ 27121, // Rule ID 8653 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] })) => (ORNv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8653, GIR_Done, // Label 631: @27121 GIM_Try, /*On fail goto*//*Label 632*/ 27144, // Rule ID 8659 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (ORRv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8659, GIR_Done, // Label 632: @27144 GIM_Reject, // Label 617: @27145 GIM_Reject, // Label 541: @27146 GIM_Try, /*On fail goto*//*Label 633*/ 28442, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 634*/ 27264, // Rule ID 11519 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11519, GIR_Done, // Label 634: @27264 GIM_Try, /*On fail goto*//*Label 635*/ 27372, // Rule ID 11518 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11518, GIR_Done, // Label 635: @27372 GIM_Try, /*On fail goto*//*Label 636*/ 27480, // Rule ID 11521 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] })), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11521, GIR_Done, // Label 636: @27480 GIM_Try, /*On fail goto*//*Label 637*/ 27588, // Rule ID 11520 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] })), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11520, GIR_Done, // Label 637: @27588 GIM_Try, /*On fail goto*//*Label 638*/ 27696, // Rule ID 6791 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6791, GIR_Done, // Label 638: @27696 GIM_Try, /*On fail goto*//*Label 639*/ 27804, // Rule ID 11516 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11516, GIR_Done, // Label 639: @27804 GIM_Try, /*On fail goto*//*Label 640*/ 27912, // Rule ID 11515 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }))) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11515, GIR_Done, // Label 640: @27912 GIM_Try, /*On fail goto*//*Label 641*/ 28020, // Rule ID 11517 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }))) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11517, GIR_Done, // Label 641: @28020 GIM_Try, /*On fail goto*//*Label 642*/ 28087, // Rule ID 10920 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v4i32] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v4i32] }:$Rd)<> => (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10920, GIR_Done, // Label 642: @28087 GIM_Try, /*On fail goto*//*Label 643*/ 28154, // Rule ID 10941 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v4i32] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v4i32] }:$Rd)<> => (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10941, GIR_Done, // Label 643: @28154 GIM_Try, /*On fail goto*//*Label 644*/ 28221, // Rule ID 2154 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2154, GIR_Done, // Label 644: @28221 GIM_Try, /*On fail goto*//*Label 645*/ 28288, // Rule ID 2213 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2213, GIR_Done, // Label 645: @28288 GIM_Try, /*On fail goto*//*Label 646*/ 28353, // Rule ID 11767 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$LHS) => (ORNv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11767, GIR_Done, // Label 646: @28353 GIM_Try, /*On fail goto*//*Label 647*/ 28418, // Rule ID 8657 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] })) => (ORNv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8657, GIR_Done, // Label 647: @28418 GIM_Try, /*On fail goto*//*Label 648*/ 28441, // Rule ID 8663 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (ORRv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8663, GIR_Done, // Label 648: @28441 GIM_Reject, // Label 633: @28442 GIM_Reject, // Label 542: @28443 GIM_Try, /*On fail goto*//*Label 649*/ 29739, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_Try, /*On fail goto*//*Label 650*/ 28561, // Rule ID 10764 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[4] Rd GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i8] } (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10764, GIR_Done, // Label 650: @28561 GIM_Try, /*On fail goto*//*Label 651*/ 28669, // Rule ID 10763 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s8, // MIs[4] Rd GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i8] } (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10763, GIR_Done, // Label 651: @28669 GIM_Try, /*On fail goto*//*Label 652*/ 28777, // Rule ID 10766 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[4] Rd GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] })), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10766, GIR_Done, // Label 652: @28777 GIM_Try, /*On fail goto*//*Label 653*/ 28885, // Rule ID 10765 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s8, // MIs[4] Rd GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] })), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10765, GIR_Done, // Label 653: @28885 GIM_Try, /*On fail goto*//*Label 654*/ 28993, // Rule ID 1568 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8, // MIs[3] Rd GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn), (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1568, GIR_Done, // Label 654: @28993 GIM_Try, /*On fail goto*//*Label 655*/ 29101, // Rule ID 10761 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8, // MIs[3] Rd GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd), (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10761, GIR_Done, // Label 655: @29101 GIM_Try, /*On fail goto*//*Label 656*/ 29209, // Rule ID 10760 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8, // MIs[3] Rd GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }))) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10760, GIR_Done, // Label 656: @29209 GIM_Try, /*On fail goto*//*Label 657*/ 29317, // Rule ID 10762 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8, // MIs[3] Rd GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }))) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10762, GIR_Done, // Label 657: @29317 GIM_Try, /*On fail goto*//*Label 658*/ 29384, // Rule ID 10910 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v8i8] } (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<>:$imm), V64:{ *:[v8i8] }:$Rd)<> => (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10910, GIR_Done, // Label 658: @29384 GIM_Try, /*On fail goto*//*Label 659*/ 29451, // Rule ID 10931 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<>:$imm), V64:{ *:[v8i8] }:$Rd)<> => (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10931, GIR_Done, // Label 659: @29451 GIM_Try, /*On fail goto*//*Label 660*/ 29518, // Rule ID 2144 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2144, GIR_Done, // Label 660: @29518 GIM_Try, /*On fail goto*//*Label 661*/ 29585, // Rule ID 2203 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2203, GIR_Done, // Label 661: @29585 GIM_Try, /*On fail goto*//*Label 662*/ 29650, // Rule ID 10758 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rn) => (ORNv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10758, GIR_Done, // Label 662: @29650 GIM_Try, /*On fail goto*//*Label 663*/ 29715, // Rule ID 1564 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] })) => (ORNv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1564, GIR_Done, // Label 663: @29715 GIM_Try, /*On fail goto*//*Label 664*/ 29738, // Rule ID 1566 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ORRv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1566, GIR_Done, // Label 664: @29738 GIM_Reject, // Label 649: @29739 GIM_Reject, // Label 543: @29740 GIM_Try, /*On fail goto*//*Label 665*/ 31036, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 666*/ 29858, // Rule ID 11512 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11512, GIR_Done, // Label 666: @29858 GIM_Try, /*On fail goto*//*Label 667*/ 29966, // Rule ID 11511 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11511, GIR_Done, // Label 667: @29966 GIM_Try, /*On fail goto*//*Label 668*/ 30074, // Rule ID 11514 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] })), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11514, GIR_Done, // Label 668: @30074 GIM_Try, /*On fail goto*//*Label 669*/ 30182, // Rule ID 11513 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16, // MIs[4] LHS GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] })), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11513, GIR_Done, // Label 669: @30182 GIM_Try, /*On fail goto*//*Label 670*/ 30290, // Rule ID 6790 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS), (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6790, GIR_Done, // Label 670: @30290 GIM_Try, /*On fail goto*//*Label 671*/ 30398, // Rule ID 11509 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS), (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11509, GIR_Done, // Label 671: @30398 GIM_Try, /*On fail goto*//*Label 672*/ 30506, // Rule ID 11508 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }))) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11508, GIR_Done, // Label 672: @30506 GIM_Try, /*On fail goto*//*Label 673*/ 30614, // Rule ID 11510 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, // MIs[3] LHS GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }))) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11510, GIR_Done, // Label 673: @30614 GIM_Try, /*On fail goto*//*Label 674*/ 30681, // Rule ID 10916 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v8i16] }:$Rd)<> => (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10916, GIR_Done, // Label 674: @30681 GIM_Try, /*On fail goto*//*Label 675*/ 30748, // Rule ID 10937 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v8i16] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v8i16] }:$Rd)<> => (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10937, GIR_Done, // Label 675: @30748 GIM_Try, /*On fail goto*//*Label 676*/ 30815, // Rule ID 2150 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2150, GIR_Done, // Label 676: @30815 GIM_Try, /*On fail goto*//*Label 677*/ 30882, // Rule ID 2209 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2209, GIR_Done, // Label 677: @30882 GIM_Try, /*On fail goto*//*Label 678*/ 30947, // Rule ID 11766 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$LHS) => (ORNv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11766, GIR_Done, // Label 678: @30947 GIM_Try, /*On fail goto*//*Label 679*/ 31012, // Rule ID 8656 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] })) => (ORNv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8656, GIR_Done, // Label 679: @31012 GIM_Try, /*On fail goto*//*Label 680*/ 31035, // Rule ID 8662 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (ORRv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8662, GIR_Done, // Label 680: @31035 GIM_Reject, // Label 665: @31036 GIM_Reject, // Label 544: @31037 GIM_Try, /*On fail goto*//*Label 681*/ 32333, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 682*/ 31155, // Rule ID 10771 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[4] Rd GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10771, GIR_Done, // Label 682: @31155 GIM_Try, /*On fail goto*//*Label 683*/ 31263, // Rule ID 10770 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v16s8, // MIs[4] Rd GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10770, GIR_Done, // Label 683: @31263 GIM_Try, /*On fail goto*//*Label 684*/ 31371, // Rule ID 10773 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[4] Rd GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] })), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10773, GIR_Done, // Label 684: @31371 GIM_Try, /*On fail goto*//*Label 685*/ 31479, // Rule ID 10772 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v16s8, // MIs[4] Rd GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] })), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10772, GIR_Done, // Label 685: @31479 GIM_Try, /*On fail goto*//*Label 686*/ 31587, // Rule ID 1569 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8, // MIs[3] Rd GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn), (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1569, GIR_Done, // Label 686: @31587 GIM_Try, /*On fail goto*//*Label 687*/ 31695, // Rule ID 10768 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8, // MIs[3] Rd GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd), (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10768, GIR_Done, // Label 687: @31695 GIM_Try, /*On fail goto*//*Label 688*/ 31803, // Rule ID 10767 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8, // MIs[3] Rd GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }))) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10767, GIR_Done, // Label 688: @31803 GIM_Try, /*On fail goto*//*Label 689*/ 31911, // Rule ID 10769 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8, // MIs[3] Rd GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/4, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }))) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10769, GIR_Done, // Label 689: @31911 GIM_Try, /*On fail goto*//*Label 690*/ 31978, // Rule ID 10912 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v16i8] } (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v16i8] }:$Rd)<> => (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10912, GIR_Done, // Label 690: @31978 GIM_Try, /*On fail goto*//*Label 691*/ 32045, // Rule ID 10933 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v16i8] } (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<>:$imm), V128:{ *:[v16i8] }:$Rd)<> => (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10933, GIR_Done, // Label 691: @32045 GIM_Try, /*On fail goto*//*Label 692*/ 32112, // Rule ID 2146 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2146, GIR_Done, // Label 692: @32112 GIM_Try, /*On fail goto*//*Label 693*/ 32179, // Rule ID 2205 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[2] Operand 1 // No operand predicates GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_add_and_or_is_add, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<>:$imm))<> => (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2205, GIR_Done, // Label 693: @32179 GIM_Try, /*On fail goto*//*Label 694*/ 32244, // Rule ID 10759 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rn) => (ORNv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10759, GIR_Done, // Label 694: @32244 GIM_Try, /*On fail goto*//*Label 695*/ 32309, // Rule ID 1565 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] })) => (ORNv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1565, GIR_Done, // Label 695: @32309 GIM_Try, /*On fail goto*//*Label 696*/ 32332, // Rule ID 1567 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ORRv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1567, GIR_Done, // Label 696: @32332 GIM_Reject, // Label 681: @32333 GIM_Reject, // Label 545: @32334 GIM_Reject, // Label 7: @32335 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 706*/ 36563, /*GILLT_s32*//*Label 697*/ 32351, /*GILLT_s64*//*Label 698*/ 33023, 0, /*GILLT_v2s32*//*Label 699*/ 33756, /*GILLT_v2s64*//*Label 700*/ 33821, /*GILLT_v4s16*//*Label 701*/ 34348, /*GILLT_v4s32*//*Label 702*/ 34413, /*GILLT_v8s8*//*Label 703*/ 34940, /*GILLT_v8s16*//*Label 704*/ 35007, /*GILLT_v16s8*//*Label 705*/ 36034, // Label 697: @32351 GIM_Try, /*On fail goto*//*Label 707*/ 33022, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 708*/ 32416, // Rule ID 10653 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] })) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10653, GIR_Done, // Label 708: @32416 GIM_Try, /*On fail goto*//*Label 709*/ 32471, // Rule ID 10652 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10652, GIR_Done, // Label 709: @32471 GIM_Try, /*On fail goto*//*Label 710*/ 32526, // Rule ID 10650 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn), -1:{ *:[i32] }) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10650, GIR_Done, // Label 710: @32526 GIM_Try, /*On fail goto*//*Label 711*/ 32581, // Rule ID 168 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift), -1:{ *:[i32] }) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 168, GIR_Done, // Label 711: @32581 GIM_Try, /*On fail goto*//*Label 712*/ 32636, // Rule ID 10651 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }), logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10651, GIR_Done, // Label 712: @32636 GIM_Try, /*On fail goto*//*Label 713*/ 32691, // Rule ID 10654 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] })) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10654, GIR_Done, // Label 713: @32691 GIM_Try, /*On fail goto*//*Label 714*/ 32733, // Rule ID 146 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<><>:$imm) => (EORWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm32, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 146, GIR_Done, // Label 714: @32733 GIM_Try, /*On fail goto*//*Label 715*/ 32767, // Rule ID 10660 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn) => (EORWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10660, GIR_Done, // Label 715: @32767 GIM_Try, /*On fail goto*//*Label 716*/ 32801, // Rule ID 172 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) => (EORWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 172, GIR_Done, // Label 716: @32801 GIM_Try, /*On fail goto*//*Label 717*/ 32856, // Rule ID 10646 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rm) => (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10646, GIR_Done, // Label 717: @32856 GIM_Try, /*On fail goto*//*Label 718*/ 32911, // Rule ID 166 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm), -1:{ *:[i32] }) => (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 166, GIR_Done, // Label 718: @32911 GIM_Try, /*On fail goto*//*Label 719*/ 32966, // Rule ID 10647 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] })) => (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10647, GIR_Done, // Label 719: @32966 GIM_Try, /*On fail goto*//*Label 720*/ 33000, // Rule ID 7964 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] }) => (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Wm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddRegister, /*InsnID*/0, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Wm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7964, GIR_Done, // Label 720: @33000 GIM_Try, /*On fail goto*//*Label 721*/ 33021, // Rule ID 170 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (EORWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORWrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 170, GIR_Done, // Label 721: @33021 GIM_Reject, // Label 707: @33022 GIM_Reject, // Label 698: @33023 GIM_Try, /*On fail goto*//*Label 722*/ 33755, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 723*/ 33088, // Rule ID 10658 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] })) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10658, GIR_Done, // Label 723: @33088 GIM_Try, /*On fail goto*//*Label 724*/ 33143, // Rule ID 10657 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10657, GIR_Done, // Label 724: @33143 GIM_Try, /*On fail goto*//*Label 725*/ 33198, // Rule ID 10655 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn), -1:{ *:[i64] }) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10655, GIR_Done, // Label 725: @33198 GIM_Try, /*On fail goto*//*Label 726*/ 33253, // Rule ID 169 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift), -1:{ *:[i64] }) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 169, GIR_Done, // Label 726: @33253 GIM_Try, /*On fail goto*//*Label 727*/ 33308, // Rule ID 10656 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }), logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10656, GIR_Done, // Label 727: @33308 GIM_Try, /*On fail goto*//*Label 728*/ 33363, // Rule ID 10659 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] })) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10659, GIR_Done, // Label 728: @33363 GIM_Try, /*On fail goto*//*Label 729*/ 33405, // Rule ID 147 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<><>:$imm) => (EORXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm64, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 147, GIR_Done, // Label 729: @33405 GIM_Try, /*On fail goto*//*Label 730*/ 33439, // Rule ID 10661 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn) => (EORXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10661, GIR_Done, // Label 730: @33439 GIM_Try, /*On fail goto*//*Label 731*/ 33473, // Rule ID 173 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) => (EORXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm_and_shift GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 173, GIR_Done, // Label 731: @33473 GIM_Try, /*On fail goto*//*Label 732*/ 33528, // Rule ID 10648 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rm) => (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10648, GIR_Done, // Label 732: @33528 GIM_Try, /*On fail goto*//*Label 733*/ 33583, // Rule ID 167 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm), -1:{ *:[i64] }) => (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 167, GIR_Done, // Label 733: @33583 GIM_Try, /*On fail goto*//*Label 734*/ 33638, // Rule ID 10649 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] })) => (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10649, GIR_Done, // Label 734: @33638 GIM_Try, /*On fail goto*//*Label 735*/ 33672, // Rule ID 7965 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Xm, -1:{ *:[i64] }) => (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Xm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Xm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7965, GIR_Done, // Label 735: @33672 GIM_Try, /*On fail goto*//*Label 736*/ 33710, // Rule ID 8559 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, immAllOnesV:{ *:[v1i64] }) => (NOTv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8559, GIR_Done, // Label 736: @33710 GIM_Try, /*On fail goto*//*Label 737*/ 33731, // Rule ID 171 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (EORXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORXrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 171, GIR_Done, // Label 737: @33731 GIM_Try, /*On fail goto*//*Label 738*/ 33754, // Rule ID 8649 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (EORv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8649, GIR_Done, // Label 738: @33754 GIM_Reject, // Label 722: @33755 GIM_Reject, // Label 699: @33756 GIM_Try, /*On fail goto*//*Label 739*/ 33820, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 740*/ 33804, // Rule ID 8557 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllOnesV:{ *:[v2i32] }) => (NOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8557, GIR_Done, // Label 740: @33804 GIM_Try, /*On fail goto*//*Label 741*/ 33819, // Rule ID 8648 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (EORv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8648, GIR_Done, // Label 741: @33819 GIM_Reject, // Label 739: @33820 GIM_Reject, // Label 700: @33821 GIM_Try, /*On fail goto*//*Label 742*/ 34347, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 743*/ 33921, // Rule ID 11655 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$Vm), V128:{ *:[v2i64] }:$Vn) => (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11655, GIR_Done, // Label 743: @33921 GIM_Try, /*On fail goto*//*Label 744*/ 34007, // Rule ID 11654 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vm, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] })), V128:{ *:[v2i64] }:$Vn) => (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11654, GIR_Done, // Label 744: @34007 GIM_Try, /*On fail goto*//*Label 745*/ 34093, // Rule ID 11653 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$Vm)) => (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11653, GIR_Done, // Label 745: @34093 GIM_Try, /*On fail goto*//*Label 746*/ 34179, // Rule ID 7795 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vm, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] }))) => (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7795, GIR_Done, // Label 746: @34179 GIM_Try, /*On fail goto*//*Label 747*/ 34213, // Rule ID 8560 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllOnesV:{ *:[v2i64] }) => (NOTv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8560, GIR_Done, // Label 747: @34213 GIM_Try, /*On fail goto*//*Label 748*/ 34270, // Rule ID 7791 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm), V128:{ *:[v2i64] }:$Va) => (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7791, GIR_Done, // Label 748: @34270 GIM_Try, /*On fail goto*//*Label 749*/ 34327, // Rule ID 11643 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)) => (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11643, GIR_Done, // Label 749: @34327 GIM_Try, /*On fail goto*//*Label 750*/ 34346, // Rule ID 8652 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (EORv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8652, GIR_Done, // Label 750: @34346 GIM_Reject, // Label 742: @34347 GIM_Reject, // Label 701: @34348 GIM_Try, /*On fail goto*//*Label 751*/ 34412, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 752*/ 34396, // Rule ID 8555 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllOnesV:{ *:[v4i16] }) => (NOTv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8555, GIR_Done, // Label 752: @34396 GIM_Try, /*On fail goto*//*Label 753*/ 34411, // Rule ID 8647 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (EORv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8647, GIR_Done, // Label 753: @34411 GIM_Reject, // Label 751: @34412 GIM_Reject, // Label 702: @34413 GIM_Try, /*On fail goto*//*Label 754*/ 34939, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 755*/ 34513, // Rule ID 11652 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$Vm), V128:{ *:[v4i32] }:$Vn) => (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11652, GIR_Done, // Label 755: @34513 GIM_Try, /*On fail goto*//*Label 756*/ 34599, // Rule ID 11651 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vm, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] })), V128:{ *:[v4i32] }:$Vn) => (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11651, GIR_Done, // Label 756: @34599 GIM_Try, /*On fail goto*//*Label 757*/ 34685, // Rule ID 11650 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$Vm)) => (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11650, GIR_Done, // Label 757: @34685 GIM_Try, /*On fail goto*//*Label 758*/ 34771, // Rule ID 7794 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vm, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] }))) => (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7794, GIR_Done, // Label 758: @34771 GIM_Try, /*On fail goto*//*Label 759*/ 34805, // Rule ID 8558 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllOnesV:{ *:[v4i32] }) => (NOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8558, GIR_Done, // Label 759: @34805 GIM_Try, /*On fail goto*//*Label 760*/ 34862, // Rule ID 7790 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm), V128:{ *:[v4i32] }:$Va) => (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7790, GIR_Done, // Label 760: @34862 GIM_Try, /*On fail goto*//*Label 761*/ 34919, // Rule ID 11642 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)) => (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11642, GIR_Done, // Label 761: @34919 GIM_Try, /*On fail goto*//*Label 762*/ 34938, // Rule ID 8651 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (EORv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8651, GIR_Done, // Label 762: @34938 GIM_Reject, // Label 754: @34939 GIM_Reject, // Label 703: @34940 GIM_Try, /*On fail goto*//*Label 763*/ 35006, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 764*/ 34990, // Rule ID 945 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllOnesV:{ *:[v8i8] }) => (NOTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 945, GIR_Done, // Label 764: @34990 GIM_Try, /*On fail goto*//*Label 765*/ 35005, // Rule ID 1562 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (EORv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1562, GIR_Done, // Label 765: @35005 GIM_Reject, // Label 763: @35006 GIM_Reject, // Label 704: @35007 GIM_Try, /*On fail goto*//*Label 766*/ 36033, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 767*/ 35146, // Rule ID 11726 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5] GIM_CheckOpcode, /*MI*/5, AArch64::G_VASHR, GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v8s16, // MIs[5] Operand 2 GIM_CheckLiteralInt, /*MI*/5, /*Op*/2, 15, GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6] GIM_CheckOpcode, /*MI*/6, AArch64::G_VASHR, // MIs[6] src GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1, // MIs[6] Operand 2 GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, 15, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, GIM_CheckIsSafeToFold, /*InsnID*/5, GIM_CheckIsSafeToFold, /*InsnID*/6, // (xor:{ *:[v8i16] } (add:{ *:[v8i16] } (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opB)), (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] })), (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] })) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA, V64:{ *:[v8i8] }:$opB) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // opB GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11726, GIR_Done, // Label 767: @35146 GIM_Try, /*On fail goto*//*Label 768*/ 35271, // Rule ID 11727 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VASHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, // MIs[2] Operand 2 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 15, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/5, /*MI*/3, /*OpIdx*/2, // MIs[5] GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/5, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6] GIM_CheckOpcode, /*MI*/6, AArch64::G_VASHR, // MIs[6] src GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, // MIs[6] Operand 2 GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, 15, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, GIM_CheckIsSafeToFold, /*InsnID*/5, GIM_CheckIsSafeToFold, /*InsnID*/6, // (xor:{ *:[v8i16] } (add:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] }), (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opB))), (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] })) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA, V64:{ *:[v8i8] }:$opB) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // opA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // opB GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11727, GIR_Done, // Label 768: @35271 GIM_Try, /*On fail goto*//*Label 769*/ 35396, // Rule ID 8507 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, // MIs[1] Operand 2 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 15, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/5, /*MI*/3, /*OpIdx*/2, // MIs[5] GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/5, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/2, // MIs[6] GIM_CheckOpcode, /*MI*/6, AArch64::G_VASHR, // MIs[6] src GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, // MIs[6] Operand 2 GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, 15, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, GIM_CheckIsSafeToFold, /*InsnID*/5, GIM_CheckIsSafeToFold, /*InsnID*/6, // (xor:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] }), (add:{ *:[v8i16] } (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opB)), (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] }))) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA, V64:{ *:[v8i8] }:$opB) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // opA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // opB GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8507, GIR_Done, // Label 769: @35396 GIM_Try, /*On fail goto*//*Label 770*/ 35521, // Rule ID 11725 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, // MIs[1] Operand 2 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 15, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, AArch64::G_VASHR, // MIs[3] src GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, // MIs[3] Operand 2 GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, 15, GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5] GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/5, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/6, /*MI*/4, /*OpIdx*/2, // MIs[6] GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/6, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, GIM_CheckIsSafeToFold, /*InsnID*/5, GIM_CheckIsSafeToFold, /*InsnID*/6, // (xor:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] }), (add:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] }), (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opB)))) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA, V64:{ *:[v8i8] }:$opB) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // opA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // opB GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11725, GIR_Done, // Label 770: @35521 GIM_Try, /*On fail goto*//*Label 771*/ 35607, // Rule ID 11649 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$Vm), V128:{ *:[v8i16] }:$Vn) => (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11649, GIR_Done, // Label 771: @35607 GIM_Try, /*On fail goto*//*Label 772*/ 35693, // Rule ID 11648 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vm, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] })), V128:{ *:[v8i16] }:$Vn) => (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11648, GIR_Done, // Label 772: @35693 GIM_Try, /*On fail goto*//*Label 773*/ 35779, // Rule ID 11647 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$Vm)) => (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11647, GIR_Done, // Label 773: @35779 GIM_Try, /*On fail goto*//*Label 774*/ 35865, // Rule ID 7793 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vm, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] }))) => (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7793, GIR_Done, // Label 774: @35865 GIM_Try, /*On fail goto*//*Label 775*/ 35899, // Rule ID 8556 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllOnesV:{ *:[v8i16] }) => (NOTv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8556, GIR_Done, // Label 775: @35899 GIM_Try, /*On fail goto*//*Label 776*/ 35956, // Rule ID 7789 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm), V128:{ *:[v8i16] }:$Va) => (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7789, GIR_Done, // Label 776: @35956 GIM_Try, /*On fail goto*//*Label 777*/ 36013, // Rule ID 11641 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)) => (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11641, GIR_Done, // Label 777: @36013 GIM_Try, /*On fail goto*//*Label 778*/ 36032, // Rule ID 8650 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (EORv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8650, GIR_Done, // Label 778: @36032 GIM_Reject, // Label 766: @36033 GIM_Reject, // Label 705: @36034 GIM_Try, /*On fail goto*//*Label 779*/ 36562, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 780*/ 36134, // Rule ID 11646 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Vm), V128:{ *:[v16i8] }:$Vn) => (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11646, GIR_Done, // Label 780: @36134 GIM_Try, /*On fail goto*//*Label 781*/ 36220, // Rule ID 11645 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] })), V128:{ *:[v16i8] }:$Vn) => (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11645, GIR_Done, // Label 781: @36220 GIM_Try, /*On fail goto*//*Label 782*/ 36306, // Rule ID 11644 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Vm)) => (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11644, GIR_Done, // Label 782: @36306 GIM_Try, /*On fail goto*//*Label 783*/ 36392, // Rule ID 7792 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/3, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] }))) => (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7792, GIR_Done, // Label 783: @36392 GIM_Try, /*On fail goto*//*Label 784*/ 36428, // Rule ID 946 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, GIM_CheckIsBuildVectorAllOnes, /*MI*/1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllOnesV:{ *:[v16i8] }) => (NOTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 946, GIR_Done, // Label 784: @36428 GIM_Try, /*On fail goto*//*Label 785*/ 36485, // Rule ID 7788 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm), V128:{ *:[v16i8] }:$Va) => (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7788, GIR_Done, // Label 785: @36485 GIM_Try, /*On fail goto*//*Label 786*/ 36542, // Rule ID 11640 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)) => (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11640, GIR_Done, // Label 786: @36542 GIM_Try, /*On fail goto*//*Label 787*/ 36561, // Rule ID 1563 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (EORv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1563, GIR_Done, // Label 787: @36561 GIM_Reject, // Label 779: @36562 GIM_Reject, // Label 706: @36563 GIM_Reject, // Label 8: @36564 GIM_Try, /*On fail goto*//*Label 788*/ 44955, GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 11, /*)*//*default:*//*Label 793*/ 44954, /*GILLT_v2s64*//*Label 789*/ 36581, 0, /*GILLT_v4s32*//*Label 790*/ 36957, 0, /*GILLT_v8s16*//*Label 791*/ 39965, /*GILLT_v16s8*//*Label 792*/ 42633, // Label 789: @36581 GIM_Try, /*On fail goto*//*Label 794*/ 36956, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 795*/ 36655, // Rule ID 9066 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v2i64] } V64:{ *:[v1i64] }:$Rn, (undef:{ *:[v1i64] })) => (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR64RegClassID, // GIR_Coverage, 9066, GIR_Done, // Label 795: @36655 GIM_Try, /*On fail goto*//*Label 796*/ 36711, // Rule ID 9067 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v2f64] } V64:{ *:[v1f64] }:$Rn, (undef:{ *:[v1f64] })) => (INSERT_SUBREG:{ *:[v2f64] } (IMPLICIT_DEF:{ *:[v2f64] }), V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR64RegClassID, // GIR_Coverage, 9067, GIR_Done, // Label 796: @36711 GIM_Try, /*On fail goto*//*Label 797*/ 36833, // Rule ID 9058 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (concat_vectors:{ *:[v2i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v1i64] }:$Rn) => (INSvi64lane:{ *:[v2i64] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/3, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9058, GIR_Done, // Label 797: @36833 GIM_Try, /*On fail goto*//*Label 798*/ 36955, // Rule ID 9059 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (concat_vectors:{ *:[v2f64] } V64:{ *:[v1f64] }:$Rd, V64:{ *:[v1f64] }:$Rn) => (INSvi64lane:{ *:[v2f64] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1f64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/3, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9059, GIR_Done, // Label 798: @36955 GIM_Reject, // Label 794: @36956 GIM_Reject, // Label 790: @36957 GIM_Try, /*On fail goto*//*Label 799*/ 39964, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 800*/ 37129, // Rule ID 11792 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ADD, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, AArch64::G_DUP, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/4, /*Op*/1, 2147483648, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // MIs[2] Operand 2 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 32, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Vd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (add:{ *:[v2i64] } (AArch64dup:{ *:[v2i64] } 2147483648:{ *:[i64] }), V128:{ *:[v2i64] }:$Vn), 32:{ *:[i32] }))) => (RADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Vd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Vn, (MOVIv2d_ns:{ *:[v2i64] } 0:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::MOVIv2d_ns, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/3, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv2i64_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Vn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11792, GIR_Done, // Label 800: @37129 GIM_Try, /*On fail goto*//*Label 801*/ 37287, // Rule ID 9474 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ADD, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, AArch64::G_DUP, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/4, /*Op*/1, 2147483648, // MIs[2] Operand 2 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 32, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Vd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, (AArch64dup:{ *:[v2i64] } 2147483648:{ *:[i64] })), 32:{ *:[i32] }))) => (RADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Vd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Vn, (MOVIv2d_ns:{ *:[v2i64] } 0:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::MOVIv2d_ns, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/3, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv2i64_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Vn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9474, GIR_Done, // Label 801: @37287 GIM_Try, /*On fail goto*//*Label 802*/ 37400, // Rule ID 8833 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ADD, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // MIs[2] Operand 2 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 32, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] }))) => (ADDHNv2i64_v4i32:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv2i64_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8833, GIR_Done, // Label 802: @37400 GIM_Try, /*On fail goto*//*Label 803*/ 37513, // Rule ID 8839 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // MIs[2] Operand 2 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 32, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] }))) => (SUBHNv2i64_v4i32:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv2i64_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8839, GIR_Done, // Label 803: @37513 GIM_Try, /*On fail goto*//*Label 804*/ 37603, // Rule ID 8920 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[2] Operand 2 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, AArch64::G_VLSHR, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[4] Operand 2 GIM_CheckLiteralInt, /*MI*/4, /*Op*/2, 32, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (concat_vectors:{ *:[v4i32] } (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, 32:{ *:[i32] })), (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vm, 32:{ *:[i32] }))) => (UZP2v4i32:{ *:[v4i32] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8920, GIR_Done, // Label 804: @37603 GIM_Try, /*On fail goto*//*Label 805*/ 37719, // Rule ID 9452 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 582:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQRSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9452, GIR_Done, // Label 805: @37719 GIM_Try, /*On fail goto*//*Label 806*/ 37835, // Rule ID 9455 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 583:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQRSHRUNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9455, GIR_Done, // Label 806: @37835 GIM_Try, /*On fail goto*//*Label 807*/ 37951, // Rule ID 9458 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 586:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9458, GIR_Done, // Label 807: @37951 GIM_Try, /*On fail goto*//*Label 808*/ 38067, // Rule ID 9461 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 587:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQSHRUNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9461, GIR_Done, // Label 808: @38067 GIM_Try, /*On fail goto*//*Label 809*/ 38183, // Rule ID 9465 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 631:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (UQRSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9465, GIR_Done, // Label 809: @38183 GIM_Try, /*On fail goto*//*Label 810*/ 38299, // Rule ID 9468 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 633:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (UQSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9468, GIR_Done, // Label 810: @38299 GIM_Try, /*On fail goto*//*Label 811*/ 38417, // Rule ID 9448 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VASHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[2] imm GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm))) => (SHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9448, GIR_Done, // Label 811: @38417 GIM_Try, /*On fail goto*//*Label 812*/ 38533, // Rule ID 9480 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[2] imm GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm))) => (SHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9480, GIR_Done, // Label 812: @38533 GIM_Try, /*On fail goto*//*Label 813*/ 38642, // Rule ID 6812 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_addhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 479:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (ADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv2i64_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6812, GIR_Done, // Label 813: @38642 GIM_Try, /*On fail goto*//*Label 814*/ 38751, // Rule ID 8809 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_subhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 604:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (SUBHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv2i64_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8809, GIR_Done, // Label 814: @38751 GIM_Try, /*On fail goto*//*Label 815*/ 38860, // Rule ID 8812 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_raddhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 546:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (RADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv2i64_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8812, GIR_Done, // Label 815: @38860 GIM_Try, /*On fail goto*//*Label 816*/ 38969, // Rule ID 8815 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 548:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (RSUBHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv2i64_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8815, GIR_Done, // Label 816: @38969 GIM_Try, /*On fail goto*//*Label 817*/ 39066, // Rule ID 6808 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 589:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)) => (SQXTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6808, GIR_Done, // Label 817: @39066 GIM_Try, /*On fail goto*//*Label 818*/ 39163, // Rule ID 6809 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_fcvtxn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, (intrinsic_wo_chain:{ *:[v2f32] } 502:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)) => (FCVTXNv4f32:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTXNv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6809, GIR_Done, // Label 818: @39163 GIM_Try, /*On fail goto*//*Label 819*/ 39260, // Rule ID 8563 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 590:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)) => (SQXTUNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8563, GIR_Done, // Label 819: @39260 GIM_Try, /*On fail goto*//*Label 820*/ 39357, // Rule ID 8566 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 635:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)) => (UQXTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8566, GIR_Done, // Label 820: @39357 GIM_Try, /*On fail goto*//*Label 821*/ 39413, // Rule ID 8917 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v4i32] } (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vn), (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vm)) => (UZP1v4i32:{ *:[v4i32] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP1v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8917, GIR_Done, // Label 821: @39413 GIM_Try, /*On fail goto*//*Label 822*/ 39501, // Rule ID 8534 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FPTRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, (fpround:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn)) => (FCVTNv4i32:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8534, GIR_Done, // Label 822: @39501 GIM_Try, /*On fail goto*//*Label 823*/ 39591, // Rule ID 8569 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)) => (XTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XTNv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8569, GIR_Done, // Label 823: @39591 GIM_Try, /*On fail goto*//*Label 824*/ 39651, // Rule ID 9068 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rn, (undef:{ *:[v2i32] })) => (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR64RegClassID, // GIR_Coverage, 9068, GIR_Done, // Label 824: @39651 GIM_Try, /*On fail goto*//*Label 825*/ 39711, // Rule ID 9069 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rn, (undef:{ *:[v2f32] })) => (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR64RegClassID, // GIR_Coverage, 9069, GIR_Done, // Label 825: @39711 GIM_Try, /*On fail goto*//*Label 826*/ 39837, // Rule ID 9060 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) => (INSvi64lane:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/3, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9060, GIR_Done, // Label 826: @39837 GIM_Try, /*On fail goto*//*Label 827*/ 39963, // Rule ID 9061 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn) => (INSvi64lane:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/3, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9061, GIR_Done, // Label 827: @39963 GIM_Reject, // Label 799: @39964 GIM_Reject, // Label 791: @39965 GIM_Try, /*On fail goto*//*Label 828*/ 42632, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 829*/ 40092, // Rule ID 8832 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ADD, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // MIs[2] Operand 2 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] }))) => (ADDHNv4i32_v8i16:{ *:[v8i16] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv4i32_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8832, GIR_Done, // Label 829: @40092 GIM_Try, /*On fail goto*//*Label 830*/ 40205, // Rule ID 8838 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // MIs[2] Operand 2 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] }))) => (SUBHNv4i32_v8i16:{ *:[v8i16] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv4i32_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8838, GIR_Done, // Label 830: @40205 GIM_Try, /*On fail goto*//*Label 831*/ 40295, // Rule ID 8919 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[2] Operand 2 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, AArch64::G_VLSHR, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[4] Operand 2 GIM_CheckLiteralInt, /*MI*/4, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (concat_vectors:{ *:[v8i16] } (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, 16:{ *:[i32] })), (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vm, 16:{ *:[i32] }))) => (UZP2v8i16:{ *:[v8i16] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8919, GIR_Done, // Label 831: @40295 GIM_Try, /*On fail goto*//*Label 832*/ 40411, // Rule ID 9451 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 582:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQRSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9451, GIR_Done, // Label 832: @40411 GIM_Try, /*On fail goto*//*Label 833*/ 40527, // Rule ID 9454 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 583:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQRSHRUNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9454, GIR_Done, // Label 833: @40527 GIM_Try, /*On fail goto*//*Label 834*/ 40643, // Rule ID 9457 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 586:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9457, GIR_Done, // Label 834: @40643 GIM_Try, /*On fail goto*//*Label 835*/ 40759, // Rule ID 9460 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 587:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQSHRUNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9460, GIR_Done, // Label 835: @40759 GIM_Try, /*On fail goto*//*Label 836*/ 40875, // Rule ID 9464 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 631:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (UQRSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9464, GIR_Done, // Label 836: @40875 GIM_Try, /*On fail goto*//*Label 837*/ 40991, // Rule ID 9467 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 633:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (UQSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9467, GIR_Done, // Label 837: @40991 GIM_Try, /*On fail goto*//*Label 838*/ 41109, // Rule ID 9447 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VASHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[2] imm GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm))) => (SHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9447, GIR_Done, // Label 838: @41109 GIM_Try, /*On fail goto*//*Label 839*/ 41225, // Rule ID 9479 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[2] imm GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm))) => (SHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9479, GIR_Done, // Label 839: @41225 GIM_Try, /*On fail goto*//*Label 840*/ 41334, // Rule ID 6811 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_addhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 479:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (ADDHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv4i32_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6811, GIR_Done, // Label 840: @41334 GIM_Try, /*On fail goto*//*Label 841*/ 41443, // Rule ID 8808 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_subhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 604:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (SUBHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv4i32_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8808, GIR_Done, // Label 841: @41443 GIM_Try, /*On fail goto*//*Label 842*/ 41552, // Rule ID 8811 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_raddhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 546:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (RADDHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv4i32_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8811, GIR_Done, // Label 842: @41552 GIM_Try, /*On fail goto*//*Label 843*/ 41661, // Rule ID 8814 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 548:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (RSUBHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv4i32_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8814, GIR_Done, // Label 843: @41661 GIM_Try, /*On fail goto*//*Label 844*/ 41758, // Rule ID 6807 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 589:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (SQXTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6807, GIR_Done, // Label 844: @41758 GIM_Try, /*On fail goto*//*Label 845*/ 41853, // Rule ID 8528 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2hf, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 654:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)) => (FCVTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8528, GIR_Done, // Label 845: @41853 GIM_Try, /*On fail goto*//*Label 846*/ 41950, // Rule ID 8562 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 590:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (SQXTUNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8562, GIR_Done, // Label 846: @41950 GIM_Try, /*On fail goto*//*Label 847*/ 42047, // Rule ID 8565 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 635:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (UQXTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8565, GIR_Done, // Label 847: @42047 GIM_Try, /*On fail goto*//*Label 848*/ 42103, // Rule ID 8916 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v8i16] } (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vn), (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vm)) => (UZP1v8i16:{ *:[v8i16] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP1v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8916, GIR_Done, // Label 848: @42103 GIM_Try, /*On fail goto*//*Label 849*/ 42193, // Rule ID 8568 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)) => (XTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XTNv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8568, GIR_Done, // Label 849: @42193 GIM_Try, /*On fail goto*//*Label 850*/ 42253, // Rule ID 9070 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rn, (undef:{ *:[v4i16] })) => (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR64RegClassID, // GIR_Coverage, 9070, GIR_Done, // Label 850: @42253 GIM_Try, /*On fail goto*//*Label 851*/ 42379, // Rule ID 9062 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) => (INSvi64lane:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/3, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9062, GIR_Done, // Label 851: @42379 GIM_Try, /*On fail goto*//*Label 852*/ 42505, // Rule ID 9063 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn) => (INSvi64lane:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/3, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9063, GIR_Done, // Label 852: @42505 GIM_Try, /*On fail goto*//*Label 853*/ 42631, // Rule ID 9064 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (concat_vectors:{ *:[v8bf16] } V64:{ *:[v4bf16] }:$Rd, V64:{ *:[v4bf16] }:$Rn) => (INSvi64lane:{ *:[v8bf16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4bf16] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4bf16] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/3, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9064, GIR_Done, // Label 853: @42631 GIM_Reject, // Label 828: @42632 GIM_Reject, // Label 792: @42633 GIM_Try, /*On fail goto*//*Label 854*/ 44953, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 855*/ 42760, // Rule ID 8831 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ADD, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // MIs[2] Operand 2 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 8, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] }))) => (ADDHNv8i16_v16i8:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv8i16_v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8831, GIR_Done, // Label 855: @42760 GIM_Try, /*On fail goto*//*Label 856*/ 42873, // Rule ID 8837 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // MIs[2] Operand 2 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 8, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] }))) => (SUBHNv8i16_v16i8:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv8i16_v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8837, GIR_Done, // Label 856: @42873 GIM_Try, /*On fail goto*//*Label 857*/ 42963, // Rule ID 8918 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[2] Operand 2 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 8, GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, AArch64::G_VLSHR, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[4] Operand 2 GIM_CheckLiteralInt, /*MI*/4, /*Op*/2, 8, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (concat_vectors:{ *:[v16i8] } (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, 8:{ *:[i32] })), (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vm, 8:{ *:[i32] }))) => (UZP2v16i8:{ *:[v16i8] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8918, GIR_Done, // Label 857: @42963 GIM_Try, /*On fail goto*//*Label 858*/ 43079, // Rule ID 9450 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 582:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQRSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9450, GIR_Done, // Label 858: @43079 GIM_Try, /*On fail goto*//*Label 859*/ 43195, // Rule ID 9453 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 583:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQRSHRUNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9453, GIR_Done, // Label 859: @43195 GIM_Try, /*On fail goto*//*Label 860*/ 43311, // Rule ID 9456 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 586:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9456, GIR_Done, // Label 860: @43311 GIM_Try, /*On fail goto*//*Label 861*/ 43427, // Rule ID 9459 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 587:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQSHRUNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9459, GIR_Done, // Label 861: @43427 GIM_Try, /*On fail goto*//*Label 862*/ 43543, // Rule ID 9463 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 631:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (UQRSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9463, GIR_Done, // Label 862: @43543 GIM_Try, /*On fail goto*//*Label 863*/ 43659, // Rule ID 9466 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 633:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (UQSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9466, GIR_Done, // Label 863: @43659 GIM_Try, /*On fail goto*//*Label 864*/ 43777, // Rule ID 9446 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VASHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[2] imm GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm))) => (SHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9446, GIR_Done, // Label 864: @43777 GIM_Try, /*On fail goto*//*Label 865*/ 43893, // Rule ID 9478 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[2] imm GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm))) => (SHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9478, GIR_Done, // Label 865: @43893 GIM_Try, /*On fail goto*//*Label 866*/ 44002, // Rule ID 6810 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_addhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 479:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (ADDHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv8i16_v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6810, GIR_Done, // Label 866: @44002 GIM_Try, /*On fail goto*//*Label 867*/ 44111, // Rule ID 8807 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_subhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 604:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (SUBHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv8i16_v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8807, GIR_Done, // Label 867: @44111 GIM_Try, /*On fail goto*//*Label 868*/ 44220, // Rule ID 8810 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_raddhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 546:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (RADDHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv8i16_v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8810, GIR_Done, // Label 868: @44220 GIM_Try, /*On fail goto*//*Label 869*/ 44329, // Rule ID 8813 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 548:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (RSUBHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv8i16_v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8813, GIR_Done, // Label 869: @44329 GIM_Try, /*On fail goto*//*Label 870*/ 44426, // Rule ID 6806 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 589:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SQXTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6806, GIR_Done, // Label 870: @44426 GIM_Try, /*On fail goto*//*Label 871*/ 44523, // Rule ID 8561 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 590:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SQXTUNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8561, GIR_Done, // Label 871: @44523 GIM_Try, /*On fail goto*//*Label 872*/ 44620, // Rule ID 8564 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 635:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (UQXTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8564, GIR_Done, // Label 872: @44620 GIM_Try, /*On fail goto*//*Label 873*/ 44676, // Rule ID 8915 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v16i8] } (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Vn), (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Vm)) => (UZP1v16i8:{ *:[v16i8] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP1v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8915, GIR_Done, // Label 873: @44676 GIM_Try, /*On fail goto*//*Label 874*/ 44766, // Rule ID 8567 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)) => (XTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XTNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8567, GIR_Done, // Label 874: @44766 GIM_Try, /*On fail goto*//*Label 875*/ 44826, // Rule ID 9071 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rn, (undef:{ *:[v8i8] })) => (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR64RegClassID, // GIR_Coverage, 9071, GIR_Done, // Label 875: @44826 GIM_Try, /*On fail goto*//*Label 876*/ 44952, // Rule ID 9065 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) => (INSvi64lane:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/3, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9065, GIR_Done, // Label 876: @44952 GIM_Reject, // Label 854: @44953 GIM_Reject, // Label 793: @44954 GIM_Reject, // Label 788: @44955 GIM_Reject, // Label 9: @44956 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 23, /*)*//*default:*//*Label 892*/ 56738, /*GILLT_s16*//*Label 877*/ 44985, /*GILLT_s32*//*Label 878*/ 45041, /*GILLT_s64*//*Label 879*/ 45331, /*GILLT_s128*//*Label 880*/ 47411, /*GILLT_v2s32*//*Label 881*/ 48188, /*GILLT_v2s64*//*Label 882*/ 49197, /*GILLT_v4s16*//*Label 883*/ 50092, /*GILLT_v4s32*//*Label 884*/ 51466, /*GILLT_v8s8*//*Label 885*/ 52425, /*GILLT_v8s16*//*Label 886*/ 53026, /*GILLT_v16s8*//*Label 887*/ 54325, 0, 0, 0, 0, /*GILLT_nxv2s64*//*Label 888*/ 54830, 0, 0, /*GILLT_nxv4s32*//*Label 889*/ 55307, 0, /*GILLT_nxv8s16*//*Label 890*/ 55784, 0, /*GILLT_nxv16s8*//*Label 891*/ 56499, // Label 877: @44985 GIM_Try, /*On fail goto*//*Label 893*/ 45040, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_Try, /*On fail goto*//*Label 894*/ 45019, // Rule ID 9827 // // (bitconvert:{ *:[f16] } FPR16:{ *:[bf16] }:$src) => FPR16:{ *:[f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR16RegClassID, // GIR_Coverage, 9827, GIR_Done, // Label 894: @45019 GIM_Try, /*On fail goto*//*Label 895*/ 45039, // Rule ID 9828 // // (bitconvert:{ *:[bf16] } FPR16:{ *:[f16] }:$src) => FPR16:{ *:[bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR16RegClassID, // GIR_Coverage, 9828, GIR_Done, // Label 895: @45039 GIM_Reject, // Label 893: @45040 GIM_Reject, // Label 878: @45041 GIM_Try, /*On fail goto*//*Label 896*/ 45330, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 897*/ 45110, // Rule ID 10208 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><>) => (LDRSroW:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10208, GIR_Done, // Label 897: @45110 GIM_Try, /*On fail goto*//*Label 898*/ 45173, // Rule ID 10209 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><>) => (LDRSroX:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10209, GIR_Done, // Label 898: @45173 GIM_Try, /*On fail goto*//*Label 899*/ 45232, // Rule ID 10210 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><>) => (LDRSui:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10210, GIR_Done, // Label 899: @45232 GIM_Try, /*On fail goto*//*Label 900*/ 45291, // Rule ID 10211 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><>) => (LDURSi:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10211, GIR_Done, // Label 900: @45291 GIM_Try, /*On fail goto*//*Label 901*/ 45310, // Rule ID 9822 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (bitconvert:{ *:[f32] } GPR32:{ *:[i32] }:$Xn) => (COPY_TO_REGCLASS:{ *:[f32] } GPR32:{ *:[i32] }:$Xn, FPR32:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, // GIR_Coverage, 9822, GIR_Done, // Label 901: @45310 GIM_Try, /*On fail goto*//*Label 902*/ 45329, // Rule ID 9823 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Xn) => (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$Xn, GPR32:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, // GIR_Coverage, 9823, GIR_Done, // Label 902: @45329 GIM_Reject, // Label 896: @45330 GIM_Reject, // Label 879: @45331 GIM_Try, /*On fail goto*//*Label 903*/ 45398, // Rule ID 10212 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><>) => (LDRDroW:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10212, GIR_Done, // Label 903: @45398 GIM_Try, /*On fail goto*//*Label 904*/ 45465, // Rule ID 10213 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><>) => (LDRDroX:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10213, GIR_Done, // Label 904: @45465 GIM_Try, /*On fail goto*//*Label 905*/ 45528, // Rule ID 10214 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><>) => (LDRDui:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10214, GIR_Done, // Label 905: @45528 GIM_Try, /*On fail goto*//*Label 906*/ 45591, // Rule ID 10215 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><>) => (LDURDi:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10215, GIR_Done, // Label 906: @45591 GIM_Try, /*On fail goto*//*Label 907*/ 45616, // Rule ID 9797 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v8i8] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v8i8] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, // GIR_Coverage, 9797, GIR_Done, // Label 907: @45616 GIM_Try, /*On fail goto*//*Label 908*/ 45641, // Rule ID 9798 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v4i16] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4i16] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, // GIR_Coverage, 9798, GIR_Done, // Label 908: @45641 GIM_Try, /*On fail goto*//*Label 909*/ 45666, // Rule ID 9799 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v2i32] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2i32] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, // GIR_Coverage, 9799, GIR_Done, // Label 909: @45666 GIM_Try, /*On fail goto*//*Label 910*/ 45691, // Rule ID 9800 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v4f16] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4f16] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, // GIR_Coverage, 9800, GIR_Done, // Label 910: @45691 GIM_Try, /*On fail goto*//*Label 911*/ 45716, // Rule ID 9801 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v4bf16] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4bf16] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, // GIR_Coverage, 9801, GIR_Done, // Label 911: @45716 GIM_Try, /*On fail goto*//*Label 912*/ 45741, // Rule ID 9802 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v2f32] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2f32] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, // GIR_Coverage, 9802, GIR_Done, // Label 912: @45741 GIM_Try, /*On fail goto*//*Label 913*/ 45766, // Rule ID 9803 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f64] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, // GIR_Coverage, 9803, GIR_Done, // Label 913: @45766 GIM_Try, /*On fail goto*//*Label 914*/ 45814, // Rule ID 9810 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v8i8] }:$Vn) => (REV64v8i8:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v8i8] }:$Vn, GPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9810, GIR_Done, // Label 914: @45814 GIM_Try, /*On fail goto*//*Label 915*/ 45862, // Rule ID 9811 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v4i16] }:$Vn) => (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4i16] }:$Vn, GPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9811, GIR_Done, // Label 915: @45862 GIM_Try, /*On fail goto*//*Label 916*/ 45910, // Rule ID 9812 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v2i32] }:$Vn) => (REV64v2i32:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2i32] }:$Vn, GPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9812, GIR_Done, // Label 916: @45910 GIM_Try, /*On fail goto*//*Label 917*/ 45958, // Rule ID 9813 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v4f16] }:$Vn) => (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4f16] }:$Vn, GPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9813, GIR_Done, // Label 917: @45958 GIM_Try, /*On fail goto*//*Label 918*/ 46006, // Rule ID 9814 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v4bf16] }:$Vn) => (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4bf16] }:$Vn, GPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9814, GIR_Done, // Label 918: @46006 GIM_Try, /*On fail goto*//*Label 919*/ 46054, // Rule ID 9815 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v2f32] }:$Vn) => (REV64v2i32:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2f32] }:$Vn, GPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9815, GIR_Done, // Label 919: @46054 GIM_Try, /*On fail goto*//*Label 920*/ 46077, // Rule ID 9816 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9816, GIR_Done, // Label 920: @46077 GIM_Try, /*On fail goto*//*Label 921*/ 46100, // Rule ID 9817 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9817, GIR_Done, // Label 921: @46100 GIM_Try, /*On fail goto*//*Label 922*/ 46123, // Rule ID 9818 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v1i64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1i64] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, // GIR_Coverage, 9818, GIR_Done, // Label 922: @46123 GIM_Try, /*On fail goto*//*Label 923*/ 46146, // Rule ID 9824 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[f64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9824, GIR_Done, // Label 923: @46146 GIM_Try, /*On fail goto*//*Label 924*/ 46169, // Rule ID 9825 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[i64] } FPR64:{ *:[f64] }:$Xn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, // GIR_Coverage, 9825, GIR_Done, // Label 924: @46169 GIM_Try, /*On fail goto*//*Label 925*/ 46192, // Rule ID 9826 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f64] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, // GIR_Coverage, 9826, GIR_Done, // Label 925: @46192 GIM_Try, /*On fail goto*//*Label 926*/ 46226, // Rule ID 9829 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9829, GIR_Done, // Label 926: @46226 GIM_Try, /*On fail goto*//*Label 927*/ 46260, // Rule ID 9830 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9830, GIR_Done, // Label 927: @46260 GIM_Try, /*On fail goto*//*Label 928*/ 46294, // Rule ID 9831 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9831, GIR_Done, // Label 928: @46294 GIM_Try, /*On fail goto*//*Label 929*/ 46328, // Rule ID 9832 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9832, GIR_Done, // Label 929: @46328 GIM_Try, /*On fail goto*//*Label 930*/ 46362, // Rule ID 9833 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9833, GIR_Done, // Label 930: @46362 GIM_Try, /*On fail goto*//*Label 931*/ 46396, // Rule ID 9834 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9834, GIR_Done, // Label 931: @46396 GIM_Try, /*On fail goto*//*Label 932*/ 46419, // Rule ID 9835 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src) => (REV64v2i32:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9835, GIR_Done, // Label 932: @46419 GIM_Try, /*On fail goto*//*Label 933*/ 46442, // Rule ID 9836 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src) => (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9836, GIR_Done, // Label 933: @46442 GIM_Try, /*On fail goto*//*Label 934*/ 46465, // Rule ID 9837 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src) => (REV64v8i8:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9837, GIR_Done, // Label 934: @46465 GIM_Try, /*On fail goto*//*Label 935*/ 46488, // Rule ID 9838 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src) => (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9838, GIR_Done, // Label 935: @46488 GIM_Try, /*On fail goto*//*Label 936*/ 46511, // Rule ID 9839 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4bf16] }:$src) => (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4bf16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9839, GIR_Done, // Label 936: @46511 GIM_Try, /*On fail goto*//*Label 937*/ 46534, // Rule ID 9840 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src) => (REV64v2i32:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9840, GIR_Done, // Label 937: @46534 GIM_Try, /*On fail goto*//*Label 938*/ 46566, // Rule ID 9841 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9841, GIR_Done, // Label 938: @46566 GIM_Try, /*On fail goto*//*Label 939*/ 46598, // Rule ID 9842 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9842, GIR_Done, // Label 939: @46598 GIM_Try, /*On fail goto*//*Label 940*/ 46632, // Rule ID 9914 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9914, GIR_Done, // Label 940: @46632 GIM_Try, /*On fail goto*//*Label 941*/ 46666, // Rule ID 9915 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9915, GIR_Done, // Label 941: @46666 GIM_Try, /*On fail goto*//*Label 942*/ 46700, // Rule ID 9916 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9916, GIR_Done, // Label 942: @46700 GIM_Try, /*On fail goto*//*Label 943*/ 46734, // Rule ID 9917 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9917, GIR_Done, // Label 943: @46734 GIM_Try, /*On fail goto*//*Label 944*/ 46768, // Rule ID 9918 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9918, GIR_Done, // Label 944: @46768 GIM_Try, /*On fail goto*//*Label 945*/ 46802, // Rule ID 9919 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9919, GIR_Done, // Label 945: @46802 GIM_Try, /*On fail goto*//*Label 946*/ 46825, // Rule ID 9920 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v2i32] }:$src) => (REV64v2i32:{ *:[f64] } FPR64:{ *:[v2i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9920, GIR_Done, // Label 946: @46825 GIM_Try, /*On fail goto*//*Label 947*/ 46848, // Rule ID 9921 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v4i16] }:$src) => (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9921, GIR_Done, // Label 947: @46848 GIM_Try, /*On fail goto*//*Label 948*/ 46871, // Rule ID 9922 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v2f32] }:$src) => (REV64v2i32:{ *:[f64] } FPR64:{ *:[v2f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9922, GIR_Done, // Label 948: @46871 GIM_Try, /*On fail goto*//*Label 949*/ 46894, // Rule ID 9923 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v8i8] }:$src) => (REV64v8i8:{ *:[f64] } FPR64:{ *:[v8i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9923, GIR_Done, // Label 949: @46894 GIM_Try, /*On fail goto*//*Label 950*/ 46917, // Rule ID 9924 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v4f16] }:$src) => (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9924, GIR_Done, // Label 950: @46917 GIM_Try, /*On fail goto*//*Label 951*/ 46940, // Rule ID 9925 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v4bf16] }:$src) => (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4bf16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9925, GIR_Done, // Label 951: @46940 GIM_Try, /*On fail goto*//*Label 952*/ 46972, // Rule ID 9926 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9926, GIR_Done, // Label 952: @46972 GIM_Try, /*On fail goto*//*Label 953*/ 47004, // Rule ID 9927 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9927, GIR_Done, // Label 953: @47004 GIM_Try, /*On fail goto*//*Label 954*/ 47038, // Rule ID 9928 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v1f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9928, GIR_Done, // Label 954: @47038 GIM_Try, /*On fail goto*//*Label 955*/ 47072, // Rule ID 9929 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v1f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9929, GIR_Done, // Label 955: @47072 GIM_Try, /*On fail goto*//*Label 956*/ 47106, // Rule ID 9930 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v1f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9930, GIR_Done, // Label 956: @47106 GIM_Try, /*On fail goto*//*Label 957*/ 47140, // Rule ID 9931 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v1f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9931, GIR_Done, // Label 957: @47140 GIM_Try, /*On fail goto*//*Label 958*/ 47174, // Rule ID 9932 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v1f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9932, GIR_Done, // Label 958: @47174 GIM_Try, /*On fail goto*//*Label 959*/ 47208, // Rule ID 9933 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v1f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9933, GIR_Done, // Label 959: @47208 GIM_Try, /*On fail goto*//*Label 960*/ 47231, // Rule ID 9934 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src) => (REV64v2i32:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9934, GIR_Done, // Label 960: @47231 GIM_Try, /*On fail goto*//*Label 961*/ 47254, // Rule ID 9935 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src) => (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9935, GIR_Done, // Label 961: @47254 GIM_Try, /*On fail goto*//*Label 962*/ 47277, // Rule ID 9936 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src) => (REV64v8i8:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9936, GIR_Done, // Label 962: @47277 GIM_Try, /*On fail goto*//*Label 963*/ 47300, // Rule ID 9937 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src) => (REV64v2i32:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9937, GIR_Done, // Label 963: @47300 GIM_Try, /*On fail goto*//*Label 964*/ 47323, // Rule ID 9938 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src) => (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9938, GIR_Done, // Label 964: @47323 GIM_Try, /*On fail goto*//*Label 965*/ 47346, // Rule ID 9939 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4bf16] }:$src) => (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4bf16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9939, GIR_Done, // Label 965: @47346 GIM_Try, /*On fail goto*//*Label 966*/ 47378, // Rule ID 9940 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v1f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9940, GIR_Done, // Label 966: @47378 GIM_Try, /*On fail goto*//*Label 967*/ 47410, // Rule ID 9941 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v1f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9941, GIR_Done, // Label 967: @47410 GIM_Reject, // Label 880: @47411 GIM_Try, /*On fail goto*//*Label 968*/ 47445, // Rule ID 9957 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[f128] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9957, GIR_Done, // Label 968: @47445 GIM_Try, /*On fail goto*//*Label 969*/ 47479, // Rule ID 9958 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[f128] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9958, GIR_Done, // Label 969: @47479 GIM_Try, /*On fail goto*//*Label 970*/ 47513, // Rule ID 9959 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[f128] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9959, GIR_Done, // Label 970: @47513 GIM_Try, /*On fail goto*//*Label 971*/ 47547, // Rule ID 9960 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[f128] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9960, GIR_Done, // Label 971: @47547 GIM_Try, /*On fail goto*//*Label 972*/ 47581, // Rule ID 9961 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[f128] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9961, GIR_Done, // Label 972: @47581 GIM_Try, /*On fail goto*//*Label 973*/ 47615, // Rule ID 9962 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[f128] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9962, GIR_Done, // Label 973: @47615 GIM_Try, /*On fail goto*//*Label 974*/ 47649, // Rule ID 9963 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[f128] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9963, GIR_Done, // Label 974: @47649 GIM_Try, /*On fail goto*//*Label 975*/ 47683, // Rule ID 9964 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[f128] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9964, GIR_Done, // Label 975: @47683 GIM_Try, /*On fail goto*//*Label 976*/ 47722, // Rule ID 9965 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v2i64] }:$src) => (EXTv16i8:{ *:[f128] } FPR128:{ *:[v2i64] }:$src, FPR128:{ *:[v2i64] }:$src, 8:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9965, GIR_Done, // Label 976: @47722 GIM_Try, /*On fail goto*//*Label 977*/ 47793, // Rule ID 9966 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v4i32] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4i32] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4i32] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9966, GIR_Done, // Label 977: @47793 GIM_Try, /*On fail goto*//*Label 978*/ 47864, // Rule ID 9967 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v8i16] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8i16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8i16] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9967, GIR_Done, // Label 978: @47864 GIM_Try, /*On fail goto*//*Label 979*/ 47935, // Rule ID 9968 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v8f16] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8f16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8f16] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9968, GIR_Done, // Label 979: @47935 GIM_Try, /*On fail goto*//*Label 980*/ 48006, // Rule ID 9969 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v8bf16] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8bf16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8bf16] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9969, GIR_Done, // Label 980: @48006 GIM_Try, /*On fail goto*//*Label 981*/ 48045, // Rule ID 9970 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v2f64] }:$src) => (EXTv16i8:{ *:[f128] } FPR128:{ *:[v2f64] }:$src, FPR128:{ *:[v2f64] }:$src, 8:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9970, GIR_Done, // Label 981: @48045 GIM_Try, /*On fail goto*//*Label 982*/ 48116, // Rule ID 9971 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v4f32] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4f32] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4f32] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9971, GIR_Done, // Label 982: @48116 GIM_Try, /*On fail goto*//*Label 983*/ 48187, // Rule ID 9972 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v16i8] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v16i8:{ *:[f128] } FPR128:{ *:[v16i8] }:$src), (REV64v16i8:{ *:[f128] } FPR128:{ *:[v16i8] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v16i8, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v16i8, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9972, GIR_Done, // Label 983: @48187 GIM_Reject, // Label 881: @48188 GIM_Try, /*On fail goto*//*Label 984*/ 48213, // Rule ID 9793 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9793, GIR_Done, // Label 984: @48213 GIM_Try, /*On fail goto*//*Label 985*/ 48238, // Rule ID 9796 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9796, GIR_Done, // Label 985: @48238 GIM_Try, /*On fail goto*//*Label 986*/ 48286, // Rule ID 9806 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn) => (REV64v2i32:{ *:[v2i32] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9806, GIR_Done, // Label 986: @48286 GIM_Try, /*On fail goto*//*Label 987*/ 48334, // Rule ID 9809 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn) => (REV64v2i32:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9809, GIR_Done, // Label 987: @48334 GIM_Try, /*On fail goto*//*Label 988*/ 48368, // Rule ID 9843 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9843, GIR_Done, // Label 988: @48368 GIM_Try, /*On fail goto*//*Label 989*/ 48402, // Rule ID 9844 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9844, GIR_Done, // Label 989: @48402 GIM_Try, /*On fail goto*//*Label 990*/ 48436, // Rule ID 9845 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9845, GIR_Done, // Label 990: @48436 GIM_Try, /*On fail goto*//*Label 991*/ 48470, // Rule ID 9846 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9846, GIR_Done, // Label 991: @48470 GIM_Try, /*On fail goto*//*Label 992*/ 48504, // Rule ID 9847 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9847, GIR_Done, // Label 992: @48504 GIM_Try, /*On fail goto*//*Label 993*/ 48538, // Rule ID 9848 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9848, GIR_Done, // Label 993: @48538 GIM_Try, /*On fail goto*//*Label 994*/ 48572, // Rule ID 9849 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9849, GIR_Done, // Label 994: @48572 GIM_Try, /*On fail goto*//*Label 995*/ 48595, // Rule ID 9850 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src) => (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9850, GIR_Done, // Label 995: @48595 GIM_Try, /*On fail goto*//*Label 996*/ 48618, // Rule ID 9851 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src) => (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9851, GIR_Done, // Label 996: @48618 GIM_Try, /*On fail goto*//*Label 997*/ 48641, // Rule ID 9852 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src) => (REV32v8i8:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9852, GIR_Done, // Label 997: @48641 GIM_Try, /*On fail goto*//*Label 998*/ 48664, // Rule ID 9853 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[f64] }:$src) => (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9853, GIR_Done, // Label 998: @48664 GIM_Try, /*On fail goto*//*Label 999*/ 48687, // Rule ID 9854 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src) => (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9854, GIR_Done, // Label 999: @48687 GIM_Try, /*On fail goto*//*Label 1000*/ 48710, // Rule ID 9855 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src) => (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9855, GIR_Done, // Label 1000: @48710 GIM_Try, /*On fail goto*//*Label 1001*/ 48733, // Rule ID 9856 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4bf16] }:$src) => (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4bf16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9856, GIR_Done, // Label 1001: @48733 GIM_Try, /*On fail goto*//*Label 1002*/ 48765, // Rule ID 9857 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9857, GIR_Done, // Label 1002: @48765 GIM_Try, /*On fail goto*//*Label 1003*/ 48799, // Rule ID 9942 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9942, GIR_Done, // Label 1003: @48799 GIM_Try, /*On fail goto*//*Label 1004*/ 48833, // Rule ID 9943 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9943, GIR_Done, // Label 1004: @48833 GIM_Try, /*On fail goto*//*Label 1005*/ 48867, // Rule ID 9944 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9944, GIR_Done, // Label 1005: @48867 GIM_Try, /*On fail goto*//*Label 1006*/ 48901, // Rule ID 9945 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9945, GIR_Done, // Label 1006: @48901 GIM_Try, /*On fail goto*//*Label 1007*/ 48935, // Rule ID 9946 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9946, GIR_Done, // Label 1007: @48935 GIM_Try, /*On fail goto*//*Label 1008*/ 48969, // Rule ID 9947 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9947, GIR_Done, // Label 1008: @48969 GIM_Try, /*On fail goto*//*Label 1009*/ 49003, // Rule ID 9948 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9948, GIR_Done, // Label 1009: @49003 GIM_Try, /*On fail goto*//*Label 1010*/ 49026, // Rule ID 9949 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src) => (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9949, GIR_Done, // Label 1010: @49026 GIM_Try, /*On fail goto*//*Label 1011*/ 49049, // Rule ID 9950 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src) => (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9950, GIR_Done, // Label 1011: @49049 GIM_Try, /*On fail goto*//*Label 1012*/ 49072, // Rule ID 9951 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src) => (REV32v8i8:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9951, GIR_Done, // Label 1012: @49072 GIM_Try, /*On fail goto*//*Label 1013*/ 49095, // Rule ID 9952 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src) => (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9952, GIR_Done, // Label 1013: @49095 GIM_Try, /*On fail goto*//*Label 1014*/ 49118, // Rule ID 9953 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[f64] }:$src) => (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9953, GIR_Done, // Label 1014: @49118 GIM_Try, /*On fail goto*//*Label 1015*/ 49141, // Rule ID 9954 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src) => (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9954, GIR_Done, // Label 1015: @49141 GIM_Try, /*On fail goto*//*Label 1016*/ 49164, // Rule ID 9955 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4bf16] }:$src) => (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4bf16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9955, GIR_Done, // Label 1016: @49164 GIM_Try, /*On fail goto*//*Label 1017*/ 49196, // Rule ID 9956 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9956, GIR_Done, // Label 1017: @49196 GIM_Reject, // Label 882: @49197 GIM_Try, /*On fail goto*//*Label 1018*/ 49231, // Rule ID 9973 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9973, GIR_Done, // Label 1018: @49231 GIM_Try, /*On fail goto*//*Label 1019*/ 49265, // Rule ID 9974 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9974, GIR_Done, // Label 1019: @49265 GIM_Try, /*On fail goto*//*Label 1020*/ 49299, // Rule ID 9975 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9975, GIR_Done, // Label 1020: @49299 GIM_Try, /*On fail goto*//*Label 1021*/ 49333, // Rule ID 9976 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9976, GIR_Done, // Label 1021: @49333 GIM_Try, /*On fail goto*//*Label 1022*/ 49367, // Rule ID 9977 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9977, GIR_Done, // Label 1022: @49367 GIM_Try, /*On fail goto*//*Label 1023*/ 49401, // Rule ID 9978 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9978, GIR_Done, // Label 1023: @49401 GIM_Try, /*On fail goto*//*Label 1024*/ 49435, // Rule ID 9979 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9979, GIR_Done, // Label 1024: @49435 GIM_Try, /*On fail goto*//*Label 1025*/ 49474, // Rule ID 9980 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v2f64] } FPR128:{ *:[f128] }:$src, FPR128:{ *:[f128] }:$src, 8:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9980, GIR_Done, // Label 1025: @49474 GIM_Try, /*On fail goto*//*Label 1026*/ 49497, // Rule ID 9981 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src) => (REV64v4i32:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9981, GIR_Done, // Label 1026: @49497 GIM_Try, /*On fail goto*//*Label 1027*/ 49520, // Rule ID 9982 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src) => (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9982, GIR_Done, // Label 1027: @49520 GIM_Try, /*On fail goto*//*Label 1028*/ 49543, // Rule ID 9983 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) => (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9983, GIR_Done, // Label 1028: @49543 GIM_Try, /*On fail goto*//*Label 1029*/ 49566, // Rule ID 9984 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8bf16] }:$src) => (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8bf16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9984, GIR_Done, // Label 1029: @49566 GIM_Try, /*On fail goto*//*Label 1030*/ 49589, // Rule ID 9985 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src) => (REV64v16i8:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9985, GIR_Done, // Label 1030: @49589 GIM_Try, /*On fail goto*//*Label 1031*/ 49612, // Rule ID 9986 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src) => (REV64v4i32:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9986, GIR_Done, // Label 1031: @49612 GIM_Try, /*On fail goto*//*Label 1032*/ 49644, // Rule ID 9987 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9987, GIR_Done, // Label 1032: @49644 GIM_Try, /*On fail goto*//*Label 1033*/ 49678, // Rule ID 10003 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10003, GIR_Done, // Label 1033: @49678 GIM_Try, /*On fail goto*//*Label 1034*/ 49712, // Rule ID 10004 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10004, GIR_Done, // Label 1034: @49712 GIM_Try, /*On fail goto*//*Label 1035*/ 49746, // Rule ID 10005 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10005, GIR_Done, // Label 1035: @49746 GIM_Try, /*On fail goto*//*Label 1036*/ 49780, // Rule ID 10006 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10006, GIR_Done, // Label 1036: @49780 GIM_Try, /*On fail goto*//*Label 1037*/ 49814, // Rule ID 10007 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10007, GIR_Done, // Label 1037: @49814 GIM_Try, /*On fail goto*//*Label 1038*/ 49848, // Rule ID 10008 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10008, GIR_Done, // Label 1038: @49848 GIM_Try, /*On fail goto*//*Label 1039*/ 49882, // Rule ID 10009 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10009, GIR_Done, // Label 1039: @49882 GIM_Try, /*On fail goto*//*Label 1040*/ 49921, // Rule ID 10010 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v2i64] } FPR128:{ *:[f128] }:$src, FPR128:{ *:[f128] }:$src, 8:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10010, GIR_Done, // Label 1040: @49921 GIM_Try, /*On fail goto*//*Label 1041*/ 49944, // Rule ID 10011 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src) => (REV64v4i32:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10011, GIR_Done, // Label 1041: @49944 GIM_Try, /*On fail goto*//*Label 1042*/ 49967, // Rule ID 10012 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src) => (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10012, GIR_Done, // Label 1042: @49967 GIM_Try, /*On fail goto*//*Label 1043*/ 49990, // Rule ID 10013 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src) => (REV64v16i8:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10013, GIR_Done, // Label 1043: @49990 GIM_Try, /*On fail goto*//*Label 1044*/ 50013, // Rule ID 10014 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src) => (REV64v4i32:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10014, GIR_Done, // Label 1044: @50013 GIM_Try, /*On fail goto*//*Label 1045*/ 50036, // Rule ID 10015 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) => (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10015, GIR_Done, // Label 1045: @50036 GIM_Try, /*On fail goto*//*Label 1046*/ 50059, // Rule ID 10016 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8bf16] }:$src) => (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8bf16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10016, GIR_Done, // Label 1046: @50059 GIM_Try, /*On fail goto*//*Label 1047*/ 50091, // Rule ID 10017 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10017, GIR_Done, // Label 1047: @50091 GIM_Reject, // Label 883: @50092 GIM_Try, /*On fail goto*//*Label 1048*/ 50117, // Rule ID 9792 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9792, GIR_Done, // Label 1048: @50117 GIM_Try, /*On fail goto*//*Label 1049*/ 50142, // Rule ID 9794 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9794, GIR_Done, // Label 1049: @50142 GIM_Try, /*On fail goto*//*Label 1050*/ 50167, // Rule ID 9795 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v4bf16] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v4bf16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9795, GIR_Done, // Label 1050: @50167 GIM_Try, /*On fail goto*//*Label 1051*/ 50215, // Rule ID 9805 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn) => (REV64v4i16:{ *:[v4i16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9805, GIR_Done, // Label 1051: @50215 GIM_Try, /*On fail goto*//*Label 1052*/ 50263, // Rule ID 9807 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn) => (REV64v4i16:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9807, GIR_Done, // Label 1052: @50263 GIM_Try, /*On fail goto*//*Label 1053*/ 50311, // Rule ID 9808 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v4bf16] } GPR64:{ *:[i64] }:$Xn) => (REV64v4i16:{ *:[v4bf16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9808, GIR_Done, // Label 1053: @50311 GIM_Try, /*On fail goto*//*Label 1054*/ 50345, // Rule ID 9858 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9858, GIR_Done, // Label 1054: @50345 GIM_Try, /*On fail goto*//*Label 1055*/ 50379, // Rule ID 9859 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9859, GIR_Done, // Label 1055: @50379 GIM_Try, /*On fail goto*//*Label 1056*/ 50413, // Rule ID 9860 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9860, GIR_Done, // Label 1056: @50413 GIM_Try, /*On fail goto*//*Label 1057*/ 50447, // Rule ID 9861 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9861, GIR_Done, // Label 1057: @50447 GIM_Try, /*On fail goto*//*Label 1058*/ 50481, // Rule ID 9862 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9862, GIR_Done, // Label 1058: @50481 GIM_Try, /*On fail goto*//*Label 1059*/ 50515, // Rule ID 9863 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9863, GIR_Done, // Label 1059: @50515 GIM_Try, /*On fail goto*//*Label 1060*/ 50538, // Rule ID 9864 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src) => (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9864, GIR_Done, // Label 1060: @50538 GIM_Try, /*On fail goto*//*Label 1061*/ 50561, // Rule ID 9865 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src) => (REV32v4i16:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9865, GIR_Done, // Label 1061: @50561 GIM_Try, /*On fail goto*//*Label 1062*/ 50584, // Rule ID 9866 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src) => (REV16v8i8:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9866, GIR_Done, // Label 1062: @50584 GIM_Try, /*On fail goto*//*Label 1063*/ 50607, // Rule ID 9867 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[f64] }:$src) => (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9867, GIR_Done, // Label 1063: @50607 GIM_Try, /*On fail goto*//*Label 1064*/ 50630, // Rule ID 9868 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src) => (REV32v4i16:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9868, GIR_Done, // Label 1064: @50630 GIM_Try, /*On fail goto*//*Label 1065*/ 50653, // Rule ID 9869 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src) => (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9869, GIR_Done, // Label 1065: @50653 GIM_Try, /*On fail goto*//*Label 1066*/ 50685, // Rule ID 9870 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9870, GIR_Done, // Label 1066: @50685 GIM_Try, /*On fail goto*//*Label 1067*/ 50717, // Rule ID 9871 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9871, GIR_Done, // Label 1067: @50717 GIM_Try, /*On fail goto*//*Label 1068*/ 50751, // Rule ID 9872 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9872, GIR_Done, // Label 1068: @50751 GIM_Try, /*On fail goto*//*Label 1069*/ 50785, // Rule ID 9873 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9873, GIR_Done, // Label 1069: @50785 GIM_Try, /*On fail goto*//*Label 1070*/ 50819, // Rule ID 9874 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9874, GIR_Done, // Label 1070: @50819 GIM_Try, /*On fail goto*//*Label 1071*/ 50853, // Rule ID 9875 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9875, GIR_Done, // Label 1071: @50853 GIM_Try, /*On fail goto*//*Label 1072*/ 50887, // Rule ID 9876 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9876, GIR_Done, // Label 1072: @50887 GIM_Try, /*On fail goto*//*Label 1073*/ 50921, // Rule ID 9877 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9877, GIR_Done, // Label 1073: @50921 GIM_Try, /*On fail goto*//*Label 1074*/ 50955, // Rule ID 9878 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v4bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9878, GIR_Done, // Label 1074: @50955 GIM_Try, /*On fail goto*//*Label 1075*/ 50989, // Rule ID 9879 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v4bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9879, GIR_Done, // Label 1075: @50989 GIM_Try, /*On fail goto*//*Label 1076*/ 51023, // Rule ID 9880 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v4bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9880, GIR_Done, // Label 1076: @51023 GIM_Try, /*On fail goto*//*Label 1077*/ 51057, // Rule ID 9881 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v4bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9881, GIR_Done, // Label 1077: @51057 GIM_Try, /*On fail goto*//*Label 1078*/ 51091, // Rule ID 9882 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v4bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9882, GIR_Done, // Label 1078: @51091 GIM_Try, /*On fail goto*//*Label 1079*/ 51125, // Rule ID 9883 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v4bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9883, GIR_Done, // Label 1079: @51125 GIM_Try, /*On fail goto*//*Label 1080*/ 51148, // Rule ID 9884 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src) => (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9884, GIR_Done, // Label 1080: @51148 GIM_Try, /*On fail goto*//*Label 1081*/ 51171, // Rule ID 9885 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src) => (REV32v4i16:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9885, GIR_Done, // Label 1081: @51171 GIM_Try, /*On fail goto*//*Label 1082*/ 51194, // Rule ID 9886 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src) => (REV16v8i8:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9886, GIR_Done, // Label 1082: @51194 GIM_Try, /*On fail goto*//*Label 1083*/ 51217, // Rule ID 9887 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[f64] }:$src) => (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9887, GIR_Done, // Label 1083: @51217 GIM_Try, /*On fail goto*//*Label 1084*/ 51240, // Rule ID 9888 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src) => (REV32v4i16:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9888, GIR_Done, // Label 1084: @51240 GIM_Try, /*On fail goto*//*Label 1085*/ 51263, // Rule ID 9889 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src) => (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9889, GIR_Done, // Label 1085: @51263 GIM_Try, /*On fail goto*//*Label 1086*/ 51286, // Rule ID 9890 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v1i64] }:$src) => (REV64v4i16:{ *:[v4bf16] } FPR64:{ *:[v1i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9890, GIR_Done, // Label 1086: @51286 GIM_Try, /*On fail goto*//*Label 1087*/ 51309, // Rule ID 9891 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v2i32] }:$src) => (REV32v4i16:{ *:[v4bf16] } FPR64:{ *:[v2i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9891, GIR_Done, // Label 1087: @51309 GIM_Try, /*On fail goto*//*Label 1088*/ 51332, // Rule ID 9892 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v8i8] }:$src) => (REV16v8i8:{ *:[v4bf16] } FPR64:{ *:[v8i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9892, GIR_Done, // Label 1088: @51332 GIM_Try, /*On fail goto*//*Label 1089*/ 51355, // Rule ID 9893 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[f64] }:$src) => (REV64v4i16:{ *:[v4bf16] } FPR64:{ *:[f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9893, GIR_Done, // Label 1089: @51355 GIM_Try, /*On fail goto*//*Label 1090*/ 51378, // Rule ID 9894 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v2f32] }:$src) => (REV32v4i16:{ *:[v4bf16] } FPR64:{ *:[v2f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9894, GIR_Done, // Label 1090: @51378 GIM_Try, /*On fail goto*//*Label 1091*/ 51401, // Rule ID 9895 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v1f64] }:$src) => (REV64v4i16:{ *:[v4bf16] } FPR64:{ *:[v1f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9895, GIR_Done, // Label 1091: @51401 GIM_Try, /*On fail goto*//*Label 1092*/ 51433, // Rule ID 9896 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9896, GIR_Done, // Label 1092: @51433 GIM_Try, /*On fail goto*//*Label 1093*/ 51465, // Rule ID 9897 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v4bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9897, GIR_Done, // Label 1093: @51465 GIM_Reject, // Label 884: @51466 GIM_Try, /*On fail goto*//*Label 1094*/ 51500, // Rule ID 9988 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9988, GIR_Done, // Label 1094: @51500 GIM_Try, /*On fail goto*//*Label 1095*/ 51534, // Rule ID 9989 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9989, GIR_Done, // Label 1095: @51534 GIM_Try, /*On fail goto*//*Label 1096*/ 51568, // Rule ID 9990 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9990, GIR_Done, // Label 1096: @51568 GIM_Try, /*On fail goto*//*Label 1097*/ 51602, // Rule ID 9991 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9991, GIR_Done, // Label 1097: @51602 GIM_Try, /*On fail goto*//*Label 1098*/ 51636, // Rule ID 9992 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9992, GIR_Done, // Label 1098: @51636 GIM_Try, /*On fail goto*//*Label 1099*/ 51670, // Rule ID 9993 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9993, GIR_Done, // Label 1099: @51670 GIM_Try, /*On fail goto*//*Label 1100*/ 51704, // Rule ID 9994 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 9994, GIR_Done, // Label 1100: @51704 GIM_Try, /*On fail goto*//*Label 1101*/ 51775, // Rule ID 9995 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v4f32] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9995, GIR_Done, // Label 1101: @51775 GIM_Try, /*On fail goto*//*Label 1102*/ 51798, // Rule ID 9996 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src) => (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9996, GIR_Done, // Label 1102: @51798 GIM_Try, /*On fail goto*//*Label 1103*/ 51821, // Rule ID 9997 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) => (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9997, GIR_Done, // Label 1103: @51821 GIM_Try, /*On fail goto*//*Label 1104*/ 51844, // Rule ID 9998 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8bf16] }:$src) => (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8bf16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9998, GIR_Done, // Label 1104: @51844 GIM_Try, /*On fail goto*//*Label 1105*/ 51867, // Rule ID 9999 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src) => (REV32v16i8:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9999, GIR_Done, // Label 1105: @51867 GIM_Try, /*On fail goto*//*Label 1106*/ 51890, // Rule ID 10000 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src) => (REV64v4i32:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10000, GIR_Done, // Label 1106: @51890 GIM_Try, /*On fail goto*//*Label 1107*/ 51913, // Rule ID 10001 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src) => (REV64v4i32:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10001, GIR_Done, // Label 1107: @51913 GIM_Try, /*On fail goto*//*Label 1108*/ 51945, // Rule ID 10002 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10002, GIR_Done, // Label 1108: @51945 GIM_Try, /*On fail goto*//*Label 1109*/ 51979, // Rule ID 10018 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10018, GIR_Done, // Label 1109: @51979 GIM_Try, /*On fail goto*//*Label 1110*/ 52013, // Rule ID 10019 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10019, GIR_Done, // Label 1110: @52013 GIM_Try, /*On fail goto*//*Label 1111*/ 52047, // Rule ID 10020 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10020, GIR_Done, // Label 1111: @52047 GIM_Try, /*On fail goto*//*Label 1112*/ 52081, // Rule ID 10021 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10021, GIR_Done, // Label 1112: @52081 GIM_Try, /*On fail goto*//*Label 1113*/ 52115, // Rule ID 10022 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10022, GIR_Done, // Label 1113: @52115 GIM_Try, /*On fail goto*//*Label 1114*/ 52149, // Rule ID 10023 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10023, GIR_Done, // Label 1114: @52149 GIM_Try, /*On fail goto*//*Label 1115*/ 52183, // Rule ID 10024 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10024, GIR_Done, // Label 1115: @52183 GIM_Try, /*On fail goto*//*Label 1116*/ 52254, // Rule ID 10025 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v4i32] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10025, GIR_Done, // Label 1116: @52254 GIM_Try, /*On fail goto*//*Label 1117*/ 52277, // Rule ID 10026 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src) => (REV64v4i32:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10026, GIR_Done, // Label 1117: @52277 GIM_Try, /*On fail goto*//*Label 1118*/ 52300, // Rule ID 10027 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src) => (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10027, GIR_Done, // Label 1118: @52300 GIM_Try, /*On fail goto*//*Label 1119*/ 52323, // Rule ID 10028 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src) => (REV32v16i8:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10028, GIR_Done, // Label 1119: @52323 GIM_Try, /*On fail goto*//*Label 1120*/ 52346, // Rule ID 10029 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src) => (REV64v4i32:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10029, GIR_Done, // Label 1120: @52346 GIM_Try, /*On fail goto*//*Label 1121*/ 52369, // Rule ID 10030 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src) => (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10030, GIR_Done, // Label 1121: @52369 GIM_Try, /*On fail goto*//*Label 1122*/ 52392, // Rule ID 10031 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8bf16] }:$src) => (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8bf16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10031, GIR_Done, // Label 1122: @52392 GIM_Try, /*On fail goto*//*Label 1123*/ 52424, // Rule ID 10032 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10032, GIR_Done, // Label 1123: @52424 GIM_Reject, // Label 885: @52425 GIM_Try, /*On fail goto*//*Label 1124*/ 52496, // Rule ID 8997 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (bitconvert:{ *:[v8i8] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn)) => (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i32] }, (FMOVWSr:{ *:[f32] } GPR32:{ *:[i32] }:$Rn), ssub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FMOVWSr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR32RegClassID, // GIR_Coverage, 8997, GIR_Done, // Label 1124: @52496 GIM_Try, /*On fail goto*//*Label 1125*/ 52521, // Rule ID 9791 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9791, GIR_Done, // Label 1125: @52521 GIM_Try, /*On fail goto*//*Label 1126*/ 52569, // Rule ID 9804 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn) => (REV64v8i8:{ *:[v8i8] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9804, GIR_Done, // Label 1126: @52569 GIM_Try, /*On fail goto*//*Label 1127*/ 52603, // Rule ID 9898 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9898, GIR_Done, // Label 1127: @52603 GIM_Try, /*On fail goto*//*Label 1128*/ 52637, // Rule ID 9899 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9899, GIR_Done, // Label 1128: @52637 GIM_Try, /*On fail goto*//*Label 1129*/ 52671, // Rule ID 9900 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9900, GIR_Done, // Label 1129: @52671 GIM_Try, /*On fail goto*//*Label 1130*/ 52705, // Rule ID 9901 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9901, GIR_Done, // Label 1130: @52705 GIM_Try, /*On fail goto*//*Label 1131*/ 52739, // Rule ID 9902 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9902, GIR_Done, // Label 1131: @52739 GIM_Try, /*On fail goto*//*Label 1132*/ 52773, // Rule ID 9903 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9903, GIR_Done, // Label 1132: @52773 GIM_Try, /*On fail goto*//*Label 1133*/ 52807, // Rule ID 9904 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9904, GIR_Done, // Label 1133: @52807 GIM_Try, /*On fail goto*//*Label 1134*/ 52841, // Rule ID 9905 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 9905, GIR_Done, // Label 1134: @52841 GIM_Try, /*On fail goto*//*Label 1135*/ 52864, // Rule ID 9906 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src) => (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9906, GIR_Done, // Label 1135: @52864 GIM_Try, /*On fail goto*//*Label 1136*/ 52887, // Rule ID 9907 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src) => (REV32v8i8:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9907, GIR_Done, // Label 1136: @52887 GIM_Try, /*On fail goto*//*Label 1137*/ 52910, // Rule ID 9908 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src) => (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9908, GIR_Done, // Label 1137: @52910 GIM_Try, /*On fail goto*//*Label 1138*/ 52933, // Rule ID 9909 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[f64] }:$src) => (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9909, GIR_Done, // Label 1138: @52933 GIM_Try, /*On fail goto*//*Label 1139*/ 52956, // Rule ID 9910 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src) => (REV32v8i8:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9910, GIR_Done, // Label 1139: @52956 GIM_Try, /*On fail goto*//*Label 1140*/ 52979, // Rule ID 9911 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src) => (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9911, GIR_Done, // Label 1140: @52979 GIM_Try, /*On fail goto*//*Label 1141*/ 53002, // Rule ID 9912 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src) => (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9912, GIR_Done, // Label 1141: @53002 GIM_Try, /*On fail goto*//*Label 1142*/ 53025, // Rule ID 9913 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4bf16] }:$src) => (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4bf16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9913, GIR_Done, // Label 1142: @53025 GIM_Reject, // Label 886: @53026 GIM_Try, /*On fail goto*//*Label 1143*/ 53060, // Rule ID 10033 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10033, GIR_Done, // Label 1143: @53060 GIM_Try, /*On fail goto*//*Label 1144*/ 53094, // Rule ID 10034 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10034, GIR_Done, // Label 1144: @53094 GIM_Try, /*On fail goto*//*Label 1145*/ 53128, // Rule ID 10035 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10035, GIR_Done, // Label 1145: @53128 GIM_Try, /*On fail goto*//*Label 1146*/ 53162, // Rule ID 10036 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10036, GIR_Done, // Label 1146: @53162 GIM_Try, /*On fail goto*//*Label 1147*/ 53196, // Rule ID 10037 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10037, GIR_Done, // Label 1147: @53196 GIM_Try, /*On fail goto*//*Label 1148*/ 53230, // Rule ID 10038 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10038, GIR_Done, // Label 1148: @53230 GIM_Try, /*On fail goto*//*Label 1149*/ 53301, // Rule ID 10039 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v8i16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10039, GIR_Done, // Label 1149: @53301 GIM_Try, /*On fail goto*//*Label 1150*/ 53324, // Rule ID 10040 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src) => (REV64v8i16:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10040, GIR_Done, // Label 1150: @53324 GIM_Try, /*On fail goto*//*Label 1151*/ 53347, // Rule ID 10041 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src) => (REV32v8i16:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10041, GIR_Done, // Label 1151: @53347 GIM_Try, /*On fail goto*//*Label 1152*/ 53370, // Rule ID 10042 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src) => (REV16v16i8:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10042, GIR_Done, // Label 1152: @53370 GIM_Try, /*On fail goto*//*Label 1153*/ 53393, // Rule ID 10043 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src) => (REV64v8i16:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10043, GIR_Done, // Label 1153: @53393 GIM_Try, /*On fail goto*//*Label 1154*/ 53416, // Rule ID 10044 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src) => (REV32v8i16:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10044, GIR_Done, // Label 1154: @53416 GIM_Try, /*On fail goto*//*Label 1155*/ 53448, // Rule ID 10045 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10045, GIR_Done, // Label 1155: @53448 GIM_Try, /*On fail goto*//*Label 1156*/ 53480, // Rule ID 10046 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10046, GIR_Done, // Label 1156: @53480 GIM_Try, /*On fail goto*//*Label 1157*/ 53514, // Rule ID 10047 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10047, GIR_Done, // Label 1157: @53514 GIM_Try, /*On fail goto*//*Label 1158*/ 53548, // Rule ID 10048 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10048, GIR_Done, // Label 1158: @53548 GIM_Try, /*On fail goto*//*Label 1159*/ 53582, // Rule ID 10049 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10049, GIR_Done, // Label 1159: @53582 GIM_Try, /*On fail goto*//*Label 1160*/ 53616, // Rule ID 10050 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10050, GIR_Done, // Label 1160: @53616 GIM_Try, /*On fail goto*//*Label 1161*/ 53650, // Rule ID 10051 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10051, GIR_Done, // Label 1161: @53650 GIM_Try, /*On fail goto*//*Label 1162*/ 53684, // Rule ID 10052 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10052, GIR_Done, // Label 1162: @53684 GIM_Try, /*On fail goto*//*Label 1163*/ 53718, // Rule ID 10053 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v8bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10053, GIR_Done, // Label 1163: @53718 GIM_Try, /*On fail goto*//*Label 1164*/ 53752, // Rule ID 10054 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v8bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10054, GIR_Done, // Label 1164: @53752 GIM_Try, /*On fail goto*//*Label 1165*/ 53786, // Rule ID 10055 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v8bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10055, GIR_Done, // Label 1165: @53786 GIM_Try, /*On fail goto*//*Label 1166*/ 53820, // Rule ID 10056 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v8bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10056, GIR_Done, // Label 1166: @53820 GIM_Try, /*On fail goto*//*Label 1167*/ 53854, // Rule ID 10057 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v8bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10057, GIR_Done, // Label 1167: @53854 GIM_Try, /*On fail goto*//*Label 1168*/ 53888, // Rule ID 10058 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v8bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10058, GIR_Done, // Label 1168: @53888 GIM_Try, /*On fail goto*//*Label 1169*/ 53959, // Rule ID 10059 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v8f16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10059, GIR_Done, // Label 1169: @53959 GIM_Try, /*On fail goto*//*Label 1170*/ 53982, // Rule ID 10060 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src) => (REV64v8i16:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10060, GIR_Done, // Label 1170: @53982 GIM_Try, /*On fail goto*//*Label 1171*/ 54005, // Rule ID 10061 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src) => (REV32v8i16:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10061, GIR_Done, // Label 1171: @54005 GIM_Try, /*On fail goto*//*Label 1172*/ 54028, // Rule ID 10062 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src) => (REV16v16i8:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10062, GIR_Done, // Label 1172: @54028 GIM_Try, /*On fail goto*//*Label 1173*/ 54051, // Rule ID 10063 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src) => (REV64v8i16:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10063, GIR_Done, // Label 1173: @54051 GIM_Try, /*On fail goto*//*Label 1174*/ 54074, // Rule ID 10064 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src) => (REV32v8i16:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10064, GIR_Done, // Label 1174: @54074 GIM_Try, /*On fail goto*//*Label 1175*/ 54145, // Rule ID 10065 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v8bf16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10065, GIR_Done, // Label 1175: @54145 GIM_Try, /*On fail goto*//*Label 1176*/ 54168, // Rule ID 10066 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v2i64] }:$src) => (REV64v8i16:{ *:[v8bf16] } FPR128:{ *:[v2i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10066, GIR_Done, // Label 1176: @54168 GIM_Try, /*On fail goto*//*Label 1177*/ 54191, // Rule ID 10067 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v4i32] }:$src) => (REV32v8i16:{ *:[v8bf16] } FPR128:{ *:[v4i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10067, GIR_Done, // Label 1177: @54191 GIM_Try, /*On fail goto*//*Label 1178*/ 54214, // Rule ID 10068 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v16i8] }:$src) => (REV16v16i8:{ *:[v8bf16] } FPR128:{ *:[v16i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10068, GIR_Done, // Label 1178: @54214 GIM_Try, /*On fail goto*//*Label 1179*/ 54237, // Rule ID 10069 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v2f64] }:$src) => (REV64v8i16:{ *:[v8bf16] } FPR128:{ *:[v2f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10069, GIR_Done, // Label 1179: @54237 GIM_Try, /*On fail goto*//*Label 1180*/ 54260, // Rule ID 10070 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v4f32] }:$src) => (REV32v8i16:{ *:[v8bf16] } FPR128:{ *:[v4f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10070, GIR_Done, // Label 1180: @54260 GIM_Try, /*On fail goto*//*Label 1181*/ 54292, // Rule ID 10071 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10071, GIR_Done, // Label 1181: @54292 GIM_Try, /*On fail goto*//*Label 1182*/ 54324, // Rule ID 10072 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v8bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10072, GIR_Done, // Label 1182: @54324 GIM_Reject, // Label 887: @54325 GIM_Try, /*On fail goto*//*Label 1183*/ 54359, // Rule ID 10073 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10073, GIR_Done, // Label 1183: @54359 GIM_Try, /*On fail goto*//*Label 1184*/ 54393, // Rule ID 10074 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10074, GIR_Done, // Label 1184: @54393 GIM_Try, /*On fail goto*//*Label 1185*/ 54427, // Rule ID 10075 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10075, GIR_Done, // Label 1185: @54427 GIM_Try, /*On fail goto*//*Label 1186*/ 54461, // Rule ID 10076 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10076, GIR_Done, // Label 1186: @54461 GIM_Try, /*On fail goto*//*Label 1187*/ 54495, // Rule ID 10077 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10077, GIR_Done, // Label 1187: @54495 GIM_Try, /*On fail goto*//*Label 1188*/ 54529, // Rule ID 10078 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10078, GIR_Done, // Label 1188: @54529 GIM_Try, /*On fail goto*//*Label 1189*/ 54563, // Rule ID 10079 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10079, GIR_Done, // Label 1189: @54563 GIM_Try, /*On fail goto*//*Label 1190*/ 54597, // Rule ID 10080 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, // GIR_Coverage, 10080, GIR_Done, // Label 1190: @54597 GIM_Try, /*On fail goto*//*Label 1191*/ 54668, // Rule ID 10081 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v16i8] } (REV64v16i8:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v16i8:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v16i8, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v16i8, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10081, GIR_Done, // Label 1191: @54668 GIM_Try, /*On fail goto*//*Label 1192*/ 54691, // Rule ID 10082 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src) => (REV64v16i8:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10082, GIR_Done, // Label 1192: @54691 GIM_Try, /*On fail goto*//*Label 1193*/ 54714, // Rule ID 10083 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src) => (REV32v16i8:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10083, GIR_Done, // Label 1193: @54714 GIM_Try, /*On fail goto*//*Label 1194*/ 54737, // Rule ID 10084 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src) => (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10084, GIR_Done, // Label 1194: @54737 GIM_Try, /*On fail goto*//*Label 1195*/ 54760, // Rule ID 10085 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src) => (REV64v16i8:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10085, GIR_Done, // Label 1195: @54760 GIM_Try, /*On fail goto*//*Label 1196*/ 54783, // Rule ID 10086 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src) => (REV32v16i8:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10086, GIR_Done, // Label 1196: @54783 GIM_Try, /*On fail goto*//*Label 1197*/ 54806, // Rule ID 10087 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src) => (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10087, GIR_Done, // Label 1197: @54806 GIM_Try, /*On fail goto*//*Label 1198*/ 54829, // Rule ID 10088 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8bf16] }:$src) => (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8bf16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10088, GIR_Done, // Label 1198: @54829 GIM_Reject, // Label 888: @54830 GIM_Try, /*On fail goto*//*Label 1199*/ 54864, // Rule ID 5127 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5127, GIR_Done, // Label 1199: @54864 GIM_Try, /*On fail goto*//*Label 1200*/ 54898, // Rule ID 5128 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5128, GIR_Done, // Label 1200: @54898 GIM_Try, /*On fail goto*//*Label 1201*/ 54932, // Rule ID 5129 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5129, GIR_Done, // Label 1201: @54932 GIM_Try, /*On fail goto*//*Label 1202*/ 54966, // Rule ID 5130 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5130, GIR_Done, // Label 1202: @54966 GIM_Try, /*On fail goto*//*Label 1203*/ 55000, // Rule ID 5131 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5131, GIR_Done, // Label 1203: @55000 GIM_Try, /*On fail goto*//*Label 1204*/ 55034, // Rule ID 5132 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5132, GIR_Done, // Label 1204: @55034 GIM_Try, /*On fail goto*//*Label 1205*/ 55068, // Rule ID 5145 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5145, GIR_Done, // Label 1205: @55068 GIM_Try, /*On fail goto*//*Label 1206*/ 55102, // Rule ID 5146 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5146, GIR_Done, // Label 1206: @55102 GIM_Try, /*On fail goto*//*Label 1207*/ 55136, // Rule ID 5147 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5147, GIR_Done, // Label 1207: @55136 GIM_Try, /*On fail goto*//*Label 1208*/ 55170, // Rule ID 5148 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5148, GIR_Done, // Label 1208: @55170 GIM_Try, /*On fail goto*//*Label 1209*/ 55204, // Rule ID 5149 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5149, GIR_Done, // Label 1209: @55204 GIM_Try, /*On fail goto*//*Label 1210*/ 55238, // Rule ID 5150 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5150, GIR_Done, // Label 1210: @55238 GIM_Try, /*On fail goto*//*Label 1211*/ 55272, // Rule ID 5161 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv8bf16] }:$src) => ZPR:{ *:[nxv2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5161, GIR_Done, // Label 1211: @55272 GIM_Try, /*On fail goto*//*Label 1212*/ 55306, // Rule ID 5164 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv8bf16] }:$src) => ZPR:{ *:[nxv2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5164, GIR_Done, // Label 1212: @55306 GIM_Reject, // Label 889: @55307 GIM_Try, /*On fail goto*//*Label 1213*/ 55341, // Rule ID 5121 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5121, GIR_Done, // Label 1213: @55341 GIM_Try, /*On fail goto*//*Label 1214*/ 55375, // Rule ID 5122 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5122, GIR_Done, // Label 1214: @55375 GIM_Try, /*On fail goto*//*Label 1215*/ 55409, // Rule ID 5123 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5123, GIR_Done, // Label 1215: @55409 GIM_Try, /*On fail goto*//*Label 1216*/ 55443, // Rule ID 5124 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5124, GIR_Done, // Label 1216: @55443 GIM_Try, /*On fail goto*//*Label 1217*/ 55477, // Rule ID 5125 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5125, GIR_Done, // Label 1217: @55477 GIM_Try, /*On fail goto*//*Label 1218*/ 55511, // Rule ID 5126 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5126, GIR_Done, // Label 1218: @55511 GIM_Try, /*On fail goto*//*Label 1219*/ 55545, // Rule ID 5139 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5139, GIR_Done, // Label 1219: @55545 GIM_Try, /*On fail goto*//*Label 1220*/ 55579, // Rule ID 5140 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5140, GIR_Done, // Label 1220: @55579 GIM_Try, /*On fail goto*//*Label 1221*/ 55613, // Rule ID 5141 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5141, GIR_Done, // Label 1221: @55613 GIM_Try, /*On fail goto*//*Label 1222*/ 55647, // Rule ID 5142 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5142, GIR_Done, // Label 1222: @55647 GIM_Try, /*On fail goto*//*Label 1223*/ 55681, // Rule ID 5143 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5143, GIR_Done, // Label 1223: @55681 GIM_Try, /*On fail goto*//*Label 1224*/ 55715, // Rule ID 5144 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5144, GIR_Done, // Label 1224: @55715 GIM_Try, /*On fail goto*//*Label 1225*/ 55749, // Rule ID 5160 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv8bf16] }:$src) => ZPR:{ *:[nxv4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5160, GIR_Done, // Label 1225: @55749 GIM_Try, /*On fail goto*//*Label 1226*/ 55783, // Rule ID 5163 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv8bf16] }:$src) => ZPR:{ *:[nxv4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5163, GIR_Done, // Label 1226: @55783 GIM_Reject, // Label 890: @55784 GIM_Try, /*On fail goto*//*Label 1227*/ 55818, // Rule ID 5115 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5115, GIR_Done, // Label 1227: @55818 GIM_Try, /*On fail goto*//*Label 1228*/ 55852, // Rule ID 5116 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5116, GIR_Done, // Label 1228: @55852 GIM_Try, /*On fail goto*//*Label 1229*/ 55886, // Rule ID 5117 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5117, GIR_Done, // Label 1229: @55886 GIM_Try, /*On fail goto*//*Label 1230*/ 55920, // Rule ID 5118 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5118, GIR_Done, // Label 1230: @55920 GIM_Try, /*On fail goto*//*Label 1231*/ 55954, // Rule ID 5119 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5119, GIR_Done, // Label 1231: @55954 GIM_Try, /*On fail goto*//*Label 1232*/ 55988, // Rule ID 5120 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5120, GIR_Done, // Label 1232: @55988 GIM_Try, /*On fail goto*//*Label 1233*/ 56022, // Rule ID 5133 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5133, GIR_Done, // Label 1233: @56022 GIM_Try, /*On fail goto*//*Label 1234*/ 56056, // Rule ID 5134 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5134, GIR_Done, // Label 1234: @56056 GIM_Try, /*On fail goto*//*Label 1235*/ 56090, // Rule ID 5135 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5135, GIR_Done, // Label 1235: @56090 GIM_Try, /*On fail goto*//*Label 1236*/ 56124, // Rule ID 5136 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5136, GIR_Done, // Label 1236: @56124 GIM_Try, /*On fail goto*//*Label 1237*/ 56158, // Rule ID 5137 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5137, GIR_Done, // Label 1237: @56158 GIM_Try, /*On fail goto*//*Label 1238*/ 56192, // Rule ID 5138 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5138, GIR_Done, // Label 1238: @56192 GIM_Try, /*On fail goto*//*Label 1239*/ 56226, // Rule ID 5151 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8bf16] } ZPR:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv8bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5151, GIR_Done, // Label 1239: @56226 GIM_Try, /*On fail goto*//*Label 1240*/ 56260, // Rule ID 5152 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8bf16] } ZPR:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv8bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5152, GIR_Done, // Label 1240: @56260 GIM_Try, /*On fail goto*//*Label 1241*/ 56294, // Rule ID 5153 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8bf16] } ZPR:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv8bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5153, GIR_Done, // Label 1241: @56294 GIM_Try, /*On fail goto*//*Label 1242*/ 56328, // Rule ID 5154 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8bf16] } ZPR:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv8bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5154, GIR_Done, // Label 1242: @56328 GIM_Try, /*On fail goto*//*Label 1243*/ 56362, // Rule ID 5155 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8bf16] } ZPR:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv8bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5155, GIR_Done, // Label 1243: @56362 GIM_Try, /*On fail goto*//*Label 1244*/ 56396, // Rule ID 5156 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8bf16] } ZPR:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv8bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5156, GIR_Done, // Label 1244: @56396 GIM_Try, /*On fail goto*//*Label 1245*/ 56430, // Rule ID 5157 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8bf16] } ZPR:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv8bf16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5157, GIR_Done, // Label 1245: @56430 GIM_Try, /*On fail goto*//*Label 1246*/ 56464, // Rule ID 5159 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv8bf16] }:$src) => ZPR:{ *:[nxv8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5159, GIR_Done, // Label 1246: @56464 GIM_Try, /*On fail goto*//*Label 1247*/ 56498, // Rule ID 5162 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv8bf16] }:$src) => ZPR:{ *:[nxv8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5162, GIR_Done, // Label 1247: @56498 GIM_Reject, // Label 891: @56499 GIM_Try, /*On fail goto*//*Label 1248*/ 56533, // Rule ID 5109 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5109, GIR_Done, // Label 1248: @56533 GIM_Try, /*On fail goto*//*Label 1249*/ 56567, // Rule ID 5110 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5110, GIR_Done, // Label 1249: @56567 GIM_Try, /*On fail goto*//*Label 1250*/ 56601, // Rule ID 5111 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5111, GIR_Done, // Label 1250: @56601 GIM_Try, /*On fail goto*//*Label 1251*/ 56635, // Rule ID 5112 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5112, GIR_Done, // Label 1251: @56635 GIM_Try, /*On fail goto*//*Label 1252*/ 56669, // Rule ID 5113 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5113, GIR_Done, // Label 1252: @56669 GIM_Try, /*On fail goto*//*Label 1253*/ 56703, // Rule ID 5114 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5114, GIR_Done, // Label 1253: @56703 GIM_Try, /*On fail goto*//*Label 1254*/ 56737, // Rule ID 5158 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv8bf16] }:$src) => ZPR:{ *:[nxv16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::ZPRRegClassID, // GIR_Coverage, 5158, GIR_Done, // Label 1254: @56737 GIM_Reject, // Label 892: @56738 GIM_Reject, // Label 10: @56739 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 1263*/ 56971, /*GILLT_s16*//*Label 1255*/ 56755, /*GILLT_s32*//*Label 1256*/ 56782, /*GILLT_s64*//*Label 1257*/ 56809, 0, /*GILLT_v2s32*//*Label 1258*/ 56836, /*GILLT_v2s64*//*Label 1259*/ 56863, /*GILLT_v4s16*//*Label 1260*/ 56890, /*GILLT_v4s32*//*Label 1261*/ 56917, 0, /*GILLT_v8s16*//*Label 1262*/ 56944, // Label 1255: @56755 GIM_Try, /*On fail goto*//*Label 1264*/ 56781, // Rule ID 545 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (ftrunc:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTZHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 545, GIR_Done, // Label 1264: @56781 GIM_Reject, // Label 1256: @56782 GIM_Try, /*On fail goto*//*Label 1265*/ 56808, // Rule ID 547 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (ftrunc:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTZSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZSr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 547, GIR_Done, // Label 1265: @56808 GIM_Reject, // Label 1257: @56809 GIM_Try, /*On fail goto*//*Label 1266*/ 56835, // Rule ID 549 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ftrunc:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTZDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 549, GIR_Done, // Label 1266: @56835 GIM_Reject, // Label 1258: @56836 GIM_Try, /*On fail goto*//*Label 1267*/ 56862, // Rule ID 906 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ftrunc:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTZv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 906, GIR_Done, // Label 1267: @56862 GIM_Reject, // Label 1259: @56863 GIM_Try, /*On fail goto*//*Label 1268*/ 56889, // Rule ID 910 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ftrunc:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTZv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 910, GIR_Done, // Label 1268: @56889 GIM_Reject, // Label 1260: @56890 GIM_Try, /*On fail goto*//*Label 1269*/ 56916, // Rule ID 902 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ftrunc:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTZv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 902, GIR_Done, // Label 1269: @56916 GIM_Reject, // Label 1261: @56917 GIM_Try, /*On fail goto*//*Label 1270*/ 56943, // Rule ID 908 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ftrunc:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTZv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 908, GIR_Done, // Label 1270: @56943 GIM_Reject, // Label 1262: @56944 GIM_Try, /*On fail goto*//*Label 1271*/ 56970, // Rule ID 904 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ftrunc:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTZv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 904, GIR_Done, // Label 1271: @56970 GIM_Reject, // Label 1263: @56971 GIM_Reject, // Label 11: @56972 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 1280*/ 57204, /*GILLT_s16*//*Label 1272*/ 56988, /*GILLT_s32*//*Label 1273*/ 57015, /*GILLT_s64*//*Label 1274*/ 57042, 0, /*GILLT_v2s32*//*Label 1275*/ 57069, /*GILLT_v2s64*//*Label 1276*/ 57096, /*GILLT_v4s16*//*Label 1277*/ 57123, /*GILLT_v4s32*//*Label 1278*/ 57150, 0, /*GILLT_v8s16*//*Label 1279*/ 57177, // Label 1272: @56988 GIM_Try, /*On fail goto*//*Label 1281*/ 57014, // Rule ID 509 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fround:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTAHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 509, GIR_Done, // Label 1281: @57014 GIM_Reject, // Label 1273: @57015 GIM_Try, /*On fail goto*//*Label 1282*/ 57041, // Rule ID 511 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fround:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTASr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTASr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 511, GIR_Done, // Label 1282: @57041 GIM_Reject, // Label 1274: @57042 GIM_Try, /*On fail goto*//*Label 1283*/ 57068, // Rule ID 513 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fround:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTADr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTADr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 513, GIR_Done, // Label 1283: @57068 GIM_Reject, // Label 1275: @57069 GIM_Try, /*On fail goto*//*Label 1284*/ 57095, // Rule ID 846 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fround:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 846, GIR_Done, // Label 1284: @57095 GIM_Reject, // Label 1276: @57096 GIM_Try, /*On fail goto*//*Label 1285*/ 57122, // Rule ID 850 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fround:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 850, GIR_Done, // Label 1285: @57122 GIM_Reject, // Label 1277: @57123 GIM_Try, /*On fail goto*//*Label 1286*/ 57149, // Rule ID 842 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fround:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 842, GIR_Done, // Label 1286: @57149 GIM_Reject, // Label 1278: @57150 GIM_Try, /*On fail goto*//*Label 1287*/ 57176, // Rule ID 848 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fround:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 848, GIR_Done, // Label 1287: @57176 GIM_Reject, // Label 1279: @57177 GIM_Try, /*On fail goto*//*Label 1288*/ 57203, // Rule ID 844 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fround:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 844, GIR_Done, // Label 1288: @57203 GIM_Reject, // Label 1280: @57204 GIM_Reject, // Label 12: @57205 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1291*/ 57471, /*GILLT_s32*//*Label 1289*/ 57213, /*GILLT_s64*//*Label 1290*/ 57342, // Label 1289: @57213 GIM_Try, /*On fail goto*//*Label 1292*/ 57257, // Rule ID 8475 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // (lrint:{ *:[i32] } f16:{ *:[f16] }:$Rn) => (FCVTZSUWHr:{ *:[i32] } (FRINTXHr:{ *:[bf16] } f16:{ *:[f16] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FRINTXHr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8475, GIR_Done, // Label 1292: @57257 GIM_Try, /*On fail goto*//*Label 1293*/ 57299, // Rule ID 8481 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // (lrint:{ *:[i32] } f32:{ *:[f32] }:$Rn) => (FCVTZSUWSr:{ *:[i32] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FRINTXSr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8481, GIR_Done, // Label 1293: @57299 GIM_Try, /*On fail goto*//*Label 1294*/ 57341, // Rule ID 8483 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // (lrint:{ *:[i32] } f64:{ *:[f64] }:$Rn) => (FCVTZSUWDr:{ *:[i32] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FRINTXDr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8483, GIR_Done, // Label 1294: @57341 GIM_Reject, // Label 1290: @57342 GIM_Try, /*On fail goto*//*Label 1295*/ 57386, // Rule ID 8477 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (lrint:{ *:[i64] } f16:{ *:[f16] }:$Rn) => (FCVTZSUXHr:{ *:[i64] } (FRINTXHr:{ *:[bf16] } f16:{ *:[f16] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FRINTXHr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8477, GIR_Done, // Label 1295: @57386 GIM_Try, /*On fail goto*//*Label 1296*/ 57428, // Rule ID 8485 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (lrint:{ *:[i64] } f32:{ *:[f32] }:$Rn) => (FCVTZSUXSr:{ *:[i64] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FRINTXSr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8485, GIR_Done, // Label 1296: @57428 GIM_Try, /*On fail goto*//*Label 1297*/ 57470, // Rule ID 8487 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (lrint:{ *:[i64] } f64:{ *:[f64] }:$Rn) => (FCVTZSUXDr:{ *:[i64] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FRINTXDr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8487, GIR_Done, // Label 1297: @57470 GIM_Reject, // Label 1291: @57471 GIM_Reject, // Label 13: @57472 GIM_Try, /*On fail goto*//*Label 1298*/ 57497, // Rule ID 7866 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (readcyclecounter:{ *:[i64] }) => (MRS:{ *:[i64] }:{ *:[i32] } 57090:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MRS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddImm, /*InsnID*/0, /*Imm*/57090, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7866, GIR_Done, // Label 1298: @57497 GIM_Reject, // Label 14: @57498 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 23, /*)*//*default:*//*Label 1318*/ 65307, /*GILLT_s16*//*Label 1299*/ 57527, /*GILLT_s32*//*Label 1300*/ 57709, /*GILLT_s64*//*Label 1301*/ 59615, /*GILLT_s128*//*Label 1302*/ 61991, /*GILLT_v2s32*//*Label 1303*/ 62173, /*GILLT_v2s64*//*Label 1304*/ 62517, /*GILLT_v4s16*//*Label 1305*/ 62861, /*GILLT_v4s32*//*Label 1306*/ 63324, /*GILLT_v8s8*//*Label 1307*/ 63668, /*GILLT_v8s16*//*Label 1308*/ 63856, /*GILLT_v16s8*//*Label 1309*/ 64319, 0, 0, /*GILLT_nxv2s16*//*Label 1310*/ 64507, /*GILLT_nxv2s32*//*Label 1311*/ 64622, /*GILLT_nxv2s64*//*Label 1312*/ 64688, 0, /*GILLT_nxv4s16*//*Label 1313*/ 64803, /*GILLT_nxv4s32*//*Label 1314*/ 64918, 0, /*GILLT_nxv8s16*//*Label 1315*/ 65033, /*GILLT_nxv16s1*//*Label 1316*/ 65194, /*GILLT_nxv16s8*//*Label 1317*/ 65241, // Label 1299: @57527 GIM_Try, /*On fail goto*//*Label 1319*/ 57708, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_Try, /*On fail goto*//*Label 1320*/ 57579, // Rule ID 236 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><> => (LDRHroW:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 236, GIR_Done, // Label 1320: @57579 GIM_Try, /*On fail goto*//*Label 1321*/ 57614, // Rule ID 237 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><> => (LDRHroX:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 237, GIR_Done, // Label 1321: @57614 GIM_Try, /*On fail goto*//*Label 1322*/ 57645, // Rule ID 259 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><> => (LDRHui:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 259, GIR_Done, // Label 1322: @57645 GIM_Try, /*On fail goto*//*Label 1323*/ 57676, // Rule ID 280 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURHi:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 280, GIR_Done, // Label 1323: @57676 GIM_Try, /*On fail goto*//*Label 1324*/ 57707, // Rule ID 8113 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (ld:{ *:[bf16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><> => (LDRHui:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8113, GIR_Done, // Label 1324: @57707 GIM_Reject, // Label 1319: @57708 GIM_Reject, // Label 1300: @57709 GIM_Try, /*On fail goto*//*Label 1325*/ 57759, // Rule ID 230 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><> => (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 230, GIR_Done, // Label 1325: @57759 GIM_Try, /*On fail goto*//*Label 1326*/ 57809, // Rule ID 231 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><> => (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 231, GIR_Done, // Label 1326: @57809 GIM_Try, /*On fail goto*//*Label 1327*/ 57859, // Rule ID 238 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><> => (LDRSroW:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 238, GIR_Done, // Label 1327: @57859 GIM_Try, /*On fail goto*//*Label 1328*/ 57909, // Rule ID 239 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><> => (LDRSroX:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 239, GIR_Done, // Label 1328: @57909 GIM_Try, /*On fail goto*//*Label 1329*/ 57963, // Rule ID 8105 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8105, GIR_Done, // Label 1329: @57963 GIM_Try, /*On fail goto*//*Label 1330*/ 58017, // Rule ID 8106 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8106, GIR_Done, // Label 1330: @58017 GIM_Try, /*On fail goto*//*Label 1331*/ 58071, // Rule ID 8107 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><> => (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8107, GIR_Done, // Label 1331: @58071 GIM_Try, /*On fail goto*//*Label 1332*/ 58125, // Rule ID 8108 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><><> => (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8108, GIR_Done, // Label 1332: @58125 GIM_Try, /*On fail goto*//*Label 1333*/ 58179, // Rule ID 8109 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><><> => (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8109, GIR_Done, // Label 1333: @58179 GIM_Try, /*On fail goto*//*Label 1334*/ 58233, // Rule ID 8110 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><><> => (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8110, GIR_Done, // Label 1334: @58233 GIM_Try, /*On fail goto*//*Label 1335*/ 58279, // Rule ID 257 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><> => (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 257, GIR_Done, // Label 1335: @58279 GIM_Try, /*On fail goto*//*Label 1336*/ 58325, // Rule ID 260 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><> => (LDRSui:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 260, GIR_Done, // Label 1336: @58325 GIM_Try, /*On fail goto*//*Label 1337*/ 58378, // Rule ID 10176 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (atomic_load:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset))<><> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10176, GIR_Done, // Label 1337: @58378 GIM_Try, /*On fail goto*//*Label 1338*/ 58431, // Rule ID 10178 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (atomic_load:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset))<><> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10178, GIR_Done, // Label 1338: @58431 GIM_Try, /*On fail goto*//*Label 1339*/ 58484, // Rule ID 10188 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (atomic_load:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><> => (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10188, GIR_Done, // Label 1339: @58484 GIM_Try, /*On fail goto*//*Label 1340*/ 58537, // Rule ID 10190 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (atomic_load:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><> => (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10190, GIR_Done, // Label 1340: @58537 GIM_Try, /*On fail goto*//*Label 1341*/ 58590, // Rule ID 10198 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (atomic_load:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><> => (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10198, GIR_Done, // Label 1341: @58590 GIM_Try, /*On fail goto*//*Label 1342*/ 58643, // Rule ID 10199 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (atomic_load:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><> => (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10199, GIR_Done, // Label 1342: @58643 GIM_Try, /*On fail goto*//*Label 1343*/ 58689, // Rule ID 278 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURWi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 278, GIR_Done, // Label 1343: @58689 GIM_Try, /*On fail goto*//*Label 1344*/ 58735, // Rule ID 281 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURSi:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 281, GIR_Done, // Label 1344: @58735 GIM_Try, /*On fail goto*//*Label 1345*/ 58784, // Rule ID 10180 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (atomic_load:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10180, GIR_Done, // Label 1345: @58784 GIM_Try, /*On fail goto*//*Label 1346*/ 58833, // Rule ID 10182 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10182, GIR_Done, // Label 1346: @58833 GIM_Try, /*On fail goto*//*Label 1347*/ 58882, // Rule ID 10192 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (atomic_load:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10192, GIR_Done, // Label 1347: @58882 GIM_Try, /*On fail goto*//*Label 1348*/ 58931, // Rule ID 10194 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10194, GIR_Done, // Label 1348: @58931 GIM_Try, /*On fail goto*//*Label 1349*/ 58980, // Rule ID 10200 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (atomic_load:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><> => (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10200, GIR_Done, // Label 1349: @58980 GIM_Try, /*On fail goto*//*Label 1350*/ 59029, // Rule ID 10201 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (atomic_load:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURWi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10201, GIR_Done, // Label 1350: @59029 GIM_Try, /*On fail goto*//*Label 1351*/ 59079, // Rule ID 8143 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8143, GIR_Done, // Label 1351: @59079 GIM_Try, /*On fail goto*//*Label 1352*/ 59129, // Rule ID 8144 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8144, GIR_Done, // Label 1352: @59129 GIM_Try, /*On fail goto*//*Label 1353*/ 59179, // Rule ID 8145 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8145, GIR_Done, // Label 1353: @59179 GIM_Try, /*On fail goto*//*Label 1354*/ 59229, // Rule ID 8166 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8166, GIR_Done, // Label 1354: @59229 GIM_Try, /*On fail goto*//*Label 1355*/ 59279, // Rule ID 8167 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8167, GIR_Done, // Label 1355: @59279 GIM_Try, /*On fail goto*//*Label 1356*/ 59329, // Rule ID 8168 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8168, GIR_Done, // Label 1356: @59329 GIM_Try, /*On fail goto*//*Label 1357*/ 59362, // Rule ID 10168 // GIM_CheckFeatures, GIFBS_HasRCPC, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDAPRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDAPRB, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10168, GIR_Done, // Label 1357: @59362 GIM_Try, /*On fail goto*//*Label 1358*/ 59395, // Rule ID 10169 // GIM_CheckFeatures, GIFBS_HasRCPC, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDAPRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDAPRH, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10169, GIR_Done, // Label 1358: @59395 GIM_Try, /*On fail goto*//*Label 1359*/ 59428, // Rule ID 10170 // GIM_CheckFeatures, GIFBS_HasRCPC, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDAPRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDAPRW, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10170, GIR_Done, // Label 1359: @59428 GIM_Try, /*On fail goto*//*Label 1360*/ 59459, // Rule ID 10172 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARB, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10172, GIR_Done, // Label 1360: @59459 GIM_Try, /*On fail goto*//*Label 1361*/ 59490, // Rule ID 10174 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARB, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10174, GIR_Done, // Label 1361: @59490 GIM_Try, /*On fail goto*//*Label 1362*/ 59521, // Rule ID 10184 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARH, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10184, GIR_Done, // Label 1362: @59521 GIM_Try, /*On fail goto*//*Label 1363*/ 59552, // Rule ID 10186 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARH, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10186, GIR_Done, // Label 1363: @59552 GIM_Try, /*On fail goto*//*Label 1364*/ 59583, // Rule ID 10196 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDARW:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARW, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10196, GIR_Done, // Label 1364: @59583 GIM_Try, /*On fail goto*//*Label 1365*/ 59614, // Rule ID 10197 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDARW:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARW, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10197, GIR_Done, // Label 1365: @59614 GIM_Reject, // Label 1301: @59615 GIM_Try, /*On fail goto*//*Label 1366*/ 59665, // Rule ID 232 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 232, GIR_Done, // Label 1366: @59665 GIM_Try, /*On fail goto*//*Label 1367*/ 59715, // Rule ID 233 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 233, GIR_Done, // Label 1367: @59715 GIM_Try, /*On fail goto*//*Label 1368*/ 59765, // Rule ID 240 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 240, GIR_Done, // Label 1368: @59765 GIM_Try, /*On fail goto*//*Label 1369*/ 59815, // Rule ID 241 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 241, GIR_Done, // Label 1369: @59815 GIM_Try, /*On fail goto*//*Label 1370*/ 59865, // Rule ID 8069 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[v1i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8069, GIR_Done, // Label 1370: @59865 GIM_Try, /*On fail goto*//*Label 1371*/ 59915, // Rule ID 8070 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[v1i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8070, GIR_Done, // Label 1371: @59915 GIM_Try, /*On fail goto*//*Label 1372*/ 59965, // Rule ID 8071 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[v1f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8071, GIR_Done, // Label 1372: @59965 GIM_Try, /*On fail goto*//*Label 1373*/ 60015, // Rule ID 8072 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[v1f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8072, GIR_Done, // Label 1373: @60015 GIM_Try, /*On fail goto*//*Label 1374*/ 60097, // Rule ID 8097 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8097, GIR_Done, // Label 1374: @60097 GIM_Try, /*On fail goto*//*Label 1375*/ 60179, // Rule ID 8098 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8098, GIR_Done, // Label 1375: @60179 GIM_Try, /*On fail goto*//*Label 1376*/ 60261, // Rule ID 8099 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8099, GIR_Done, // Label 1376: @60261 GIM_Try, /*On fail goto*//*Label 1377*/ 60343, // Rule ID 8100 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8100, GIR_Done, // Label 1377: @60343 GIM_Try, /*On fail goto*//*Label 1378*/ 60425, // Rule ID 8101 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8101, GIR_Done, // Label 1378: @60425 GIM_Try, /*On fail goto*//*Label 1379*/ 60507, // Rule ID 8102 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8102, GIR_Done, // Label 1379: @60507 GIM_Try, /*On fail goto*//*Label 1380*/ 60589, // Rule ID 8103 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8103, GIR_Done, // Label 1380: @60589 GIM_Try, /*On fail goto*//*Label 1381*/ 60671, // Rule ID 8104 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8104, GIR_Done, // Label 1381: @60671 GIM_Try, /*On fail goto*//*Label 1382*/ 60717, // Rule ID 256 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 256, GIR_Done, // Label 1382: @60717 GIM_Try, /*On fail goto*//*Label 1383*/ 60763, // Rule ID 261 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 261, GIR_Done, // Label 1383: @60763 GIM_Try, /*On fail goto*//*Label 1384*/ 60816, // Rule ID 10204 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (atomic_load:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10204, GIR_Done, // Label 1384: @60816 GIM_Try, /*On fail goto*//*Label 1385*/ 60869, // Rule ID 10205 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (atomic_load:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10205, GIR_Done, // Label 1385: @60869 GIM_Try, /*On fail goto*//*Label 1386*/ 60915, // Rule ID 277 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURXi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 277, GIR_Done, // Label 1386: @60915 GIM_Try, /*On fail goto*//*Label 1387*/ 60961, // Rule ID 282 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 282, GIR_Done, // Label 1387: @60961 GIM_Try, /*On fail goto*//*Label 1388*/ 61010, // Rule ID 10206 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (atomic_load:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10206, GIR_Done, // Label 1388: @61010 GIM_Try, /*On fail goto*//*Label 1389*/ 61059, // Rule ID 10207 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (atomic_load:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURXi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10207, GIR_Done, // Label 1389: @61059 GIM_Try, /*On fail goto*//*Label 1390*/ 61105, // Rule ID 8128 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[v1f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8128, GIR_Done, // Label 1390: @61105 GIM_Try, /*On fail goto*//*Label 1391*/ 61151, // Rule ID 8129 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[v1i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8129, GIR_Done, // Label 1391: @61151 GIM_Try, /*On fail goto*//*Label 1392*/ 61197, // Rule ID 8157 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[v1f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8157, GIR_Done, // Label 1392: @61197 GIM_Try, /*On fail goto*//*Label 1393*/ 61243, // Rule ID 8158 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[v1i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8158, GIR_Done, // Label 1393: @61243 GIM_Try, /*On fail goto*//*Label 1394*/ 61321, // Rule ID 8146 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8146, GIR_Done, // Label 1394: @61321 GIM_Try, /*On fail goto*//*Label 1395*/ 61399, // Rule ID 8147 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8147, GIR_Done, // Label 1395: @61399 GIM_Try, /*On fail goto*//*Label 1396*/ 61477, // Rule ID 8148 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8148, GIR_Done, // Label 1396: @61477 GIM_Try, /*On fail goto*//*Label 1397*/ 61555, // Rule ID 8149 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8149, GIR_Done, // Label 1397: @61555 GIM_Try, /*On fail goto*//*Label 1398*/ 61633, // Rule ID 8169 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURWi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8169, GIR_Done, // Label 1398: @61633 GIM_Try, /*On fail goto*//*Label 1399*/ 61711, // Rule ID 8170 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURHHi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8170, GIR_Done, // Label 1399: @61711 GIM_Try, /*On fail goto*//*Label 1400*/ 61789, // Rule ID 8171 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8171, GIR_Done, // Label 1400: @61789 GIM_Try, /*On fail goto*//*Label 1401*/ 61867, // Rule ID 8172 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8172, GIR_Done, // Label 1401: @61867 GIM_Try, /*On fail goto*//*Label 1402*/ 61900, // Rule ID 10171 // GIM_CheckFeatures, GIFBS_HasRCPC, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDAPRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDAPRX, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10171, GIR_Done, // Label 1402: @61900 GIM_Try, /*On fail goto*//*Label 1403*/ 61931, // Rule ID 10202 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDARX:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARX, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10202, GIR_Done, // Label 1403: @61931 GIM_Try, /*On fail goto*//*Label 1404*/ 61962, // Rule ID 10203 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDARX:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARX, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10203, GIR_Done, // Label 1404: @61962 GIM_Try, /*On fail goto*//*Label 1405*/ 61990, // Rule ID 9522 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev1d:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev1d, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9522, GIR_Done, // Label 1405: @61990 GIM_Reject, // Label 1302: @61991 GIM_Try, /*On fail goto*//*Label 1406*/ 62172, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_Try, /*On fail goto*//*Label 1407*/ 62043, // Rule ID 242 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[f128] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 242, GIR_Done, // Label 1407: @62043 GIM_Try, /*On fail goto*//*Label 1408*/ 62078, // Rule ID 243 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[f128] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 243, GIR_Done, // Label 1408: @62078 GIM_Try, /*On fail goto*//*Label 1409*/ 62109, // Rule ID 262 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 262, GIR_Done, // Label 1409: @62109 GIM_Try, /*On fail goto*//*Label 1410*/ 62140, // Rule ID 283 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[f128] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 283, GIR_Done, // Label 1410: @62140 GIM_Try, /*On fail goto*//*Label 1411*/ 62171, // Rule ID 8138 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8138, GIR_Done, // Label 1411: @62171 GIM_Reject, // Label 1406: @62172 GIM_Reject, // Label 1303: @62173 GIM_Try, /*On fail goto*//*Label 1412*/ 62516, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 1413*/ 62227, // Rule ID 8057 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[v2i32] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8057, GIR_Done, // Label 1413: @62227 GIM_Try, /*On fail goto*//*Label 1414*/ 62268, // Rule ID 8058 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[v2i32] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8058, GIR_Done, // Label 1414: @62268 GIM_Try, /*On fail goto*//*Label 1415*/ 62309, // Rule ID 8059 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[v2f32] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8059, GIR_Done, // Label 1415: @62309 GIM_Try, /*On fail goto*//*Label 1416*/ 62350, // Rule ID 8060 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[v2f32] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8060, GIR_Done, // Label 1416: @62350 GIM_Try, /*On fail goto*//*Label 1417*/ 62387, // Rule ID 8122 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[v2f32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8122, GIR_Done, // Label 1417: @62387 GIM_Try, /*On fail goto*//*Label 1418*/ 62424, // Rule ID 8125 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[v2i32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8125, GIR_Done, // Label 1418: @62424 GIM_Try, /*On fail goto*//*Label 1419*/ 62461, // Rule ID 8152 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[v2f32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8152, GIR_Done, // Label 1419: @62461 GIM_Try, /*On fail goto*//*Label 1420*/ 62498, // Rule ID 8153 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[v2i32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8153, GIR_Done, // Label 1420: @62498 GIM_Try, /*On fail goto*//*Label 1421*/ 62515, // Rule ID 9521 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev2s:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev2s, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9521, GIR_Done, // Label 1421: @62515 GIM_Reject, // Label 1412: @62516 GIM_Reject, // Label 1304: @62517 GIM_Try, /*On fail goto*//*Label 1422*/ 62860, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 1423*/ 62571, // Rule ID 8073 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[v2i64] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8073, GIR_Done, // Label 1423: @62571 GIM_Try, /*On fail goto*//*Label 1424*/ 62612, // Rule ID 8074 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[v2i64] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8074, GIR_Done, // Label 1424: @62612 GIM_Try, /*On fail goto*//*Label 1425*/ 62653, // Rule ID 8075 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[v2f64] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8075, GIR_Done, // Label 1425: @62653 GIM_Try, /*On fail goto*//*Label 1426*/ 62694, // Rule ID 8076 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[v2f64] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8076, GIR_Done, // Label 1426: @62694 GIM_Try, /*On fail goto*//*Label 1427*/ 62731, // Rule ID 8131 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[v2f64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8131, GIR_Done, // Label 1427: @62731 GIM_Try, /*On fail goto*//*Label 1428*/ 62768, // Rule ID 8135 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[v2i64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8135, GIR_Done, // Label 1428: @62768 GIM_Try, /*On fail goto*//*Label 1429*/ 62805, // Rule ID 8159 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[v2f64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8159, GIR_Done, // Label 1429: @62805 GIM_Try, /*On fail goto*//*Label 1430*/ 62842, // Rule ID 8160 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[v2i64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8160, GIR_Done, // Label 1430: @62842 GIM_Try, /*On fail goto*//*Label 1431*/ 62859, // Rule ID 9518 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev2d, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9518, GIR_Done, // Label 1431: @62859 GIM_Reject, // Label 1422: @62860 GIM_Reject, // Label 1305: @62861 GIM_Try, /*On fail goto*//*Label 1432*/ 63323, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 1433*/ 62915, // Rule ID 8063 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[v4i16] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8063, GIR_Done, // Label 1433: @62915 GIM_Try, /*On fail goto*//*Label 1434*/ 62956, // Rule ID 8064 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[v4i16] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8064, GIR_Done, // Label 1434: @62956 GIM_Try, /*On fail goto*//*Label 1435*/ 62997, // Rule ID 8065 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[v4f16] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8065, GIR_Done, // Label 1435: @62997 GIM_Try, /*On fail goto*//*Label 1436*/ 63038, // Rule ID 8066 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[v4f16] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8066, GIR_Done, // Label 1436: @63038 GIM_Try, /*On fail goto*//*Label 1437*/ 63079, // Rule ID 8067 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[v4bf16] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[v4bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8067, GIR_Done, // Label 1437: @63079 GIM_Try, /*On fail goto*//*Label 1438*/ 63120, // Rule ID 8068 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[v4bf16] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[v4bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8068, GIR_Done, // Label 1438: @63120 GIM_Try, /*On fail goto*//*Label 1439*/ 63157, // Rule ID 8124 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[v4i16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8124, GIR_Done, // Label 1439: @63157 GIM_Try, /*On fail goto*//*Label 1440*/ 63194, // Rule ID 8126 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[v4f16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8126, GIR_Done, // Label 1440: @63194 GIM_Try, /*On fail goto*//*Label 1441*/ 63231, // Rule ID 8127 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[v4bf16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[v4bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8127, GIR_Done, // Label 1441: @63231 GIM_Try, /*On fail goto*//*Label 1442*/ 63268, // Rule ID 8154 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[v4i16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8154, GIR_Done, // Label 1442: @63268 GIM_Try, /*On fail goto*//*Label 1443*/ 63305, // Rule ID 8156 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[v4f16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8156, GIR_Done, // Label 1443: @63305 GIM_Try, /*On fail goto*//*Label 1444*/ 63322, // Rule ID 9520 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev4h:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev4h, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9520, GIR_Done, // Label 1444: @63322 GIM_Reject, // Label 1432: @63323 GIM_Reject, // Label 1306: @63324 GIM_Try, /*On fail goto*//*Label 1445*/ 63667, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 1446*/ 63378, // Rule ID 8077 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[v4i32] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8077, GIR_Done, // Label 1446: @63378 GIM_Try, /*On fail goto*//*Label 1447*/ 63419, // Rule ID 8078 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[v4i32] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8078, GIR_Done, // Label 1447: @63419 GIM_Try, /*On fail goto*//*Label 1448*/ 63460, // Rule ID 8079 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[v4f32] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8079, GIR_Done, // Label 1448: @63460 GIM_Try, /*On fail goto*//*Label 1449*/ 63501, // Rule ID 8080 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[v4f32] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8080, GIR_Done, // Label 1449: @63501 GIM_Try, /*On fail goto*//*Label 1450*/ 63538, // Rule ID 8130 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[v4f32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8130, GIR_Done, // Label 1450: @63538 GIM_Try, /*On fail goto*//*Label 1451*/ 63575, // Rule ID 8134 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[v4i32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8134, GIR_Done, // Label 1451: @63575 GIM_Try, /*On fail goto*//*Label 1452*/ 63612, // Rule ID 8161 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[v4f32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8161, GIR_Done, // Label 1452: @63612 GIM_Try, /*On fail goto*//*Label 1453*/ 63649, // Rule ID 8162 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[v4i32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8162, GIR_Done, // Label 1453: @63649 GIM_Try, /*On fail goto*//*Label 1454*/ 63666, // Rule ID 9517 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev4s, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9517, GIR_Done, // Label 1454: @63666 GIM_Reject, // Label 1445: @63667 GIM_Reject, // Label 1307: @63668 GIM_Try, /*On fail goto*//*Label 1455*/ 63855, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 1456*/ 63722, // Rule ID 8061 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[v8i8] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8061, GIR_Done, // Label 1456: @63722 GIM_Try, /*On fail goto*//*Label 1457*/ 63763, // Rule ID 8062 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[v8i8] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8062, GIR_Done, // Label 1457: @63763 GIM_Try, /*On fail goto*//*Label 1458*/ 63800, // Rule ID 8123 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[v8i8] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8123, GIR_Done, // Label 1458: @63800 GIM_Try, /*On fail goto*//*Label 1459*/ 63837, // Rule ID 8155 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[v8i8] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8155, GIR_Done, // Label 1459: @63837 GIM_Try, /*On fail goto*//*Label 1460*/ 63854, // Rule ID 9519 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev8b:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev8b, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9519, GIR_Done, // Label 1460: @63854 GIM_Reject, // Label 1455: @63855 GIM_Reject, // Label 1308: @63856 GIM_Try, /*On fail goto*//*Label 1461*/ 64318, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 1462*/ 63910, // Rule ID 8081 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[v8i16] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8081, GIR_Done, // Label 1462: @63910 GIM_Try, /*On fail goto*//*Label 1463*/ 63951, // Rule ID 8082 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[v8i16] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8082, GIR_Done, // Label 1463: @63951 GIM_Try, /*On fail goto*//*Label 1464*/ 63992, // Rule ID 8083 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[v8f16] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8083, GIR_Done, // Label 1464: @63992 GIM_Try, /*On fail goto*//*Label 1465*/ 64033, // Rule ID 8084 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[v8f16] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8084, GIR_Done, // Label 1465: @64033 GIM_Try, /*On fail goto*//*Label 1466*/ 64074, // Rule ID 8085 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[v8bf16] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[v8bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8085, GIR_Done, // Label 1466: @64074 GIM_Try, /*On fail goto*//*Label 1467*/ 64115, // Rule ID 8086 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[v8bf16] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[v8bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8086, GIR_Done, // Label 1467: @64115 GIM_Try, /*On fail goto*//*Label 1468*/ 64152, // Rule ID 8133 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[v8i16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8133, GIR_Done, // Label 1468: @64152 GIM_Try, /*On fail goto*//*Label 1469*/ 64189, // Rule ID 8136 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[v8f16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8136, GIR_Done, // Label 1469: @64189 GIM_Try, /*On fail goto*//*Label 1470*/ 64226, // Rule ID 8137 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[v8bf16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[v8bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8137, GIR_Done, // Label 1470: @64226 GIM_Try, /*On fail goto*//*Label 1471*/ 64263, // Rule ID 8163 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[v8i16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8163, GIR_Done, // Label 1471: @64263 GIM_Try, /*On fail goto*//*Label 1472*/ 64300, // Rule ID 8165 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[v8f16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8165, GIR_Done, // Label 1472: @64300 GIM_Try, /*On fail goto*//*Label 1473*/ 64317, // Rule ID 9516 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev8h, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9516, GIR_Done, // Label 1473: @64317 GIM_Reject, // Label 1461: @64318 GIM_Reject, // Label 1309: @64319 GIM_Try, /*On fail goto*//*Label 1474*/ 64506, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 1475*/ 64373, // Rule ID 8087 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[v16i8] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8087, GIR_Done, // Label 1475: @64373 GIM_Try, /*On fail goto*//*Label 1476*/ 64414, // Rule ID 8088 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[v16i8] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8088, GIR_Done, // Label 1476: @64414 GIM_Try, /*On fail goto*//*Label 1477*/ 64451, // Rule ID 8132 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[v16i8] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8132, GIR_Done, // Label 1477: @64451 GIM_Try, /*On fail goto*//*Label 1478*/ 64488, // Rule ID 8164 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[v16i8] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8164, GIR_Done, // Label 1478: @64488 GIM_Try, /*On fail goto*//*Label 1479*/ 64505, // Rule ID 9515 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev16b, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9515, GIR_Done, // Label 1479: @64505 GIM_Reject, // Label 1474: @64506 GIM_Reject, // Label 1310: @64507 GIM_Try, /*On fail goto*//*Label 1480*/ 64621, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 1481*/ 64574, // Rule ID 5494 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (ld:{ *:[nxv2f16] } GPR64:{ *:[i64] }:$base)<><> => (LD1H_D_IMM:{ *:[nxv2f16] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1H_D_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5494, GIR_Done, // Label 1481: @64574 GIM_Try, /*On fail goto*//*Label 1482*/ 64620, // Rule ID 5497 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (ld:{ *:[nxv2bf16] } GPR64:{ *:[i64] }:$base)<><> => (LD1H_D_IMM:{ *:[nxv2bf16] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1H_D_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5497, GIR_Done, // Label 1482: @64620 GIM_Reject, // Label 1480: @64621 GIM_Reject, // Label 1311: @64622 GIM_Try, /*On fail goto*//*Label 1483*/ 64687, // Rule ID 5503 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (ld:{ *:[nxv2f32] } GPR64:{ *:[i64] }:$base)<><> => (LD1W_D_IMM:{ *:[nxv2f32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1W_D_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5503, GIR_Done, // Label 1483: @64687 GIM_Reject, // Label 1312: @64688 GIM_Try, /*On fail goto*//*Label 1484*/ 64802, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 1485*/ 64755, // Rule ID 5479 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (ld:{ *:[nxv2i64] } GPR64:{ *:[i64] }:$base)<><> => (LD1D_IMM:{ *:[nxv2i64] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1D_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5479, GIR_Done, // Label 1485: @64755 GIM_Try, /*On fail goto*//*Label 1486*/ 64801, // Rule ID 5506 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (ld:{ *:[nxv2f64] } GPR64:{ *:[i64] }:$base)<><> => (LD1D_IMM:{ *:[nxv2f64] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1D_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5506, GIR_Done, // Label 1486: @64801 GIM_Reject, // Label 1484: @64802 GIM_Reject, // Label 1313: @64803 GIM_Try, /*On fail goto*//*Label 1487*/ 64917, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 1488*/ 64870, // Rule ID 5488 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (ld:{ *:[nxv4f16] } GPR64:{ *:[i64] }:$base)<><> => (LD1H_S_IMM:{ *:[nxv4f16] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_S, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1H_S_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5488, GIR_Done, // Label 1488: @64870 GIM_Try, /*On fail goto*//*Label 1489*/ 64916, // Rule ID 5491 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (ld:{ *:[nxv4bf16] } GPR64:{ *:[i64] }:$base)<><> => (LD1H_S_IMM:{ *:[nxv4bf16] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_S, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1H_S_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5491, GIR_Done, // Label 1489: @64916 GIM_Reject, // Label 1487: @64917 GIM_Reject, // Label 1314: @64918 GIM_Try, /*On fail goto*//*Label 1490*/ 65032, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 1491*/ 64985, // Rule ID 5467 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (ld:{ *:[nxv4i32] } GPR64:{ *:[i64] }:$base)<><> => (LD1W_IMM:{ *:[nxv4i32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_S, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1W_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5467, GIR_Done, // Label 1491: @64985 GIM_Try, /*On fail goto*//*Label 1492*/ 65031, // Rule ID 5500 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (ld:{ *:[nxv4f32] } GPR64:{ *:[i64] }:$base)<><> => (LD1W_IMM:{ *:[nxv4f32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_S, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1W_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5500, GIR_Done, // Label 1492: @65031 GIM_Reject, // Label 1490: @65032 GIM_Reject, // Label 1315: @65033 GIM_Try, /*On fail goto*//*Label 1493*/ 65193, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 1494*/ 65100, // Rule ID 5446 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (ld:{ *:[nxv8i16] } GPR64:{ *:[i64] }:$base)<><> => (LD1H_IMM:{ *:[nxv8i16] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_H, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1H_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5446, GIR_Done, // Label 1494: @65100 GIM_Try, /*On fail goto*//*Label 1495*/ 65146, // Rule ID 5482 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (ld:{ *:[nxv8f16] } GPR64:{ *:[i64] }:$base)<><> => (LD1H_IMM:{ *:[nxv8f16] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_H, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1H_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5482, GIR_Done, // Label 1495: @65146 GIM_Try, /*On fail goto*//*Label 1496*/ 65192, // Rule ID 5485 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (ld:{ *:[nxv8bf16] } GPR64:{ *:[i64] }:$base)<><> => (LD1H_IMM:{ *:[nxv8bf16] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_H, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1H_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5485, GIR_Done, // Label 1496: @65192 GIM_Reject, // Label 1493: @65193 GIM_Reject, // Label 1316: @65194 GIM_Try, /*On fail goto*//*Label 1497*/ 65240, // Rule ID 2291 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (ld:{ *:[nxv16i1] } GPR64:{ *:[i64] }:$base)<><> => (LDR_PXI:{ *:[nxv16i1] } GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDR_PXI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2291, GIR_Done, // Label 1497: @65240 GIM_Reject, // Label 1317: @65241 GIM_Try, /*On fail goto*//*Label 1498*/ 65306, // Rule ID 5414 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (ld:{ *:[nxv16i8] } GPR64:{ *:[i64] }:$base)<><> => (LD1B_IMM:{ *:[nxv16i8] } (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_B, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1B_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5414, GIR_Done, // Label 1498: @65306 GIM_Reject, // Label 1318: @65307 GIM_Reject, // Label 15: @65308 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1501*/ 66278, /*GILLT_s32*//*Label 1499*/ 65316, /*GILLT_s64*//*Label 1500*/ 65701, // Label 1499: @65316 GIM_Try, /*On fail goto*//*Label 1502*/ 65366, // Rule ID 244 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><> => (LDRSHWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHWroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 244, GIR_Done, // Label 1502: @65366 GIM_Try, /*On fail goto*//*Label 1503*/ 65416, // Rule ID 245 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><><> => (LDRSHWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHWroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 245, GIR_Done, // Label 1503: @65416 GIM_Try, /*On fail goto*//*Label 1504*/ 65466, // Rule ID 248 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (LDRSBWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBWroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 248, GIR_Done, // Label 1504: @65466 GIM_Try, /*On fail goto*//*Label 1505*/ 65516, // Rule ID 249 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (LDRSBWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBWroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 249, GIR_Done, // Label 1505: @65516 GIM_Try, /*On fail goto*//*Label 1506*/ 65562, // Rule ID 265 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><> => (LDRSHWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHWui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 265, GIR_Done, // Label 1506: @65562 GIM_Try, /*On fail goto*//*Label 1507*/ 65608, // Rule ID 267 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (LDRSBWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBWui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 267, GIR_Done, // Label 1507: @65608 GIM_Try, /*On fail goto*//*Label 1508*/ 65654, // Rule ID 286 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURSHWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSHWi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 286, GIR_Done, // Label 1508: @65654 GIM_Try, /*On fail goto*//*Label 1509*/ 65700, // Rule ID 288 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURSBWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSBWi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 288, GIR_Done, // Label 1509: @65700 GIM_Reject, // Label 1500: @65701 GIM_Try, /*On fail goto*//*Label 1510*/ 65751, // Rule ID 246 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><> => (LDRSHXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHXroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 246, GIR_Done, // Label 1510: @65751 GIM_Try, /*On fail goto*//*Label 1511*/ 65801, // Rule ID 247 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><><> => (LDRSHXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHXroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 247, GIR_Done, // Label 1511: @65801 GIM_Try, /*On fail goto*//*Label 1512*/ 65851, // Rule ID 250 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (LDRSBXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBXroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 250, GIR_Done, // Label 1512: @65851 GIM_Try, /*On fail goto*//*Label 1513*/ 65901, // Rule ID 251 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (LDRSBXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBXroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 251, GIR_Done, // Label 1513: @65901 GIM_Try, /*On fail goto*//*Label 1514*/ 65951, // Rule ID 252 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><><> => (LDRSWroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSWroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 252, GIR_Done, // Label 1514: @65951 GIM_Try, /*On fail goto*//*Label 1515*/ 66001, // Rule ID 253 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><><> => (LDRSWroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSWroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 253, GIR_Done, // Label 1515: @66001 GIM_Try, /*On fail goto*//*Label 1516*/ 66047, // Rule ID 266 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><> => (LDRSHXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHXui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 266, GIR_Done, // Label 1516: @66047 GIM_Try, /*On fail goto*//*Label 1517*/ 66093, // Rule ID 268 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (LDRSBXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBXui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 268, GIR_Done, // Label 1517: @66093 GIM_Try, /*On fail goto*//*Label 1518*/ 66139, // Rule ID 269 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><><> => (LDRSWui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSWui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 269, GIR_Done, // Label 1518: @66139 GIM_Try, /*On fail goto*//*Label 1519*/ 66185, // Rule ID 287 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURSHXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSHXi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 287, GIR_Done, // Label 1519: @66185 GIM_Try, /*On fail goto*//*Label 1520*/ 66231, // Rule ID 289 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURSBXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSBXi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 289, GIR_Done, // Label 1520: @66231 GIM_Try, /*On fail goto*//*Label 1521*/ 66277, // Rule ID 290 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURSWi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSWi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 290, GIR_Done, // Label 1521: @66277 GIM_Reject, // Label 1501: @66278 GIM_Reject, // Label 16: @66279 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1524*/ 68853, /*GILLT_s32*//*Label 1522*/ 66287, /*GILLT_s64*//*Label 1523*/ 67488, // Label 1522: @66287 GIM_Try, /*On fail goto*//*Label 1525*/ 66337, // Rule ID 226 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 226, GIR_Done, // Label 1525: @66337 GIM_Try, /*On fail goto*//*Label 1526*/ 66387, // Rule ID 227 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 227, GIR_Done, // Label 1526: @66387 GIM_Try, /*On fail goto*//*Label 1527*/ 66437, // Rule ID 228 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><> => (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 228, GIR_Done, // Label 1527: @66437 GIM_Try, /*On fail goto*//*Label 1528*/ 66487, // Rule ID 229 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><><> => (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 229, GIR_Done, // Label 1528: @66487 GIM_Try, /*On fail goto*//*Label 1529*/ 66537, // Rule ID 8111 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8111, GIR_Done, // Label 1529: @66537 GIM_Try, /*On fail goto*//*Label 1530*/ 66587, // Rule ID 8112 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8112, GIR_Done, // Label 1530: @66587 GIM_Try, /*On fail goto*//*Label 1531*/ 66633, // Rule ID 263 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 263, GIR_Done, // Label 1531: @66633 GIM_Try, /*On fail goto*//*Label 1532*/ 66679, // Rule ID 264 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 264, GIR_Done, // Label 1532: @66679 GIM_Try, /*On fail goto*//*Label 1533*/ 66732, // Rule ID 10177 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (atomic_load:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset))<><><> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10177, GIR_Done, // Label 1533: @66732 GIM_Try, /*On fail goto*//*Label 1534*/ 66785, // Rule ID 10179 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (atomic_load:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset))<><><> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10179, GIR_Done, // Label 1534: @66785 GIM_Try, /*On fail goto*//*Label 1535*/ 66838, // Rule ID 10189 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (atomic_load:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><> => (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10189, GIR_Done, // Label 1535: @66838 GIM_Try, /*On fail goto*//*Label 1536*/ 66891, // Rule ID 10191 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (atomic_load:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><><> => (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10191, GIR_Done, // Label 1536: @66891 GIM_Try, /*On fail goto*//*Label 1537*/ 66937, // Rule ID 284 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 284, GIR_Done, // Label 1537: @66937 GIM_Try, /*On fail goto*//*Label 1538*/ 66983, // Rule ID 285 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 285, GIR_Done, // Label 1538: @66983 GIM_Try, /*On fail goto*//*Label 1539*/ 67029, // Rule ID 8141 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8141, GIR_Done, // Label 1539: @67029 GIM_Try, /*On fail goto*//*Label 1540*/ 67075, // Rule ID 8173 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8173, GIR_Done, // Label 1540: @67075 GIM_Try, /*On fail goto*//*Label 1541*/ 67121, // Rule ID 8174 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8174, GIR_Done, // Label 1541: @67121 GIM_Try, /*On fail goto*//*Label 1542*/ 67167, // Rule ID 8175 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8175, GIR_Done, // Label 1542: @67167 GIM_Try, /*On fail goto*//*Label 1543*/ 67216, // Rule ID 10181 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (atomic_load:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10181, GIR_Done, // Label 1543: @67216 GIM_Try, /*On fail goto*//*Label 1544*/ 67265, // Rule ID 10183 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10183, GIR_Done, // Label 1544: @67265 GIM_Try, /*On fail goto*//*Label 1545*/ 67314, // Rule ID 10193 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (atomic_load:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10193, GIR_Done, // Label 1545: @67314 GIM_Try, /*On fail goto*//*Label 1546*/ 67363, // Rule ID 10195 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10195, GIR_Done, // Label 1546: @67363 GIM_Try, /*On fail goto*//*Label 1547*/ 67394, // Rule ID 10173 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><><> => (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARB, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10173, GIR_Done, // Label 1547: @67394 GIM_Try, /*On fail goto*//*Label 1548*/ 67425, // Rule ID 10175 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><><> => (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARB, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10175, GIR_Done, // Label 1548: @67425 GIM_Try, /*On fail goto*//*Label 1549*/ 67456, // Rule ID 10185 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><><> => (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARH, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10185, GIR_Done, // Label 1549: @67456 GIM_Try, /*On fail goto*//*Label 1550*/ 67487, // Rule ID 10187 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><><> => (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARH, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10187, GIR_Done, // Label 1550: @67487 GIM_Reject, // Label 1523: @67488 GIM_Try, /*On fail goto*//*Label 1551*/ 67566, // Rule ID 8089 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8089, GIR_Done, // Label 1551: @67566 GIM_Try, /*On fail goto*//*Label 1552*/ 67644, // Rule ID 8090 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8090, GIR_Done, // Label 1552: @67644 GIM_Try, /*On fail goto*//*Label 1553*/ 67722, // Rule ID 8091 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8091, GIR_Done, // Label 1553: @67722 GIM_Try, /*On fail goto*//*Label 1554*/ 67800, // Rule ID 8092 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8092, GIR_Done, // Label 1554: @67800 GIM_Try, /*On fail goto*//*Label 1555*/ 67878, // Rule ID 8093 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8093, GIR_Done, // Label 1555: @67878 GIM_Try, /*On fail goto*//*Label 1556*/ 67956, // Rule ID 8094 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8094, GIR_Done, // Label 1556: @67956 GIM_Try, /*On fail goto*//*Label 1557*/ 68034, // Rule ID 8095 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8095, GIR_Done, // Label 1557: @68034 GIM_Try, /*On fail goto*//*Label 1558*/ 68112, // Rule ID 8096 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8096, GIR_Done, // Label 1558: @68112 GIM_Try, /*On fail goto*//*Label 1559*/ 68186, // Rule ID 8139 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8139, GIR_Done, // Label 1559: @68186 GIM_Try, /*On fail goto*//*Label 1560*/ 68260, // Rule ID 8140 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8140, GIR_Done, // Label 1560: @68260 GIM_Try, /*On fail goto*//*Label 1561*/ 68334, // Rule ID 8142 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8142, GIR_Done, // Label 1561: @68334 GIM_Try, /*On fail goto*//*Label 1562*/ 68408, // Rule ID 8150 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8150, GIR_Done, // Label 1562: @68408 GIM_Try, /*On fail goto*//*Label 1563*/ 68482, // Rule ID 8176 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURWi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8176, GIR_Done, // Label 1563: @68482 GIM_Try, /*On fail goto*//*Label 1564*/ 68556, // Rule ID 8177 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURHHi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8177, GIR_Done, // Label 1564: @68556 GIM_Try, /*On fail goto*//*Label 1565*/ 68630, // Rule ID 8178 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8178, GIR_Done, // Label 1565: @68630 GIM_Try, /*On fail goto*//*Label 1566*/ 68704, // Rule ID 8179 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8179, GIR_Done, // Label 1566: @68704 GIM_Try, /*On fail goto*//*Label 1567*/ 68778, // Rule ID 8180 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8180, GIR_Done, // Label 1567: @68778 GIM_Try, /*On fail goto*//*Label 1568*/ 68852, // Rule ID 8181 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURHHi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 8181, GIR_Done, // Label 1568: @68852 GIM_Reject, // Label 1524: @68853 GIM_Reject, // Label 17: @68854 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 23, /*)*//*default:*//*Label 1588*/ 77896, /*GILLT_s16*//*Label 1569*/ 68883, /*GILLT_s32*//*Label 1570*/ 69425, /*GILLT_s64*//*Label 1571*/ 71925, /*GILLT_s128*//*Label 1572*/ 74265, /*GILLT_v2s32*//*Label 1573*/ 74451, /*GILLT_v2s64*//*Label 1574*/ 74823, /*GILLT_v4s16*//*Label 1575*/ 75236, /*GILLT_v4s32*//*Label 1576*/ 75780, /*GILLT_v8s8*//*Label 1577*/ 76152, /*GILLT_v8s16*//*Label 1578*/ 76352, /*GILLT_v16s8*//*Label 1579*/ 76896, 0, 0, /*GILLT_nxv2s16*//*Label 1580*/ 77096, /*GILLT_nxv2s32*//*Label 1581*/ 77211, /*GILLT_nxv2s64*//*Label 1582*/ 77277, 0, /*GILLT_nxv4s16*//*Label 1583*/ 77392, /*GILLT_nxv4s32*//*Label 1584*/ 77507, 0, /*GILLT_nxv8s16*//*Label 1585*/ 77622, /*GILLT_nxv16s1*//*Label 1586*/ 77783, /*GILLT_nxv16s8*//*Label 1587*/ 77830, // Label 1569: @68883 GIM_Try, /*On fail goto*//*Label 1589*/ 69424, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1590*/ 68960, // Rule ID 9573 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i16 VecListOne128:{ *:[v8f16] }:$Vt, (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9573, GIR_Done, // Label 1590: @68960 GIM_Try, /*On fail goto*//*Label 1591*/ 69028, // Rule ID 9574 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[bf16] } VecListOne128:{ *:[v8bf16] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i16 VecListOne128:{ *:[v8bf16] }:$Vt, (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9574, GIR_Done, // Label 1591: @69028 GIM_Try, /*On fail goto*//*Label 1592*/ 69124, // Rule ID 9579 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[f16] } VecListOne64:{ *:[v4f16] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i16 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4f16] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i16, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9579, GIR_Done, // Label 1592: @69124 GIM_Try, /*On fail goto*//*Label 1593*/ 69220, // Rule ID 9580 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[bf16] } VecListOne64:{ *:[v4bf16] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i16 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4bf16] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i16, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9580, GIR_Done, // Label 1593: @69220 GIM_Try, /*On fail goto*//*Label 1594*/ 69263, // Rule ID 302 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (st FPR16Op:{ *:[f16] }:$Rt, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><> => (STRHroW FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 302, GIR_Done, // Label 1594: @69263 GIM_Try, /*On fail goto*//*Label 1595*/ 69306, // Rule ID 303 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (st FPR16Op:{ *:[f16] }:$Rt, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><> => (STRHroX FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 303, GIR_Done, // Label 1595: @69306 GIM_Try, /*On fail goto*//*Label 1596*/ 69345, // Rule ID 311 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (st FPR16Op:{ *:[f16] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><> => (STRHui FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 311, GIR_Done, // Label 1596: @69345 GIM_Try, /*On fail goto*//*Label 1597*/ 69384, // Rule ID 319 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (st FPR16Op:{ *:[f16] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURHi FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURHi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 319, GIR_Done, // Label 1597: @69384 GIM_Try, /*On fail goto*//*Label 1598*/ 69423, // Rule ID 8236 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (st FPR16Op:{ *:[bf16] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><> => (STRHui FPR16:{ *:[bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8236, GIR_Done, // Label 1598: @69423 GIM_Reject, // Label 1589: @69424 GIM_Reject, // Label 1570: @69425 GIM_Try, /*On fail goto*//*Label 1599*/ 69500, // Rule ID 9569 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i32 VecListOne128:{ *:[v4i32] }:$Vt, (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9569, GIR_Done, // Label 1599: @69500 GIM_Try, /*On fail goto*//*Label 1600*/ 69575, // Rule ID 9570 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i32 VecListOne128:{ *:[v4f32] }:$Vt, (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9570, GIR_Done, // Label 1600: @69575 GIM_Try, /*On fail goto*//*Label 1601*/ 69678, // Rule ID 9577 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i32 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2i32] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9577, GIR_Done, // Label 1601: @69678 GIM_Try, /*On fail goto*//*Label 1602*/ 69781, // Rule ID 9578 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[f32] } VecListOne64:{ *:[v2f32] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i32 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2f32] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9578, GIR_Done, // Label 1602: @69781 GIM_Try, /*On fail goto*//*Label 1603*/ 69860, // Rule ID 9567 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v16i8] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><><> => (ST1i8 VecListOne128:{ *:[v16i8] }:$Vt, (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9567, GIR_Done, // Label 1603: @69860 GIM_Try, /*On fail goto*//*Label 1604*/ 69939, // Rule ID 9568 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><><> => (ST1i16 VecListOne128:{ *:[v8i16] }:$Vt, (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9568, GIR_Done, // Label 1604: @69939 GIM_Try, /*On fail goto*//*Label 1605*/ 70046, // Rule ID 9575 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v8i8] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><><> => (ST1i8 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v8i8] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i8, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9575, GIR_Done, // Label 1605: @70046 GIM_Try, /*On fail goto*//*Label 1606*/ 70153, // Rule ID 9576 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v4i16] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><><> => (ST1i16 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4i16] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i16, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9576, GIR_Done, // Label 1606: @70153 GIM_Try, /*On fail goto*//*Label 1607*/ 70203, // Rule ID 296 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (st GPR32:{ *:[i32] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><> => (STRWroW GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 296, GIR_Done, // Label 1607: @70203 GIM_Try, /*On fail goto*//*Label 1608*/ 70253, // Rule ID 297 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (st GPR32:{ *:[i32] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><> => (STRWroX GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 297, GIR_Done, // Label 1608: @70253 GIM_Try, /*On fail goto*//*Label 1609*/ 70303, // Rule ID 304 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (st FPR32Op:{ *:[f32] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><> => (STRSroW FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 304, GIR_Done, // Label 1609: @70303 GIM_Try, /*On fail goto*//*Label 1610*/ 70353, // Rule ID 305 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (st FPR32Op:{ *:[f32] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><> => (STRSroX FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 305, GIR_Done, // Label 1610: @70353 GIM_Try, /*On fail goto*//*Label 1611*/ 70407, // Rule ID 292 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (st GPR32:{ *:[i32] }:$Rt, (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (STRBBroW GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRBBroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 292, GIR_Done, // Label 1611: @70407 GIM_Try, /*On fail goto*//*Label 1612*/ 70461, // Rule ID 293 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (st GPR32:{ *:[i32] }:$Rt, (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (STRBBroX GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRBBroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 293, GIR_Done, // Label 1612: @70461 GIM_Try, /*On fail goto*//*Label 1613*/ 70515, // Rule ID 294 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (st GPR32:{ *:[i32] }:$Rt, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><> => (STRHHroW GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHHroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 294, GIR_Done, // Label 1613: @70515 GIM_Try, /*On fail goto*//*Label 1614*/ 70569, // Rule ID 295 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (st GPR32:{ *:[i32] }:$Rt, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><><> => (STRHHroX GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHHroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 295, GIR_Done, // Label 1614: @70569 GIM_Try, /*On fail goto*//*Label 1615*/ 70616, // Rule ID 309 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><> => (STRWui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWui, GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::WZR, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 309, GIR_Done, // Label 1615: @70616 GIM_Try, /*On fail goto*//*Label 1616*/ 70662, // Rule ID 312 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (st FPR32Op:{ *:[f32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><> => (STRSui FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 312, GIR_Done, // Label 1616: @70662 GIM_Try, /*On fail goto*//*Label 1617*/ 70713, // Rule ID 314 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><> => (STRHHui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHHui, GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::WZR, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 314, GIR_Done, // Label 1617: @70713 GIM_Try, /*On fail goto*//*Label 1618*/ 70764, // Rule ID 315 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (STRBBui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRBBui, GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::WZR, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 315, GIR_Done, // Label 1618: @70764 GIM_Try, /*On fail goto*//*Label 1619*/ 70831, // Rule ID 10236 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (atomic_store (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val))<><> => (STRSroW FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10236, GIR_Done, // Label 1619: @70831 GIM_Try, /*On fail goto*//*Label 1620*/ 70898, // Rule ID 10237 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (atomic_store (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val))<><> => (STRSroX FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10237, GIR_Done, // Label 1620: @70898 GIM_Try, /*On fail goto*//*Label 1621*/ 70951, // Rule ID 10217 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (atomic_store (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), GPR32:{ *:[i32] }:$val)<><> => (STRBBroW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRBBroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10217, GIR_Done, // Label 1621: @70951 GIM_Try, /*On fail goto*//*Label 1622*/ 71004, // Rule ID 10218 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (atomic_store (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), GPR32:{ *:[i32] }:$val)<><> => (STRBBroX GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRBBroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10218, GIR_Done, // Label 1622: @71004 GIM_Try, /*On fail goto*//*Label 1623*/ 71057, // Rule ID 10222 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (atomic_store (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), GPR32:{ *:[i32] }:$val)<><> => (STRHHroW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHHroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10222, GIR_Done, // Label 1623: @71057 GIM_Try, /*On fail goto*//*Label 1624*/ 71110, // Rule ID 10223 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (atomic_store (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), GPR32:{ *:[i32] }:$val)<><> => (STRHHroX GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHHroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10223, GIR_Done, // Label 1624: @71110 GIM_Try, /*On fail goto*//*Label 1625*/ 71163, // Rule ID 10227 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (atomic_store (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), GPR32:{ *:[i32] }:$val)<><> => (STRWroW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10227, GIR_Done, // Label 1625: @71163 GIM_Try, /*On fail goto*//*Label 1626*/ 71216, // Rule ID 10228 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (atomic_store (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), GPR32:{ *:[i32] }:$val)<><> => (STRWroX GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10228, GIR_Done, // Label 1626: @71216 GIM_Try, /*On fail goto*//*Label 1627*/ 71279, // Rule ID 10238 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (atomic_store (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val))<><> => (STRSui FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10238, GIR_Done, // Label 1627: @71279 GIM_Try, /*On fail goto*//*Label 1628*/ 71342, // Rule ID 10239 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (atomic_store (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val))<><> => (STURSi FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURSi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10239, GIR_Done, // Label 1628: @71342 GIM_Try, /*On fail goto*//*Label 1629*/ 71389, // Rule ID 317 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURWi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURWi, GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::WZR, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 317, GIR_Done, // Label 1629: @71389 GIM_Try, /*On fail goto*//*Label 1630*/ 71435, // Rule ID 320 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (st FPR32Op:{ *:[f32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURSi FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURSi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 320, GIR_Done, // Label 1630: @71435 GIM_Try, /*On fail goto*//*Label 1631*/ 71486, // Rule ID 323 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (STURHHi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURHHi, GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::WZR, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 323, GIR_Done, // Label 1631: @71486 GIM_Try, /*On fail goto*//*Label 1632*/ 71537, // Rule ID 324 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (STURBBi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURBBi, GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::WZR, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 324, GIR_Done, // Label 1632: @71537 GIM_Try, /*On fail goto*//*Label 1633*/ 71586, // Rule ID 10219 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (atomic_store (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), GPR32:{ *:[i32] }:$val)<><> => (STRBBui GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRBBui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10219, GIR_Done, // Label 1633: @71586 GIM_Try, /*On fail goto*//*Label 1634*/ 71635, // Rule ID 10220 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (atomic_store (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), GPR32:{ *:[i32] }:$val)<><> => (STURBBi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURBBi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10220, GIR_Done, // Label 1634: @71635 GIM_Try, /*On fail goto*//*Label 1635*/ 71684, // Rule ID 10224 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (atomic_store (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), GPR32:{ *:[i32] }:$val)<><> => (STRHHui GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHHui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10224, GIR_Done, // Label 1635: @71684 GIM_Try, /*On fail goto*//*Label 1636*/ 71733, // Rule ID 10225 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (atomic_store (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), GPR32:{ *:[i32] }:$val)<><> => (STURHHi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURHHi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10225, GIR_Done, // Label 1636: @71733 GIM_Try, /*On fail goto*//*Label 1637*/ 71782, // Rule ID 10229 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (atomic_store (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), GPR32:{ *:[i32] }:$val)<><> => (STRWui GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10229, GIR_Done, // Label 1637: @71782 GIM_Try, /*On fail goto*//*Label 1638*/ 71831, // Rule ID 10230 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (atomic_store (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), GPR32:{ *:[i32] }:$val)<><> => (STURWi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURWi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10230, GIR_Done, // Label 1638: @71831 GIM_Try, /*On fail goto*//*Label 1639*/ 71862, // Rule ID 10216 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // (atomic_store GPR64sp:{ *:[i64] }:$ptr, GPR32:{ *:[i32] }:$val)<><> => (STLRB GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::STLRB, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10216, GIR_Done, // Label 1639: @71862 GIM_Try, /*On fail goto*//*Label 1640*/ 71893, // Rule ID 10221 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // (atomic_store GPR64sp:{ *:[i64] }:$ptr, GPR32:{ *:[i32] }:$val)<><> => (STLRH GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::STLRH, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10221, GIR_Done, // Label 1640: @71893 GIM_Try, /*On fail goto*//*Label 1641*/ 71924, // Rule ID 10226 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // (atomic_store GPR64sp:{ *:[i64] }:$ptr, GPR32:{ *:[i32] }:$val)<><> => (STLRW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::STLRW, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10226, GIR_Done, // Label 1641: @71924 GIM_Reject, // Label 1571: @71925 GIM_Try, /*On fail goto*//*Label 1642*/ 72000, // Rule ID 9571 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i64 VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9571, GIR_Done, // Label 1642: @72000 GIM_Try, /*On fail goto*//*Label 1643*/ 72075, // Rule ID 9572 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i64 VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9572, GIR_Done, // Label 1643: @72075 GIM_Try, /*On fail goto*//*Label 1644*/ 72125, // Rule ID 298 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRXroW GPR64:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 298, GIR_Done, // Label 1644: @72125 GIM_Try, /*On fail goto*//*Label 1645*/ 72175, // Rule ID 299 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRXroX GPR64:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 299, GIR_Done, // Label 1645: @72175 GIM_Try, /*On fail goto*//*Label 1646*/ 72225, // Rule ID 306 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64Op:{ *:[f64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 306, GIR_Done, // Label 1646: @72225 GIM_Try, /*On fail goto*//*Label 1647*/ 72275, // Rule ID 307 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64Op:{ *:[f64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 307, GIR_Done, // Label 1647: @72275 GIM_Try, /*On fail goto*//*Label 1648*/ 72325, // Rule ID 8204 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64:{ *:[v1i64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8204, GIR_Done, // Label 1648: @72325 GIM_Try, /*On fail goto*//*Label 1649*/ 72375, // Rule ID 8205 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64:{ *:[v1i64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8205, GIR_Done, // Label 1649: @72375 GIM_Try, /*On fail goto*//*Label 1650*/ 72425, // Rule ID 8206 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64:{ *:[v1f64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8206, GIR_Done, // Label 1650: @72425 GIM_Try, /*On fail goto*//*Label 1651*/ 72475, // Rule ID 8207 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64:{ *:[v1f64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8207, GIR_Done, // Label 1651: @72475 GIM_Try, /*On fail goto*//*Label 1652*/ 72552, // Rule ID 8186 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (STRBBroW (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/15, // Rt GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRBBroW, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8186, GIR_Done, // Label 1652: @72552 GIM_Try, /*On fail goto*//*Label 1653*/ 72629, // Rule ID 8187 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (STRBBroX (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/15, // Rt GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRBBroX, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8187, GIR_Done, // Label 1653: @72629 GIM_Try, /*On fail goto*//*Label 1654*/ 72706, // Rule ID 8188 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><> => (STRHHroW (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/15, // Rt GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHHroW, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8188, GIR_Done, // Label 1654: @72706 GIM_Try, /*On fail goto*//*Label 1655*/ 72783, // Rule ID 8189 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><><> => (STRHHroX (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/15, // Rt GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHHroX, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8189, GIR_Done, // Label 1655: @72783 GIM_Try, /*On fail goto*//*Label 1656*/ 72860, // Rule ID 8190 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><><> => (STRWroW (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/15, // Rt GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWroW, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8190, GIR_Done, // Label 1656: @72860 GIM_Try, /*On fail goto*//*Label 1657*/ 72937, // Rule ID 8191 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><><> => (STRWroX (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/15, // Rt GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWroX, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8191, GIR_Done, // Label 1657: @72937 GIM_Try, /*On fail goto*//*Label 1658*/ 72984, // Rule ID 308 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st GPR64z:{ *:[i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRXui GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXui, GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::XZR, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 308, GIR_Done, // Label 1658: @72984 GIM_Try, /*On fail goto*//*Label 1659*/ 73030, // Rule ID 313 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64Op:{ *:[f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 313, GIR_Done, // Label 1659: @73030 GIM_Try, /*On fail goto*//*Label 1660*/ 73076, // Rule ID 8237 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64:{ *:[v1i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8237, GIR_Done, // Label 1660: @73076 GIM_Try, /*On fail goto*//*Label 1661*/ 73122, // Rule ID 8238 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64:{ *:[v1f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8238, GIR_Done, // Label 1661: @73122 GIM_Try, /*On fail goto*//*Label 1662*/ 73195, // Rule ID 8254 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (st GPR64:{ *:[i64] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><><> => (STRWui (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/15, // Rt GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWui, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8254, GIR_Done, // Label 1662: @73195 GIM_Try, /*On fail goto*//*Label 1663*/ 73268, // Rule ID 8255 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (st GPR64:{ *:[i64] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><> => (STRHHui (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/15, // Rt GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHHui, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8255, GIR_Done, // Label 1663: @73268 GIM_Try, /*On fail goto*//*Label 1664*/ 73341, // Rule ID 8256 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (st GPR64:{ *:[i64] }:$Rt, (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (STRBBui (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/15, // Rt GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRBBui, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8256, GIR_Done, // Label 1664: @73341 GIM_Try, /*On fail goto*//*Label 1665*/ 73408, // Rule ID 10240 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (atomic_store (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val))<><> => (STRDroW FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10240, GIR_Done, // Label 1665: @73408 GIM_Try, /*On fail goto*//*Label 1666*/ 73475, // Rule ID 10241 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (atomic_store (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val))<><> => (STRDroX FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10241, GIR_Done, // Label 1666: @73475 GIM_Try, /*On fail goto*//*Label 1667*/ 73528, // Rule ID 10232 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (atomic_store (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), GPR64:{ *:[i64] }:$val)<><> => (STRXroW GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10232, GIR_Done, // Label 1667: @73528 GIM_Try, /*On fail goto*//*Label 1668*/ 73581, // Rule ID 10233 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (atomic_store (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), GPR64:{ *:[i64] }:$val)<><> => (STRXroX GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10233, GIR_Done, // Label 1668: @73581 GIM_Try, /*On fail goto*//*Label 1669*/ 73644, // Rule ID 10242 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (atomic_store (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val))<><> => (STRDui FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10242, GIR_Done, // Label 1669: @73644 GIM_Try, /*On fail goto*//*Label 1670*/ 73707, // Rule ID 10243 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (atomic_store (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val))<><> => (STURDi FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10243, GIR_Done, // Label 1670: @73707 GIM_Try, /*On fail goto*//*Label 1671*/ 73754, // Rule ID 316 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st GPR64z:{ *:[i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURXi GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURXi, GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::XZR, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 316, GIR_Done, // Label 1671: @73754 GIM_Try, /*On fail goto*//*Label 1672*/ 73800, // Rule ID 321 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64Op:{ *:[f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 321, GIR_Done, // Label 1672: @73800 GIM_Try, /*On fail goto*//*Label 1673*/ 73849, // Rule ID 10234 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (atomic_store (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), GPR64:{ *:[i64] }:$val)<><> => (STRXui GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10234, GIR_Done, // Label 1673: @73849 GIM_Try, /*On fail goto*//*Label 1674*/ 73898, // Rule ID 10235 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (atomic_store (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), GPR64:{ *:[i64] }:$val)<><> => (STURXi GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURXi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10235, GIR_Done, // Label 1674: @73898 GIM_Try, /*On fail goto*//*Label 1675*/ 73944, // Rule ID 8263 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64:{ *:[v1f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8263, GIR_Done, // Label 1675: @73944 GIM_Try, /*On fail goto*//*Label 1676*/ 73990, // Rule ID 8264 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64:{ *:[v1i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8264, GIR_Done, // Label 1676: @73990 GIM_Try, /*On fail goto*//*Label 1677*/ 74063, // Rule ID 8281 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (st GPR64:{ *:[i64] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (STURWi (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/15, // Rt GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURWi, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8281, GIR_Done, // Label 1677: @74063 GIM_Try, /*On fail goto*//*Label 1678*/ 74136, // Rule ID 8282 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (st GPR64:{ *:[i64] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (STURHHi (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/15, // Rt GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURHHi, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8282, GIR_Done, // Label 1678: @74136 GIM_Try, /*On fail goto*//*Label 1679*/ 74209, // Rule ID 8283 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (st GPR64:{ *:[i64] }:$Rt, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (STURBBi (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/15, // Rt GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURBBi, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8283, GIR_Done, // Label 1679: @74209 GIM_Try, /*On fail goto*//*Label 1680*/ 74240, // Rule ID 10231 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (atomic_store GPR64sp:{ *:[i64] }:$ptr, GPR64:{ *:[i64] }:$val)<><> => (STLRX GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::STLRX, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10231, GIR_Done, // Label 1680: @74240 GIM_Try, /*On fail goto*//*Label 1681*/ 74264, // Rule ID 9530 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v1i64:{ *:[v1i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev1d v1i64:{ *:[v1i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev1d, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9530, GIR_Done, // Label 1681: @74264 GIM_Reject, // Label 1572: @74265 GIM_Try, /*On fail goto*//*Label 1682*/ 74450, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_Try, /*On fail goto*//*Label 1683*/ 74319, // Rule ID 8184 // GIM_CheckFeatures, GIFBS_UseSTRQro, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[f128] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8184, GIR_Done, // Label 1683: @74319 GIM_Try, /*On fail goto*//*Label 1684*/ 74356, // Rule ID 8185 // GIM_CheckFeatures, GIFBS_UseSTRQro, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[f128] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8185, GIR_Done, // Label 1684: @74356 GIM_Try, /*On fail goto*//*Label 1685*/ 74387, // Rule ID 8245 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[f128] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8245, GIR_Done, // Label 1685: @74387 GIM_Try, /*On fail goto*//*Label 1686*/ 74418, // Rule ID 8271 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8271, GIR_Done, // Label 1686: @74418 GIM_Try, /*On fail goto*//*Label 1687*/ 74449, // Rule ID 322 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128Op:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128Op:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 322, GIR_Done, // Label 1687: @74449 GIM_Reject, // Label 1682: @74450 GIM_Reject, // Label 1573: @74451 GIM_Try, /*On fail goto*//*Label 1688*/ 74822, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1689*/ 74505, // Rule ID 8192 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64:{ *:[v2i32] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8192, GIR_Done, // Label 1689: @74505 GIM_Try, /*On fail goto*//*Label 1690*/ 74550, // Rule ID 8193 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64:{ *:[v2i32] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8193, GIR_Done, // Label 1690: @74550 GIM_Try, /*On fail goto*//*Label 1691*/ 74595, // Rule ID 8194 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64:{ *:[v2f32] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8194, GIR_Done, // Label 1691: @74595 GIM_Try, /*On fail goto*//*Label 1692*/ 74640, // Rule ID 8195 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64:{ *:[v2f32] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8195, GIR_Done, // Label 1692: @74640 GIM_Try, /*On fail goto*//*Label 1693*/ 74681, // Rule ID 8239 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64:{ *:[v2f32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8239, GIR_Done, // Label 1693: @74681 GIM_Try, /*On fail goto*//*Label 1694*/ 74722, // Rule ID 8242 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64:{ *:[v2i32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8242, GIR_Done, // Label 1694: @74722 GIM_Try, /*On fail goto*//*Label 1695*/ 74763, // Rule ID 8265 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64:{ *:[v2f32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8265, GIR_Done, // Label 1695: @74763 GIM_Try, /*On fail goto*//*Label 1696*/ 74804, // Rule ID 8268 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64:{ *:[v2i32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8268, GIR_Done, // Label 1696: @74804 GIM_Try, /*On fail goto*//*Label 1697*/ 74821, // Rule ID 9529 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v2i32:{ *:[v2i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev2s v2i32:{ *:[v2i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev2s, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9529, GIR_Done, // Label 1697: @74821 GIM_Reject, // Label 1688: @74822 GIM_Reject, // Label 1574: @74823 GIM_Try, /*On fail goto*//*Label 1698*/ 75235, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1699*/ 74877, // Rule ID 8208 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[v2i64] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8208, GIR_Done, // Label 1699: @74877 GIM_Try, /*On fail goto*//*Label 1700*/ 74922, // Rule ID 8209 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[v2i64] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8209, GIR_Done, // Label 1700: @74922 GIM_Try, /*On fail goto*//*Label 1701*/ 74967, // Rule ID 8210 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[v2f64] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8210, GIR_Done, // Label 1701: @74967 GIM_Try, /*On fail goto*//*Label 1702*/ 75012, // Rule ID 8211 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[v2f64] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8211, GIR_Done, // Label 1702: @75012 GIM_Try, /*On fail goto*//*Label 1703*/ 75053, // Rule ID 8247 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[v2f64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8247, GIR_Done, // Label 1703: @75053 GIM_Try, /*On fail goto*//*Label 1704*/ 75094, // Rule ID 8251 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[v2i64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8251, GIR_Done, // Label 1704: @75094 GIM_Try, /*On fail goto*//*Label 1705*/ 75135, // Rule ID 8273 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8273, GIR_Done, // Label 1705: @75135 GIM_Try, /*On fail goto*//*Label 1706*/ 75176, // Rule ID 8277 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v2i64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8277, GIR_Done, // Label 1706: @75176 GIM_Try, /*On fail goto*//*Label 1707*/ 75217, // Rule ID 8278 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8278, GIR_Done, // Label 1707: @75217 GIM_Try, /*On fail goto*//*Label 1708*/ 75234, // Rule ID 9526 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v2i64:{ *:[v2i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev2d v2i64:{ *:[v2i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev2d, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9526, GIR_Done, // Label 1708: @75234 GIM_Reject, // Label 1698: @75235 GIM_Reject, // Label 1575: @75236 GIM_Try, /*On fail goto*//*Label 1709*/ 75779, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1710*/ 75290, // Rule ID 8196 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64:{ *:[v4i16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8196, GIR_Done, // Label 1710: @75290 GIM_Try, /*On fail goto*//*Label 1711*/ 75335, // Rule ID 8197 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64:{ *:[v4i16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8197, GIR_Done, // Label 1711: @75335 GIM_Try, /*On fail goto*//*Label 1712*/ 75380, // Rule ID 8200 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64:{ *:[v4f16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8200, GIR_Done, // Label 1712: @75380 GIM_Try, /*On fail goto*//*Label 1713*/ 75425, // Rule ID 8201 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64:{ *:[v4f16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8201, GIR_Done, // Label 1713: @75425 GIM_Try, /*On fail goto*//*Label 1714*/ 75470, // Rule ID 8202 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64:{ *:[v4bf16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64:{ *:[v4bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8202, GIR_Done, // Label 1714: @75470 GIM_Try, /*On fail goto*//*Label 1715*/ 75515, // Rule ID 8203 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64:{ *:[v4bf16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64:{ *:[v4bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8203, GIR_Done, // Label 1715: @75515 GIM_Try, /*On fail goto*//*Label 1716*/ 75556, // Rule ID 8241 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64:{ *:[v4i16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8241, GIR_Done, // Label 1716: @75556 GIM_Try, /*On fail goto*//*Label 1717*/ 75597, // Rule ID 8243 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64:{ *:[v4f16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8243, GIR_Done, // Label 1717: @75597 GIM_Try, /*On fail goto*//*Label 1718*/ 75638, // Rule ID 8244 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64:{ *:[v4bf16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64:{ *:[v4bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8244, GIR_Done, // Label 1718: @75638 GIM_Try, /*On fail goto*//*Label 1719*/ 75679, // Rule ID 8267 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64:{ *:[v4i16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8267, GIR_Done, // Label 1719: @75679 GIM_Try, /*On fail goto*//*Label 1720*/ 75720, // Rule ID 8269 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64:{ *:[v4f16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8269, GIR_Done, // Label 1720: @75720 GIM_Try, /*On fail goto*//*Label 1721*/ 75761, // Rule ID 8270 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64:{ *:[v4bf16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64:{ *:[v4bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8270, GIR_Done, // Label 1721: @75761 GIM_Try, /*On fail goto*//*Label 1722*/ 75778, // Rule ID 9528 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v4i16:{ *:[v4i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev4h v4i16:{ *:[v4i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev4h, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9528, GIR_Done, // Label 1722: @75778 GIM_Reject, // Label 1709: @75779 GIM_Reject, // Label 1576: @75780 GIM_Try, /*On fail goto*//*Label 1723*/ 76151, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1724*/ 75834, // Rule ID 8212 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[v4i32] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8212, GIR_Done, // Label 1724: @75834 GIM_Try, /*On fail goto*//*Label 1725*/ 75879, // Rule ID 8213 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[v4i32] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8213, GIR_Done, // Label 1725: @75879 GIM_Try, /*On fail goto*//*Label 1726*/ 75924, // Rule ID 8214 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[v4f32] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8214, GIR_Done, // Label 1726: @75924 GIM_Try, /*On fail goto*//*Label 1727*/ 75969, // Rule ID 8215 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[v4f32] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8215, GIR_Done, // Label 1727: @75969 GIM_Try, /*On fail goto*//*Label 1728*/ 76010, // Rule ID 8246 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[v4f32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8246, GIR_Done, // Label 1728: @76010 GIM_Try, /*On fail goto*//*Label 1729*/ 76051, // Rule ID 8250 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[v4i32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8250, GIR_Done, // Label 1729: @76051 GIM_Try, /*On fail goto*//*Label 1730*/ 76092, // Rule ID 8272 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v4f32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8272, GIR_Done, // Label 1730: @76092 GIM_Try, /*On fail goto*//*Label 1731*/ 76133, // Rule ID 8276 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v4i32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8276, GIR_Done, // Label 1731: @76133 GIM_Try, /*On fail goto*//*Label 1732*/ 76150, // Rule ID 9525 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v4i32:{ *:[v4i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev4s v4i32:{ *:[v4i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev4s, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9525, GIR_Done, // Label 1732: @76150 GIM_Reject, // Label 1723: @76151 GIM_Reject, // Label 1577: @76152 GIM_Try, /*On fail goto*//*Label 1733*/ 76351, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1734*/ 76206, // Rule ID 8198 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64:{ *:[v8i8] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8198, GIR_Done, // Label 1734: @76206 GIM_Try, /*On fail goto*//*Label 1735*/ 76251, // Rule ID 8199 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64:{ *:[v8i8] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8199, GIR_Done, // Label 1735: @76251 GIM_Try, /*On fail goto*//*Label 1736*/ 76292, // Rule ID 8240 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64:{ *:[v8i8] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8240, GIR_Done, // Label 1736: @76292 GIM_Try, /*On fail goto*//*Label 1737*/ 76333, // Rule ID 8266 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64:{ *:[v8i8] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8266, GIR_Done, // Label 1737: @76333 GIM_Try, /*On fail goto*//*Label 1738*/ 76350, // Rule ID 9527 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v8i8:{ *:[v8i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev8b v8i8:{ *:[v8i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev8b, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9527, GIR_Done, // Label 1738: @76350 GIM_Reject, // Label 1733: @76351 GIM_Reject, // Label 1578: @76352 GIM_Try, /*On fail goto*//*Label 1739*/ 76895, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1740*/ 76406, // Rule ID 8216 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[v8i16] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8216, GIR_Done, // Label 1740: @76406 GIM_Try, /*On fail goto*//*Label 1741*/ 76451, // Rule ID 8217 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[v8i16] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8217, GIR_Done, // Label 1741: @76451 GIM_Try, /*On fail goto*//*Label 1742*/ 76496, // Rule ID 8220 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[v8f16] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8220, GIR_Done, // Label 1742: @76496 GIM_Try, /*On fail goto*//*Label 1743*/ 76541, // Rule ID 8221 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[v8f16] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8221, GIR_Done, // Label 1743: @76541 GIM_Try, /*On fail goto*//*Label 1744*/ 76586, // Rule ID 8222 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[v8bf16] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[v8bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8222, GIR_Done, // Label 1744: @76586 GIM_Try, /*On fail goto*//*Label 1745*/ 76631, // Rule ID 8223 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[v8bf16] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[v8bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8223, GIR_Done, // Label 1745: @76631 GIM_Try, /*On fail goto*//*Label 1746*/ 76672, // Rule ID 8249 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[v8i16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8249, GIR_Done, // Label 1746: @76672 GIM_Try, /*On fail goto*//*Label 1747*/ 76713, // Rule ID 8252 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[v8f16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8252, GIR_Done, // Label 1747: @76713 GIM_Try, /*On fail goto*//*Label 1748*/ 76754, // Rule ID 8253 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[v8bf16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[v8bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8253, GIR_Done, // Label 1748: @76754 GIM_Try, /*On fail goto*//*Label 1749*/ 76795, // Rule ID 8275 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v8i16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8275, GIR_Done, // Label 1749: @76795 GIM_Try, /*On fail goto*//*Label 1750*/ 76836, // Rule ID 8279 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v8f16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8279, GIR_Done, // Label 1750: @76836 GIM_Try, /*On fail goto*//*Label 1751*/ 76877, // Rule ID 8280 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v8bf16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v8bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8280, GIR_Done, // Label 1751: @76877 GIM_Try, /*On fail goto*//*Label 1752*/ 76894, // Rule ID 9524 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v8i16:{ *:[v8i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev8h v8i16:{ *:[v8i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev8h, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9524, GIR_Done, // Label 1752: @76894 GIM_Reject, // Label 1739: @76895 GIM_Reject, // Label 1579: @76896 GIM_Try, /*On fail goto*//*Label 1753*/ 77095, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1754*/ 76950, // Rule ID 8218 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[v16i8] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8218, GIR_Done, // Label 1754: @76950 GIM_Try, /*On fail goto*//*Label 1755*/ 76995, // Rule ID 8219 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[v16i8] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8219, GIR_Done, // Label 1755: @76995 GIM_Try, /*On fail goto*//*Label 1756*/ 77036, // Rule ID 8248 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[v16i8] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8248, GIR_Done, // Label 1756: @77036 GIM_Try, /*On fail goto*//*Label 1757*/ 77077, // Rule ID 8274 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v16i8] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8274, GIR_Done, // Label 1757: @77077 GIM_Try, /*On fail goto*//*Label 1758*/ 77094, // Rule ID 9523 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v16i8:{ *:[v16i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev16b v16i8:{ *:[v16i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev16b, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9523, GIR_Done, // Label 1758: @77094 GIM_Reject, // Label 1753: @77095 GIM_Reject, // Label 1580: @77096 GIM_Try, /*On fail goto*//*Label 1759*/ 77210, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 1760*/ 77163, // Rule ID 5401 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (st ZPR:{ *:[nxv2f16] }:$val, GPR64:{ *:[i64] }:$base)<><> => (ST1H_D_IMM ZPR:{ *:[nxv2f16] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1H_D_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5401, GIR_Done, // Label 1760: @77163 GIM_Try, /*On fail goto*//*Label 1761*/ 77209, // Rule ID 5404 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (st ZPR:{ *:[nxv2bf16] }:$val, GPR64:{ *:[i64] }:$base)<><> => (ST1H_D_IMM ZPR:{ *:[nxv2bf16] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1H_D_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5404, GIR_Done, // Label 1761: @77209 GIM_Reject, // Label 1759: @77210 GIM_Reject, // Label 1581: @77211 GIM_Try, /*On fail goto*//*Label 1762*/ 77276, // Rule ID 5410 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (st ZPR:{ *:[nxv2f32] }:$val, GPR64:{ *:[i64] }:$base)<><> => (ST1W_D_IMM ZPR:{ *:[nxv2f32] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1W_D_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5410, GIR_Done, // Label 1762: @77276 GIM_Reject, // Label 1582: @77277 GIM_Try, /*On fail goto*//*Label 1763*/ 77391, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 1764*/ 77344, // Rule ID 5386 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (st ZPR:{ *:[nxv2i64] }:$val, GPR64:{ *:[i64] }:$base)<><> => (ST1D_IMM ZPR:{ *:[nxv2i64] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1D_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5386, GIR_Done, // Label 1764: @77344 GIM_Try, /*On fail goto*//*Label 1765*/ 77390, // Rule ID 5413 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (st ZPR:{ *:[nxv2f64] }:$val, GPR64:{ *:[i64] }:$base)<><> => (ST1D_IMM ZPR:{ *:[nxv2f64] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1D_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5413, GIR_Done, // Label 1765: @77390 GIM_Reject, // Label 1763: @77391 GIM_Reject, // Label 1583: @77392 GIM_Try, /*On fail goto*//*Label 1766*/ 77506, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 1767*/ 77459, // Rule ID 5395 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (st ZPR:{ *:[nxv4f16] }:$val, GPR64:{ *:[i64] }:$base)<><> => (ST1H_S_IMM ZPR:{ *:[nxv4f16] }:$val, (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_S, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1H_S_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5395, GIR_Done, // Label 1767: @77459 GIM_Try, /*On fail goto*//*Label 1768*/ 77505, // Rule ID 5398 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (st ZPR:{ *:[nxv4bf16] }:$val, GPR64:{ *:[i64] }:$base)<><> => (ST1H_S_IMM ZPR:{ *:[nxv4bf16] }:$val, (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_S, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1H_S_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5398, GIR_Done, // Label 1768: @77505 GIM_Reject, // Label 1766: @77506 GIM_Reject, // Label 1584: @77507 GIM_Try, /*On fail goto*//*Label 1769*/ 77621, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 1770*/ 77574, // Rule ID 5380 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (st ZPR:{ *:[nxv4i32] }:$val, GPR64:{ *:[i64] }:$base)<><> => (ST1W_IMM ZPR:{ *:[nxv4i32] }:$val, (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_S, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1W_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5380, GIR_Done, // Label 1770: @77574 GIM_Try, /*On fail goto*//*Label 1771*/ 77620, // Rule ID 5407 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (st ZPR:{ *:[nxv4f32] }:$val, GPR64:{ *:[i64] }:$base)<><> => (ST1W_IMM ZPR:{ *:[nxv4f32] }:$val, (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_S, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1W_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5407, GIR_Done, // Label 1771: @77620 GIM_Reject, // Label 1769: @77621 GIM_Reject, // Label 1585: @77622 GIM_Try, /*On fail goto*//*Label 1772*/ 77782, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 1773*/ 77689, // Rule ID 5371 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (st ZPR:{ *:[nxv8i16] }:$val, GPR64:{ *:[i64] }:$base)<><> => (ST1H_IMM ZPR:{ *:[nxv8i16] }:$val, (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_H, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1H_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5371, GIR_Done, // Label 1773: @77689 GIM_Try, /*On fail goto*//*Label 1774*/ 77735, // Rule ID 5389 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (st ZPR:{ *:[nxv8f16] }:$val, GPR64:{ *:[i64] }:$base)<><> => (ST1H_IMM ZPR:{ *:[nxv8f16] }:$val, (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_H, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1H_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5389, GIR_Done, // Label 1774: @77735 GIM_Try, /*On fail goto*//*Label 1775*/ 77781, // Rule ID 5392 // GIM_CheckFeatures, GIFBS_HasSVEorSME, // (st ZPR:{ *:[nxv8bf16] }:$val, GPR64:{ *:[i64] }:$base)<><> => (ST1H_IMM ZPR:{ *:[nxv8bf16] }:$val, (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_H, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1H_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5392, GIR_Done, // Label 1775: @77781 GIM_Reject, // Label 1772: @77782 GIM_Reject, // Label 1586: @77783 GIM_Try, /*On fail goto*//*Label 1776*/ 77829, // Rule ID 2293 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (st PPR:{ *:[nxv16i1] }:$Val, GPR64:{ *:[i64] }:$base)<><> => (STR_PXI PPR:{ *:[nxv16i1] }:$Val, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STR_PXI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2293, GIR_Done, // Label 1776: @77829 GIM_Reject, // Label 1587: @77830 GIM_Try, /*On fail goto*//*Label 1777*/ 77895, // Rule ID 5357 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (st ZPR:{ *:[nxv16i8] }:$val, GPR64:{ *:[i64] }:$base)<><> => (ST1B_IMM ZPR:{ *:[nxv16i8] }:$val, (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::PTRUE_B, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/31, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1B_IMM, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5357, GIR_Done, // Label 1777: @77895 GIM_Reject, // Label 1588: @77896 GIM_Reject, // Label 18: @77897 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1780*/ 79341, /*GILLT_s32*//*Label 1778*/ 77905, /*GILLT_s64*//*Label 1779*/ 78991, // Label 1778: @77905 GIM_Try, /*On fail goto*//*Label 1781*/ 78990, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1782*/ 77978, // Rule ID 6772 // GIM_CheckFeatures, GIFBS_HasNoLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)<> => (CMP_SWAP_8:{ *:[i32] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CMP_SWAP_8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // desired GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6772, GIR_Done, // Label 1782: @77978 GIM_Try, /*On fail goto*//*Label 1783*/ 78041, // Rule ID 6773 // GIM_CheckFeatures, GIFBS_HasNoLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)<> => (CMP_SWAP_16:{ *:[i32] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CMP_SWAP_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // desired GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6773, GIR_Done, // Label 1783: @78041 GIM_Try, /*On fail goto*//*Label 1784*/ 78104, // Rule ID 6774 // GIM_CheckFeatures, GIFBS_HasNoLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)<> => (CMP_SWAP_32:{ *:[i32] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CMP_SWAP_32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // desired GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6774, GIR_Done, // Label 1784: @78104 GIM_Try, /*On fail goto*//*Label 1785*/ 78163, // Rule ID 10454 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10454, GIR_Done, // Label 1785: @78163 GIM_Try, /*On fail goto*//*Label 1786*/ 78222, // Rule ID 10455 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10455, GIR_Done, // Label 1786: @78222 GIM_Try, /*On fail goto*//*Label 1787*/ 78281, // Rule ID 10456 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10456, GIR_Done, // Label 1787: @78281 GIM_Try, /*On fail goto*//*Label 1788*/ 78340, // Rule ID 10457 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10457, GIR_Done, // Label 1788: @78340 GIM_Try, /*On fail goto*//*Label 1789*/ 78399, // Rule ID 10458 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10458, GIR_Done, // Label 1789: @78399 GIM_Try, /*On fail goto*//*Label 1790*/ 78458, // Rule ID 10459 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10459, GIR_Done, // Label 1790: @78458 GIM_Try, /*On fail goto*//*Label 1791*/ 78517, // Rule ID 10460 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10460, GIR_Done, // Label 1791: @78517 GIM_Try, /*On fail goto*//*Label 1792*/ 78576, // Rule ID 10461 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10461, GIR_Done, // Label 1792: @78576 GIM_Try, /*On fail goto*//*Label 1793*/ 78635, // Rule ID 10462 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10462, GIR_Done, // Label 1793: @78635 GIM_Try, /*On fail goto*//*Label 1794*/ 78694, // Rule ID 10463 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10463, GIR_Done, // Label 1794: @78694 GIM_Try, /*On fail goto*//*Label 1795*/ 78753, // Rule ID 10464 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10464, GIR_Done, // Label 1795: @78753 GIM_Try, /*On fail goto*//*Label 1796*/ 78812, // Rule ID 10465 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10465, GIR_Done, // Label 1796: @78812 GIM_Try, /*On fail goto*//*Label 1797*/ 78871, // Rule ID 10466 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10466, GIR_Done, // Label 1797: @78871 GIM_Try, /*On fail goto*//*Label 1798*/ 78930, // Rule ID 10467 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10467, GIR_Done, // Label 1798: @78930 GIM_Try, /*On fail goto*//*Label 1799*/ 78989, // Rule ID 10468 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10468, GIR_Done, // Label 1799: @78989 GIM_Reject, // Label 1781: @78990 GIM_Reject, // Label 1779: @78991 GIM_Try, /*On fail goto*//*Label 1800*/ 79340, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1801*/ 79064, // Rule ID 6775 // GIM_CheckFeatures, GIFBS_HasNoLSE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (atomic_cmp_swap:{ *:[i64] } GPR64:{ *:[i64] }:$addr, GPR64:{ *:[i64] }:$desired, GPR64:{ *:[i64] }:$new)<> => (CMP_SWAP_64:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR64:{ *:[i64] }:$desired, GPR64:{ *:[i64] }:$new) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CMP_SWAP_64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // desired GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6775, GIR_Done, // Label 1801: @79064 GIM_Try, /*On fail goto*//*Label 1802*/ 79119, // Rule ID 6878 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<><> => (CASX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6878, GIR_Done, // Label 1802: @79119 GIM_Try, /*On fail goto*//*Label 1803*/ 79174, // Rule ID 6879 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<><> => (CASAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6879, GIR_Done, // Label 1803: @79174 GIM_Try, /*On fail goto*//*Label 1804*/ 79229, // Rule ID 6880 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<><> => (CASLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6880, GIR_Done, // Label 1804: @79229 GIM_Try, /*On fail goto*//*Label 1805*/ 79284, // Rule ID 6881 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<><> => (CASALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6881, GIR_Done, // Label 1805: @79284 GIM_Try, /*On fail goto*//*Label 1806*/ 79339, // Rule ID 6882 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<><> => (CASALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6882, GIR_Done, // Label 1806: @79339 GIM_Reject, // Label 1800: @79340 GIM_Reject, // Label 1780: @79341 GIM_Reject, // Label 19: @79342 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1809*/ 80370, /*GILLT_s32*//*Label 1807*/ 79350, /*GILLT_s64*//*Label 1808*/ 80123, // Label 1807: @79350 GIM_Try, /*On fail goto*//*Label 1810*/ 80122, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1811*/ 79407, // Rule ID 10439 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10439, GIR_Done, // Label 1811: @79407 GIM_Try, /*On fail goto*//*Label 1812*/ 79458, // Rule ID 10440 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10440, GIR_Done, // Label 1812: @79458 GIM_Try, /*On fail goto*//*Label 1813*/ 79509, // Rule ID 10441 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10441, GIR_Done, // Label 1813: @79509 GIM_Try, /*On fail goto*//*Label 1814*/ 79560, // Rule ID 10442 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10442, GIR_Done, // Label 1814: @79560 GIM_Try, /*On fail goto*//*Label 1815*/ 79611, // Rule ID 10443 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10443, GIR_Done, // Label 1815: @79611 GIM_Try, /*On fail goto*//*Label 1816*/ 79662, // Rule ID 10444 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10444, GIR_Done, // Label 1816: @79662 GIM_Try, /*On fail goto*//*Label 1817*/ 79713, // Rule ID 10445 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10445, GIR_Done, // Label 1817: @79713 GIM_Try, /*On fail goto*//*Label 1818*/ 79764, // Rule ID 10446 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10446, GIR_Done, // Label 1818: @79764 GIM_Try, /*On fail goto*//*Label 1819*/ 79815, // Rule ID 10447 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10447, GIR_Done, // Label 1819: @79815 GIM_Try, /*On fail goto*//*Label 1820*/ 79866, // Rule ID 10448 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10448, GIR_Done, // Label 1820: @79866 GIM_Try, /*On fail goto*//*Label 1821*/ 79917, // Rule ID 10449 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10449, GIR_Done, // Label 1821: @79917 GIM_Try, /*On fail goto*//*Label 1822*/ 79968, // Rule ID 10450 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10450, GIR_Done, // Label 1822: @79968 GIM_Try, /*On fail goto*//*Label 1823*/ 80019, // Rule ID 10451 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10451, GIR_Done, // Label 1823: @80019 GIM_Try, /*On fail goto*//*Label 1824*/ 80070, // Rule ID 10452 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10452, GIR_Done, // Label 1824: @80070 GIM_Try, /*On fail goto*//*Label 1825*/ 80121, // Rule ID 10453 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10453, GIR_Done, // Label 1825: @80121 GIM_Reject, // Label 1810: @80122 GIM_Reject, // Label 1808: @80123 GIM_Try, /*On fail goto*//*Label 1826*/ 80369, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1827*/ 80180, // Rule ID 10434 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (SWPX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10434, GIR_Done, // Label 1827: @80180 GIM_Try, /*On fail goto*//*Label 1828*/ 80227, // Rule ID 10435 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (SWPAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10435, GIR_Done, // Label 1828: @80227 GIM_Try, /*On fail goto*//*Label 1829*/ 80274, // Rule ID 10436 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (SWPLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10436, GIR_Done, // Label 1829: @80274 GIM_Try, /*On fail goto*//*Label 1830*/ 80321, // Rule ID 10437 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (SWPALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10437, GIR_Done, // Label 1830: @80321 GIM_Try, /*On fail goto*//*Label 1831*/ 80368, // Rule ID 10438 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (SWPALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10438, GIR_Done, // Label 1831: @80368 GIM_Reject, // Label 1826: @80369 GIM_Reject, // Label 1809: @80370 GIM_Reject, // Label 20: @80371 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1834*/ 81399, /*GILLT_s32*//*Label 1832*/ 80379, /*GILLT_s64*//*Label 1833*/ 81152, // Label 1832: @80379 GIM_Try, /*On fail goto*//*Label 1835*/ 81151, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1836*/ 80436, // Rule ID 10279 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10279, GIR_Done, // Label 1836: @80436 GIM_Try, /*On fail goto*//*Label 1837*/ 80487, // Rule ID 10280 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10280, GIR_Done, // Label 1837: @80487 GIM_Try, /*On fail goto*//*Label 1838*/ 80538, // Rule ID 10281 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10281, GIR_Done, // Label 1838: @80538 GIM_Try, /*On fail goto*//*Label 1839*/ 80589, // Rule ID 10282 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10282, GIR_Done, // Label 1839: @80589 GIM_Try, /*On fail goto*//*Label 1840*/ 80640, // Rule ID 10283 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10283, GIR_Done, // Label 1840: @80640 GIM_Try, /*On fail goto*//*Label 1841*/ 80691, // Rule ID 10284 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10284, GIR_Done, // Label 1841: @80691 GIM_Try, /*On fail goto*//*Label 1842*/ 80742, // Rule ID 10285 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10285, GIR_Done, // Label 1842: @80742 GIM_Try, /*On fail goto*//*Label 1843*/ 80793, // Rule ID 10286 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10286, GIR_Done, // Label 1843: @80793 GIM_Try, /*On fail goto*//*Label 1844*/ 80844, // Rule ID 10287 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10287, GIR_Done, // Label 1844: @80844 GIM_Try, /*On fail goto*//*Label 1845*/ 80895, // Rule ID 10288 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10288, GIR_Done, // Label 1845: @80895 GIM_Try, /*On fail goto*//*Label 1846*/ 80946, // Rule ID 10289 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10289, GIR_Done, // Label 1846: @80946 GIM_Try, /*On fail goto*//*Label 1847*/ 80997, // Rule ID 10290 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10290, GIR_Done, // Label 1847: @80997 GIM_Try, /*On fail goto*//*Label 1848*/ 81048, // Rule ID 10291 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10291, GIR_Done, // Label 1848: @81048 GIM_Try, /*On fail goto*//*Label 1849*/ 81099, // Rule ID 10292 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10292, GIR_Done, // Label 1849: @81099 GIM_Try, /*On fail goto*//*Label 1850*/ 81150, // Rule ID 10293 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10293, GIR_Done, // Label 1850: @81150 GIM_Reject, // Label 1835: @81151 GIM_Reject, // Label 1833: @81152 GIM_Try, /*On fail goto*//*Label 1851*/ 81398, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1852*/ 81209, // Rule ID 6873 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6873, GIR_Done, // Label 1852: @81209 GIM_Try, /*On fail goto*//*Label 1853*/ 81256, // Rule ID 6874 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6874, GIR_Done, // Label 1853: @81256 GIM_Try, /*On fail goto*//*Label 1854*/ 81303, // Rule ID 6875 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6875, GIR_Done, // Label 1854: @81303 GIM_Try, /*On fail goto*//*Label 1855*/ 81350, // Rule ID 6876 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6876, GIR_Done, // Label 1855: @81350 GIM_Try, /*On fail goto*//*Label 1856*/ 81397, // Rule ID 6877 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6877, GIR_Done, // Label 1856: @81397 GIM_Reject, // Label 1851: @81398 GIM_Reject, // Label 1834: @81399 GIM_Reject, // Label 21: @81400 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1859*/ 82828, /*GILLT_s32*//*Label 1857*/ 81408, /*GILLT_s64*//*Label 1858*/ 82481, // Label 1857: @81408 GIM_Try, /*On fail goto*//*Label 1860*/ 82480, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1861*/ 81485, // Rule ID 10474 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10474, GIR_Done, // Label 1861: @81485 GIM_Try, /*On fail goto*//*Label 1862*/ 81556, // Rule ID 10475 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDAW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10475, GIR_Done, // Label 1862: @81556 GIM_Try, /*On fail goto*//*Label 1863*/ 81627, // Rule ID 10476 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDLW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10476, GIR_Done, // Label 1863: @81627 GIM_Try, /*On fail goto*//*Label 1864*/ 81698, // Rule ID 10477 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10477, GIR_Done, // Label 1864: @81698 GIM_Try, /*On fail goto*//*Label 1865*/ 81769, // Rule ID 10478 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10478, GIR_Done, // Label 1865: @81769 GIM_Try, /*On fail goto*//*Label 1866*/ 81840, // Rule ID 10479 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10479, GIR_Done, // Label 1866: @81840 GIM_Try, /*On fail goto*//*Label 1867*/ 81911, // Rule ID 10480 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDAH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10480, GIR_Done, // Label 1867: @81911 GIM_Try, /*On fail goto*//*Label 1868*/ 81982, // Rule ID 10481 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDLH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10481, GIR_Done, // Label 1868: @81982 GIM_Try, /*On fail goto*//*Label 1869*/ 82053, // Rule ID 10482 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10482, GIR_Done, // Label 1869: @82053 GIM_Try, /*On fail goto*//*Label 1870*/ 82124, // Rule ID 10483 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10483, GIR_Done, // Label 1870: @82124 GIM_Try, /*On fail goto*//*Label 1871*/ 82195, // Rule ID 10484 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10484, GIR_Done, // Label 1871: @82195 GIM_Try, /*On fail goto*//*Label 1872*/ 82266, // Rule ID 10485 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDAB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10485, GIR_Done, // Label 1872: @82266 GIM_Try, /*On fail goto*//*Label 1873*/ 82337, // Rule ID 10486 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDLB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10486, GIR_Done, // Label 1873: @82337 GIM_Try, /*On fail goto*//*Label 1874*/ 82408, // Rule ID 10487 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10487, GIR_Done, // Label 1874: @82408 GIM_Try, /*On fail goto*//*Label 1875*/ 82479, // Rule ID 10488 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10488, GIR_Done, // Label 1875: @82479 GIM_Reject, // Label 1860: @82480 GIM_Reject, // Label 1858: @82481 GIM_Try, /*On fail goto*//*Label 1876*/ 82827, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1877*/ 82558, // Rule ID 10469 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10469, GIR_Done, // Label 1877: @82558 GIM_Try, /*On fail goto*//*Label 1878*/ 82625, // Rule ID 10470 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDAX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10470, GIR_Done, // Label 1878: @82625 GIM_Try, /*On fail goto*//*Label 1879*/ 82692, // Rule ID 10471 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDLX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10471, GIR_Done, // Label 1879: @82692 GIM_Try, /*On fail goto*//*Label 1880*/ 82759, // Rule ID 10472 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDALX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10472, GIR_Done, // Label 1880: @82759 GIM_Try, /*On fail goto*//*Label 1881*/ 82826, // Rule ID 10473 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDALX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10473, GIR_Done, // Label 1881: @82826 GIM_Reject, // Label 1876: @82827 GIM_Reject, // Label 1859: @82828 GIM_Reject, // Label 22: @82829 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1884*/ 84257, /*GILLT_s32*//*Label 1882*/ 82837, /*GILLT_s64*//*Label 1883*/ 83910, // Label 1882: @82837 GIM_Try, /*On fail goto*//*Label 1885*/ 83909, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1886*/ 82914, // Rule ID 10494 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10494, GIR_Done, // Label 1886: @82914 GIM_Try, /*On fail goto*//*Label 1887*/ 82985, // Rule ID 10495 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRAW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10495, GIR_Done, // Label 1887: @82985 GIM_Try, /*On fail goto*//*Label 1888*/ 83056, // Rule ID 10496 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRLW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10496, GIR_Done, // Label 1888: @83056 GIM_Try, /*On fail goto*//*Label 1889*/ 83127, // Rule ID 10497 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRALW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10497, GIR_Done, // Label 1889: @83127 GIM_Try, /*On fail goto*//*Label 1890*/ 83198, // Rule ID 10498 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRALW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10498, GIR_Done, // Label 1890: @83198 GIM_Try, /*On fail goto*//*Label 1891*/ 83269, // Rule ID 10499 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10499, GIR_Done, // Label 1891: @83269 GIM_Try, /*On fail goto*//*Label 1892*/ 83340, // Rule ID 10500 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRAH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10500, GIR_Done, // Label 1892: @83340 GIM_Try, /*On fail goto*//*Label 1893*/ 83411, // Rule ID 10501 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRLH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10501, GIR_Done, // Label 1893: @83411 GIM_Try, /*On fail goto*//*Label 1894*/ 83482, // Rule ID 10502 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRALH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10502, GIR_Done, // Label 1894: @83482 GIM_Try, /*On fail goto*//*Label 1895*/ 83553, // Rule ID 10503 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRALH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10503, GIR_Done, // Label 1895: @83553 GIM_Try, /*On fail goto*//*Label 1896*/ 83624, // Rule ID 10504 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10504, GIR_Done, // Label 1896: @83624 GIM_Try, /*On fail goto*//*Label 1897*/ 83695, // Rule ID 10505 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRAB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10505, GIR_Done, // Label 1897: @83695 GIM_Try, /*On fail goto*//*Label 1898*/ 83766, // Rule ID 10506 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRLB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10506, GIR_Done, // Label 1898: @83766 GIM_Try, /*On fail goto*//*Label 1899*/ 83837, // Rule ID 10507 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRALB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10507, GIR_Done, // Label 1899: @83837 GIM_Try, /*On fail goto*//*Label 1900*/ 83908, // Rule ID 10508 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRALB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10508, GIR_Done, // Label 1900: @83908 GIM_Reject, // Label 1885: @83909 GIM_Reject, // Label 1883: @83910 GIM_Try, /*On fail goto*//*Label 1901*/ 84256, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1902*/ 83987, // Rule ID 10489 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDCLRX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10489, GIR_Done, // Label 1902: @83987 GIM_Try, /*On fail goto*//*Label 1903*/ 84054, // Rule ID 10490 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDCLRAX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10490, GIR_Done, // Label 1903: @84054 GIM_Try, /*On fail goto*//*Label 1904*/ 84121, // Rule ID 10491 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDCLRLX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10491, GIR_Done, // Label 1904: @84121 GIM_Try, /*On fail goto*//*Label 1905*/ 84188, // Rule ID 10492 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDCLRALX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10492, GIR_Done, // Label 1905: @84188 GIM_Try, /*On fail goto*//*Label 1906*/ 84255, // Rule ID 10493 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDCLRALX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10493, GIR_Done, // Label 1906: @84255 GIM_Reject, // Label 1901: @84256 GIM_Reject, // Label 1884: @84257 GIM_Reject, // Label 23: @84258 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1909*/ 85286, /*GILLT_s32*//*Label 1907*/ 84266, /*GILLT_s64*//*Label 1908*/ 85039, // Label 1907: @84266 GIM_Try, /*On fail goto*//*Label 1910*/ 85038, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1911*/ 84323, // Rule ID 10299 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10299, GIR_Done, // Label 1911: @84323 GIM_Try, /*On fail goto*//*Label 1912*/ 84374, // Rule ID 10300 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10300, GIR_Done, // Label 1912: @84374 GIM_Try, /*On fail goto*//*Label 1913*/ 84425, // Rule ID 10301 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10301, GIR_Done, // Label 1913: @84425 GIM_Try, /*On fail goto*//*Label 1914*/ 84476, // Rule ID 10302 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10302, GIR_Done, // Label 1914: @84476 GIM_Try, /*On fail goto*//*Label 1915*/ 84527, // Rule ID 10303 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10303, GIR_Done, // Label 1915: @84527 GIM_Try, /*On fail goto*//*Label 1916*/ 84578, // Rule ID 10304 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10304, GIR_Done, // Label 1916: @84578 GIM_Try, /*On fail goto*//*Label 1917*/ 84629, // Rule ID 10305 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10305, GIR_Done, // Label 1917: @84629 GIM_Try, /*On fail goto*//*Label 1918*/ 84680, // Rule ID 10306 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10306, GIR_Done, // Label 1918: @84680 GIM_Try, /*On fail goto*//*Label 1919*/ 84731, // Rule ID 10307 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10307, GIR_Done, // Label 1919: @84731 GIM_Try, /*On fail goto*//*Label 1920*/ 84782, // Rule ID 10308 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10308, GIR_Done, // Label 1920: @84782 GIM_Try, /*On fail goto*//*Label 1921*/ 84833, // Rule ID 10309 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10309, GIR_Done, // Label 1921: @84833 GIM_Try, /*On fail goto*//*Label 1922*/ 84884, // Rule ID 10310 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10310, GIR_Done, // Label 1922: @84884 GIM_Try, /*On fail goto*//*Label 1923*/ 84935, // Rule ID 10311 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10311, GIR_Done, // Label 1923: @84935 GIM_Try, /*On fail goto*//*Label 1924*/ 84986, // Rule ID 10312 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10312, GIR_Done, // Label 1924: @84986 GIM_Try, /*On fail goto*//*Label 1925*/ 85037, // Rule ID 10313 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10313, GIR_Done, // Label 1925: @85037 GIM_Reject, // Label 1910: @85038 GIM_Reject, // Label 1908: @85039 GIM_Try, /*On fail goto*//*Label 1926*/ 85285, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1927*/ 85096, // Rule ID 10294 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSETX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10294, GIR_Done, // Label 1927: @85096 GIM_Try, /*On fail goto*//*Label 1928*/ 85143, // Rule ID 10295 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSETAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10295, GIR_Done, // Label 1928: @85143 GIM_Try, /*On fail goto*//*Label 1929*/ 85190, // Rule ID 10296 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSETLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10296, GIR_Done, // Label 1929: @85190 GIM_Try, /*On fail goto*//*Label 1930*/ 85237, // Rule ID 10297 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSETALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10297, GIR_Done, // Label 1930: @85237 GIM_Try, /*On fail goto*//*Label 1931*/ 85284, // Rule ID 10298 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSETALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10298, GIR_Done, // Label 1931: @85284 GIM_Reject, // Label 1926: @85285 GIM_Reject, // Label 1909: @85286 GIM_Reject, // Label 24: @85287 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1934*/ 86315, /*GILLT_s32*//*Label 1932*/ 85295, /*GILLT_s64*//*Label 1933*/ 86068, // Label 1932: @85295 GIM_Try, /*On fail goto*//*Label 1935*/ 86067, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1936*/ 85352, // Rule ID 10319 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10319, GIR_Done, // Label 1936: @85352 GIM_Try, /*On fail goto*//*Label 1937*/ 85403, // Rule ID 10320 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10320, GIR_Done, // Label 1937: @85403 GIM_Try, /*On fail goto*//*Label 1938*/ 85454, // Rule ID 10321 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10321, GIR_Done, // Label 1938: @85454 GIM_Try, /*On fail goto*//*Label 1939*/ 85505, // Rule ID 10322 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10322, GIR_Done, // Label 1939: @85505 GIM_Try, /*On fail goto*//*Label 1940*/ 85556, // Rule ID 10323 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10323, GIR_Done, // Label 1940: @85556 GIM_Try, /*On fail goto*//*Label 1941*/ 85607, // Rule ID 10324 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10324, GIR_Done, // Label 1941: @85607 GIM_Try, /*On fail goto*//*Label 1942*/ 85658, // Rule ID 10325 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10325, GIR_Done, // Label 1942: @85658 GIM_Try, /*On fail goto*//*Label 1943*/ 85709, // Rule ID 10326 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10326, GIR_Done, // Label 1943: @85709 GIM_Try, /*On fail goto*//*Label 1944*/ 85760, // Rule ID 10327 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10327, GIR_Done, // Label 1944: @85760 GIM_Try, /*On fail goto*//*Label 1945*/ 85811, // Rule ID 10328 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10328, GIR_Done, // Label 1945: @85811 GIM_Try, /*On fail goto*//*Label 1946*/ 85862, // Rule ID 10329 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10329, GIR_Done, // Label 1946: @85862 GIM_Try, /*On fail goto*//*Label 1947*/ 85913, // Rule ID 10330 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10330, GIR_Done, // Label 1947: @85913 GIM_Try, /*On fail goto*//*Label 1948*/ 85964, // Rule ID 10331 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10331, GIR_Done, // Label 1948: @85964 GIM_Try, /*On fail goto*//*Label 1949*/ 86015, // Rule ID 10332 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10332, GIR_Done, // Label 1949: @86015 GIM_Try, /*On fail goto*//*Label 1950*/ 86066, // Rule ID 10333 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10333, GIR_Done, // Label 1950: @86066 GIM_Reject, // Label 1935: @86067 GIM_Reject, // Label 1933: @86068 GIM_Try, /*On fail goto*//*Label 1951*/ 86314, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1952*/ 86125, // Rule ID 10314 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDEORX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10314, GIR_Done, // Label 1952: @86125 GIM_Try, /*On fail goto*//*Label 1953*/ 86172, // Rule ID 10315 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDEORAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10315, GIR_Done, // Label 1953: @86172 GIM_Try, /*On fail goto*//*Label 1954*/ 86219, // Rule ID 10316 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDEORLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10316, GIR_Done, // Label 1954: @86219 GIM_Try, /*On fail goto*//*Label 1955*/ 86266, // Rule ID 10317 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDEORALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10317, GIR_Done, // Label 1955: @86266 GIM_Try, /*On fail goto*//*Label 1956*/ 86313, // Rule ID 10318 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDEORALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10318, GIR_Done, // Label 1956: @86313 GIM_Reject, // Label 1951: @86314 GIM_Reject, // Label 1934: @86315 GIM_Reject, // Label 25: @86316 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1959*/ 87344, /*GILLT_s32*//*Label 1957*/ 86324, /*GILLT_s64*//*Label 1958*/ 87097, // Label 1957: @86324 GIM_Try, /*On fail goto*//*Label 1960*/ 87096, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1961*/ 86381, // Rule ID 10359 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10359, GIR_Done, // Label 1961: @86381 GIM_Try, /*On fail goto*//*Label 1962*/ 86432, // Rule ID 10360 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10360, GIR_Done, // Label 1962: @86432 GIM_Try, /*On fail goto*//*Label 1963*/ 86483, // Rule ID 10361 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10361, GIR_Done, // Label 1963: @86483 GIM_Try, /*On fail goto*//*Label 1964*/ 86534, // Rule ID 10362 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10362, GIR_Done, // Label 1964: @86534 GIM_Try, /*On fail goto*//*Label 1965*/ 86585, // Rule ID 10363 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10363, GIR_Done, // Label 1965: @86585 GIM_Try, /*On fail goto*//*Label 1966*/ 86636, // Rule ID 10364 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10364, GIR_Done, // Label 1966: @86636 GIM_Try, /*On fail goto*//*Label 1967*/ 86687, // Rule ID 10365 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10365, GIR_Done, // Label 1967: @86687 GIM_Try, /*On fail goto*//*Label 1968*/ 86738, // Rule ID 10366 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10366, GIR_Done, // Label 1968: @86738 GIM_Try, /*On fail goto*//*Label 1969*/ 86789, // Rule ID 10367 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10367, GIR_Done, // Label 1969: @86789 GIM_Try, /*On fail goto*//*Label 1970*/ 86840, // Rule ID 10368 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10368, GIR_Done, // Label 1970: @86840 GIM_Try, /*On fail goto*//*Label 1971*/ 86891, // Rule ID 10369 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10369, GIR_Done, // Label 1971: @86891 GIM_Try, /*On fail goto*//*Label 1972*/ 86942, // Rule ID 10370 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10370, GIR_Done, // Label 1972: @86942 GIM_Try, /*On fail goto*//*Label 1973*/ 86993, // Rule ID 10371 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10371, GIR_Done, // Label 1973: @86993 GIM_Try, /*On fail goto*//*Label 1974*/ 87044, // Rule ID 10372 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10372, GIR_Done, // Label 1974: @87044 GIM_Try, /*On fail goto*//*Label 1975*/ 87095, // Rule ID 10373 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10373, GIR_Done, // Label 1975: @87095 GIM_Reject, // Label 1960: @87096 GIM_Reject, // Label 1958: @87097 GIM_Try, /*On fail goto*//*Label 1976*/ 87343, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1977*/ 87154, // Rule ID 10354 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMAXX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10354, GIR_Done, // Label 1977: @87154 GIM_Try, /*On fail goto*//*Label 1978*/ 87201, // Rule ID 10355 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMAXAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10355, GIR_Done, // Label 1978: @87201 GIM_Try, /*On fail goto*//*Label 1979*/ 87248, // Rule ID 10356 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMAXLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10356, GIR_Done, // Label 1979: @87248 GIM_Try, /*On fail goto*//*Label 1980*/ 87295, // Rule ID 10357 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10357, GIR_Done, // Label 1980: @87295 GIM_Try, /*On fail goto*//*Label 1981*/ 87342, // Rule ID 10358 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10358, GIR_Done, // Label 1981: @87342 GIM_Reject, // Label 1976: @87343 GIM_Reject, // Label 1959: @87344 GIM_Reject, // Label 26: @87345 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1984*/ 88373, /*GILLT_s32*//*Label 1982*/ 87353, /*GILLT_s64*//*Label 1983*/ 88126, // Label 1982: @87353 GIM_Try, /*On fail goto*//*Label 1985*/ 88125, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1986*/ 87410, // Rule ID 10379 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10379, GIR_Done, // Label 1986: @87410 GIM_Try, /*On fail goto*//*Label 1987*/ 87461, // Rule ID 10380 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10380, GIR_Done, // Label 1987: @87461 GIM_Try, /*On fail goto*//*Label 1988*/ 87512, // Rule ID 10381 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10381, GIR_Done, // Label 1988: @87512 GIM_Try, /*On fail goto*//*Label 1989*/ 87563, // Rule ID 10382 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10382, GIR_Done, // Label 1989: @87563 GIM_Try, /*On fail goto*//*Label 1990*/ 87614, // Rule ID 10383 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10383, GIR_Done, // Label 1990: @87614 GIM_Try, /*On fail goto*//*Label 1991*/ 87665, // Rule ID 10384 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10384, GIR_Done, // Label 1991: @87665 GIM_Try, /*On fail goto*//*Label 1992*/ 87716, // Rule ID 10385 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10385, GIR_Done, // Label 1992: @87716 GIM_Try, /*On fail goto*//*Label 1993*/ 87767, // Rule ID 10386 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10386, GIR_Done, // Label 1993: @87767 GIM_Try, /*On fail goto*//*Label 1994*/ 87818, // Rule ID 10387 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10387, GIR_Done, // Label 1994: @87818 GIM_Try, /*On fail goto*//*Label 1995*/ 87869, // Rule ID 10388 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10388, GIR_Done, // Label 1995: @87869 GIM_Try, /*On fail goto*//*Label 1996*/ 87920, // Rule ID 10389 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10389, GIR_Done, // Label 1996: @87920 GIM_Try, /*On fail goto*//*Label 1997*/ 87971, // Rule ID 10390 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10390, GIR_Done, // Label 1997: @87971 GIM_Try, /*On fail goto*//*Label 1998*/ 88022, // Rule ID 10391 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10391, GIR_Done, // Label 1998: @88022 GIM_Try, /*On fail goto*//*Label 1999*/ 88073, // Rule ID 10392 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10392, GIR_Done, // Label 1999: @88073 GIM_Try, /*On fail goto*//*Label 2000*/ 88124, // Rule ID 10393 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10393, GIR_Done, // Label 2000: @88124 GIM_Reject, // Label 1985: @88125 GIM_Reject, // Label 1983: @88126 GIM_Try, /*On fail goto*//*Label 2001*/ 88372, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 2002*/ 88183, // Rule ID 10374 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMINX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10374, GIR_Done, // Label 2002: @88183 GIM_Try, /*On fail goto*//*Label 2003*/ 88230, // Rule ID 10375 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMINAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10375, GIR_Done, // Label 2003: @88230 GIM_Try, /*On fail goto*//*Label 2004*/ 88277, // Rule ID 10376 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMINLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10376, GIR_Done, // Label 2004: @88277 GIM_Try, /*On fail goto*//*Label 2005*/ 88324, // Rule ID 10377 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10377, GIR_Done, // Label 2005: @88324 GIM_Try, /*On fail goto*//*Label 2006*/ 88371, // Rule ID 10378 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10378, GIR_Done, // Label 2006: @88371 GIM_Reject, // Label 2001: @88372 GIM_Reject, // Label 1984: @88373 GIM_Reject, // Label 27: @88374 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2009*/ 89402, /*GILLT_s32*//*Label 2007*/ 88382, /*GILLT_s64*//*Label 2008*/ 89155, // Label 2007: @88382 GIM_Try, /*On fail goto*//*Label 2010*/ 89154, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 2011*/ 88439, // Rule ID 10399 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10399, GIR_Done, // Label 2011: @88439 GIM_Try, /*On fail goto*//*Label 2012*/ 88490, // Rule ID 10400 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10400, GIR_Done, // Label 2012: @88490 GIM_Try, /*On fail goto*//*Label 2013*/ 88541, // Rule ID 10401 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10401, GIR_Done, // Label 2013: @88541 GIM_Try, /*On fail goto*//*Label 2014*/ 88592, // Rule ID 10402 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10402, GIR_Done, // Label 2014: @88592 GIM_Try, /*On fail goto*//*Label 2015*/ 88643, // Rule ID 10403 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10403, GIR_Done, // Label 2015: @88643 GIM_Try, /*On fail goto*//*Label 2016*/ 88694, // Rule ID 10404 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10404, GIR_Done, // Label 2016: @88694 GIM_Try, /*On fail goto*//*Label 2017*/ 88745, // Rule ID 10405 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10405, GIR_Done, // Label 2017: @88745 GIM_Try, /*On fail goto*//*Label 2018*/ 88796, // Rule ID 10406 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10406, GIR_Done, // Label 2018: @88796 GIM_Try, /*On fail goto*//*Label 2019*/ 88847, // Rule ID 10407 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10407, GIR_Done, // Label 2019: @88847 GIM_Try, /*On fail goto*//*Label 2020*/ 88898, // Rule ID 10408 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10408, GIR_Done, // Label 2020: @88898 GIM_Try, /*On fail goto*//*Label 2021*/ 88949, // Rule ID 10409 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10409, GIR_Done, // Label 2021: @88949 GIM_Try, /*On fail goto*//*Label 2022*/ 89000, // Rule ID 10410 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10410, GIR_Done, // Label 2022: @89000 GIM_Try, /*On fail goto*//*Label 2023*/ 89051, // Rule ID 10411 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10411, GIR_Done, // Label 2023: @89051 GIM_Try, /*On fail goto*//*Label 2024*/ 89102, // Rule ID 10412 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10412, GIR_Done, // Label 2024: @89102 GIM_Try, /*On fail goto*//*Label 2025*/ 89153, // Rule ID 10413 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10413, GIR_Done, // Label 2025: @89153 GIM_Reject, // Label 2010: @89154 GIM_Reject, // Label 2008: @89155 GIM_Try, /*On fail goto*//*Label 2026*/ 89401, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 2027*/ 89212, // Rule ID 10394 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMAXX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10394, GIR_Done, // Label 2027: @89212 GIM_Try, /*On fail goto*//*Label 2028*/ 89259, // Rule ID 10395 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMAXAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10395, GIR_Done, // Label 2028: @89259 GIM_Try, /*On fail goto*//*Label 2029*/ 89306, // Rule ID 10396 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMAXLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10396, GIR_Done, // Label 2029: @89306 GIM_Try, /*On fail goto*//*Label 2030*/ 89353, // Rule ID 10397 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10397, GIR_Done, // Label 2030: @89353 GIM_Try, /*On fail goto*//*Label 2031*/ 89400, // Rule ID 10398 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10398, GIR_Done, // Label 2031: @89400 GIM_Reject, // Label 2026: @89401 GIM_Reject, // Label 2009: @89402 GIM_Reject, // Label 28: @89403 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2034*/ 90431, /*GILLT_s32*//*Label 2032*/ 89411, /*GILLT_s64*//*Label 2033*/ 90184, // Label 2032: @89411 GIM_Try, /*On fail goto*//*Label 2035*/ 90183, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 2036*/ 89468, // Rule ID 10419 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10419, GIR_Done, // Label 2036: @89468 GIM_Try, /*On fail goto*//*Label 2037*/ 89519, // Rule ID 10420 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10420, GIR_Done, // Label 2037: @89519 GIM_Try, /*On fail goto*//*Label 2038*/ 89570, // Rule ID 10421 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10421, GIR_Done, // Label 2038: @89570 GIM_Try, /*On fail goto*//*Label 2039*/ 89621, // Rule ID 10422 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10422, GIR_Done, // Label 2039: @89621 GIM_Try, /*On fail goto*//*Label 2040*/ 89672, // Rule ID 10423 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10423, GIR_Done, // Label 2040: @89672 GIM_Try, /*On fail goto*//*Label 2041*/ 89723, // Rule ID 10424 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10424, GIR_Done, // Label 2041: @89723 GIM_Try, /*On fail goto*//*Label 2042*/ 89774, // Rule ID 10425 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10425, GIR_Done, // Label 2042: @89774 GIM_Try, /*On fail goto*//*Label 2043*/ 89825, // Rule ID 10426 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10426, GIR_Done, // Label 2043: @89825 GIM_Try, /*On fail goto*//*Label 2044*/ 89876, // Rule ID 10427 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10427, GIR_Done, // Label 2044: @89876 GIM_Try, /*On fail goto*//*Label 2045*/ 89927, // Rule ID 10428 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10428, GIR_Done, // Label 2045: @89927 GIM_Try, /*On fail goto*//*Label 2046*/ 89978, // Rule ID 10429 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10429, GIR_Done, // Label 2046: @89978 GIM_Try, /*On fail goto*//*Label 2047*/ 90029, // Rule ID 10430 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10430, GIR_Done, // Label 2047: @90029 GIM_Try, /*On fail goto*//*Label 2048*/ 90080, // Rule ID 10431 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10431, GIR_Done, // Label 2048: @90080 GIM_Try, /*On fail goto*//*Label 2049*/ 90131, // Rule ID 10432 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10432, GIR_Done, // Label 2049: @90131 GIM_Try, /*On fail goto*//*Label 2050*/ 90182, // Rule ID 10433 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10433, GIR_Done, // Label 2050: @90182 GIM_Reject, // Label 2035: @90183 GIM_Reject, // Label 2033: @90184 GIM_Try, /*On fail goto*//*Label 2051*/ 90430, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 2052*/ 90241, // Rule ID 10414 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMINX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10414, GIR_Done, // Label 2052: @90241 GIM_Try, /*On fail goto*//*Label 2053*/ 90288, // Rule ID 10415 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMINAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10415, GIR_Done, // Label 2053: @90288 GIM_Try, /*On fail goto*//*Label 2054*/ 90335, // Rule ID 10416 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMINLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10416, GIR_Done, // Label 2054: @90335 GIM_Try, /*On fail goto*//*Label 2055*/ 90382, // Rule ID 10417 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10417, GIR_Done, // Label 2055: @90382 GIM_Try, /*On fail goto*//*Label 2056*/ 90429, // Rule ID 10418 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10418, GIR_Done, // Label 2056: @90429 GIM_Reject, // Label 2051: @90430 GIM_Reject, // Label 2034: @90431 GIM_Reject, // Label 29: @90432 GIM_Try, /*On fail goto*//*Label 2057*/ 90460, // Rule ID 10166 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 4, // MIs[0] Operand 1 GIM_CheckIsImm, /*MI*/0, /*Op*/1, // (atomic_fence 4:{ *:[i64] }, (timm:{ *:[i64] })) => (DMB 9:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DMB, GIR_AddImm, /*InsnID*/0, /*Imm*/9, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10166, GIR_Done, // Label 2057: @90460 GIM_Try, /*On fail goto*//*Label 2058*/ 90483, // Rule ID 10167 // // MIs[0] Operand 0 GIM_CheckIsImm, /*MI*/0, /*Op*/0, // MIs[0] Operand 1 GIM_CheckIsImm, /*MI*/0, /*Op*/1, // (atomic_fence (timm:{ *:[iPTR] }), (timm:{ *:[iPTR] })) => (DMB 11:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DMB, GIR_AddImm, /*InsnID*/0, /*Imm*/11, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10167, GIR_Done, // Label 2058: @90483 GIM_Reject, // Label 30: @90484 GIM_Try, /*On fail goto*//*Label 2059*/ 101320, GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, GIM_Try, /*On fail goto*//*Label 2060*/ 90577, // Rule ID 9613 // GIM_CheckFeatures, GIFBS_HasFuseAES, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesmc, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_crypto_aese, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 428:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 426:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) => (AESMCrrTied:{ *:[v16i8] } (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::AESErr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESMCrrTied, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9613, GIR_Done, // Label 2060: @90577 GIM_Try, /*On fail goto*//*Label 2061*/ 90665, // Rule ID 9614 // GIM_CheckFeatures, GIFBS_HasFuseAES, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesimc, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_crypto_aesd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 427:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 425:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) => (AESIMCrrTied:{ *:[v16i8] } (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::AESDrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESIMCrrTied, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9614, GIR_Done, // Label 2061: @90665 GIM_Try, /*On fail goto*//*Label 2062*/ 90707, // Rule ID 4524 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_cnth, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] pattern GIM_CheckIsImm, /*MI*/0, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, // (intrinsic_wo_chain:{ *:[i64] } 889:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern) => (CNTH_XPiI:{ *:[i64] } (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CNTH_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4524, GIR_Done, // Label 2062: @90707 GIM_Try, /*On fail goto*//*Label 2063*/ 90749, // Rule ID 4527 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_cntw, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] pattern GIM_CheckIsImm, /*MI*/0, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, // (intrinsic_wo_chain:{ *:[i64] } 891:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern) => (CNTW_XPiI:{ *:[i64] } (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CNTW_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4527, GIR_Done, // Label 2063: @90749 GIM_Try, /*On fail goto*//*Label 2064*/ 90791, // Rule ID 4530 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_cntd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] pattern GIM_CheckIsImm, /*MI*/0, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, // (intrinsic_wo_chain:{ *:[i64] } 888:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern) => (CNTD_XPiI:{ *:[i64] } (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CNTD_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4530, GIR_Done, // Label 2064: @90791 GIM_Try, /*On fail goto*//*Label 2065*/ 90833, // Rule ID 6930 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_cntb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] pattern GIM_CheckIsImm, /*MI*/0, /*Op*/2, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIPFP_I64_Predicate_sve_pred_enum, // (intrinsic_wo_chain:{ *:[i64] } 887:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern) => (CNTB_XPiI:{ *:[i64] } (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CNTB_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6930, GIR_Done, // Label 2065: @90833 GIM_Try, /*On fail goto*//*Label 2066*/ 90873, // Rule ID 36 // GIM_CheckFeatures, GIFBS_HasBF16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfcvtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8bf16] } 482:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (BFCVTN:{ *:[v8bf16] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFCVTN, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 36, GIR_Done, // Label 2066: @90873 GIM_Try, /*On fail goto*//*Label 2067*/ 90913, // Rule ID 38 // GIM_CheckFeatures, GIFBS_HasBF16_HasNEONorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfcvt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[bf16] } 481:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (BFCVT:{ *:[bf16] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFCVT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 38, GIR_Done, // Label 2067: @90913 GIM_Try, /*On fail goto*//*Label 2068*/ 90953, // Rule ID 73 // GIM_CheckFeatures, GIFBS_HasFPARMv8_HasJS, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_fjcvtzs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 460:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FJCVTZS:{ *:[i32] }:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FJCVTZS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 73, GIR_Done, // Label 2068: @90953 GIM_Try, /*On fail goto*//*Label 2069*/ 90993, // Rule ID 343 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 494:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTASUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 343, GIR_Done, // Label 2069: @90993 GIM_Try, /*On fail goto*//*Label 2070*/ 91033, // Rule ID 344 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 494:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTASUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 344, GIR_Done, // Label 2070: @91033 GIM_Try, /*On fail goto*//*Label 2071*/ 91073, // Rule ID 345 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 494:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTASUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 345, GIR_Done, // Label 2071: @91073 GIM_Try, /*On fail goto*//*Label 2072*/ 91113, // Rule ID 346 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 494:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTASUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 346, GIR_Done, // Label 2072: @91113 GIM_Try, /*On fail goto*//*Label 2073*/ 91153, // Rule ID 347 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 494:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTASUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 347, GIR_Done, // Label 2073: @91153 GIM_Try, /*On fail goto*//*Label 2074*/ 91193, // Rule ID 348 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 494:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTASUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 348, GIR_Done, // Label 2074: @91193 GIM_Try, /*On fail goto*//*Label 2075*/ 91233, // Rule ID 349 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 495:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTAUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 349, GIR_Done, // Label 2075: @91233 GIM_Try, /*On fail goto*//*Label 2076*/ 91273, // Rule ID 350 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 495:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTAUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 350, GIR_Done, // Label 2076: @91273 GIM_Try, /*On fail goto*//*Label 2077*/ 91313, // Rule ID 351 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 495:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTAUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 351, GIR_Done, // Label 2077: @91313 GIM_Try, /*On fail goto*//*Label 2078*/ 91353, // Rule ID 352 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 495:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTAUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 352, GIR_Done, // Label 2078: @91353 GIM_Try, /*On fail goto*//*Label 2079*/ 91393, // Rule ID 353 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 495:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTAUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 353, GIR_Done, // Label 2079: @91393 GIM_Try, /*On fail goto*//*Label 2080*/ 91433, // Rule ID 354 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 495:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTAUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 354, GIR_Done, // Label 2080: @91433 GIM_Try, /*On fail goto*//*Label 2081*/ 91473, // Rule ID 355 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 496:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 355, GIR_Done, // Label 2081: @91473 GIM_Try, /*On fail goto*//*Label 2082*/ 91513, // Rule ID 356 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 496:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 356, GIR_Done, // Label 2082: @91513 GIM_Try, /*On fail goto*//*Label 2083*/ 91553, // Rule ID 357 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 496:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 357, GIR_Done, // Label 2083: @91553 GIM_Try, /*On fail goto*//*Label 2084*/ 91593, // Rule ID 358 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 496:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 358, GIR_Done, // Label 2084: @91593 GIM_Try, /*On fail goto*//*Label 2085*/ 91633, // Rule ID 359 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 496:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 359, GIR_Done, // Label 2085: @91633 GIM_Try, /*On fail goto*//*Label 2086*/ 91673, // Rule ID 360 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 496:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 360, GIR_Done, // Label 2086: @91673 GIM_Try, /*On fail goto*//*Label 2087*/ 91713, // Rule ID 361 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 497:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 361, GIR_Done, // Label 2087: @91713 GIM_Try, /*On fail goto*//*Label 2088*/ 91753, // Rule ID 362 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 497:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 362, GIR_Done, // Label 2088: @91753 GIM_Try, /*On fail goto*//*Label 2089*/ 91793, // Rule ID 363 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 497:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 363, GIR_Done, // Label 2089: @91793 GIM_Try, /*On fail goto*//*Label 2090*/ 91833, // Rule ID 364 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 497:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 364, GIR_Done, // Label 2090: @91833 GIM_Try, /*On fail goto*//*Label 2091*/ 91873, // Rule ID 365 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 497:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 365, GIR_Done, // Label 2091: @91873 GIM_Try, /*On fail goto*//*Label 2092*/ 91913, // Rule ID 366 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 497:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 366, GIR_Done, // Label 2092: @91913 GIM_Try, /*On fail goto*//*Label 2093*/ 91953, // Rule ID 367 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 498:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 367, GIR_Done, // Label 2093: @91953 GIM_Try, /*On fail goto*//*Label 2094*/ 91993, // Rule ID 368 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 498:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 368, GIR_Done, // Label 2094: @91993 GIM_Try, /*On fail goto*//*Label 2095*/ 92033, // Rule ID 369 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 498:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 369, GIR_Done, // Label 2095: @92033 GIM_Try, /*On fail goto*//*Label 2096*/ 92073, // Rule ID 370 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 498:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 370, GIR_Done, // Label 2096: @92073 GIM_Try, /*On fail goto*//*Label 2097*/ 92113, // Rule ID 371 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 498:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 371, GIR_Done, // Label 2097: @92113 GIM_Try, /*On fail goto*//*Label 2098*/ 92153, // Rule ID 372 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 498:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 372, GIR_Done, // Label 2098: @92153 GIM_Try, /*On fail goto*//*Label 2099*/ 92193, // Rule ID 373 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 499:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 373, GIR_Done, // Label 2099: @92193 GIM_Try, /*On fail goto*//*Label 2100*/ 92233, // Rule ID 374 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 499:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 374, GIR_Done, // Label 2100: @92233 GIM_Try, /*On fail goto*//*Label 2101*/ 92273, // Rule ID 375 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 499:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 375, GIR_Done, // Label 2101: @92273 GIM_Try, /*On fail goto*//*Label 2102*/ 92313, // Rule ID 376 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 499:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 376, GIR_Done, // Label 2102: @92313 GIM_Try, /*On fail goto*//*Label 2103*/ 92353, // Rule ID 377 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 499:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 377, GIR_Done, // Label 2103: @92353 GIM_Try, /*On fail goto*//*Label 2104*/ 92393, // Rule ID 378 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 499:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 378, GIR_Done, // Label 2104: @92393 GIM_Try, /*On fail goto*//*Label 2105*/ 92433, // Rule ID 379 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 500:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 379, GIR_Done, // Label 2105: @92433 GIM_Try, /*On fail goto*//*Label 2106*/ 92473, // Rule ID 380 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 500:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 380, GIR_Done, // Label 2106: @92473 GIM_Try, /*On fail goto*//*Label 2107*/ 92513, // Rule ID 381 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 500:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 381, GIR_Done, // Label 2107: @92513 GIM_Try, /*On fail goto*//*Label 2108*/ 92553, // Rule ID 382 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 500:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 382, GIR_Done, // Label 2108: @92553 GIM_Try, /*On fail goto*//*Label 2109*/ 92593, // Rule ID 383 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 500:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 383, GIR_Done, // Label 2109: @92593 GIM_Try, /*On fail goto*//*Label 2110*/ 92633, // Rule ID 384 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 500:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 384, GIR_Done, // Label 2110: @92633 GIM_Try, /*On fail goto*//*Label 2111*/ 92673, // Rule ID 385 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 501:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 385, GIR_Done, // Label 2111: @92673 GIM_Try, /*On fail goto*//*Label 2112*/ 92713, // Rule ID 386 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 501:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 386, GIR_Done, // Label 2112: @92713 GIM_Try, /*On fail goto*//*Label 2113*/ 92753, // Rule ID 387 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 501:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 387, GIR_Done, // Label 2113: @92753 GIM_Try, /*On fail goto*//*Label 2114*/ 92793, // Rule ID 388 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 501:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 388, GIR_Done, // Label 2114: @92793 GIM_Try, /*On fail goto*//*Label 2115*/ 92833, // Rule ID 389 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 501:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 389, GIR_Done, // Label 2115: @92833 GIM_Try, /*On fail goto*//*Label 2116*/ 92873, // Rule ID 390 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 501:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 390, GIR_Done, // Label 2116: @92873 GIM_Try, /*On fail goto*//*Label 2117*/ 92913, // Rule ID 556 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_frint32z, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 462:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRINT32ZSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT32ZSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 556, GIR_Done, // Label 2117: @92913 GIM_Try, /*On fail goto*//*Label 2118*/ 92953, // Rule ID 557 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_frint32z, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 462:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRINT32ZDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT32ZDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 557, GIR_Done, // Label 2118: @92953 GIM_Try, /*On fail goto*//*Label 2119*/ 92993, // Rule ID 558 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_frint64z, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 464:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRINT64ZSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT64ZSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 558, GIR_Done, // Label 2119: @92993 GIM_Try, /*On fail goto*//*Label 2120*/ 93033, // Rule ID 559 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_frint64z, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 464:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRINT64ZDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT64ZDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 559, GIR_Done, // Label 2120: @93033 GIM_Try, /*On fail goto*//*Label 2121*/ 93073, // Rule ID 560 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_frint32x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 461:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRINT32XSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT32XSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 560, GIR_Done, // Label 2121: @93073 GIM_Try, /*On fail goto*//*Label 2122*/ 93113, // Rule ID 561 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_frint32x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 461:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRINT32XDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT32XDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 561, GIR_Done, // Label 2122: @93113 GIM_Try, /*On fail goto*//*Label 2123*/ 93153, // Rule ID 562 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_frint64x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 463:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRINT64XSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT64XSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 562, GIR_Done, // Label 2123: @93153 GIM_Try, /*On fail goto*//*Label 2124*/ 93193, // Rule ID 563 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_frint64x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 463:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRINT64XDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT64XDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 563, GIR_Done, // Label 2124: @93193 GIM_Try, /*On fail goto*//*Label 2125*/ 93233, // Rule ID 691 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 488:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (CLSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 691, GIR_Done, // Label 2125: @93233 GIM_Try, /*On fail goto*//*Label 2126*/ 93273, // Rule ID 692 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 488:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (CLSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 692, GIR_Done, // Label 2126: @93273 GIM_Try, /*On fail goto*//*Label 2127*/ 93313, // Rule ID 693 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 488:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (CLSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 693, GIR_Done, // Label 2127: @93313 GIM_Try, /*On fail goto*//*Label 2128*/ 93353, // Rule ID 694 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 488:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (CLSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 694, GIR_Done, // Label 2128: @93353 GIM_Try, /*On fail goto*//*Label 2129*/ 93393, // Rule ID 695 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 488:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (CLSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 695, GIR_Done, // Label 2129: @93393 GIM_Try, /*On fail goto*//*Label 2130*/ 93433, // Rule ID 696 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 488:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (CLSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 696, GIR_Done, // Label 2130: @93433 GIM_Try, /*On fail goto*//*Label 2131*/ 93473, // Rule ID 770 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 494:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTASv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 770, GIR_Done, // Label 2131: @93473 GIM_Try, /*On fail goto*//*Label 2132*/ 93513, // Rule ID 771 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 494:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTASv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 771, GIR_Done, // Label 2132: @93513 GIM_Try, /*On fail goto*//*Label 2133*/ 93553, // Rule ID 772 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 494:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTASv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 772, GIR_Done, // Label 2133: @93553 GIM_Try, /*On fail goto*//*Label 2134*/ 93593, // Rule ID 773 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 494:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTASv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 773, GIR_Done, // Label 2134: @93593 GIM_Try, /*On fail goto*//*Label 2135*/ 93633, // Rule ID 774 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 494:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTASv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 774, GIR_Done, // Label 2135: @93633 GIM_Try, /*On fail goto*//*Label 2136*/ 93673, // Rule ID 775 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 495:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTAUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 775, GIR_Done, // Label 2136: @93673 GIM_Try, /*On fail goto*//*Label 2137*/ 93713, // Rule ID 776 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 495:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTAUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 776, GIR_Done, // Label 2137: @93713 GIM_Try, /*On fail goto*//*Label 2138*/ 93753, // Rule ID 777 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 495:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTAUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 777, GIR_Done, // Label 2138: @93753 GIM_Try, /*On fail goto*//*Label 2139*/ 93793, // Rule ID 778 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 495:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTAUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 778, GIR_Done, // Label 2139: @93793 GIM_Try, /*On fail goto*//*Label 2140*/ 93833, // Rule ID 779 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 495:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTAUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 779, GIR_Done, // Label 2140: @93833 GIM_Try, /*On fail goto*//*Label 2141*/ 93873, // Rule ID 780 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 496:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTMSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 780, GIR_Done, // Label 2141: @93873 GIM_Try, /*On fail goto*//*Label 2142*/ 93913, // Rule ID 781 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 496:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTMSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 781, GIR_Done, // Label 2142: @93913 GIM_Try, /*On fail goto*//*Label 2143*/ 93953, // Rule ID 782 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 496:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTMSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 782, GIR_Done, // Label 2143: @93953 GIM_Try, /*On fail goto*//*Label 2144*/ 93993, // Rule ID 783 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 496:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTMSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 783, GIR_Done, // Label 2144: @93993 GIM_Try, /*On fail goto*//*Label 2145*/ 94033, // Rule ID 784 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 496:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTMSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 784, GIR_Done, // Label 2145: @94033 GIM_Try, /*On fail goto*//*Label 2146*/ 94073, // Rule ID 785 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 497:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTMUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 785, GIR_Done, // Label 2146: @94073 GIM_Try, /*On fail goto*//*Label 2147*/ 94113, // Rule ID 786 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 497:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTMUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 786, GIR_Done, // Label 2147: @94113 GIM_Try, /*On fail goto*//*Label 2148*/ 94153, // Rule ID 787 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 497:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTMUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 787, GIR_Done, // Label 2148: @94153 GIM_Try, /*On fail goto*//*Label 2149*/ 94193, // Rule ID 788 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 497:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTMUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 788, GIR_Done, // Label 2149: @94193 GIM_Try, /*On fail goto*//*Label 2150*/ 94233, // Rule ID 789 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 497:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTMUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 789, GIR_Done, // Label 2150: @94233 GIM_Try, /*On fail goto*//*Label 2151*/ 94273, // Rule ID 790 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 498:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTNSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 790, GIR_Done, // Label 2151: @94273 GIM_Try, /*On fail goto*//*Label 2152*/ 94313, // Rule ID 791 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 498:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTNSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 791, GIR_Done, // Label 2152: @94313 GIM_Try, /*On fail goto*//*Label 2153*/ 94353, // Rule ID 792 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 498:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTNSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 792, GIR_Done, // Label 2153: @94353 GIM_Try, /*On fail goto*//*Label 2154*/ 94393, // Rule ID 793 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 498:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTNSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 793, GIR_Done, // Label 2154: @94393 GIM_Try, /*On fail goto*//*Label 2155*/ 94433, // Rule ID 794 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 498:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTNSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 794, GIR_Done, // Label 2155: @94433 GIM_Try, /*On fail goto*//*Label 2156*/ 94473, // Rule ID 795 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 499:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTNUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 795, GIR_Done, // Label 2156: @94473 GIM_Try, /*On fail goto*//*Label 2157*/ 94513, // Rule ID 796 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 499:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTNUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 796, GIR_Done, // Label 2157: @94513 GIM_Try, /*On fail goto*//*Label 2158*/ 94553, // Rule ID 797 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 499:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTNUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 797, GIR_Done, // Label 2158: @94553 GIM_Try, /*On fail goto*//*Label 2159*/ 94593, // Rule ID 798 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 499:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTNUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 798, GIR_Done, // Label 2159: @94593 GIM_Try, /*On fail goto*//*Label 2160*/ 94633, // Rule ID 799 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 499:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTNUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 799, GIR_Done, // Label 2160: @94633 GIM_Try, /*On fail goto*//*Label 2161*/ 94673, // Rule ID 800 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 500:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTPSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 800, GIR_Done, // Label 2161: @94673 GIM_Try, /*On fail goto*//*Label 2162*/ 94713, // Rule ID 801 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 500:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTPSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 801, GIR_Done, // Label 2162: @94713 GIM_Try, /*On fail goto*//*Label 2163*/ 94753, // Rule ID 802 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 500:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTPSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 802, GIR_Done, // Label 2163: @94753 GIM_Try, /*On fail goto*//*Label 2164*/ 94793, // Rule ID 803 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 500:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTPSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 803, GIR_Done, // Label 2164: @94793 GIM_Try, /*On fail goto*//*Label 2165*/ 94833, // Rule ID 804 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 500:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTPSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 804, GIR_Done, // Label 2165: @94833 GIM_Try, /*On fail goto*//*Label 2166*/ 94873, // Rule ID 805 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 501:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTPUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 805, GIR_Done, // Label 2166: @94873 GIM_Try, /*On fail goto*//*Label 2167*/ 94913, // Rule ID 806 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 501:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTPUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 806, GIR_Done, // Label 2167: @94913 GIM_Try, /*On fail goto*//*Label 2168*/ 94953, // Rule ID 807 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 501:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTPUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 807, GIR_Done, // Label 2168: @94953 GIM_Try, /*On fail goto*//*Label 2169*/ 94993, // Rule ID 808 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 501:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTPUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 808, GIR_Done, // Label 2169: @94993 GIM_Try, /*On fail goto*//*Label 2170*/ 95033, // Rule ID 809 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 501:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTPUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 809, GIR_Done, // Label 2170: @95033 GIM_Try, /*On fail goto*//*Label 2171*/ 95073, // Rule ID 810 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtxn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 502:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTXNv2f32:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTXNv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 810, GIR_Done, // Label 2171: @95073 GIM_Try, /*On fail goto*//*Label 2172*/ 95113, // Rule ID 836 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 522:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FRECPEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 836, GIR_Done, // Label 2172: @95113 GIM_Try, /*On fail goto*//*Label 2173*/ 95153, // Rule ID 837 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 522:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FRECPEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 837, GIR_Done, // Label 2173: @95153 GIM_Try, /*On fail goto*//*Label 2174*/ 95193, // Rule ID 838 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 522:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRECPEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 838, GIR_Done, // Label 2174: @95193 GIM_Try, /*On fail goto*//*Label 2175*/ 95233, // Rule ID 839 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 522:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRECPEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 839, GIR_Done, // Label 2175: @95233 GIM_Try, /*On fail goto*//*Label 2176*/ 95273, // Rule ID 840 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 522:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRECPEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 840, GIR_Done, // Label 2176: @95273 GIM_Try, /*On fail goto*//*Label 2177*/ 95313, // Rule ID 911 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frint32z, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 526:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRINT32Zv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT32Zv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 911, GIR_Done, // Label 2177: @95313 GIM_Try, /*On fail goto*//*Label 2178*/ 95353, // Rule ID 912 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frint32z, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 526:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRINT32Zv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT32Zv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 912, GIR_Done, // Label 2178: @95353 GIM_Try, /*On fail goto*//*Label 2179*/ 95393, // Rule ID 913 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frint32z, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 526:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRINT32Zv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT32Zv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 913, GIR_Done, // Label 2179: @95393 GIM_Try, /*On fail goto*//*Label 2180*/ 95433, // Rule ID 914 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frint64z, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 528:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRINT64Zv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT64Zv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 914, GIR_Done, // Label 2180: @95433 GIM_Try, /*On fail goto*//*Label 2181*/ 95473, // Rule ID 915 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frint64z, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 528:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRINT64Zv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT64Zv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 915, GIR_Done, // Label 2181: @95473 GIM_Try, /*On fail goto*//*Label 2182*/ 95513, // Rule ID 916 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frint64z, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 528:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRINT64Zv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT64Zv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 916, GIR_Done, // Label 2182: @95513 GIM_Try, /*On fail goto*//*Label 2183*/ 95553, // Rule ID 917 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frint32x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 525:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRINT32Xv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT32Xv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 917, GIR_Done, // Label 2183: @95553 GIM_Try, /*On fail goto*//*Label 2184*/ 95593, // Rule ID 918 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frint32x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 525:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRINT32Xv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT32Xv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 918, GIR_Done, // Label 2184: @95593 GIM_Try, /*On fail goto*//*Label 2185*/ 95633, // Rule ID 919 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frint32x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 525:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRINT32Xv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT32Xv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 919, GIR_Done, // Label 2185: @95633 GIM_Try, /*On fail goto*//*Label 2186*/ 95673, // Rule ID 920 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frint64x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 527:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRINT64Xv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT64Xv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 920, GIR_Done, // Label 2186: @95673 GIM_Try, /*On fail goto*//*Label 2187*/ 95713, // Rule ID 921 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frint64x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 527:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRINT64Xv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT64Xv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 921, GIR_Done, // Label 2187: @95713 GIM_Try, /*On fail goto*//*Label 2188*/ 95753, // Rule ID 922 // GIM_CheckFeatures, GIFBS_HasFRInt3264, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frint64x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 527:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRINT64Xv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINT64Xv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 922, GIR_Done, // Label 2188: @95753 GIM_Try, /*On fail goto*//*Label 2189*/ 95793, // Rule ID 923 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 529:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FRSQRTEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 923, GIR_Done, // Label 2189: @95793 GIM_Try, /*On fail goto*//*Label 2190*/ 95833, // Rule ID 924 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 529:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FRSQRTEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 924, GIR_Done, // Label 2190: @95833 GIM_Try, /*On fail goto*//*Label 2191*/ 95873, // Rule ID 925 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 529:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRSQRTEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 925, GIR_Done, // Label 2191: @95873 GIM_Try, /*On fail goto*//*Label 2192*/ 95913, // Rule ID 926 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 529:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRSQRTEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 926, GIR_Done, // Label 2192: @95913 GIM_Try, /*On fail goto*//*Label 2193*/ 95953, // Rule ID 927 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 529:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRSQRTEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 927, GIR_Done, // Label 2193: @95953 GIM_Try, /*On fail goto*//*Label 2194*/ 95993, // Rule ID 974 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 550:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv8i8_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 974, GIR_Done, // Label 2194: @95993 GIM_Try, /*On fail goto*//*Label 2195*/ 96033, // Rule ID 976 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 550:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv16i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 976, GIR_Done, // Label 2195: @96033 GIM_Try, /*On fail goto*//*Label 2196*/ 96073, // Rule ID 978 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 550:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv4i16_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 978, GIR_Done, // Label 2196: @96073 GIM_Try, /*On fail goto*//*Label 2197*/ 96113, // Rule ID 980 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 550:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv8i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 980, GIR_Done, // Label 2197: @96113 GIM_Try, /*On fail goto*//*Label 2198*/ 96153, // Rule ID 982 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 550:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (SADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv2i32_v1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 982, GIR_Done, // Label 2198: @96153 GIM_Try, /*On fail goto*//*Label 2199*/ 96193, // Rule ID 984 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 550:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv4i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 984, GIR_Done, // Label 2199: @96193 GIM_Try, /*On fail goto*//*Label 2200*/ 96233, // Rule ID 995 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 568:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SQABSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 995, GIR_Done, // Label 2200: @96233 GIM_Try, /*On fail goto*//*Label 2201*/ 96273, // Rule ID 996 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 568:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SQABSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 996, GIR_Done, // Label 2201: @96273 GIM_Try, /*On fail goto*//*Label 2202*/ 96313, // Rule ID 997 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 568:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SQABSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 997, GIR_Done, // Label 2202: @96313 GIM_Try, /*On fail goto*//*Label 2203*/ 96353, // Rule ID 998 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 568:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQABSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 998, GIR_Done, // Label 2203: @96353 GIM_Try, /*On fail goto*//*Label 2204*/ 96393, // Rule ID 999 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 568:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (SQABSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 999, GIR_Done, // Label 2204: @96393 GIM_Try, /*On fail goto*//*Label 2205*/ 96433, // Rule ID 1000 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 568:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQABSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1000, GIR_Done, // Label 2205: @96433 GIM_Try, /*On fail goto*//*Label 2206*/ 96473, // Rule ID 1001 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 568:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQABSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1001, GIR_Done, // Label 2206: @96473 GIM_Try, /*On fail goto*//*Label 2207*/ 96513, // Rule ID 1002 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 575:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SQNEGv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1002, GIR_Done, // Label 2207: @96513 GIM_Try, /*On fail goto*//*Label 2208*/ 96553, // Rule ID 1003 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 575:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SQNEGv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1003, GIR_Done, // Label 2208: @96553 GIM_Try, /*On fail goto*//*Label 2209*/ 96593, // Rule ID 1004 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 575:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SQNEGv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1004, GIR_Done, // Label 2209: @96593 GIM_Try, /*On fail goto*//*Label 2210*/ 96633, // Rule ID 1005 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 575:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQNEGv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1005, GIR_Done, // Label 2210: @96633 GIM_Try, /*On fail goto*//*Label 2211*/ 96673, // Rule ID 1006 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 575:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (SQNEGv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1006, GIR_Done, // Label 2211: @96673 GIM_Try, /*On fail goto*//*Label 2212*/ 96713, // Rule ID 1007 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 575:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQNEGv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1007, GIR_Done, // Label 2212: @96713 GIM_Try, /*On fail goto*//*Label 2213*/ 96753, // Rule ID 1008 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 575:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQNEGv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1008, GIR_Done, // Label 2213: @96753 GIM_Try, /*On fail goto*//*Label 2214*/ 96793, // Rule ID 1009 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 589:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQXTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1009, GIR_Done, // Label 2214: @96793 GIM_Try, /*On fail goto*//*Label 2215*/ 96833, // Rule ID 1010 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 589:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQXTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1010, GIR_Done, // Label 2215: @96833 GIM_Try, /*On fail goto*//*Label 2216*/ 96873, // Rule ID 1011 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 589:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQXTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1011, GIR_Done, // Label 2216: @96873 GIM_Try, /*On fail goto*//*Label 2217*/ 96913, // Rule ID 1012 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 590:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQXTUNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1012, GIR_Done, // Label 2217: @96913 GIM_Try, /*On fail goto*//*Label 2218*/ 96953, // Rule ID 1013 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 590:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQXTUNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1013, GIR_Done, // Label 2218: @96953 GIM_Try, /*On fail goto*//*Label 2219*/ 96993, // Rule ID 1014 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 590:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQXTUNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1014, GIR_Done, // Label 2219: @96993 GIM_Try, /*On fail goto*//*Label 2220*/ 97033, // Rule ID 1035 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 615:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (UADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv8i8_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1035, GIR_Done, // Label 2220: @97033 GIM_Try, /*On fail goto*//*Label 2221*/ 97073, // Rule ID 1037 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 615:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (UADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv16i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1037, GIR_Done, // Label 2221: @97073 GIM_Try, /*On fail goto*//*Label 2222*/ 97113, // Rule ID 1039 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 615:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (UADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv4i16_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1039, GIR_Done, // Label 2222: @97113 GIM_Try, /*On fail goto*//*Label 2223*/ 97153, // Rule ID 1041 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 615:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (UADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv8i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1041, GIR_Done, // Label 2223: @97153 GIM_Try, /*On fail goto*//*Label 2224*/ 97193, // Rule ID 1043 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 615:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (UADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv2i32_v1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1043, GIR_Done, // Label 2224: @97193 GIM_Try, /*On fail goto*//*Label 2225*/ 97233, // Rule ID 1045 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 615:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (UADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv4i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1045, GIR_Done, // Label 2225: @97233 GIM_Try, /*On fail goto*//*Label 2226*/ 97273, // Rule ID 1056 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 635:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (UQXTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1056, GIR_Done, // Label 2226: @97273 GIM_Try, /*On fail goto*//*Label 2227*/ 97313, // Rule ID 1057 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 635:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (UQXTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1057, GIR_Done, // Label 2227: @97313 GIM_Try, /*On fail goto*//*Label 2228*/ 97353, // Rule ID 1058 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 635:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (UQXTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1058, GIR_Done, // Label 2228: @97353 GIM_Try, /*On fail goto*//*Label 2229*/ 97393, // Rule ID 1059 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 636:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (URECPEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URECPEv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1059, GIR_Done, // Label 2229: @97393 GIM_Try, /*On fail goto*//*Label 2230*/ 97433, // Rule ID 1060 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 636:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (URECPEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URECPEv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1060, GIR_Done, // Label 2230: @97433 GIM_Try, /*On fail goto*//*Label 2231*/ 97473, // Rule ID 1061 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ursqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 639:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (URSQRTEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSQRTEv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1061, GIR_Done, // Label 2231: @97473 GIM_Try, /*On fail goto*//*Label 2232*/ 97513, // Rule ID 1062 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ursqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 639:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (URSQRTEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSQRTEv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1062, GIR_Done, // Label 2232: @97513 GIM_Try, /*On fail goto*//*Label 2233*/ 97553, // Rule ID 1618 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fcvtxn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 668:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTXNv1i64:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTXNv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1618, GIR_Done, // Label 2233: @97553 GIM_Try, /*On fail goto*//*Label 2234*/ 97593, // Rule ID 1623 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 568:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQABSv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1623, GIR_Done, // Label 2234: @97593 GIM_Try, /*On fail goto*//*Label 2235*/ 97633, // Rule ID 1624 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 568:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn) => (SQABSv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1624, GIR_Done, // Label 2235: @97633 GIM_Try, /*On fail goto*//*Label 2236*/ 97673, // Rule ID 1625 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 575:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQNEGv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1625, GIR_Done, // Label 2236: @97673 GIM_Try, /*On fail goto*//*Label 2237*/ 97713, // Rule ID 1626 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 575:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn) => (SQNEGv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1626, GIR_Done, // Label 2237: @97713 GIM_Try, /*On fail goto*//*Label 2238*/ 97753, // Rule ID 1627 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_scalar_sqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 553:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (SQXTNv1i32:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1627, GIR_Done, // Label 2238: @97753 GIM_Try, /*On fail goto*//*Label 2239*/ 97793, // Rule ID 1628 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_scalar_sqxtun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 554:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (SQXTUNv1i32:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1628, GIR_Done, // Label 2239: @97793 GIM_Try, /*On fail goto*//*Label 2240*/ 97833, // Rule ID 1634 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_scalar_uqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 555:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (UQXTNv1i32:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1634, GIR_Done, // Label 2240: @97833 GIM_Try, /*On fail goto*//*Label 2241*/ 97873, // Rule ID 1906 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 508:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMAXNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMVv4i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1906, GIR_Done, // Label 2241: @97873 GIM_Try, /*On fail goto*//*Label 2242*/ 97913, // Rule ID 1907 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 508:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMAXNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMVv8i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1907, GIR_Done, // Label 2242: @97913 GIM_Try, /*On fail goto*//*Label 2243*/ 97953, // Rule ID 1908 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 508:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMAXNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMVv4i32v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1908, GIR_Done, // Label 2243: @97953 GIM_Try, /*On fail goto*//*Label 2244*/ 97993, // Rule ID 1909 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 510:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMAXVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXVv4i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1909, GIR_Done, // Label 2244: @97993 GIM_Try, /*On fail goto*//*Label 2245*/ 98033, // Rule ID 1910 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 510:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMAXVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXVv8i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1910, GIR_Done, // Label 2245: @98033 GIM_Try, /*On fail goto*//*Label 2246*/ 98073, // Rule ID 1911 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 510:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMAXVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXVv4i32v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1911, GIR_Done, // Label 2246: @98073 GIM_Try, /*On fail goto*//*Label 2247*/ 98113, // Rule ID 1912 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 514:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMINNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMVv4i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1912, GIR_Done, // Label 2247: @98113 GIM_Try, /*On fail goto*//*Label 2248*/ 98153, // Rule ID 1913 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 514:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMINNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMVv8i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1913, GIR_Done, // Label 2248: @98153 GIM_Try, /*On fail goto*//*Label 2249*/ 98193, // Rule ID 1914 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 514:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMINNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMVv4i32v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1914, GIR_Done, // Label 2249: @98193 GIM_Try, /*On fail goto*//*Label 2250*/ 98233, // Rule ID 1915 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 516:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMINVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINVv4i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1915, GIR_Done, // Label 2250: @98233 GIM_Try, /*On fail goto*//*Label 2251*/ 98273, // Rule ID 1916 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 516:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMINVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINVv8i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1916, GIR_Done, // Label 2251: @98273 GIM_Try, /*On fail goto*//*Label 2252*/ 98313, // Rule ID 1917 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 516:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMINVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINVv4i32v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1917, GIR_Done, // Label 2252: @98313 GIM_Try, /*On fail goto*//*Label 2253*/ 98353, // Rule ID 2218 // GIM_CheckFeatures, GIFBS_HasAES, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesmc, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 428:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (AESMCrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESMCrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2218, GIR_Done, // Label 2253: @98353 GIM_Try, /*On fail goto*//*Label 2254*/ 98393, // Rule ID 2219 // GIM_CheckFeatures, GIFBS_HasAES, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesimc, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 427:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (AESIMCrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESIMCrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2219, GIR_Done, // Label 2254: @98393 GIM_Try, /*On fail goto*//*Label 2255*/ 98433, // Rule ID 2227 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1h, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 435:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn) => (SHA1Hrr:{ *:[i32] } FPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Hrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2227, GIR_Done, // Label 2255: @98433 GIM_Try, /*On fail goto*//*Label 2256*/ 98473, // Rule ID 6828 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 568:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn) => (SQABSv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6828, GIR_Done, // Label 2256: @98473 GIM_Try, /*On fail goto*//*Label 2257*/ 98511, // Rule ID 7970 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_cls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 415:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn) => (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7970, GIR_Done, // Label 2257: @98511 GIM_Try, /*On fail goto*//*Label 2258*/ 98572, // Rule ID 7971 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_cls64, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 416:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rm) => (EXTRACT_SUBREG:{ *:[i32] } (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rm), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::CLSXr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::sub_32, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64RegClassID, // GIR_Coverage, 7971, GIR_Done, // Label 2258: @98572 GIM_Try, /*On fail goto*//*Label 2259*/ 98610, // Rule ID 8521 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvthf2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 657:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (FCVTLv4i16:{ *:[v4f32] } V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8521, GIR_Done, // Label 2259: @98610 GIM_Try, /*On fail goto*//*Label 2260*/ 98648, // Rule ID 8527 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2hf, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 654:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTNv4i16:{ *:[v4i16] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8527, GIR_Done, // Label 2260: @98648 GIM_Try, /*On fail goto*//*Label 2261*/ 98688, // Rule ID 8717 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 575:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn) => (SQNEGv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8717, GIR_Done, // Label 2261: @98688 GIM_Try, /*On fail goto*//*Label 2262*/ 98726, // Rule ID 8720 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 494:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTASv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8720, GIR_Done, // Label 2262: @98726 GIM_Try, /*On fail goto*//*Label 2263*/ 98764, // Rule ID 8721 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 495:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTAUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8721, GIR_Done, // Label 2263: @98764 GIM_Try, /*On fail goto*//*Label 2264*/ 98802, // Rule ID 8722 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 496:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTMSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8722, GIR_Done, // Label 2264: @98802 GIM_Try, /*On fail goto*//*Label 2265*/ 98840, // Rule ID 8723 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 497:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTMUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8723, GIR_Done, // Label 2265: @98840 GIM_Try, /*On fail goto*//*Label 2266*/ 98878, // Rule ID 8724 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 498:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTNSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8724, GIR_Done, // Label 2266: @98878 GIM_Try, /*On fail goto*//*Label 2267*/ 98916, // Rule ID 8725 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 499:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTNUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8725, GIR_Done, // Label 2267: @98916 GIM_Try, /*On fail goto*//*Label 2268*/ 98954, // Rule ID 8726 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 500:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTPSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8726, GIR_Done, // Label 2268: @98954 GIM_Try, /*On fail goto*//*Label 2269*/ 98992, // Rule ID 8727 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 501:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTPUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8727, GIR_Done, // Label 2269: @98992 GIM_Try, /*On fail goto*//*Label 2270*/ 99030, // Rule ID 8728 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtzs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 503:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTZSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8728, GIR_Done, // Label 2270: @99030 GIM_Try, /*On fail goto*//*Label 2271*/ 99068, // Rule ID 8729 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtzu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 504:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTZUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8729, GIR_Done, // Label 2271: @99068 GIM_Try, /*On fail goto*//*Label 2272*/ 99106, // Rule ID 8730 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 522:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRECPEv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8730, GIR_Done, // Label 2272: @99106 GIM_Try, /*On fail goto*//*Label 2273*/ 99144, // Rule ID 8731 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 522:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRECPEv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8731, GIR_Done, // Label 2273: @99144 GIM_Try, /*On fail goto*//*Label 2274*/ 99182, // Rule ID 8732 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 522:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRECPEv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8732, GIR_Done, // Label 2274: @99182 GIM_Try, /*On fail goto*//*Label 2275*/ 99220, // Rule ID 8733 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1f64] } 522:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRECPEv1i64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8733, GIR_Done, // Label 2275: @99220 GIM_Try, /*On fail goto*//*Label 2276*/ 99258, // Rule ID 8745 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 524:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRECPXv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPXv1f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8745, GIR_Done, // Label 2276: @99258 GIM_Try, /*On fail goto*//*Label 2277*/ 99296, // Rule ID 8746 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 524:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRECPXv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPXv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8746, GIR_Done, // Label 2277: @99296 GIM_Try, /*On fail goto*//*Label 2278*/ 99334, // Rule ID 8747 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 524:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRECPXv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPXv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8747, GIR_Done, // Label 2278: @99334 GIM_Try, /*On fail goto*//*Label 2279*/ 99372, // Rule ID 8748 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 529:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRSQRTEv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8748, GIR_Done, // Label 2279: @99372 GIM_Try, /*On fail goto*//*Label 2280*/ 99410, // Rule ID 8749 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 529:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRSQRTEv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8749, GIR_Done, // Label 2280: @99410 GIM_Try, /*On fail goto*//*Label 2281*/ 99448, // Rule ID 8750 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 529:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRSQRTEv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8750, GIR_Done, // Label 2281: @99448 GIM_Try, /*On fail goto*//*Label 2282*/ 99486, // Rule ID 8751 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1f64] } 529:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRSQRTEv1i64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8751, GIR_Done, // Label 2282: @99486 GIM_Try, /*On fail goto*//*Label 2283*/ 99524, // Rule ID 8932 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 493:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FADDPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8932, GIR_Done, // Label 2283: @99524 GIM_Try, /*On fail goto*//*Label 2284*/ 99605, // Rule ID 8933 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 493:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } (FADDPv4f32:{ *:[f128] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rn), dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FADDPv4f32, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8933, GIR_Done, // Label 2284: @99605 GIM_Try, /*On fail goto*//*Label 2285*/ 99643, // Rule ID 8934 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 493:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FADDPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8934, GIR_Done, // Label 2285: @99643 GIM_Try, /*On fail goto*//*Label 2286*/ 99681, // Rule ID 8935 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 508:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMAXNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8935, GIR_Done, // Label 2286: @99681 GIM_Try, /*On fail goto*//*Label 2287*/ 99719, // Rule ID 8936 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 508:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMAXNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8936, GIR_Done, // Label 2287: @99719 GIM_Try, /*On fail goto*//*Label 2288*/ 99757, // Rule ID 8937 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 510:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMAXPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8937, GIR_Done, // Label 2288: @99757 GIM_Try, /*On fail goto*//*Label 2289*/ 99795, // Rule ID 8938 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 510:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMAXPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8938, GIR_Done, // Label 2289: @99795 GIM_Try, /*On fail goto*//*Label 2290*/ 99833, // Rule ID 8939 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 514:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMINNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8939, GIR_Done, // Label 2290: @99833 GIM_Try, /*On fail goto*//*Label 2291*/ 99871, // Rule ID 8940 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 514:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMINNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8940, GIR_Done, // Label 2291: @99871 GIM_Try, /*On fail goto*//*Label 2292*/ 99909, // Rule ID 8941 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 516:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMINPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8941, GIR_Done, // Label 2292: @99909 GIM_Try, /*On fail goto*//*Label 2293*/ 99947, // Rule ID 8942 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 516:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMINPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8942, GIR_Done, // Label 2293: @99947 GIM_Try, /*On fail goto*//*Label 2294*/ 100049, // Rule ID 9182 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 551:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv8i8v:{ *:[bf16] } V64:{ *:[v8i8] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLVv8i8v, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMOVvi16to32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9182, GIR_Done, // Label 2294: @100049 GIM_Try, /*On fail goto*//*Label 2295*/ 100151, // Rule ID 9183 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 551:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv16i8v:{ *:[bf16] } V128:{ *:[v16i8] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLVv16i8v, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMOVvi16to32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9183, GIR_Done, // Label 2295: @100151 GIM_Try, /*On fail goto*//*Label 2296*/ 100257, // Rule ID 9184 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 551:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLVv4i16v, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, // GIR_Coverage, 9184, GIR_Done, // Label 2296: @100257 GIM_Try, /*On fail goto*//*Label 2297*/ 100363, // Rule ID 9185 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 551:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLVv8i16v, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, // GIR_Coverage, 9185, GIR_Done, // Label 2297: @100363 GIM_Try, /*On fail goto*//*Label 2298*/ 100469, // Rule ID 9186 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 551:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLVv4i32v, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::dsub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, // GIR_Coverage, 9186, GIR_Done, // Label 2298: @100469 GIM_Try, /*On fail goto*//*Label 2299*/ 100575, // Rule ID 9187 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 616:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLVv8i8v:{ *:[bf16] } V64:{ *:[v8i8] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::UADDLVv8i8v, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, // GIR_Coverage, 9187, GIR_Done, // Label 2299: @100575 GIM_Try, /*On fail goto*//*Label 2300*/ 100681, // Rule ID 9188 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 616:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLVv16i8v:{ *:[bf16] } V128:{ *:[v16i8] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::UADDLVv16i8v, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, // GIR_Coverage, 9188, GIR_Done, // Label 2300: @100681 GIM_Try, /*On fail goto*//*Label 2301*/ 100787, // Rule ID 9189 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 616:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::UADDLVv4i16v, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, // GIR_Coverage, 9189, GIR_Done, // Label 2301: @100787 GIM_Try, /*On fail goto*//*Label 2302*/ 100893, // Rule ID 9190 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 616:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::UADDLVv8i16v, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, // GIR_Coverage, 9190, GIR_Done, // Label 2302: @100893 GIM_Try, /*On fail goto*//*Label 2303*/ 100999, // Rule ID 9191 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 616:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::UADDLVv4i32v, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::dsub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, // GIR_Coverage, 9191, GIR_Done, // Label 2303: @100999 GIM_Try, /*On fail goto*//*Label 2304*/ 101105, // Rule ID 9192 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 551:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLPv2i32_v1i64:{ *:[i64] } V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLPv2i32_v1i64, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::dsub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, // GIR_Coverage, 9192, GIR_Done, // Label 2304: @101105 GIM_Try, /*On fail goto*//*Label 2305*/ 101211, // Rule ID 9193 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 616:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLPv2i32_v1i64:{ *:[i64] } V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::UADDLPv2i32_v1i64, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::dsub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, // GIR_Coverage, 9193, GIR_Done, // Label 2305: @101211 GIM_Try, /*On fail goto*//*Label 2306*/ 101247, // Rule ID 2261 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_rev_b16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1106:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn) => (REV_PP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV_PP_H, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2261, GIR_Done, // Label 2306: @101247 GIM_Try, /*On fail goto*//*Label 2307*/ 101283, // Rule ID 2262 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_rev_b32, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1107:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn) => (REV_PP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV_PP_S, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2262, GIR_Done, // Label 2307: @101283 GIM_Try, /*On fail goto*//*Label 2308*/ 101319, // Rule ID 2263 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_rev_b64, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1108:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn) => (REV_PP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV_PP_D, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2263, GIR_Done, // Label 2308: @101319 GIM_Reject, // Label 2059: @101320 GIM_Try, /*On fail goto*//*Label 2309*/ 128155, GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, GIM_Try, /*On fail goto*//*Label 2310*/ 101485, // Rule ID 6866 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3] GIM_CheckOpcode, /*MI*/3, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[4] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (intrinsic_wo_chain:{ *:[i32] } 569:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 573:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx)), 0:{ *:[i64] })) => (SQDMLALv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[bf16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/7, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR16RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6866, GIR_Done, // Label 2310: @101485 GIM_Try, /*On fail goto*//*Label 2311*/ 101645, // Rule ID 9409 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3] GIM_CheckOpcode, /*MI*/3, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[4] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (intrinsic_wo_chain:{ *:[i32] } 588:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 573:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx)), 0:{ *:[i64] })) => (SQDMLSLv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[bf16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/7, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR16RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9409, GIR_Done, // Label 2311: @101645 GIM_Try, /*On fail goto*//*Label 2312*/ 101821, // Rule ID 6865 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[i32] } 569:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 573:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] })) => (SQDMLALv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[bf16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v4i16] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/2, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/7, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR16RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6865, GIR_Done, // Label 2312: @101821 GIM_Try, /*On fail goto*//*Label 2313*/ 101997, // Rule ID 9408 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[i32] } 588:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 573:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] })) => (SQDMLSLv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[bf16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v4i16] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/2, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/7, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR16RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9408, GIR_Done, // Label 2313: @101997 GIM_Try, /*On fail goto*//*Label 2314*/ 102113, // Rule ID 1989 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[v4i32] } 569:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 573:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx))) => (SQDMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1989, GIR_Done, // Label 2314: @102113 GIM_Try, /*On fail goto*//*Label 2315*/ 102229, // Rule ID 1994 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[v4i32] } 588:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 573:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx))) => (SQDMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1994, GIR_Done, // Label 2315: @102229 GIM_Try, /*On fail goto*//*Label 2316*/ 102345, // Rule ID 1991 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[v2i64] } 569:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 573:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx))) => (SQDMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1991, GIR_Done, // Label 2316: @102345 GIM_Try, /*On fail goto*//*Label 2317*/ 102461, // Rule ID 1996 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[v2i64] } 588:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 573:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx))) => (SQDMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1996, GIR_Done, // Label 2317: @102461 GIM_Try, /*On fail goto*//*Label 2318*/ 102577, // Rule ID 1993 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[i64] } 569:{ *:[iPTR] }, FPR64Op:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 574:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx))) => (SQDMLALv1i64_indexed:{ *:[i64] } FPR64Op:{ *:[i64] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1993, GIR_Done, // Label 2318: @102577 GIM_Try, /*On fail goto*//*Label 2319*/ 102693, // Rule ID 1998 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[i64] } 588:{ *:[iPTR] }, FPR64Op:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 574:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx))) => (SQDMLSLv1i64_indexed:{ *:[i64] } FPR64Op:{ *:[i64] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1998, GIR_Done, // Label 2319: @102693 GIM_Try, /*On fail goto*//*Label 2320*/ 102794, // Rule ID 9426 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[f16] } 656:{ *:[iPTR] }, (and:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (imm:{ *:[i32] })<>:$imm) => (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[bf16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/7, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR16RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9426, GIR_Done, // Label 2320: @102794 GIM_Try, /*On fail goto*//*Label 2321*/ 102878, // Rule ID 1706 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 569:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 573:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQDMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1706, GIR_Done, // Label 2321: @102878 GIM_Try, /*On fail goto*//*Label 2322*/ 102962, // Rule ID 1708 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i64] } 569:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 573:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQDMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1708, GIR_Done, // Label 2322: @102962 GIM_Try, /*On fail goto*//*Label 2323*/ 103046, // Rule ID 1710 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 588:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 573:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQDMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1710, GIR_Done, // Label 2323: @103046 GIM_Try, /*On fail goto*//*Label 2324*/ 103130, // Rule ID 1712 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i64] } 588:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 573:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQDMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1712, GIR_Done, // Label 2324: @103130 GIM_Try, /*On fail goto*//*Label 2325*/ 103212, // Rule ID 8706 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i64] } 569:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 574:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQDMLALi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8706, GIR_Done, // Label 2325: @103212 GIM_Try, /*On fail goto*//*Label 2326*/ 103294, // Rule ID 8707 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i64] } 588:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 574:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQDMLSLi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8707, GIR_Done, // Label 2326: @103294 GIM_Try, /*On fail goto*//*Label 2327*/ 103378, // Rule ID 10828 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4f16] } 521:{ *:[iPTR] }, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v4f16] }:$Rn) => (FMULXv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10828, GIR_Done, // Label 2327: @103378 GIM_Try, /*On fail goto*//*Label 2328*/ 103462, // Rule ID 10829 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v8f16] } 521:{ *:[iPTR] }, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v8f16] }:$Rn) => (FMULXv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10829, GIR_Done, // Label 2328: @103462 GIM_Try, /*On fail goto*//*Label 2329*/ 103546, // Rule ID 10830 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v2f32] } 521:{ *:[iPTR] }, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v2f32] }:$Rn) => (FMULXv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10830, GIR_Done, // Label 2329: @103546 GIM_Try, /*On fail goto*//*Label 2330*/ 103630, // Rule ID 10831 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4f32] } 521:{ *:[iPTR] }, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v4f32] }:$Rn) => (FMULXv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10831, GIR_Done, // Label 2330: @103630 GIM_Try, /*On fail goto*//*Label 2331*/ 103714, // Rule ID 10832 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v2f64] } 521:{ *:[iPTR] }, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v2f64] }:$Rn) => (FMULXv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10832, GIR_Done, // Label 2331: @103714 GIM_Try, /*On fail goto*//*Label 2332*/ 103798, // Rule ID 10833 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[f16] } 521:{ *:[iPTR] }, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR16Op:{ *:[f16] }:$Rn) => (FMULXv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10833, GIR_Done, // Label 2332: @103798 GIM_Try, /*On fail goto*//*Label 2333*/ 103882, // Rule ID 10834 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[f32] } 521:{ *:[iPTR] }, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32Op:{ *:[f32] }:$Rn) => (FMULXv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10834, GIR_Done, // Label 2333: @103882 GIM_Try, /*On fail goto*//*Label 2334*/ 103966, // Rule ID 10835 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[f64] } 521:{ *:[iPTR] }, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR64Op:{ *:[f64] }:$Rn) => (FMULXv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10835, GIR_Done, // Label 2334: @103966 GIM_Try, /*On fail goto*//*Label 2335*/ 104050, // Rule ID 1939 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4f16] } 521:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULXv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1939, GIR_Done, // Label 2335: @104050 GIM_Try, /*On fail goto*//*Label 2336*/ 104134, // Rule ID 1940 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v8f16] } 521:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULXv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1940, GIR_Done, // Label 2336: @104134 GIM_Try, /*On fail goto*//*Label 2337*/ 104218, // Rule ID 1963 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4i16] } 570:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQDMULHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1963, GIR_Done, // Label 2337: @104218 GIM_Try, /*On fail goto*//*Label 2338*/ 104302, // Rule ID 1964 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v8i16] } 570:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQDMULHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1964, GIR_Done, // Label 2338: @104302 GIM_Try, /*On fail goto*//*Label 2339*/ 104386, // Rule ID 1968 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4i16] } 578:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMULHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1968, GIR_Done, // Label 2339: @104386 GIM_Try, /*On fail goto*//*Label 2340*/ 104470, // Rule ID 1969 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v8i16] } 578:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMULHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1969, GIR_Done, // Label 2340: @104470 GIM_Try, /*On fail goto*//*Label 2341*/ 104554, // Rule ID 2009 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4i32] } 573:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQDMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2009, GIR_Done, // Label 2341: @104554 GIM_Try, /*On fail goto*//*Label 2342*/ 104638, // Rule ID 1941 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v2f32] } 521:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULXv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1941, GIR_Done, // Label 2342: @104638 GIM_Try, /*On fail goto*//*Label 2343*/ 104722, // Rule ID 1942 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4f32] } 521:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULXv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1942, GIR_Done, // Label 2343: @104722 GIM_Try, /*On fail goto*//*Label 2344*/ 104806, // Rule ID 1965 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v2i32] } 570:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQDMULHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1965, GIR_Done, // Label 2344: @104806 GIM_Try, /*On fail goto*//*Label 2345*/ 104890, // Rule ID 1966 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4i32] } 570:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQDMULHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1966, GIR_Done, // Label 2345: @104890 GIM_Try, /*On fail goto*//*Label 2346*/ 104974, // Rule ID 1970 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v2i32] } 578:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMULHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1970, GIR_Done, // Label 2346: @104974 GIM_Try, /*On fail goto*//*Label 2347*/ 105058, // Rule ID 1971 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4i32] } 578:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMULHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1971, GIR_Done, // Label 2347: @105058 GIM_Try, /*On fail goto*//*Label 2348*/ 105142, // Rule ID 2011 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v2i64] } 573:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQDMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2011, GIR_Done, // Label 2348: @105142 GIM_Try, /*On fail goto*//*Label 2349*/ 105226, // Rule ID 1943 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v2f64] } 521:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULXv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1943, GIR_Done, // Label 2349: @105226 GIM_Try, /*On fail goto*//*Label 2350*/ 105310, // Rule ID 1944 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[f16] } 521:{ *:[iPTR] }, FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULXv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1944, GIR_Done, // Label 2350: @105310 GIM_Try, /*On fail goto*//*Label 2351*/ 105394, // Rule ID 1945 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[f32] } 521:{ *:[iPTR] }, FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULXv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1945, GIR_Done, // Label 2351: @105394 GIM_Try, /*On fail goto*//*Label 2352*/ 105478, // Rule ID 1946 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[f64] } 521:{ *:[iPTR] }, FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULXv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1946, GIR_Done, // Label 2352: @105478 GIM_Try, /*On fail goto*//*Label 2353*/ 105562, // Rule ID 1967 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[i32] } 570:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQDMULHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1967, GIR_Done, // Label 2353: @105562 GIM_Try, /*On fail goto*//*Label 2354*/ 105646, // Rule ID 1972 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[i32] } 578:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMULHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1972, GIR_Done, // Label 2354: @105646 GIM_Try, /*On fail goto*//*Label 2355*/ 105728, // Rule ID 9410 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[i64] } 574:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Vm, (imm:{ *:[i64] })<>:$idx)) => (SQDMULLv1i64_indexed:{ *:[i64] } FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Vm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9410, GIR_Done, // Label 2355: @105728 GIM_Try, /*On fail goto*//*Label 2356*/ 105773, // Rule ID 7861 // GIM_CheckFeatures, GIFBS_HasPAuth, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ptrauth_strip, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 0, // (intrinsic_wo_chain:{ *:[i64] } 251:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 0:{ *:[i32] }) => (XPACI:{ *:[i64] } GPR64:{ *:[i64] }:$Rd) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XPACI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7861, GIR_Done, // Label 2356: @105773 GIM_Try, /*On fail goto*//*Label 2357*/ 105818, // Rule ID 7862 // GIM_CheckFeatures, GIFBS_HasPAuth, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ptrauth_strip, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 1, // (intrinsic_wo_chain:{ *:[i64] } 251:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 1:{ *:[i32] }) => (XPACI:{ *:[i64] } GPR64:{ *:[i64] }:$Rd) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XPACI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7862, GIR_Done, // Label 2357: @105818 GIM_Try, /*On fail goto*//*Label 2358*/ 105863, // Rule ID 7863 // GIM_CheckFeatures, GIFBS_HasPAuth, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ptrauth_strip, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 2, // (intrinsic_wo_chain:{ *:[i64] } 251:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 2:{ *:[i32] }) => (XPACD:{ *:[i64] } GPR64:{ *:[i64] }:$Rd) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XPACD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7863, GIR_Done, // Label 2358: @105863 GIM_Try, /*On fail goto*//*Label 2359*/ 105908, // Rule ID 7864 // GIM_CheckFeatures, GIFBS_HasPAuth, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ptrauth_strip, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 3, // (intrinsic_wo_chain:{ *:[i64] } 251:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 3:{ *:[i32] }) => (XPACD:{ *:[i64] } GPR64:{ *:[i64] }:$Rd) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XPACD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7864, GIR_Done, // Label 2359: @105908 GIM_Try, /*On fail goto*//*Label 2360*/ 105967, // Rule ID 2026 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 582:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2026, GIR_Done, // Label 2360: @105967 GIM_Try, /*On fail goto*//*Label 2361*/ 106026, // Rule ID 2027 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 583:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2027, GIR_Done, // Label 2361: @106026 GIM_Try, /*On fail goto*//*Label 2362*/ 106085, // Rule ID 2032 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 586:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2032, GIR_Done, // Label 2362: @106085 GIM_Try, /*On fail goto*//*Label 2363*/ 106144, // Rule ID 2033 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 587:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2033, GIR_Done, // Label 2363: @106144 GIM_Try, /*On fail goto*//*Label 2364*/ 106203, // Rule ID 2039 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 631:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2039, GIR_Done, // Label 2364: @106203 GIM_Try, /*On fail goto*//*Label 2365*/ 106262, // Rule ID 2042 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 633:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2042, GIR_Done, // Label 2365: @106262 GIM_Try, /*On fail goto*//*Label 2366*/ 106321, // Rule ID 2083 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i8] } 582:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2083, GIR_Done, // Label 2366: @106321 GIM_Try, /*On fail goto*//*Label 2367*/ 106380, // Rule ID 2084 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 582:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2084, GIR_Done, // Label 2367: @106380 GIM_Try, /*On fail goto*//*Label 2368*/ 106439, // Rule ID 2085 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 582:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2085, GIR_Done, // Label 2368: @106439 GIM_Try, /*On fail goto*//*Label 2369*/ 106498, // Rule ID 2086 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i8] } 583:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2086, GIR_Done, // Label 2369: @106498 GIM_Try, /*On fail goto*//*Label 2370*/ 106557, // Rule ID 2087 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 583:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2087, GIR_Done, // Label 2370: @106557 GIM_Try, /*On fail goto*//*Label 2371*/ 106616, // Rule ID 2088 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 583:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2088, GIR_Done, // Label 2371: @106616 GIM_Try, /*On fail goto*//*Label 2372*/ 106675, // Rule ID 2103 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i8] } 586:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2103, GIR_Done, // Label 2372: @106675 GIM_Try, /*On fail goto*//*Label 2373*/ 106734, // Rule ID 2104 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 586:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2104, GIR_Done, // Label 2373: @106734 GIM_Try, /*On fail goto*//*Label 2374*/ 106793, // Rule ID 2105 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 586:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2105, GIR_Done, // Label 2374: @106793 GIM_Try, /*On fail goto*//*Label 2375*/ 106852, // Rule ID 2106 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i8] } 587:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2106, GIR_Done, // Label 2375: @106852 GIM_Try, /*On fail goto*//*Label 2376*/ 106911, // Rule ID 2107 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 587:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2107, GIR_Done, // Label 2376: @106911 GIM_Try, /*On fail goto*//*Label 2377*/ 106970, // Rule ID 2108 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 587:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2108, GIR_Done, // Label 2377: @106970 GIM_Try, /*On fail goto*//*Label 2378*/ 107029, // Rule ID 2162 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i8] } 631:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2162, GIR_Done, // Label 2378: @107029 GIM_Try, /*On fail goto*//*Label 2379*/ 107088, // Rule ID 2163 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 631:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2163, GIR_Done, // Label 2379: @107088 GIM_Try, /*On fail goto*//*Label 2380*/ 107147, // Rule ID 2164 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 631:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2164, GIR_Done, // Label 2380: @107147 GIM_Try, /*On fail goto*//*Label 2381*/ 107206, // Rule ID 2172 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i8] } 633:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2172, GIR_Done, // Label 2381: @107206 GIM_Try, /*On fail goto*//*Label 2382*/ 107265, // Rule ID 2173 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 633:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2173, GIR_Done, // Label 2382: @107265 GIM_Try, /*On fail goto*//*Label 2383*/ 107324, // Rule ID 2174 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 633:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2174, GIR_Done, // Label 2383: @107324 GIM_Try, /*On fail goto*//*Label 2384*/ 107381, // Rule ID 9411 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 652:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (FCVTZSs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9411, GIR_Done, // Label 2384: @107381 GIM_Try, /*On fail goto*//*Label 2385*/ 107438, // Rule ID 9412 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 653:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (FCVTZUs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9412, GIR_Done, // Label 2385: @107438 GIM_Try, /*On fail goto*//*Label 2386*/ 107495, // Rule ID 9413 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i64] } 652:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (FCVTZSd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9413, GIR_Done, // Label 2386: @107495 GIM_Try, /*On fail goto*//*Label 2387*/ 107552, // Rule ID 9414 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i64] } 653:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (FCVTZUd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9414, GIR_Done, // Label 2387: @107552 GIM_Try, /*On fail goto*//*Label 2388*/ 107609, // Rule ID 9415 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v1i64] } 652:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (FCVTZSd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9415, GIR_Done, // Label 2388: @107609 GIM_Try, /*On fail goto*//*Label 2389*/ 107666, // Rule ID 9416 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v1i64] } 653:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (FCVTZUd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9416, GIR_Done, // Label 2389: @107666 GIM_Try, /*On fail goto*//*Label 2390*/ 107723, // Rule ID 9417 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f32] } 656:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9417, GIR_Done, // Label 2390: @107723 GIM_Try, /*On fail goto*//*Label 2391*/ 107780, // Rule ID 9418 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f64] } 656:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9418, GIR_Done, // Label 2391: @107780 GIM_Try, /*On fail goto*//*Label 2392*/ 107837, // Rule ID 9419 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v1f64] } 655:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9419, GIR_Done, // Label 2392: @107837 GIM_Try, /*On fail goto*//*Label 2393*/ 107894, // Rule ID 9420 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f64] } 655:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9420, GIR_Done, // Label 2393: @107894 GIM_Try, /*On fail goto*//*Label 2394*/ 107951, // Rule ID 9421 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v1f64] } 656:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9421, GIR_Done, // Label 2394: @107951 GIM_Try, /*On fail goto*//*Label 2395*/ 108008, // Rule ID 9422 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f32] } 655:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9422, GIR_Done, // Label 2395: @108008 GIM_Try, /*On fail goto*//*Label 2396*/ 108088, // Rule ID 9424 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f16] } 655:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[bf16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR16RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9424, GIR_Done, // Label 2396: @108088 GIM_Try, /*On fail goto*//*Label 2397*/ 108168, // Rule ID 9425 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f16] } 655:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[bf16] } FPR64:{ *:[i64] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR16RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9425, GIR_Done, // Label 2397: @108168 GIM_Try, /*On fail goto*//*Label 2398*/ 108248, // Rule ID 9427 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f16] } 656:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[bf16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR16RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9427, GIR_Done, // Label 2398: @108248 GIM_Try, /*On fail goto*//*Label 2399*/ 108328, // Rule ID 9428 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f16] } 656:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[bf16] } FPR64:{ *:[i64] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR16RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9428, GIR_Done, // Label 2399: @108328 GIM_Try, /*On fail goto*//*Label 2400*/ 108430, // Rule ID 9429 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 652:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FCVTZSh:{ *:[bf16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm), hsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZSh, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/7, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR16RegClassID, // GIR_Coverage, 9429, GIR_Done, // Label 2400: @108430 GIM_Try, /*On fail goto*//*Label 2401*/ 108532, // Rule ID 9430 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i64] } 652:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (FCVTZSh:{ *:[bf16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm), hsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZSh, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/7, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR16RegClassID, // GIR_Coverage, 9430, GIR_Done, // Label 2401: @108532 GIM_Try, /*On fail goto*//*Label 2402*/ 108634, // Rule ID 9431 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 653:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FCVTZUh:{ *:[bf16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm), hsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZUh, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/7, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR16RegClassID, // GIR_Coverage, 9431, GIR_Done, // Label 2402: @108634 GIM_Try, /*On fail goto*//*Label 2403*/ 108736, // Rule ID 9432 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i64] } 653:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (FCVTZUh:{ *:[bf16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm), hsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZUh, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/7, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR16RegClassID, // GIR_Coverage, 9432, GIR_Done, // Label 2403: @108736 GIM_Try, /*On fail goto*//*Label 2404*/ 108792, // Rule ID 2048 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 652:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2048, GIR_Done, // Label 2404: @108792 GIM_Try, /*On fail goto*//*Label 2405*/ 108848, // Rule ID 2049 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 652:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2049, GIR_Done, // Label 2405: @108848 GIM_Try, /*On fail goto*//*Label 2406*/ 108904, // Rule ID 2050 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 652:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2050, GIR_Done, // Label 2406: @108904 GIM_Try, /*On fail goto*//*Label 2407*/ 108960, // Rule ID 2051 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 652:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2051, GIR_Done, // Label 2407: @108960 GIM_Try, /*On fail goto*//*Label 2408*/ 109016, // Rule ID 2052 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i64] } 652:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2052, GIR_Done, // Label 2408: @109016 GIM_Try, /*On fail goto*//*Label 2409*/ 109072, // Rule ID 2053 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 653:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2053, GIR_Done, // Label 2409: @109072 GIM_Try, /*On fail goto*//*Label 2410*/ 109128, // Rule ID 2054 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 653:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2054, GIR_Done, // Label 2410: @109128 GIM_Try, /*On fail goto*//*Label 2411*/ 109184, // Rule ID 2055 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 653:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2055, GIR_Done, // Label 2411: @109184 GIM_Try, /*On fail goto*//*Label 2412*/ 109240, // Rule ID 2056 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 653:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2056, GIR_Done, // Label 2412: @109240 GIM_Try, /*On fail goto*//*Label 2413*/ 109296, // Rule ID 2057 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i64] } 653:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2057, GIR_Done, // Label 2413: @109296 GIM_Try, /*On fail goto*//*Label 2414*/ 109352, // Rule ID 2058 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4f16] } 655:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2058, GIR_Done, // Label 2414: @109352 GIM_Try, /*On fail goto*//*Label 2415*/ 109408, // Rule ID 2059 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8f16] } 655:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2059, GIR_Done, // Label 2415: @109408 GIM_Try, /*On fail goto*//*Label 2416*/ 109464, // Rule ID 2060 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2f32] } 655:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2060, GIR_Done, // Label 2416: @109464 GIM_Try, /*On fail goto*//*Label 2417*/ 109520, // Rule ID 2061 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4f32] } 655:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2061, GIR_Done, // Label 2417: @109520 GIM_Try, /*On fail goto*//*Label 2418*/ 109576, // Rule ID 2062 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2f64] } 655:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2062, GIR_Done, // Label 2418: @109576 GIM_Try, /*On fail goto*//*Label 2419*/ 109632, // Rule ID 2157 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4f16] } 656:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2157, GIR_Done, // Label 2419: @109632 GIM_Try, /*On fail goto*//*Label 2420*/ 109688, // Rule ID 2158 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8f16] } 656:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2158, GIR_Done, // Label 2420: @109688 GIM_Try, /*On fail goto*//*Label 2421*/ 109744, // Rule ID 2159 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2f32] } 656:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2159, GIR_Done, // Label 2421: @109744 GIM_Try, /*On fail goto*//*Label 2422*/ 109800, // Rule ID 2160 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4f32] } 656:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2160, GIR_Done, // Label 2422: @109800 GIM_Try, /*On fail goto*//*Label 2423*/ 109856, // Rule ID 2161 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2f64] } 656:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2161, GIR_Done, // Label 2423: @109856 GIM_Try, /*On fail goto*//*Label 2424*/ 109908, // Rule ID 37 // GIM_CheckFeatures, GIFBS_HasBF16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfcvtn2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8bf16] } 483:{ *:[iPTR] }, V128:{ *:[v8bf16] }:$Rd, V128:{ *:[v4f32] }:$Rn) => (BFCVTN2:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rd, V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFCVTN2, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 37, GIR_Done, // Label 2424: @109908 GIM_Try, /*On fail goto*//*Label 2425*/ 109960, // Rule ID 72 // GIM_CheckFeatures, GIFBS_HasPAuth, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ptrauth_sign_generic, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_wo_chain:{ *:[i64] } 250:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm) => (PACGA:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PACGA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 72, GIR_Done, // Label 2425: @109960 GIM_Try, /*On fail goto*//*Label 2426*/ 110012, // Rule ID 131 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32b, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 417:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32Brr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Brr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 131, GIR_Done, // Label 2426: @110012 GIM_Try, /*On fail goto*//*Label 2427*/ 110064, // Rule ID 132 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32h, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 422:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32Hrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Hrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 132, GIR_Done, // Label 2427: @110064 GIM_Try, /*On fail goto*//*Label 2428*/ 110116, // Rule ID 133 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32w, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 423:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32Wrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Wrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 133, GIR_Done, // Label 2428: @110116 GIM_Try, /*On fail goto*//*Label 2429*/ 110168, // Rule ID 134 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 424:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (CRC32Xrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Xrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 134, GIR_Done, // Label 2429: @110168 GIM_Try, /*On fail goto*//*Label 2430*/ 110220, // Rule ID 135 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32cb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 418:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32CBrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CBrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 135, GIR_Done, // Label 2430: @110220 GIM_Try, /*On fail goto*//*Label 2431*/ 110272, // Rule ID 136 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32ch, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 419:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32CHrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CHrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 136, GIR_Done, // Label 2431: @110272 GIM_Try, /*On fail goto*//*Label 2432*/ 110324, // Rule ID 137 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32cw, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 420:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32CWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 137, GIR_Done, // Label 2432: @110324 GIM_Try, /*On fail goto*//*Label 2433*/ 110376, // Rule ID 138 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32cx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 421:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (CRC32CXrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 138, GIR_Done, // Label 2433: @110376 GIM_Try, /*On fail goto*//*Label 2434*/ 110428, // Rule ID 1015 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 605:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) => (SUQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1015, GIR_Done, // Label 2434: @110428 GIM_Try, /*On fail goto*//*Label 2435*/ 110480, // Rule ID 1016 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 605:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (SUQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1016, GIR_Done, // Label 2435: @110480 GIM_Try, /*On fail goto*//*Label 2436*/ 110532, // Rule ID 1017 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 605:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) => (SUQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1017, GIR_Done, // Label 2436: @110532 GIM_Try, /*On fail goto*//*Label 2437*/ 110584, // Rule ID 1018 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 605:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) => (SUQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1018, GIR_Done, // Label 2437: @110584 GIM_Try, /*On fail goto*//*Label 2438*/ 110636, // Rule ID 1019 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 605:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) => (SUQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1019, GIR_Done, // Label 2438: @110636 GIM_Try, /*On fail goto*//*Label 2439*/ 110688, // Rule ID 1020 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 605:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (SUQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1020, GIR_Done, // Label 2439: @110688 GIM_Try, /*On fail goto*//*Label 2440*/ 110740, // Rule ID 1021 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 605:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) => (SUQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1021, GIR_Done, // Label 2440: @110740 GIM_Try, /*On fail goto*//*Label 2441*/ 110792, // Rule ID 1063 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 644:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) => (USQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1063, GIR_Done, // Label 2441: @110792 GIM_Try, /*On fail goto*//*Label 2442*/ 110844, // Rule ID 1064 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 644:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (USQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1064, GIR_Done, // Label 2442: @110844 GIM_Try, /*On fail goto*//*Label 2443*/ 110896, // Rule ID 1065 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 644:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) => (USQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1065, GIR_Done, // Label 2443: @110896 GIM_Try, /*On fail goto*//*Label 2444*/ 110948, // Rule ID 1066 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 644:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) => (USQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1066, GIR_Done, // Label 2444: @110948 GIM_Try, /*On fail goto*//*Label 2445*/ 111000, // Rule ID 1067 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 644:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) => (USQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1067, GIR_Done, // Label 2445: @111000 GIM_Try, /*On fail goto*//*Label 2446*/ 111052, // Rule ID 1068 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 644:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (USQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1068, GIR_Done, // Label 2446: @111052 GIM_Try, /*On fail goto*//*Label 2447*/ 111104, // Rule ID 1069 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 644:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) => (USQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1069, GIR_Done, // Label 2447: @111104 GIM_Try, /*On fail goto*//*Label 2448*/ 111156, // Rule ID 1081 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 480:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ADDPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1081, GIR_Done, // Label 2448: @111156 GIM_Try, /*On fail goto*//*Label 2449*/ 111208, // Rule ID 1083 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 480:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ADDPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1083, GIR_Done, // Label 2449: @111208 GIM_Try, /*On fail goto*//*Label 2450*/ 111260, // Rule ID 1085 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 480:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ADDPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1085, GIR_Done, // Label 2450: @111260 GIM_Try, /*On fail goto*//*Label 2451*/ 111312, // Rule ID 1087 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 480:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ADDPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1087, GIR_Done, // Label 2451: @111312 GIM_Try, /*On fail goto*//*Label 2452*/ 111364, // Rule ID 1089 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 480:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ADDPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1089, GIR_Done, // Label 2452: @111364 GIM_Try, /*On fail goto*//*Label 2453*/ 111416, // Rule ID 1091 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 480:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ADDPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1091, GIR_Done, // Label 2453: @111416 GIM_Try, /*On fail goto*//*Label 2454*/ 111468, // Rule ID 1093 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 480:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ADDPv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1093, GIR_Done, // Label 2454: @111468 GIM_Try, /*On fail goto*//*Label 2455*/ 111520, // Rule ID 1136 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 489:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FABDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1136, GIR_Done, // Label 2455: @111520 GIM_Try, /*On fail goto*//*Label 2456*/ 111572, // Rule ID 1137 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 489:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FABDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1137, GIR_Done, // Label 2456: @111572 GIM_Try, /*On fail goto*//*Label 2457*/ 111624, // Rule ID 1138 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 489:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FABDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1138, GIR_Done, // Label 2457: @111624 GIM_Try, /*On fail goto*//*Label 2458*/ 111676, // Rule ID 1139 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 489:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FABDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1139, GIR_Done, // Label 2458: @111676 GIM_Try, /*On fail goto*//*Label 2459*/ 111728, // Rule ID 1140 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 489:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FABDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1140, GIR_Done, // Label 2459: @111728 GIM_Try, /*On fail goto*//*Label 2460*/ 111780, // Rule ID 1141 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 490:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FACGEv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1141, GIR_Done, // Label 2460: @111780 GIM_Try, /*On fail goto*//*Label 2461*/ 111832, // Rule ID 1142 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 490:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FACGEv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1142, GIR_Done, // Label 2461: @111832 GIM_Try, /*On fail goto*//*Label 2462*/ 111884, // Rule ID 1143 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 490:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FACGEv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1143, GIR_Done, // Label 2462: @111884 GIM_Try, /*On fail goto*//*Label 2463*/ 111936, // Rule ID 1144 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 490:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FACGEv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1144, GIR_Done, // Label 2463: @111936 GIM_Try, /*On fail goto*//*Label 2464*/ 111988, // Rule ID 1145 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 490:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FACGEv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1145, GIR_Done, // Label 2464: @111988 GIM_Try, /*On fail goto*//*Label 2465*/ 112040, // Rule ID 1146 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 491:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FACGTv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1146, GIR_Done, // Label 2465: @112040 GIM_Try, /*On fail goto*//*Label 2466*/ 112092, // Rule ID 1147 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 491:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FACGTv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1147, GIR_Done, // Label 2466: @112092 GIM_Try, /*On fail goto*//*Label 2467*/ 112144, // Rule ID 1148 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 491:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FACGTv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1148, GIR_Done, // Label 2467: @112144 GIM_Try, /*On fail goto*//*Label 2468*/ 112196, // Rule ID 1149 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 491:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FACGTv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1149, GIR_Done, // Label 2468: @112196 GIM_Try, /*On fail goto*//*Label 2469*/ 112248, // Rule ID 1150 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 491:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FACGTv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1150, GIR_Done, // Label 2469: @112248 GIM_Try, /*On fail goto*//*Label 2470*/ 112300, // Rule ID 1152 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 492:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FADDPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1152, GIR_Done, // Label 2470: @112300 GIM_Try, /*On fail goto*//*Label 2471*/ 112352, // Rule ID 1154 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 492:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FADDPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1154, GIR_Done, // Label 2471: @112352 GIM_Try, /*On fail goto*//*Label 2472*/ 112404, // Rule ID 1156 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 492:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FADDPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1156, GIR_Done, // Label 2472: @112404 GIM_Try, /*On fail goto*//*Label 2473*/ 112456, // Rule ID 1158 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 492:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FADDPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1158, GIR_Done, // Label 2473: @112456 GIM_Try, /*On fail goto*//*Label 2474*/ 112508, // Rule ID 1160 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 492:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FADDPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1160, GIR_Done, // Label 2474: @112508 GIM_Try, /*On fail goto*//*Label 2475*/ 112560, // Rule ID 1196 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 507:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXNMPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1196, GIR_Done, // Label 2475: @112560 GIM_Try, /*On fail goto*//*Label 2476*/ 112612, // Rule ID 1197 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 507:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXNMPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1197, GIR_Done, // Label 2476: @112612 GIM_Try, /*On fail goto*//*Label 2477*/ 112664, // Rule ID 1198 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 507:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXNMPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1198, GIR_Done, // Label 2477: @112664 GIM_Try, /*On fail goto*//*Label 2478*/ 112716, // Rule ID 1199 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 507:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXNMPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1199, GIR_Done, // Label 2478: @112716 GIM_Try, /*On fail goto*//*Label 2479*/ 112768, // Rule ID 1200 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 507:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXNMPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1200, GIR_Done, // Label 2479: @112768 GIM_Try, /*On fail goto*//*Label 2480*/ 112820, // Rule ID 1211 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 509:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1211, GIR_Done, // Label 2480: @112820 GIM_Try, /*On fail goto*//*Label 2481*/ 112872, // Rule ID 1212 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 509:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1212, GIR_Done, // Label 2481: @112872 GIM_Try, /*On fail goto*//*Label 2482*/ 112924, // Rule ID 1213 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 509:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1213, GIR_Done, // Label 2482: @112924 GIM_Try, /*On fail goto*//*Label 2483*/ 112976, // Rule ID 1214 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 509:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1214, GIR_Done, // Label 2483: @112976 GIM_Try, /*On fail goto*//*Label 2484*/ 113028, // Rule ID 1215 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 509:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1215, GIR_Done, // Label 2484: @113028 GIM_Try, /*On fail goto*//*Label 2485*/ 113080, // Rule ID 1226 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 513:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINNMPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1226, GIR_Done, // Label 2485: @113080 GIM_Try, /*On fail goto*//*Label 2486*/ 113132, // Rule ID 1227 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 513:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINNMPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1227, GIR_Done, // Label 2486: @113132 GIM_Try, /*On fail goto*//*Label 2487*/ 113184, // Rule ID 1228 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 513:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINNMPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1228, GIR_Done, // Label 2487: @113184 GIM_Try, /*On fail goto*//*Label 2488*/ 113236, // Rule ID 1229 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 513:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINNMPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1229, GIR_Done, // Label 2488: @113236 GIM_Try, /*On fail goto*//*Label 2489*/ 113288, // Rule ID 1230 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 513:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINNMPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1230, GIR_Done, // Label 2489: @113288 GIM_Try, /*On fail goto*//*Label 2490*/ 113340, // Rule ID 1241 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 515:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1241, GIR_Done, // Label 2490: @113340 GIM_Try, /*On fail goto*//*Label 2491*/ 113392, // Rule ID 1242 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 515:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1242, GIR_Done, // Label 2491: @113392 GIM_Try, /*On fail goto*//*Label 2492*/ 113444, // Rule ID 1243 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 515:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1243, GIR_Done, // Label 2492: @113444 GIM_Try, /*On fail goto*//*Label 2493*/ 113496, // Rule ID 1244 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 515:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1244, GIR_Done, // Label 2493: @113496 GIM_Try, /*On fail goto*//*Label 2494*/ 113548, // Rule ID 1245 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 515:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1245, GIR_Done, // Label 2494: @113548 GIM_Try, /*On fail goto*//*Label 2495*/ 113600, // Rule ID 1276 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 521:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMULXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1276, GIR_Done, // Label 2495: @113600 GIM_Try, /*On fail goto*//*Label 2496*/ 113652, // Rule ID 1277 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 521:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMULXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1277, GIR_Done, // Label 2496: @113652 GIM_Try, /*On fail goto*//*Label 2497*/ 113704, // Rule ID 1278 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 521:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMULXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1278, GIR_Done, // Label 2497: @113704 GIM_Try, /*On fail goto*//*Label 2498*/ 113756, // Rule ID 1279 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 521:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMULXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1279, GIR_Done, // Label 2498: @113756 GIM_Try, /*On fail goto*//*Label 2499*/ 113808, // Rule ID 1280 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 521:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMULXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1280, GIR_Done, // Label 2499: @113808 GIM_Try, /*On fail goto*//*Label 2500*/ 113860, // Rule ID 1291 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 523:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FRECPSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1291, GIR_Done, // Label 2500: @113860 GIM_Try, /*On fail goto*//*Label 2501*/ 113912, // Rule ID 1292 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 523:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FRECPSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1292, GIR_Done, // Label 2501: @113912 GIM_Try, /*On fail goto*//*Label 2502*/ 113964, // Rule ID 1293 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 523:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FRECPSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1293, GIR_Done, // Label 2502: @113964 GIM_Try, /*On fail goto*//*Label 2503*/ 114016, // Rule ID 1294 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 523:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FRECPSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1294, GIR_Done, // Label 2503: @114016 GIM_Try, /*On fail goto*//*Label 2504*/ 114068, // Rule ID 1295 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 523:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FRECPSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1295, GIR_Done, // Label 2504: @114068 GIM_Try, /*On fail goto*//*Label 2505*/ 114120, // Rule ID 1296 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 530:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FRSQRTSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1296, GIR_Done, // Label 2505: @114120 GIM_Try, /*On fail goto*//*Label 2506*/ 114172, // Rule ID 1297 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 530:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FRSQRTSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1297, GIR_Done, // Label 2506: @114172 GIM_Try, /*On fail goto*//*Label 2507*/ 114224, // Rule ID 1298 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 530:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FRSQRTSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1298, GIR_Done, // Label 2507: @114224 GIM_Try, /*On fail goto*//*Label 2508*/ 114276, // Rule ID 1299 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 530:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FRSQRTSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1299, GIR_Done, // Label 2508: @114276 GIM_Try, /*On fail goto*//*Label 2509*/ 114328, // Rule ID 1300 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 530:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FRSQRTSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1300, GIR_Done, // Label 2509: @114328 GIM_Try, /*On fail goto*//*Label 2510*/ 114380, // Rule ID 1317 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_pmul, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 543:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (PMULv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1317, GIR_Done, // Label 2510: @114380 GIM_Try, /*On fail goto*//*Label 2511*/ 114432, // Rule ID 1318 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_pmul, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 543:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (PMULv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1318, GIR_Done, // Label 2511: @114432 GIM_Try, /*On fail goto*//*Label 2512*/ 114484, // Rule ID 1332 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 549:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SABDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1332, GIR_Done, // Label 2512: @114484 GIM_Try, /*On fail goto*//*Label 2513*/ 114536, // Rule ID 1334 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 549:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SABDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1334, GIR_Done, // Label 2513: @114536 GIM_Try, /*On fail goto*//*Label 2514*/ 114588, // Rule ID 1336 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 549:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SABDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1336, GIR_Done, // Label 2514: @114588 GIM_Try, /*On fail goto*//*Label 2515*/ 114640, // Rule ID 1338 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 549:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SABDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1338, GIR_Done, // Label 2515: @114640 GIM_Try, /*On fail goto*//*Label 2516*/ 114692, // Rule ID 1340 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 549:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SABDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1340, GIR_Done, // Label 2516: @114692 GIM_Try, /*On fail goto*//*Label 2517*/ 114744, // Rule ID 1342 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 549:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SABDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1342, GIR_Done, // Label 2517: @114744 GIM_Try, /*On fail goto*//*Label 2518*/ 114796, // Rule ID 1349 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 559:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SHSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1349, GIR_Done, // Label 2518: @114796 GIM_Try, /*On fail goto*//*Label 2519*/ 114848, // Rule ID 1350 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 559:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SHSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1350, GIR_Done, // Label 2519: @114848 GIM_Try, /*On fail goto*//*Label 2520*/ 114900, // Rule ID 1351 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 559:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SHSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1351, GIR_Done, // Label 2520: @114900 GIM_Try, /*On fail goto*//*Label 2521*/ 114952, // Rule ID 1352 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 559:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SHSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1352, GIR_Done, // Label 2521: @114952 GIM_Try, /*On fail goto*//*Label 2522*/ 115004, // Rule ID 1353 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 559:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SHSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1353, GIR_Done, // Label 2522: @115004 GIM_Try, /*On fail goto*//*Label 2523*/ 115056, // Rule ID 1354 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 559:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1354, GIR_Done, // Label 2523: @115056 GIM_Try, /*On fail goto*//*Label 2524*/ 115108, // Rule ID 1355 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 561:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMAXPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1355, GIR_Done, // Label 2524: @115108 GIM_Try, /*On fail goto*//*Label 2525*/ 115160, // Rule ID 1356 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 561:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMAXPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1356, GIR_Done, // Label 2525: @115160 GIM_Try, /*On fail goto*//*Label 2526*/ 115212, // Rule ID 1357 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 561:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMAXPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1357, GIR_Done, // Label 2526: @115212 GIM_Try, /*On fail goto*//*Label 2527*/ 115264, // Rule ID 1358 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 561:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMAXPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1358, GIR_Done, // Label 2527: @115264 GIM_Try, /*On fail goto*//*Label 2528*/ 115316, // Rule ID 1359 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 561:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMAXPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1359, GIR_Done, // Label 2528: @115316 GIM_Try, /*On fail goto*//*Label 2529*/ 115368, // Rule ID 1360 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 561:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMAXPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1360, GIR_Done, // Label 2529: @115368 GIM_Try, /*On fail goto*//*Label 2530*/ 115420, // Rule ID 1367 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 564:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMINPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1367, GIR_Done, // Label 2530: @115420 GIM_Try, /*On fail goto*//*Label 2531*/ 115472, // Rule ID 1368 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 564:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMINPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1368, GIR_Done, // Label 2531: @115472 GIM_Try, /*On fail goto*//*Label 2532*/ 115524, // Rule ID 1369 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 564:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMINPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1369, GIR_Done, // Label 2532: @115524 GIM_Try, /*On fail goto*//*Label 2533*/ 115576, // Rule ID 1370 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 564:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMINPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1370, GIR_Done, // Label 2533: @115576 GIM_Try, /*On fail goto*//*Label 2534*/ 115628, // Rule ID 1371 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 564:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMINPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1371, GIR_Done, // Label 2534: @115628 GIM_Try, /*On fail goto*//*Label 2535*/ 115680, // Rule ID 1372 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 564:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMINPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1372, GIR_Done, // Label 2535: @115680 GIM_Try, /*On fail goto*//*Label 2536*/ 115732, // Rule ID 1379 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 569:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1379, GIR_Done, // Label 2536: @115732 GIM_Try, /*On fail goto*//*Label 2537*/ 115784, // Rule ID 1380 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 569:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1380, GIR_Done, // Label 2537: @115784 GIM_Try, /*On fail goto*//*Label 2538*/ 115836, // Rule ID 1381 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 569:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1381, GIR_Done, // Label 2538: @115836 GIM_Try, /*On fail goto*//*Label 2539*/ 115888, // Rule ID 1382 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 569:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1382, GIR_Done, // Label 2539: @115888 GIM_Try, /*On fail goto*//*Label 2540*/ 115940, // Rule ID 1383 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 569:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1383, GIR_Done, // Label 2540: @115940 GIM_Try, /*On fail goto*//*Label 2541*/ 115992, // Rule ID 1384 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 569:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1384, GIR_Done, // Label 2541: @115992 GIM_Try, /*On fail goto*//*Label 2542*/ 116044, // Rule ID 1385 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 569:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1385, GIR_Done, // Label 2542: @116044 GIM_Try, /*On fail goto*//*Label 2543*/ 116096, // Rule ID 1386 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 570:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQDMULHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1386, GIR_Done, // Label 2543: @116096 GIM_Try, /*On fail goto*//*Label 2544*/ 116148, // Rule ID 1387 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 570:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQDMULHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1387, GIR_Done, // Label 2544: @116148 GIM_Try, /*On fail goto*//*Label 2545*/ 116200, // Rule ID 1388 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 570:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQDMULHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1388, GIR_Done, // Label 2545: @116200 GIM_Try, /*On fail goto*//*Label 2546*/ 116252, // Rule ID 1389 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 570:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQDMULHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1389, GIR_Done, // Label 2546: @116252 GIM_Try, /*On fail goto*//*Label 2547*/ 116304, // Rule ID 1390 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 578:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQRDMULHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1390, GIR_Done, // Label 2547: @116304 GIM_Try, /*On fail goto*//*Label 2548*/ 116356, // Rule ID 1391 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 578:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQRDMULHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1391, GIR_Done, // Label 2548: @116356 GIM_Try, /*On fail goto*//*Label 2549*/ 116408, // Rule ID 1392 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 578:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQRDMULHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1392, GIR_Done, // Label 2549: @116408 GIM_Try, /*On fail goto*//*Label 2550*/ 116460, // Rule ID 1393 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 578:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQRDMULHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1393, GIR_Done, // Label 2550: @116460 GIM_Try, /*On fail goto*//*Label 2551*/ 116512, // Rule ID 1394 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 581:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1394, GIR_Done, // Label 2551: @116512 GIM_Try, /*On fail goto*//*Label 2552*/ 116564, // Rule ID 1395 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 581:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1395, GIR_Done, // Label 2552: @116564 GIM_Try, /*On fail goto*//*Label 2553*/ 116616, // Rule ID 1396 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 581:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1396, GIR_Done, // Label 2553: @116616 GIM_Try, /*On fail goto*//*Label 2554*/ 116668, // Rule ID 1397 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 581:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1397, GIR_Done, // Label 2554: @116668 GIM_Try, /*On fail goto*//*Label 2555*/ 116720, // Rule ID 1398 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 581:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1398, GIR_Done, // Label 2555: @116720 GIM_Try, /*On fail goto*//*Label 2556*/ 116772, // Rule ID 1399 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 581:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1399, GIR_Done, // Label 2556: @116772 GIM_Try, /*On fail goto*//*Label 2557*/ 116824, // Rule ID 1400 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 581:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1400, GIR_Done, // Label 2557: @116824 GIM_Try, /*On fail goto*//*Label 2558*/ 116876, // Rule ID 1401 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 584:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1401, GIR_Done, // Label 2558: @116876 GIM_Try, /*On fail goto*//*Label 2559*/ 116928, // Rule ID 1402 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 584:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1402, GIR_Done, // Label 2559: @116928 GIM_Try, /*On fail goto*//*Label 2560*/ 116980, // Rule ID 1403 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 584:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1403, GIR_Done, // Label 2560: @116980 GIM_Try, /*On fail goto*//*Label 2561*/ 117032, // Rule ID 1404 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 584:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1404, GIR_Done, // Label 2561: @117032 GIM_Try, /*On fail goto*//*Label 2562*/ 117084, // Rule ID 1405 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 584:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1405, GIR_Done, // Label 2562: @117084 GIM_Try, /*On fail goto*//*Label 2563*/ 117136, // Rule ID 1406 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 584:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1406, GIR_Done, // Label 2563: @117136 GIM_Try, /*On fail goto*//*Label 2564*/ 117188, // Rule ID 1407 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 584:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1407, GIR_Done, // Label 2564: @117188 GIM_Try, /*On fail goto*//*Label 2565*/ 117240, // Rule ID 1408 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 588:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1408, GIR_Done, // Label 2565: @117240 GIM_Try, /*On fail goto*//*Label 2566*/ 117292, // Rule ID 1409 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 588:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1409, GIR_Done, // Label 2566: @117292 GIM_Try, /*On fail goto*//*Label 2567*/ 117344, // Rule ID 1410 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 588:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1410, GIR_Done, // Label 2567: @117344 GIM_Try, /*On fail goto*//*Label 2568*/ 117396, // Rule ID 1411 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 588:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1411, GIR_Done, // Label 2568: @117396 GIM_Try, /*On fail goto*//*Label 2569*/ 117448, // Rule ID 1412 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 588:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1412, GIR_Done, // Label 2569: @117448 GIM_Try, /*On fail goto*//*Label 2570*/ 117500, // Rule ID 1413 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 588:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1413, GIR_Done, // Label 2570: @117500 GIM_Try, /*On fail goto*//*Label 2571*/ 117552, // Rule ID 1414 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 588:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1414, GIR_Done, // Label 2571: @117552 GIM_Try, /*On fail goto*//*Label 2572*/ 117604, // Rule ID 1421 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 592:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1421, GIR_Done, // Label 2572: @117604 GIM_Try, /*On fail goto*//*Label 2573*/ 117656, // Rule ID 1422 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 592:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1422, GIR_Done, // Label 2573: @117656 GIM_Try, /*On fail goto*//*Label 2574*/ 117708, // Rule ID 1423 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 592:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1423, GIR_Done, // Label 2574: @117708 GIM_Try, /*On fail goto*//*Label 2575*/ 117760, // Rule ID 1424 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 592:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1424, GIR_Done, // Label 2575: @117760 GIM_Try, /*On fail goto*//*Label 2576*/ 117812, // Rule ID 1425 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 592:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1425, GIR_Done, // Label 2576: @117812 GIM_Try, /*On fail goto*//*Label 2577*/ 117864, // Rule ID 1426 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 592:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1426, GIR_Done, // Label 2577: @117864 GIM_Try, /*On fail goto*//*Label 2578*/ 117916, // Rule ID 1427 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 592:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1427, GIR_Done, // Label 2578: @117916 GIM_Try, /*On fail goto*//*Label 2579*/ 117968, // Rule ID 1428 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 593:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1428, GIR_Done, // Label 2579: @117968 GIM_Try, /*On fail goto*//*Label 2580*/ 118020, // Rule ID 1429 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 593:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1429, GIR_Done, // Label 2580: @118020 GIM_Try, /*On fail goto*//*Label 2581*/ 118072, // Rule ID 1430 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 593:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1430, GIR_Done, // Label 2581: @118072 GIM_Try, /*On fail goto*//*Label 2582*/ 118124, // Rule ID 1431 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 593:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1431, GIR_Done, // Label 2582: @118124 GIM_Try, /*On fail goto*//*Label 2583*/ 118176, // Rule ID 1432 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 593:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1432, GIR_Done, // Label 2583: @118176 GIM_Try, /*On fail goto*//*Label 2584*/ 118228, // Rule ID 1433 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 593:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1433, GIR_Done, // Label 2584: @118228 GIM_Try, /*On fail goto*//*Label 2585*/ 118280, // Rule ID 1434 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 593:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1434, GIR_Done, // Label 2585: @118280 GIM_Try, /*On fail goto*//*Label 2586*/ 118332, // Rule ID 1455 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 614:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UABDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1455, GIR_Done, // Label 2586: @118332 GIM_Try, /*On fail goto*//*Label 2587*/ 118384, // Rule ID 1457 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 614:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UABDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1457, GIR_Done, // Label 2587: @118384 GIM_Try, /*On fail goto*//*Label 2588*/ 118436, // Rule ID 1459 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 614:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UABDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1459, GIR_Done, // Label 2588: @118436 GIM_Try, /*On fail goto*//*Label 2589*/ 118488, // Rule ID 1461 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 614:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UABDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1461, GIR_Done, // Label 2589: @118488 GIM_Try, /*On fail goto*//*Label 2590*/ 118540, // Rule ID 1463 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 614:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UABDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1463, GIR_Done, // Label 2590: @118540 GIM_Try, /*On fail goto*//*Label 2591*/ 118592, // Rule ID 1465 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 614:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UABDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1465, GIR_Done, // Label 2591: @118592 GIM_Try, /*On fail goto*//*Label 2592*/ 118644, // Rule ID 1472 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 620:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UHSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1472, GIR_Done, // Label 2592: @118644 GIM_Try, /*On fail goto*//*Label 2593*/ 118696, // Rule ID 1473 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 620:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UHSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1473, GIR_Done, // Label 2593: @118696 GIM_Try, /*On fail goto*//*Label 2594*/ 118748, // Rule ID 1474 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 620:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UHSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1474, GIR_Done, // Label 2594: @118748 GIM_Try, /*On fail goto*//*Label 2595*/ 118800, // Rule ID 1475 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 620:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UHSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1475, GIR_Done, // Label 2595: @118800 GIM_Try, /*On fail goto*//*Label 2596*/ 118852, // Rule ID 1476 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 620:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UHSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1476, GIR_Done, // Label 2596: @118852 GIM_Try, /*On fail goto*//*Label 2597*/ 118904, // Rule ID 1477 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 620:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UHSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1477, GIR_Done, // Label 2597: @118904 GIM_Try, /*On fail goto*//*Label 2598*/ 118956, // Rule ID 1478 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 622:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMAXPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1478, GIR_Done, // Label 2598: @118956 GIM_Try, /*On fail goto*//*Label 2599*/ 119008, // Rule ID 1479 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 622:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMAXPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1479, GIR_Done, // Label 2599: @119008 GIM_Try, /*On fail goto*//*Label 2600*/ 119060, // Rule ID 1480 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 622:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMAXPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1480, GIR_Done, // Label 2600: @119060 GIM_Try, /*On fail goto*//*Label 2601*/ 119112, // Rule ID 1481 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 622:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMAXPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1481, GIR_Done, // Label 2601: @119112 GIM_Try, /*On fail goto*//*Label 2602*/ 119164, // Rule ID 1482 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 622:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMAXPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1482, GIR_Done, // Label 2602: @119164 GIM_Try, /*On fail goto*//*Label 2603*/ 119216, // Rule ID 1483 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 622:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMAXPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1483, GIR_Done, // Label 2603: @119216 GIM_Try, /*On fail goto*//*Label 2604*/ 119268, // Rule ID 1490 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 625:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMINPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1490, GIR_Done, // Label 2604: @119268 GIM_Try, /*On fail goto*//*Label 2605*/ 119320, // Rule ID 1491 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 625:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMINPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1491, GIR_Done, // Label 2605: @119320 GIM_Try, /*On fail goto*//*Label 2606*/ 119372, // Rule ID 1492 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 625:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMINPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1492, GIR_Done, // Label 2606: @119372 GIM_Try, /*On fail goto*//*Label 2607*/ 119424, // Rule ID 1493 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 625:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMINPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1493, GIR_Done, // Label 2607: @119424 GIM_Try, /*On fail goto*//*Label 2608*/ 119476, // Rule ID 1494 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 625:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMINPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1494, GIR_Done, // Label 2608: @119476 GIM_Try, /*On fail goto*//*Label 2609*/ 119528, // Rule ID 1495 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 625:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMINPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1495, GIR_Done, // Label 2609: @119528 GIM_Try, /*On fail goto*//*Label 2610*/ 119580, // Rule ID 1502 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 629:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1502, GIR_Done, // Label 2610: @119580 GIM_Try, /*On fail goto*//*Label 2611*/ 119632, // Rule ID 1503 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 629:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1503, GIR_Done, // Label 2611: @119632 GIM_Try, /*On fail goto*//*Label 2612*/ 119684, // Rule ID 1504 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 629:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1504, GIR_Done, // Label 2612: @119684 GIM_Try, /*On fail goto*//*Label 2613*/ 119736, // Rule ID 1505 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 629:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1505, GIR_Done, // Label 2613: @119736 GIM_Try, /*On fail goto*//*Label 2614*/ 119788, // Rule ID 1506 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 629:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1506, GIR_Done, // Label 2614: @119788 GIM_Try, /*On fail goto*//*Label 2615*/ 119840, // Rule ID 1507 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 629:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1507, GIR_Done, // Label 2615: @119840 GIM_Try, /*On fail goto*//*Label 2616*/ 119892, // Rule ID 1508 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 629:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1508, GIR_Done, // Label 2616: @119892 GIM_Try, /*On fail goto*//*Label 2617*/ 119944, // Rule ID 1509 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 630:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1509, GIR_Done, // Label 2617: @119944 GIM_Try, /*On fail goto*//*Label 2618*/ 119996, // Rule ID 1510 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 630:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1510, GIR_Done, // Label 2618: @119996 GIM_Try, /*On fail goto*//*Label 2619*/ 120048, // Rule ID 1511 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 630:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1511, GIR_Done, // Label 2619: @120048 GIM_Try, /*On fail goto*//*Label 2620*/ 120100, // Rule ID 1512 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 630:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1512, GIR_Done, // Label 2620: @120100 GIM_Try, /*On fail goto*//*Label 2621*/ 120152, // Rule ID 1513 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 630:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1513, GIR_Done, // Label 2621: @120152 GIM_Try, /*On fail goto*//*Label 2622*/ 120204, // Rule ID 1514 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 630:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1514, GIR_Done, // Label 2622: @120204 GIM_Try, /*On fail goto*//*Label 2623*/ 120256, // Rule ID 1515 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 630:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1515, GIR_Done, // Label 2623: @120256 GIM_Try, /*On fail goto*//*Label 2624*/ 120308, // Rule ID 1516 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 632:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1516, GIR_Done, // Label 2624: @120308 GIM_Try, /*On fail goto*//*Label 2625*/ 120360, // Rule ID 1517 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 632:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1517, GIR_Done, // Label 2625: @120360 GIM_Try, /*On fail goto*//*Label 2626*/ 120412, // Rule ID 1518 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 632:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1518, GIR_Done, // Label 2626: @120412 GIM_Try, /*On fail goto*//*Label 2627*/ 120464, // Rule ID 1519 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 632:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1519, GIR_Done, // Label 2627: @120464 GIM_Try, /*On fail goto*//*Label 2628*/ 120516, // Rule ID 1520 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 632:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1520, GIR_Done, // Label 2628: @120516 GIM_Try, /*On fail goto*//*Label 2629*/ 120568, // Rule ID 1521 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 632:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1521, GIR_Done, // Label 2629: @120568 GIM_Try, /*On fail goto*//*Label 2630*/ 120620, // Rule ID 1522 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 632:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1522, GIR_Done, // Label 2630: @120620 GIM_Try, /*On fail goto*//*Label 2631*/ 120672, // Rule ID 1523 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 634:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1523, GIR_Done, // Label 2631: @120672 GIM_Try, /*On fail goto*//*Label 2632*/ 120724, // Rule ID 1524 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 634:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1524, GIR_Done, // Label 2632: @120724 GIM_Try, /*On fail goto*//*Label 2633*/ 120776, // Rule ID 1525 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 634:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1525, GIR_Done, // Label 2633: @120776 GIM_Try, /*On fail goto*//*Label 2634*/ 120828, // Rule ID 1526 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 634:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1526, GIR_Done, // Label 2634: @120828 GIM_Try, /*On fail goto*//*Label 2635*/ 120880, // Rule ID 1527 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 634:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1527, GIR_Done, // Label 2635: @120880 GIM_Try, /*On fail goto*//*Label 2636*/ 120932, // Rule ID 1528 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 634:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1528, GIR_Done, // Label 2636: @120932 GIM_Try, /*On fail goto*//*Label 2637*/ 120984, // Rule ID 1529 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 634:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1529, GIR_Done, // Label 2637: @120984 GIM_Try, /*On fail goto*//*Label 2638*/ 121036, // Rule ID 1536 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 638:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (URSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1536, GIR_Done, // Label 2638: @121036 GIM_Try, /*On fail goto*//*Label 2639*/ 121088, // Rule ID 1537 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 638:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (URSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1537, GIR_Done, // Label 2639: @121088 GIM_Try, /*On fail goto*//*Label 2640*/ 121140, // Rule ID 1538 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 638:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (URSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1538, GIR_Done, // Label 2640: @121140 GIM_Try, /*On fail goto*//*Label 2641*/ 121192, // Rule ID 1539 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 638:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (URSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1539, GIR_Done, // Label 2641: @121192 GIM_Try, /*On fail goto*//*Label 2642*/ 121244, // Rule ID 1540 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 638:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (URSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1540, GIR_Done, // Label 2642: @121244 GIM_Try, /*On fail goto*//*Label 2643*/ 121296, // Rule ID 1541 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 638:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (URSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1541, GIR_Done, // Label 2643: @121296 GIM_Try, /*On fail goto*//*Label 2644*/ 121348, // Rule ID 1542 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 638:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (URSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1542, GIR_Done, // Label 2644: @121348 GIM_Try, /*On fail goto*//*Label 2645*/ 121400, // Rule ID 1543 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 641:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (USHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1543, GIR_Done, // Label 2645: @121400 GIM_Try, /*On fail goto*//*Label 2646*/ 121452, // Rule ID 1544 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 641:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (USHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1544, GIR_Done, // Label 2646: @121452 GIM_Try, /*On fail goto*//*Label 2647*/ 121504, // Rule ID 1545 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 641:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (USHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1545, GIR_Done, // Label 2647: @121504 GIM_Try, /*On fail goto*//*Label 2648*/ 121556, // Rule ID 1546 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 641:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (USHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1546, GIR_Done, // Label 2648: @121556 GIM_Try, /*On fail goto*//*Label 2649*/ 121608, // Rule ID 1547 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 641:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (USHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1547, GIR_Done, // Label 2649: @121608 GIM_Try, /*On fail goto*//*Label 2650*/ 121660, // Rule ID 1548 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 641:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (USHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1548, GIR_Done, // Label 2650: @121660 GIM_Try, /*On fail goto*//*Label 2651*/ 121712, // Rule ID 1549 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 641:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (USHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1549, GIR_Done, // Label 2651: @121712 GIM_Try, /*On fail goto*//*Label 2652*/ 121764, // Rule ID 1579 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 667:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FABD64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1579, GIR_Done, // Label 2652: @121764 GIM_Try, /*On fail goto*//*Label 2653*/ 121816, // Rule ID 1580 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 667:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FABD32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1580, GIR_Done, // Label 2653: @121816 GIM_Try, /*On fail goto*//*Label 2654*/ 121868, // Rule ID 1581 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 667:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FABD16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1581, GIR_Done, // Label 2654: @121868 GIM_Try, /*On fail goto*//*Label 2655*/ 121920, // Rule ID 1582 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 490:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FACGE64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGE64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1582, GIR_Done, // Label 2655: @121920 GIM_Try, /*On fail goto*//*Label 2656*/ 121972, // Rule ID 1583 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 490:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FACGE32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGE32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1583, GIR_Done, // Label 2656: @121972 GIM_Try, /*On fail goto*//*Label 2657*/ 122024, // Rule ID 1584 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 491:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FACGT64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGT64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1584, GIR_Done, // Label 2657: @122024 GIM_Try, /*On fail goto*//*Label 2658*/ 122076, // Rule ID 1585 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 491:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FACGT32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGT32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1585, GIR_Done, // Label 2658: @122076 GIM_Try, /*On fail goto*//*Label 2659*/ 122128, // Rule ID 1592 // GIM_CheckFeatures, GIFBS_HasNEONorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 521:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMULX64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1592, GIR_Done, // Label 2659: @122128 GIM_Try, /*On fail goto*//*Label 2660*/ 122180, // Rule ID 1593 // GIM_CheckFeatures, GIFBS_HasNEONorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 521:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMULX32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1593, GIR_Done, // Label 2660: @122180 GIM_Try, /*On fail goto*//*Label 2661*/ 122232, // Rule ID 1594 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEONorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 521:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMULX16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1594, GIR_Done, // Label 2661: @122232 GIM_Try, /*On fail goto*//*Label 2662*/ 122284, // Rule ID 1595 // GIM_CheckFeatures, GIFBS_HasNEONorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 523:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FRECPS64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1595, GIR_Done, // Label 2662: @122284 GIM_Try, /*On fail goto*//*Label 2663*/ 122336, // Rule ID 1596 // GIM_CheckFeatures, GIFBS_HasNEONorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 523:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FRECPS32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1596, GIR_Done, // Label 2663: @122336 GIM_Try, /*On fail goto*//*Label 2664*/ 122388, // Rule ID 1597 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEONorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 523:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FRECPS16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1597, GIR_Done, // Label 2664: @122388 GIM_Try, /*On fail goto*//*Label 2665*/ 122440, // Rule ID 1598 // GIM_CheckFeatures, GIFBS_HasNEONorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 530:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FRSQRTS64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1598, GIR_Done, // Label 2665: @122440 GIM_Try, /*On fail goto*//*Label 2666*/ 122492, // Rule ID 1599 // GIM_CheckFeatures, GIFBS_HasNEONorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 530:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FRSQRTS32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1599, GIR_Done, // Label 2666: @122492 GIM_Try, /*On fail goto*//*Label 2667*/ 122544, // Rule ID 1600 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEONorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 530:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FRSQRTS16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1600, GIR_Done, // Label 2667: @122544 GIM_Try, /*On fail goto*//*Label 2668*/ 122596, // Rule ID 1601 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 569:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1601, GIR_Done, // Label 2668: @122596 GIM_Try, /*On fail goto*//*Label 2669*/ 122648, // Rule ID 1602 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 570:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQDMULHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1602, GIR_Done, // Label 2669: @122648 GIM_Try, /*On fail goto*//*Label 2670*/ 122700, // Rule ID 1603 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 578:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQRDMULHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1603, GIR_Done, // Label 2670: @122700 GIM_Try, /*On fail goto*//*Label 2671*/ 122752, // Rule ID 1604 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 581:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1604, GIR_Done, // Label 2671: @122752 GIM_Try, /*On fail goto*//*Label 2672*/ 122804, // Rule ID 1605 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 584:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1605, GIR_Done, // Label 2672: @122804 GIM_Try, /*On fail goto*//*Label 2673*/ 122856, // Rule ID 1606 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 588:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQSUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1606, GIR_Done, // Label 2673: @122856 GIM_Try, /*On fail goto*//*Label 2674*/ 122908, // Rule ID 1607 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 592:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1607, GIR_Done, // Label 2674: @122908 GIM_Try, /*On fail goto*//*Label 2675*/ 122960, // Rule ID 1608 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 593:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1608, GIR_Done, // Label 2675: @122960 GIM_Try, /*On fail goto*//*Label 2676*/ 123012, // Rule ID 1610 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 629:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1610, GIR_Done, // Label 2676: @123012 GIM_Try, /*On fail goto*//*Label 2677*/ 123064, // Rule ID 1611 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 630:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1611, GIR_Done, // Label 2677: @123064 GIM_Try, /*On fail goto*//*Label 2678*/ 123116, // Rule ID 1612 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 632:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1612, GIR_Done, // Label 2678: @123116 GIM_Try, /*On fail goto*//*Label 2679*/ 123168, // Rule ID 1613 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 634:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQSUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1613, GIR_Done, // Label 2679: @123168 GIM_Try, /*On fail goto*//*Label 2680*/ 123220, // Rule ID 1614 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 638:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (URSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1614, GIR_Done, // Label 2680: @123220 GIM_Try, /*On fail goto*//*Label 2681*/ 123272, // Rule ID 1615 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 641:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (USHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1615, GIR_Done, // Label 2681: @123272 GIM_Try, /*On fail goto*//*Label 2682*/ 123324, // Rule ID 1616 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 574:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQDMULLi32:{ *:[i64] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1616, GIR_Done, // Label 2682: @123324 GIM_Try, /*On fail goto*//*Label 2683*/ 123376, // Rule ID 1629 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 605:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) => (SUQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1629, GIR_Done, // Label 2683: @123376 GIM_Try, /*On fail goto*//*Label 2684*/ 123428, // Rule ID 1630 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 605:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) => (SUQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1630, GIR_Done, // Label 2684: @123428 GIM_Try, /*On fail goto*//*Label 2685*/ 123480, // Rule ID 1635 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 644:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) => (USQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1635, GIR_Done, // Label 2685: @123480 GIM_Try, /*On fail goto*//*Label 2686*/ 123532, // Rule ID 1636 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 644:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) => (USQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1636, GIR_Done, // Label 2686: @123532 GIM_Try, /*On fail goto*//*Label 2687*/ 123584, // Rule ID 1637 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 479:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv8i16_v8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1637, GIR_Done, // Label 2687: @123584 GIM_Try, /*On fail goto*//*Label 2688*/ 123636, // Rule ID 1638 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 479:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv4i32_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1638, GIR_Done, // Label 2688: @123636 GIM_Try, /*On fail goto*//*Label 2689*/ 123688, // Rule ID 1639 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 479:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv2i64_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1639, GIR_Done, // Label 2689: @123688 GIM_Try, /*On fail goto*//*Label 2690*/ 123740, // Rule ID 1640 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_subhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 604:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv8i16_v8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1640, GIR_Done, // Label 2690: @123740 GIM_Try, /*On fail goto*//*Label 2691*/ 123792, // Rule ID 1641 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_subhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 604:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv4i32_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1641, GIR_Done, // Label 2691: @123792 GIM_Try, /*On fail goto*//*Label 2692*/ 123844, // Rule ID 1642 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_subhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 604:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv2i64_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1642, GIR_Done, // Label 2692: @123844 GIM_Try, /*On fail goto*//*Label 2693*/ 123896, // Rule ID 1643 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_raddhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 546:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (RADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv8i16_v8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1643, GIR_Done, // Label 2693: @123896 GIM_Try, /*On fail goto*//*Label 2694*/ 123948, // Rule ID 1644 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_raddhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 546:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (RADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv4i32_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1644, GIR_Done, // Label 2694: @123948 GIM_Try, /*On fail goto*//*Label 2695*/ 124000, // Rule ID 1645 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_raddhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 546:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (RADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv2i64_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1645, GIR_Done, // Label 2695: @124000 GIM_Try, /*On fail goto*//*Label 2696*/ 124052, // Rule ID 1646 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 548:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (RSUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv8i16_v8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1646, GIR_Done, // Label 2696: @124052 GIM_Try, /*On fail goto*//*Label 2697*/ 124104, // Rule ID 1647 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 548:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (RSUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv4i32_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1647, GIR_Done, // Label 2697: @124104 GIM_Try, /*On fail goto*//*Label 2698*/ 124156, // Rule ID 1648 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 548:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (RSUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv2i64_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1648, GIR_Done, // Label 2698: @124156 GIM_Try, /*On fail goto*//*Label 2699*/ 124208, // Rule ID 1714 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 573:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQDMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1714, GIR_Done, // Label 2699: @124208 GIM_Try, /*On fail goto*//*Label 2700*/ 124260, // Rule ID 1716 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 573:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQDMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1716, GIR_Done, // Label 2700: @124260 GIM_Try, /*On fail goto*//*Label 2701*/ 124312, // Rule ID 2216 // GIM_CheckFeatures, GIFBS_HasAES, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aese, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 426:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESErr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2216, GIR_Done, // Label 2701: @124312 GIM_Try, /*On fail goto*//*Label 2702*/ 124364, // Rule ID 2217 // GIM_CheckFeatures, GIFBS_HasAES, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 425:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESDrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2217, GIR_Done, // Label 2702: @124364 GIM_Try, /*On fail goto*//*Label 2703*/ 124416, // Rule ID 2228 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1su1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 439:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (SHA1SU1rr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1SU1rr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2228, GIR_Done, // Label 2703: @124416 GIM_Try, /*On fail goto*//*Label 2704*/ 124468, // Rule ID 2229 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256su0, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 442:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (SHA256SU0rr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256SU0rr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2229, GIR_Done, // Label 2704: @124468 GIM_Try, /*On fail goto*//*Label 2705*/ 124520, // Rule ID 6821 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 569:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6821, GIR_Done, // Label 2705: @124520 GIM_Try, /*On fail goto*//*Label 2706*/ 124572, // Rule ID 6822 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 569:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6822, GIR_Done, // Label 2706: @124572 GIM_Try, /*On fail goto*//*Label 2707*/ 124624, // Rule ID 6823 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1f64] } 667:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FABD64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6823, GIR_Done, // Label 2707: @124624 GIM_Try, /*On fail goto*//*Label 2708*/ 124676, // Rule ID 6824 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 490:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FACGE64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGE64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6824, GIR_Done, // Label 2708: @124676 GIM_Try, /*On fail goto*//*Label 2709*/ 124728, // Rule ID 6829 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 605:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) => (SUQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6829, GIR_Done, // Label 2709: @124728 GIM_Try, /*On fail goto*//*Label 2710*/ 124780, // Rule ID 7780 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha512su0, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 446:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (SHA512SU0:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA512SU0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vdst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7780, GIR_Done, // Label 2710: @124780 GIM_Try, /*On fail goto*//*Label 2711*/ 124832, // Rule ID 7808 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_rax1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 433:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (RAX1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RAX1, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7808, GIR_Done, // Label 2711: @124832 GIM_Try, /*On fail goto*//*Label 2712*/ 124884, // Rule ID 7817 // GIM_CheckFeatures, GIFBS_HasSM4, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sm4ekey, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 456:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (SM4ENCKEY:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SM4ENCKEY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7817, GIR_Done, // Label 2712: @124884 GIM_Try, /*On fail goto*//*Label 2713*/ 124936, // Rule ID 7818 // GIM_CheckFeatures, GIFBS_HasSM4, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sm4e, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 455:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (SM4E:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SM4E, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vdst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7818, GIR_Done, // Label 2713: @124936 GIM_Try, /*On fail goto*//*Label 2714*/ 124991, // Rule ID 7819 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot90, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 646:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7819, GIR_Done, // Label 2714: @124991 GIM_Try, /*On fail goto*//*Label 2715*/ 125046, // Rule ID 7820 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot270, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 645:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7820, GIR_Done, // Label 2715: @125046 GIM_Try, /*On fail goto*//*Label 2716*/ 125101, // Rule ID 7821 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot90, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 646:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7821, GIR_Done, // Label 2716: @125101 GIM_Try, /*On fail goto*//*Label 2717*/ 125156, // Rule ID 7822 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot270, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 645:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7822, GIR_Done, // Label 2717: @125156 GIM_Try, /*On fail goto*//*Label 2718*/ 125211, // Rule ID 7823 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot90, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 646:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7823, GIR_Done, // Label 2718: @125211 GIM_Try, /*On fail goto*//*Label 2719*/ 125266, // Rule ID 7824 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot270, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 645:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7824, GIR_Done, // Label 2719: @125266 GIM_Try, /*On fail goto*//*Label 2720*/ 125321, // Rule ID 7825 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot90, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 646:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7825, GIR_Done, // Label 2720: @125321 GIM_Try, /*On fail goto*//*Label 2721*/ 125376, // Rule ID 7826 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot270, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 645:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7826, GIR_Done, // Label 2721: @125376 GIM_Try, /*On fail goto*//*Label 2722*/ 125431, // Rule ID 7827 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot90, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 646:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7827, GIR_Done, // Label 2722: @125431 GIM_Try, /*On fail goto*//*Label 2723*/ 125486, // Rule ID 7828 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot270, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 645:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7828, GIR_Done, // Label 2723: @125486 GIM_Try, /*On fail goto*//*Label 2724*/ 125536, // Rule ID 7891 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_udiv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1488:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (UDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDIVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7891, GIR_Done, // Label 2724: @125536 GIM_Try, /*On fail goto*//*Label 2725*/ 125586, // Rule ID 7892 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_udiv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 1488:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDIVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7892, GIR_Done, // Label 2725: @125586 GIM_Try, /*On fail goto*//*Label 2726*/ 125636, // Rule ID 7893 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sdiv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 663:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDIVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7893, GIR_Done, // Label 2726: @125636 GIM_Try, /*On fail goto*//*Label 2727*/ 125686, // Rule ID 7894 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sdiv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 663:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDIVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7894, GIR_Done, // Label 2727: @125686 GIM_Try, /*On fail goto*//*Label 2728*/ 125736, // Rule ID 8679 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1f64] } 489:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FABD64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8679, GIR_Done, // Label 2728: @125736 GIM_Try, /*On fail goto*//*Label 2729*/ 125788, // Rule ID 8683 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 491:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FACGT64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGT64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8683, GIR_Done, // Label 2729: @125788 GIM_Try, /*On fail goto*//*Label 2730*/ 125840, // Rule ID 8687 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1f64] } 521:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMULX64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8687, GIR_Done, // Label 2730: @125840 GIM_Try, /*On fail goto*//*Label 2731*/ 125892, // Rule ID 8688 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1f64] } 523:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FRECPS64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8688, GIR_Done, // Label 2731: @125892 GIM_Try, /*On fail goto*//*Label 2732*/ 125944, // Rule ID 8689 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1f64] } 530:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FRSQRTS64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8689, GIR_Done, // Label 2732: @125944 GIM_Try, /*On fail goto*//*Label 2733*/ 125996, // Rule ID 8690 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 581:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8690, GIR_Done, // Label 2733: @125996 GIM_Try, /*On fail goto*//*Label 2734*/ 126048, // Rule ID 8691 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 581:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQRSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8691, GIR_Done, // Label 2734: @126048 GIM_Try, /*On fail goto*//*Label 2735*/ 126100, // Rule ID 8692 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 584:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8692, GIR_Done, // Label 2735: @126100 GIM_Try, /*On fail goto*//*Label 2736*/ 126152, // Rule ID 8693 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 584:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8693, GIR_Done, // Label 2736: @126152 GIM_Try, /*On fail goto*//*Label 2737*/ 126204, // Rule ID 8694 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 588:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQSUBv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8694, GIR_Done, // Label 2737: @126204 GIM_Try, /*On fail goto*//*Label 2738*/ 126256, // Rule ID 8695 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 588:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQSUBv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8695, GIR_Done, // Label 2738: @126256 GIM_Try, /*On fail goto*//*Label 2739*/ 126308, // Rule ID 8696 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 629:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8696, GIR_Done, // Label 2739: @126308 GIM_Try, /*On fail goto*//*Label 2740*/ 126360, // Rule ID 8697 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 629:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8697, GIR_Done, // Label 2740: @126360 GIM_Try, /*On fail goto*//*Label 2741*/ 126412, // Rule ID 8698 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 630:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8698, GIR_Done, // Label 2741: @126412 GIM_Try, /*On fail goto*//*Label 2742*/ 126464, // Rule ID 8699 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 630:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQRSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8699, GIR_Done, // Label 2742: @126464 GIM_Try, /*On fail goto*//*Label 2743*/ 126516, // Rule ID 8700 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 632:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8700, GIR_Done, // Label 2743: @126516 GIM_Try, /*On fail goto*//*Label 2744*/ 126568, // Rule ID 8701 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 632:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8701, GIR_Done, // Label 2744: @126568 GIM_Try, /*On fail goto*//*Label 2745*/ 126620, // Rule ID 8702 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 634:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQSUBv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8702, GIR_Done, // Label 2745: @126620 GIM_Try, /*On fail goto*//*Label 2746*/ 126672, // Rule ID 8703 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 634:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQSUBv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8703, GIR_Done, // Label 2746: @126672 GIM_Try, /*On fail goto*//*Label 2747*/ 126724, // Rule ID 8718 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 644:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) => (USQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8718, GIR_Done, // Label 2747: @126724 GIM_Try, /*On fail goto*//*Label 2748*/ 126774, // Rule ID 8921 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbl1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 606:{ *:[iPTR] }, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) => (TBLv8i8One:{ *:[v8i8] } VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBLv8i8One, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ri GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8921, GIR_Done, // Label 2748: @126774 GIM_Try, /*On fail goto*//*Label 2749*/ 126824, // Rule ID 8922 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbl1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 606:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) => (TBLv16i8One:{ *:[v16i8] } V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBLv16i8One, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ri GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8922, GIR_Done, // Label 2749: @126824 GIM_Try, /*On fail goto*//*Label 2750*/ 126919, // Rule ID 9433 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 490:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FACGE16:{ *:[bf16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm), hsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FACGE16, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/7, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR16RegClassID, // GIR_Coverage, 9433, GIR_Done, // Label 2750: @126919 GIM_Try, /*On fail goto*//*Label 2751*/ 127014, // Rule ID 9434 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 491:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FACGT16:{ *:[bf16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm), hsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FACGT16, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/7, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR16RegClassID, // GIR_Coverage, 9434, GIR_Done, // Label 2751: @127014 GIM_Try, /*On fail goto*//*Label 2752*/ 127064, // Rule ID 10124 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 593:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10124, GIR_Done, // Label 2752: @127064 GIM_Try, /*On fail goto*//*Label 2753*/ 127114, // Rule ID 10125 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 641:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (USHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10125, GIR_Done, // Label 2753: @127114 GIM_Try, /*On fail goto*//*Label 2754*/ 127164, // Rule ID 10126 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 592:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10126, GIR_Done, // Label 2754: @127164 GIM_Try, /*On fail goto*//*Label 2755*/ 127214, // Rule ID 10127 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 638:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (URSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10127, GIR_Done, // Label 2755: @127214 GIM_Try, /*On fail goto*//*Label 2756*/ 127266, // Rule ID 140 // GIM_CheckFeatures, GIFBS_HasMTE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_gmi, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 466:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (GMI:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::GMI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 140, GIR_Done, // Label 2756: @127266 GIM_Try, /*On fail goto*//*Label 2757*/ 127318, // Rule ID 141 // GIM_CheckFeatures, GIFBS_HasMTE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_subp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, // MIs[0] Rm GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_wo_chain:{ *:[i64] } 809:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm) => (SUBP:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBP, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 141, GIR_Done, // Label 2757: @127318 GIM_Try, /*On fail goto*//*Label 2758*/ 127362, // Rule ID 2267 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_zip1_b16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1474:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP1_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ZIP1_PPP_H, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2267, GIR_Done, // Label 2758: @127362 GIM_Try, /*On fail goto*//*Label 2759*/ 127406, // Rule ID 2268 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_zip1_b32, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1475:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP1_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ZIP1_PPP_S, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2268, GIR_Done, // Label 2759: @127406 GIM_Try, /*On fail goto*//*Label 2760*/ 127450, // Rule ID 2269 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_zip1_b64, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1476:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP1_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ZIP1_PPP_D, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2269, GIR_Done, // Label 2760: @127450 GIM_Try, /*On fail goto*//*Label 2761*/ 127494, // Rule ID 2271 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_zip2_b16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1479:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP2_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ZIP2_PPP_H, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2271, GIR_Done, // Label 2761: @127494 GIM_Try, /*On fail goto*//*Label 2762*/ 127538, // Rule ID 2272 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_zip2_b32, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1480:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP2_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ZIP2_PPP_S, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2272, GIR_Done, // Label 2762: @127538 GIM_Try, /*On fail goto*//*Label 2763*/ 127582, // Rule ID 2273 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_zip2_b64, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1481:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP2_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ZIP2_PPP_D, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2273, GIR_Done, // Label 2763: @127582 GIM_Try, /*On fail goto*//*Label 2764*/ 127626, // Rule ID 2275 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_uzp1_b16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1438:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP1_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP1_PPP_H, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2275, GIR_Done, // Label 2764: @127626 GIM_Try, /*On fail goto*//*Label 2765*/ 127670, // Rule ID 2276 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_uzp1_b32, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1439:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP1_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP1_PPP_S, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2276, GIR_Done, // Label 2765: @127670 GIM_Try, /*On fail goto*//*Label 2766*/ 127714, // Rule ID 2277 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_uzp1_b64, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1440:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP1_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP1_PPP_D, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2277, GIR_Done, // Label 2766: @127714 GIM_Try, /*On fail goto*//*Label 2767*/ 127758, // Rule ID 2279 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_uzp2_b16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1443:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP2_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2_PPP_H, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2279, GIR_Done, // Label 2767: @127758 GIM_Try, /*On fail goto*//*Label 2768*/ 127802, // Rule ID 2280 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_uzp2_b32, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1444:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP2_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2_PPP_S, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2280, GIR_Done, // Label 2768: @127802 GIM_Try, /*On fail goto*//*Label 2769*/ 127846, // Rule ID 2281 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_uzp2_b64, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1445:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP2_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2_PPP_D, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2281, GIR_Done, // Label 2769: @127846 GIM_Try, /*On fail goto*//*Label 2770*/ 127890, // Rule ID 2283 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_trn1_b16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1309:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN1_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TRN1_PPP_H, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2283, GIR_Done, // Label 2770: @127890 GIM_Try, /*On fail goto*//*Label 2771*/ 127934, // Rule ID 2284 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_trn1_b32, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1310:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN1_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TRN1_PPP_S, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2284, GIR_Done, // Label 2771: @127934 GIM_Try, /*On fail goto*//*Label 2772*/ 127978, // Rule ID 2285 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_trn1_b64, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1311:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN1_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TRN1_PPP_D, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2285, GIR_Done, // Label 2772: @127978 GIM_Try, /*On fail goto*//*Label 2773*/ 128022, // Rule ID 2287 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_trn2_b16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1314:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN2_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TRN2_PPP_H, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2287, GIR_Done, // Label 2773: @128022 GIM_Try, /*On fail goto*//*Label 2774*/ 128066, // Rule ID 2288 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_trn2_b32, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1315:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN2_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TRN2_PPP_S, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2288, GIR_Done, // Label 2774: @128066 GIM_Try, /*On fail goto*//*Label 2775*/ 128110, // Rule ID 2289 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_trn2_b64, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i1] } 1316:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN2_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TRN2_PPP_D, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Pm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2289, GIR_Done, // Label 2775: @128110 GIM_Try, /*On fail goto*//*Label 2776*/ 128154, // Rule ID 2290 // GIM_CheckFeatures, GIFBS_HasSVE2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_histseg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, // (intrinsic_wo_chain:{ *:[nxv16i8] } 1012:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm) => (HISTSEG_ZZZ:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HISTSEG_ZZZ, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Zn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2290, GIR_Done, // Label 2776: @128154 GIM_Reject, // Label 2309: @128155 GIM_Try, /*On fail goto*//*Label 2777*/ 135207, GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, GIM_Try, /*On fail goto*//*Label 2778*/ 128269, // Rule ID 46 // GIM_CheckFeatures, GIFBS_HasMatMulInt8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usdot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[v2i32] } 640:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V64:{ *:[v8i8] }:$Rn) => (SUDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUDOTlanev8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 46, GIR_Done, // Label 2778: @128269 GIM_Try, /*On fail goto*//*Label 2779*/ 128378, // Rule ID 47 // GIM_CheckFeatures, GIFBS_HasMatMulInt8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usdot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[v4i32] } 640:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V128:{ *:[v16i8] }:$Rn) => (SUDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUDOTlanev16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 47, GIR_Done, // Label 2779: @128378 GIM_Try, /*On fail goto*//*Label 2780*/ 128487, // Rule ID 29 // GIM_CheckFeatures, GIFBS_HasBF16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfdot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[v2f32] } 484:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4bf16] }:$Rn, (bitconvert:{ *:[v4bf16] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx))) => (BF16DOTlanev4bf16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4bf16] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BF16DOTlanev4bf16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 29, GIR_Done, // Label 2780: @128487 GIM_Try, /*On fail goto*//*Label 2781*/ 128596, // Rule ID 30 // GIM_CheckFeatures, GIFBS_HasBF16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfdot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[v4f32] } 484:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, (bitconvert:{ *:[v8bf16] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx))) => (BF16DOTlanev8bf16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BF16DOTlanev8bf16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 30, GIR_Done, // Label 2781: @128596 GIM_Try, /*On fail goto*//*Label 2782*/ 128705, // Rule ID 44 // GIM_CheckFeatures, GIFBS_HasMatMulInt8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usdot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[v2i32] } 640:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx))) => (USDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USDOTlanev8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 44, GIR_Done, // Label 2782: @128705 GIM_Try, /*On fail goto*//*Label 2783*/ 128814, // Rule ID 45 // GIM_CheckFeatures, GIFBS_HasMatMulInt8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usdot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[v4i32] } 640:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx))) => (USDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USDOTlanev16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 45, GIR_Done, // Label 2783: @128814 GIM_Try, /*On fail goto*//*Label 2784*/ 128866, // Rule ID 68 // GIM_CheckFeatures, GIFBS_HasPAuth, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ptrauth_sign, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[i64] } 249:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 0:{ *:[i32] }, 0:{ *:[i64] }) => (PACIZA:{ *:[i64] } GPR64:{ *:[i64] }:$Rd) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PACIZA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 68, GIR_Done, // Label 2784: @128866 GIM_Try, /*On fail goto*//*Label 2785*/ 128918, // Rule ID 69 // GIM_CheckFeatures, GIFBS_HasPAuth, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ptrauth_sign, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 2, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[i64] } 249:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 2:{ *:[i32] }, 0:{ *:[i64] }) => (PACDZA:{ *:[i64] } GPR64:{ *:[i64] }:$Rd) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PACDZA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 69, GIR_Done, // Label 2785: @128918 GIM_Try, /*On fail goto*//*Label 2786*/ 128970, // Rule ID 70 // GIM_CheckFeatures, GIFBS_HasPAuth, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ptrauth_sign, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[i64] } 249:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 1:{ *:[i32] }, 0:{ *:[i64] }) => (PACIZB:{ *:[i64] } GPR64:{ *:[i64] }:$Rd) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PACIZB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 70, GIR_Done, // Label 2786: @128970 GIM_Try, /*On fail goto*//*Label 2787*/ 129022, // Rule ID 71 // GIM_CheckFeatures, GIFBS_HasPAuth, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ptrauth_sign, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 3, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[i64] } 249:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 3:{ *:[i32] }, 0:{ *:[i64] }) => (PACDZB:{ *:[i64] } GPR64:{ *:[i64] }:$Rd) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PACDZB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 71, GIR_Done, // Label 2787: @129022 GIM_Try, /*On fail goto*//*Label 2788*/ 129118, // Rule ID 34 // GIM_CheckFeatures, GIFBS_HasBF16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfmlalb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4f32] } 485:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, (AArch64duplane16:{ *:[v8bf16] } V128_lo:{ *:[v8bf16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (BFMLALBIdx:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128_lo:{ *:[v8bf16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFMLALBIdx, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 34, GIR_Done, // Label 2788: @129118 GIM_Try, /*On fail goto*//*Label 2789*/ 129214, // Rule ID 35 // GIM_CheckFeatures, GIFBS_HasBF16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfmlalt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4f32] } 486:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, (AArch64duplane16:{ *:[v8bf16] } V128_lo:{ *:[v8bf16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (BFMLALTIdx:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128_lo:{ *:[v8bf16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFMLALTIdx, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 35, GIR_Done, // Label 2789: @129214 GIM_Try, /*On fail goto*//*Label 2790*/ 129310, // Rule ID 56 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v2f32] } 517:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMLALlanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLALlanev4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 56, GIR_Done, // Label 2790: @129310 GIM_Try, /*On fail goto*//*Label 2791*/ 129406, // Rule ID 57 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4f32] } 517:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMLALlanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLALlanev8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 57, GIR_Done, // Label 2791: @129406 GIM_Try, /*On fail goto*//*Label 2792*/ 129502, // Rule ID 58 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v2f32] } 519:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMLSLlanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSLlanev4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 58, GIR_Done, // Label 2792: @129502 GIM_Try, /*On fail goto*//*Label 2793*/ 129598, // Rule ID 59 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4f32] } 519:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMLSLlanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSLlanev8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 59, GIR_Done, // Label 2793: @129598 GIM_Try, /*On fail goto*//*Label 2794*/ 129694, // Rule ID 60 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v2f32] } 518:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMLAL2lanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAL2lanev4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 60, GIR_Done, // Label 2794: @129694 GIM_Try, /*On fail goto*//*Label 2795*/ 129790, // Rule ID 61 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4f32] } 518:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMLAL2lanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAL2lanev8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 61, GIR_Done, // Label 2795: @129790 GIM_Try, /*On fail goto*//*Label 2796*/ 129886, // Rule ID 62 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v2f32] } 520:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMLSL2lanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSL2lanev4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 62, GIR_Done, // Label 2796: @129886 GIM_Try, /*On fail goto*//*Label 2797*/ 129982, // Rule ID 63 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4f32] } 520:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMLSL2lanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSL2lanev8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 63, GIR_Done, // Label 2797: @129982 GIM_Try, /*On fail goto*//*Label 2798*/ 130078, // Rule ID 1999 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlah, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4i16] } 576:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMLAHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1999, GIR_Done, // Label 2798: @130078 GIM_Try, /*On fail goto*//*Label 2799*/ 130174, // Rule ID 2000 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlah, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v8i16] } 576:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMLAHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2000, GIR_Done, // Label 2799: @130174 GIM_Try, /*On fail goto*//*Label 2800*/ 130270, // Rule ID 2004 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlsh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4i16] } 577:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMLSHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2004, GIR_Done, // Label 2800: @130270 GIM_Try, /*On fail goto*//*Label 2801*/ 130366, // Rule ID 2005 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlsh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v8i16] } 577:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMLSHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2005, GIR_Done, // Label 2801: @130366 GIM_Try, /*On fail goto*//*Label 2802*/ 130462, // Rule ID 2001 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlah, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v2i32] } 576:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMLAHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2001, GIR_Done, // Label 2802: @130462 GIM_Try, /*On fail goto*//*Label 2803*/ 130558, // Rule ID 2002 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlah, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4i32] } 576:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMLAHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2002, GIR_Done, // Label 2803: @130558 GIM_Try, /*On fail goto*//*Label 2804*/ 130654, // Rule ID 2006 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlsh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v2i32] } 577:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMLSHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2006, GIR_Done, // Label 2804: @130654 GIM_Try, /*On fail goto*//*Label 2805*/ 130750, // Rule ID 2007 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlsh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4i32] } 577:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMLSHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2007, GIR_Done, // Label 2805: @130750 GIM_Try, /*On fail goto*//*Label 2806*/ 130846, // Rule ID 2003 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlah, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[i32] } 576:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMLAHi32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHi32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2003, GIR_Done, // Label 2806: @130846 GIM_Try, /*On fail goto*//*Label 2807*/ 130942, // Rule ID 2008 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlsh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[i32] } 577:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMLSHi32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHi32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2008, GIR_Done, // Label 2807: @130942 GIM_Try, /*On fail goto*//*Label 2808*/ 130998, // Rule ID 64 // GIM_CheckFeatures, GIFBS_HasPAuth, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ptrauth_sign, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_wo_chain:{ *:[i64] } 249:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 0:{ *:[i32] }, GPR64sp:{ *:[i64] }:$Rn) => (PACIA:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PACIA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 64, GIR_Done, // Label 2808: @130998 GIM_Try, /*On fail goto*//*Label 2809*/ 131054, // Rule ID 65 // GIM_CheckFeatures, GIFBS_HasPAuth, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ptrauth_sign, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_wo_chain:{ *:[i64] } 249:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 1:{ *:[i32] }, GPR64sp:{ *:[i64] }:$Rn) => (PACIB:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PACIB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 65, GIR_Done, // Label 2809: @131054 GIM_Try, /*On fail goto*//*Label 2810*/ 131110, // Rule ID 66 // GIM_CheckFeatures, GIFBS_HasPAuth, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ptrauth_sign, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_wo_chain:{ *:[i64] } 249:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 2:{ *:[i32] }, GPR64sp:{ *:[i64] }:$Rn) => (PACDA:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PACDA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 66, GIR_Done, // Label 2810: @131110 GIM_Try, /*On fail goto*//*Label 2811*/ 131166, // Rule ID 67 // GIM_CheckFeatures, GIFBS_HasPAuth, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::ptrauth_sign, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Operand 3 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, 3, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_wo_chain:{ *:[i64] } 249:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 3:{ *:[i32] }, GPR64sp:{ *:[i64] }:$Rn) => (PACDB:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PACDB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 67, GIR_Done, // Label 2811: @131166 GIM_Try, /*On fail goto*//*Label 2812*/ 131229, // Rule ID 7086 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_ftmad_x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] imm GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timm32_0_7, // (intrinsic_wo_chain:{ *:[nxv8f16] } 1008:{ *:[iPTR] }, ZPR16:{ *:[nxv8f16] }:$Zn, ZPR16:{ *:[nxv8f16] }:$Zm, (timm:{ *:[i32] })<>:$imm) => (FTMAD_ZZI_H:{ *:[nxv8f16] } ZPR16:{ *:[nxv8f16] }:$Zn, ZPR16:{ *:[nxv8f16] }:$Zm, (timm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FTMAD_ZZI_H, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Zn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7086, GIR_Done, // Label 2812: @131229 GIM_Try, /*On fail goto*//*Label 2813*/ 131292, // Rule ID 7087 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_ftmad_x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] imm GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timm32_0_7, // (intrinsic_wo_chain:{ *:[nxv4f32] } 1008:{ *:[iPTR] }, ZPR32:{ *:[nxv4f32] }:$Zn, ZPR32:{ *:[nxv4f32] }:$Zm, (timm:{ *:[i32] })<>:$imm) => (FTMAD_ZZI_S:{ *:[nxv4f32] } ZPR32:{ *:[nxv4f32] }:$Zn, ZPR32:{ *:[nxv4f32] }:$Zm, (timm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FTMAD_ZZI_S, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Zn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7087, GIR_Done, // Label 2813: @131292 GIM_Try, /*On fail goto*//*Label 2814*/ 131355, // Rule ID 7088 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_ftmad_x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] imm GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timm32_0_7, // (intrinsic_wo_chain:{ *:[nxv2f64] } 1008:{ *:[iPTR] }, ZPR64:{ *:[nxv2f64] }:$Zn, ZPR64:{ *:[nxv2f64] }:$Zm, (timm:{ *:[i32] })<>:$imm) => (FTMAD_ZZI_D:{ *:[nxv2f64] } ZPR64:{ *:[nxv2f64] }:$Zn, ZPR64:{ *:[nxv2f64] }:$Zm, (timm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FTMAD_ZZI_D, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Zn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7088, GIR_Done, // Label 2814: @131355 GIM_Try, /*On fail goto*//*Label 2815*/ 131418, // Rule ID 7809 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_xar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // MIs[0] imm GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_timm0_63, // (intrinsic_wo_chain:{ *:[v2i64] } 457:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, (timm:{ *:[i64] })<>:$imm) => (XAR:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, (timm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XAR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7809, GIR_Done, // Label 2815: @131418 GIM_Try, /*On fail goto*//*Label 2816*/ 131483, // Rule ID 7784 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_eor3u, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 432:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm) => (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7784, GIR_Done, // Label 2816: @131483 GIM_Try, /*On fail goto*//*Label 2817*/ 131548, // Rule ID 7785 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_eor3u, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 432:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm) => (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7785, GIR_Done, // Label 2817: @131548 GIM_Try, /*On fail goto*//*Label 2818*/ 131613, // Rule ID 7786 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_eor3u, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 432:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7786, GIR_Done, // Label 2818: @131613 GIM_Try, /*On fail goto*//*Label 2819*/ 131678, // Rule ID 7787 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_eor3u, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 432:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7787, GIR_Done, // Label 2819: @131678 GIM_Try, /*On fail goto*//*Label 2820*/ 131743, // Rule ID 7796 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_bcaxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 430:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm) => (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7796, GIR_Done, // Label 2820: @131743 GIM_Try, /*On fail goto*//*Label 2821*/ 131808, // Rule ID 7797 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_bcaxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 430:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm) => (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7797, GIR_Done, // Label 2821: @131808 GIM_Try, /*On fail goto*//*Label 2822*/ 131873, // Rule ID 7798 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_bcaxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 430:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7798, GIR_Done, // Label 2822: @131873 GIM_Try, /*On fail goto*//*Label 2823*/ 131938, // Rule ID 7799 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_bcaxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 430:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7799, GIR_Done, // Label 2823: @131938 GIM_Try, /*On fail goto*//*Label 2824*/ 132003, // Rule ID 7800 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_eor3s, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 431:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm) => (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7800, GIR_Done, // Label 2824: @132003 GIM_Try, /*On fail goto*//*Label 2825*/ 132068, // Rule ID 7801 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_eor3s, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 431:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm) => (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7801, GIR_Done, // Label 2825: @132068 GIM_Try, /*On fail goto*//*Label 2826*/ 132133, // Rule ID 7802 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_eor3s, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 431:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7802, GIR_Done, // Label 2826: @132133 GIM_Try, /*On fail goto*//*Label 2827*/ 132198, // Rule ID 7803 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_eor3s, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 431:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EOR3, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7803, GIR_Done, // Label 2827: @132198 GIM_Try, /*On fail goto*//*Label 2828*/ 132263, // Rule ID 7804 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_bcaxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 429:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm) => (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7804, GIR_Done, // Label 2828: @132263 GIM_Try, /*On fail goto*//*Label 2829*/ 132328, // Rule ID 7805 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_bcaxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 429:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm) => (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7805, GIR_Done, // Label 2829: @132328 GIM_Try, /*On fail goto*//*Label 2830*/ 132393, // Rule ID 7806 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_bcaxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 429:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7806, GIR_Done, // Label 2830: @132393 GIM_Try, /*On fail goto*//*Label 2831*/ 132458, // Rule ID 7807 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_bcaxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 429:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BCAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7807, GIR_Done, // Label 2831: @132458 GIM_Try, /*On fail goto*//*Label 2832*/ 132522, // Rule ID 27 // GIM_CheckFeatures, GIFBS_HasBF16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfdot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 484:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) => (BFDOTv4bf16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFDOTv4bf16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 27, GIR_Done, // Label 2832: @132522 GIM_Try, /*On fail goto*//*Label 2833*/ 132586, // Rule ID 28 // GIM_CheckFeatures, GIFBS_HasBF16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfdot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 484:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFDOTv8bf16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFDOTv8bf16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 28, GIR_Done, // Label 2833: @132586 GIM_Try, /*On fail goto*//*Label 2834*/ 132650, // Rule ID 31 // GIM_CheckFeatures, GIFBS_HasBF16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfmmla, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 487:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFMMLA:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFMMLA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 31, GIR_Done, // Label 2834: @132650 GIM_Try, /*On fail goto*//*Label 2835*/ 132714, // Rule ID 32 // GIM_CheckFeatures, GIFBS_HasBF16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfmlalb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 485:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFMLALB:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFMLALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 32, GIR_Done, // Label 2835: @132714 GIM_Try, /*On fail goto*//*Label 2836*/ 132778, // Rule ID 33 // GIM_CheckFeatures, GIFBS_HasBF16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfmlalt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 486:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFMLALT:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFMLALT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 33, GIR_Done, // Label 2836: @132778 GIM_Try, /*On fail goto*//*Label 2837*/ 132842, // Rule ID 39 // GIM_CheckFeatures, GIFBS_HasMatMulInt8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smmla, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 566:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMMLA:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMMLA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 39, GIR_Done, // Label 2837: @132842 GIM_Try, /*On fail goto*//*Label 2838*/ 132906, // Rule ID 40 // GIM_CheckFeatures, GIFBS_HasMatMulInt8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ummla, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 627:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMMLA:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMMLA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 40, GIR_Done, // Label 2838: @132906 GIM_Try, /*On fail goto*//*Label 2839*/ 132970, // Rule ID 41 // GIM_CheckFeatures, GIFBS_HasMatMulInt8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usmmla, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 643:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (USMMLA:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USMMLA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 41, GIR_Done, // Label 2839: @132970 GIM_Try, /*On fail goto*//*Label 2840*/ 133034, // Rule ID 42 // GIM_CheckFeatures, GIFBS_HasMatMulInt8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usdot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 640:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (USDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USDOTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 42, GIR_Done, // Label 2840: @133034 GIM_Try, /*On fail goto*//*Label 2841*/ 133098, // Rule ID 43 // GIM_CheckFeatures, GIFBS_HasMatMulInt8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usdot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 640:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (USDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USDOTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 43, GIR_Done, // Label 2841: @133098 GIM_Try, /*On fail goto*//*Label 2842*/ 133162, // Rule ID 48 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 517:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLALv4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLALv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 48, GIR_Done, // Label 2842: @133162 GIM_Try, /*On fail goto*//*Label 2843*/ 133226, // Rule ID 49 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 517:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLALv8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLALv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 49, GIR_Done, // Label 2843: @133226 GIM_Try, /*On fail goto*//*Label 2844*/ 133290, // Rule ID 50 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 519:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLSLv4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSLv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 50, GIR_Done, // Label 2844: @133290 GIM_Try, /*On fail goto*//*Label 2845*/ 133354, // Rule ID 51 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 519:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLSLv8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSLv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 51, GIR_Done, // Label 2845: @133354 GIM_Try, /*On fail goto*//*Label 2846*/ 133418, // Rule ID 52 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 518:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLAL2v4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAL2v4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 52, GIR_Done, // Label 2846: @133418 GIM_Try, /*On fail goto*//*Label 2847*/ 133482, // Rule ID 53 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 518:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLAL2v8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAL2v8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 53, GIR_Done, // Label 2847: @133482 GIM_Try, /*On fail goto*//*Label 2848*/ 133546, // Rule ID 54 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 520:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLSL2v4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSL2v4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 54, GIR_Done, // Label 2848: @133546 GIM_Try, /*On fail goto*//*Label 2849*/ 133610, // Rule ID 55 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 520:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLSL2v8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSL2v8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 55, GIR_Done, // Label 2849: @133610 GIM_Try, /*On fail goto*//*Label 2850*/ 133674, // Rule ID 1550 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlah, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 576:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQRDMLAHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1550, GIR_Done, // Label 2850: @133674 GIM_Try, /*On fail goto*//*Label 2851*/ 133738, // Rule ID 1551 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlah, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 576:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQRDMLAHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1551, GIR_Done, // Label 2851: @133738 GIM_Try, /*On fail goto*//*Label 2852*/ 133802, // Rule ID 1552 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlah, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 576:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQRDMLAHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1552, GIR_Done, // Label 2852: @133802 GIM_Try, /*On fail goto*//*Label 2853*/ 133866, // Rule ID 1553 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlah, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 576:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQRDMLAHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1553, GIR_Done, // Label 2853: @133866 GIM_Try, /*On fail goto*//*Label 2854*/ 133930, // Rule ID 1554 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlsh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 577:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQRDMLSHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1554, GIR_Done, // Label 2854: @133930 GIM_Try, /*On fail goto*//*Label 2855*/ 133994, // Rule ID 1555 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlsh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 577:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQRDMLSHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1555, GIR_Done, // Label 2855: @133994 GIM_Try, /*On fail goto*//*Label 2856*/ 134058, // Rule ID 1556 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlsh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 577:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQRDMLSHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1556, GIR_Done, // Label 2856: @134058 GIM_Try, /*On fail goto*//*Label 2857*/ 134122, // Rule ID 1557 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlsh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 577:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQRDMLSHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1557, GIR_Done, // Label 2857: @134122 GIM_Try, /*On fail goto*//*Label 2858*/ 134186, // Rule ID 2220 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1c, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 434:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1Crrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Crrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2220, GIR_Done, // Label 2858: @134186 GIM_Try, /*On fail goto*//*Label 2859*/ 134250, // Rule ID 2221 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1p, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 437:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1Prrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Prrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2221, GIR_Done, // Label 2859: @134250 GIM_Try, /*On fail goto*//*Label 2860*/ 134314, // Rule ID 2222 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1m, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 436:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1Mrrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Mrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2222, GIR_Done, // Label 2860: @134314 GIM_Try, /*On fail goto*//*Label 2861*/ 134378, // Rule ID 2223 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1su0, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 438:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1SU0rrr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1SU0rrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2223, GIR_Done, // Label 2861: @134378 GIM_Try, /*On fail goto*//*Label 2862*/ 134442, // Rule ID 2224 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256h, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 440:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA256Hrrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256Hrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2224, GIR_Done, // Label 2862: @134442 GIM_Try, /*On fail goto*//*Label 2863*/ 134506, // Rule ID 2225 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256h2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 441:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA256H2rrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256H2rrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2225, GIR_Done, // Label 2863: @134506 GIM_Try, /*On fail goto*//*Label 2864*/ 134570, // Rule ID 2226 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256su1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 443:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA256SU1rrr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256SU1rrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2226, GIR_Done, // Label 2864: @134570 GIM_Try, /*On fail goto*//*Label 2865*/ 134634, // Rule ID 7781 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha512h, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 444:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (SHA512H:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA512H, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vdst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7781, GIR_Done, // Label 2865: @134634 GIM_Try, /*On fail goto*//*Label 2866*/ 134698, // Rule ID 7782 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha512h2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 445:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (SHA512H2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA512H2, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vdst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7782, GIR_Done, // Label 2866: @134698 GIM_Try, /*On fail goto*//*Label 2867*/ 134762, // Rule ID 7783 // GIM_CheckFeatures, GIFBS_HasSHA3, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha512su1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 447:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (SHA512SU1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA512SU1, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vdst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7783, GIR_Done, // Label 2867: @134762 GIM_Try, /*On fail goto*//*Label 2868*/ 134826, // Rule ID 7810 // GIM_CheckFeatures, GIFBS_HasSM4, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sm3ss1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 450:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va) => (SM3SS1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SM3SS1, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Va GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7810, GIR_Done, // Label 2868: @134826 GIM_Try, /*On fail goto*//*Label 2869*/ 134890, // Rule ID 7811 // GIM_CheckFeatures, GIFBS_HasSM4, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sm3partw1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 448:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (SM3PARTW1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SM3PARTW1, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vdst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7811, GIR_Done, // Label 2869: @134890 GIM_Try, /*On fail goto*//*Label 2870*/ 134954, // Rule ID 7812 // GIM_CheckFeatures, GIFBS_HasSM4, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sm3partw2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 449:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (SM3PARTW2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SM3PARTW2, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vdst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7812, GIR_Done, // Label 2870: @134954 GIM_Try, /*On fail goto*//*Label 2871*/ 135018, // Rule ID 8704 // GIM_CheckFeatures, GIFBS_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlah, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 576:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQRDMLAHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8704, GIR_Done, // Label 2871: @135018 GIM_Try, /*On fail goto*//*Label 2872*/ 135082, // Rule ID 8705 // GIM_CheckFeatures, GIFBS_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmlsh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 577:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQRDMLSHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8705, GIR_Done, // Label 2872: @135082 GIM_Try, /*On fail goto*//*Label 2873*/ 135144, // Rule ID 8923 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbx1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 610:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) => (TBXv8i8One:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBXv8i8One, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ri GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8923, GIR_Done, // Label 2873: @135144 GIM_Try, /*On fail goto*//*Label 2874*/ 135206, // Rule ID 8924 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbx1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 610:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) => (TBXv16i8One:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBXv16i8One, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ri GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8924, GIR_Done, // Label 2874: @135206 GIM_Reject, // Label 2777: @135207 GIM_Try, /*On fail goto*//*Label 2875*/ 135865, GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, GIM_Try, /*On fail goto*//*Label 2876*/ 135300, // Rule ID 9024 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcopy_lane, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v16i8] } 651:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<>:$idx2) => (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<>:$idx2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi8lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9024, GIR_Done, // Label 2876: @135300 GIM_Try, /*On fail goto*//*Label 2877*/ 135388, // Rule ID 9025 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcopy_lane, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v8i16] } 651:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<>:$idx2) => (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<>:$idx2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi16lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9025, GIR_Done, // Label 2877: @135388 GIM_Try, /*On fail goto*//*Label 2878*/ 135476, // Rule ID 9026 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcopy_lane, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4i32] } 651:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<>:$idx2) => (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<>:$idx2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi32lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9026, GIR_Done, // Label 2878: @135476 GIM_Try, /*On fail goto*//*Label 2879*/ 135564, // Rule ID 9027 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcopy_lane, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v2i64] } 651:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<>:$idx2) => (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<>:$idx2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9027, GIR_Done, // Label 2879: @135564 GIM_Try, /*On fail goto*//*Label 2880*/ 135639, // Rule ID 7813 // GIM_CheckFeatures, GIFBS_HasSM4, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sm3tt1a, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // MIs[0] imm GIM_CheckIsImm, /*MI*/0, /*Op*/5, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS_timm, // (intrinsic_wo_chain:{ *:[v4i32] } 451:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<>:$imm) => (SM3TT1A:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SM3TT1A, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vdst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7813, GIR_Done, // Label 2880: @135639 GIM_Try, /*On fail goto*//*Label 2881*/ 135714, // Rule ID 7814 // GIM_CheckFeatures, GIFBS_HasSM4, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sm3tt1b, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // MIs[0] imm GIM_CheckIsImm, /*MI*/0, /*Op*/5, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS_timm, // (intrinsic_wo_chain:{ *:[v4i32] } 452:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<>:$imm) => (SM3TT1B:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SM3TT1B, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vdst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7814, GIR_Done, // Label 2881: @135714 GIM_Try, /*On fail goto*//*Label 2882*/ 135789, // Rule ID 7815 // GIM_CheckFeatures, GIFBS_HasSM4, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sm3tt2a, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // MIs[0] imm GIM_CheckIsImm, /*MI*/0, /*Op*/5, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS_timm, // (intrinsic_wo_chain:{ *:[v4i32] } 453:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<>:$imm) => (SM3TT2A:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SM3TT2A, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vdst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7815, GIR_Done, // Label 2882: @135789 GIM_Try, /*On fail goto*//*Label 2883*/ 135864, // Rule ID 7816 // GIM_CheckFeatures, GIFBS_HasSM4, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sm3tt2b, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // MIs[0] imm GIM_CheckIsImm, /*MI*/0, /*Op*/5, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS_timm, // (intrinsic_wo_chain:{ *:[v4i32] } 454:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<>:$imm) => (SM3TT2B:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SM3TT2B, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vdst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7816, GIR_Done, // Label 2883: @135864 GIM_Reject, // Label 2875: @135865 GIM_Reject, // Label 31: @135866 GIM_Try, /*On fail goto*//*Label 2884*/ 135933, GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, GIM_Try, /*On fail goto*//*Label 2885*/ 135891, // Rule ID 80 // GIM_CheckFeatures, GIFBS_HasTME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_tcommit, // (intrinsic_void 1485:{ *:[iPTR] }) => (TCOMMIT) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TCOMMIT, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 80, GIR_Done, // Label 2885: @135891 GIM_Try, /*On fail goto*//*Label 2886*/ 135911, // Rule ID 2254 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_setffr, // (intrinsic_void 1147:{ *:[iPTR] }) => (SETFFR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SETFFR, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2254, GIR_Done, // Label 2886: @135911 GIM_Try, /*On fail goto*//*Label 2887*/ 135932, // Rule ID 10278 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_clrex, // (intrinsic_void 414:{ *:[iPTR] }) => (CLREX 15:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLREX, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10278, GIR_Done, // Label 2887: @135932 GIM_Reject, // Label 2884: @135933 GIM_Try, /*On fail goto*//*Label 2888*/ 136408, GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, GIM_Try, /*On fail goto*//*Label 2889*/ 135969, // Rule ID 81 // GIM_CheckFeatures, GIFBS_HasTME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_tcancel, // MIs[0] imm GIM_CheckIsImm, /*MI*/0, /*Op*/1, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIPFP_I64_Predicate_timm64_0_65535, // (intrinsic_void 1484:{ *:[iPTR] }, (timm:{ *:[i64] })<>:$imm) => (TCANCEL (timm:{ *:[i64] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TCANCEL, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // imm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 81, GIR_Done, // Label 2889: @135969 GIM_Try, /*On fail goto*//*Label 2890*/ 135994, // Rule ID 225 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_break, // MIs[0] imm GIM_CheckIsImm, /*MI*/0, /*Op*/1, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIPFP_I64_Predicate_timm32_0_65535, // (intrinsic_void 413:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$imm) => (BRK (timm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BRK, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 225, GIR_Done, // Label 2890: @135994 GIM_Try, /*On fail goto*//*Label 2891*/ 136025, // Rule ID 7736 // GIM_CheckFeatures, GIFBS_HasSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sme_zero, // MIs[0] imm GIM_CheckIsImm, /*MI*/0, /*Op*/1, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIPFP_I64_Predicate_timm32_0_255, // (intrinsic_void 798:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$imm) => (ZERO_M_PSEUDO (timm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ZERO_M_PSEUDO, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // imm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7736, GIR_Done, // Label 2891: @136025 GIM_Try, /*On fail goto*//*Label 2892*/ 136063, // Rule ID 15 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_hint, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_127, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 467:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm) => (HINT (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HINT, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 15, GIR_Done, // Label 2892: @136063 GIM_Try, /*On fail goto*//*Label 2893*/ 136101, // Rule ID 16 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_dmb, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 458:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$CRm) => (DMB (imm:{ *:[i32] }):$CRm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DMB, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 16, GIR_Done, // Label 2893: @136101 GIM_Try, /*On fail goto*//*Label 2894*/ 136139, // Rule ID 17 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_dsb, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 459:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$CRm) => (DSB (imm:{ *:[i32] }):$CRm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DSB, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 17, GIR_Done, // Label 2894: @136139 GIM_Try, /*On fail goto*//*Label 2895*/ 136177, // Rule ID 18 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_isb, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 470:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$CRm) => (ISB (imm:{ *:[i32] }):$CRm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ISB, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 18, GIR_Done, // Label 2895: @136177 GIM_Try, /*On fail goto*//*Label 2896*/ 136203, // Rule ID 77 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_get_fpcr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_w_chain:{ *:[i64] } 465:{ *:[iPTR] }) => (MRS_FPCR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MRS_FPCR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 77, GIR_Done, // Label 2896: @136203 GIM_Try, /*On fail goto*//*Label 2897*/ 136235, // Rule ID 79 // GIM_CheckFeatures, GIFBS_HasTME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_tstart, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_w_chain:{ *:[i64] } 1486:{ *:[iPTR] }) => (TSTART:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TSTART, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 79, GIR_Done, // Label 2897: @136235 GIM_Try, /*On fail goto*//*Label 2898*/ 136263, // Rule ID 82 // GIM_CheckFeatures, GIFBS_HasTME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ttest, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_w_chain:{ *:[i64] } 1487:{ *:[iPTR] }) => (TTEST:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TTEST, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 82, GIR_Done, // Label 2898: @136263 GIM_Try, /*On fail goto*//*Label 2899*/ 136295, // Rule ID 2253 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_rdffr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (intrinsic_w_chain:{ *:[nxv16i1] } 1103:{ *:[iPTR] }) => (RDFFR_P:{ *:[nxv16i1] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RDFFR_P, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2253, GIR_Done, // Label 2899: @136295 GIM_Try, /*On fail goto*//*Label 2900*/ 136326, // Rule ID 6651 // GIM_CheckFeatures, GIFBS_HasSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sme_get_tpidr2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_w_chain:{ *:[i64] } 708:{ *:[iPTR] }) => (MRS:{ *:[i64] }:{ *:[i32] } 56965:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MRS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddImm, /*InsnID*/0, /*Imm*/56965, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6651, GIR_Done, // Label 2900: @136326 GIM_Try, /*On fail goto*//*Label 2901*/ 136358, // Rule ID 2255 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_wrffr, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPRRegClassID, // (intrinsic_void 1471:{ *:[iPTR] }, PPR8:{ *:[nxv16i1] }:$Pn) => (WRFFR:{ *:[i64] } PPR8:{ *:[nxv16i1] }:$Pn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::WRFFR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2255, GIR_Done, // Label 2901: @136358 GIM_Try, /*On fail goto*//*Label 2902*/ 136380, // Rule ID 78 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_set_fpcr, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, // (intrinsic_void 664:{ *:[iPTR] }, i64:{ *:[i64] }:$val) => (MSR_FPCR i64:{ *:[i64] }:$val) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSR_FPCR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 78, GIR_Done, // Label 2902: @136380 GIM_Try, /*On fail goto*//*Label 2903*/ 136407, // Rule ID 6650 // GIM_CheckFeatures, GIFBS_HasSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sme_set_tpidr2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, // (intrinsic_void 728:{ *:[iPTR] }, i64:{ *:[i64] }:$val) => (MSR 56965:{ *:[i32] }, GPR64:{ *:[i64] }:$val) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSR, GIR_AddImm, /*InsnID*/0, /*Imm*/56965, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6650, GIR_Done, // Label 2903: @136407 GIM_Reject, // Label 2888: @136408 GIM_Try, /*On fail goto*//*Label 2904*/ 137026, GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, GIM_Try, /*On fail goto*//*Label 2905*/ 136486, // Rule ID 10244 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldxr_1, // (intrinsic_w_chain:{ *:[i64] } 476:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRB, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 10244, GIR_Done, // Label 2905: @136486 GIM_Try, /*On fail goto*//*Label 2906*/ 136559, // Rule ID 10245 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldxr_2, // (intrinsic_w_chain:{ *:[i64] } 476:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 10245, GIR_Done, // Label 2906: @136559 GIM_Try, /*On fail goto*//*Label 2907*/ 136632, // Rule ID 10246 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldxr_4, // (intrinsic_w_chain:{ *:[i64] } 476:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 10246, GIR_Done, // Label 2907: @136632 GIM_Try, /*On fail goto*//*Label 2908*/ 136677, // Rule ID 10247 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldxr_8, // (intrinsic_w_chain:{ *:[i64] } 476:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (LDXRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDXRX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10247, GIR_Done, // Label 2908: @136677 GIM_Try, /*On fail goto*//*Label 2909*/ 136750, // Rule ID 10251 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldaxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldaxr_1, // (intrinsic_w_chain:{ *:[i64] } 473:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRB, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 10251, GIR_Done, // Label 2909: @136750 GIM_Try, /*On fail goto*//*Label 2910*/ 136823, // Rule ID 10252 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldaxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldaxr_2, // (intrinsic_w_chain:{ *:[i64] } 473:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 10252, GIR_Done, // Label 2910: @136823 GIM_Try, /*On fail goto*//*Label 2911*/ 136896, // Rule ID 10253 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldaxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldaxr_4, // (intrinsic_w_chain:{ *:[i64] } 473:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 10253, GIR_Done, // Label 2911: @136896 GIM_Try, /*On fail goto*//*Label 2912*/ 136941, // Rule ID 10254 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldaxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldaxr_8, // (intrinsic_w_chain:{ *:[i64] } 473:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (LDAXRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDAXRX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10254, GIR_Done, // Label 2912: @136941 GIM_Try, /*On fail goto*//*Label 2913*/ 136985, // Rule ID 2252 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_rdffr_z, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::PPRRegClassID, // (intrinsic_w_chain:{ *:[nxv16i1] } 1104:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pg) => (RDFFR_PPz:{ *:[nxv16i1] } PPRAny:{ *:[nxv16i1] }:$Pg) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RDFFR_PPz, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Pd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Pg GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2252, GIR_Done, // Label 2913: @136985 GIM_Try, /*On fail goto*//*Label 2914*/ 137025, // Rule ID 7963 // GIM_CheckFeatures, GIFBS_HasMTE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_irg_sp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i64] } 469:{ *:[iPTR] }, i64:{ *:[i64] }:$Rm) => (IRGstack:{ *:[i64] } SP:{ *:[i64] }, i64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::IRGstack, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddRegister, /*InsnID*/0, AArch64::SP, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7963, GIR_Done, // Label 2914: @137025 GIM_Reject, // Label 2904: @137026 GIM_Try, /*On fail goto*//*Label 2915*/ 139207, GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, GIM_Try, /*On fail goto*//*Label 2916*/ 137124, // Rule ID 10262 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 255, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_w_chain:{ *:[i32] } 808:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 255:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<> => (STXRB:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10262, GIR_Done, // Label 2916: @137124 GIM_Try, /*On fail goto*//*Label 2917*/ 137217, // Rule ID 10263 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_w_chain:{ *:[i32] } 808:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 65535:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<> => (STXRH:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10263, GIR_Done, // Label 2917: @137217 GIM_Try, /*On fail goto*//*Label 2918*/ 137310, // Rule ID 10272 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 255, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_w_chain:{ *:[i32] } 806:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 255:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<> => (STLXRB:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10272, GIR_Done, // Label 2918: @137310 GIM_Try, /*On fail goto*//*Label 2919*/ 137403, // Rule ID 10273 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_2, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_w_chain:{ *:[i32] } 806:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 65535:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<> => (STLXRH:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10273, GIR_Done, // Label 2919: @137403 GIM_Try, /*On fail goto*//*Label 2920*/ 137505, // Rule ID 10265 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 808:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 255:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<> => (STXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10265, GIR_Done, // Label 2920: @137505 GIM_Try, /*On fail goto*//*Label 2921*/ 137607, // Rule ID 10266 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_2, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 808:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 65535:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<> => (STXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10266, GIR_Done, // Label 2921: @137607 GIM_Try, /*On fail goto*//*Label 2922*/ 137709, // Rule ID 10267 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294967295, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_4, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 808:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 4294967295:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<> => (STXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10267, GIR_Done, // Label 2922: @137709 GIM_Try, /*On fail goto*//*Label 2923*/ 137811, // Rule ID 10275 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 806:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 255:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<> => (STLXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10275, GIR_Done, // Label 2923: @137811 GIM_Try, /*On fail goto*//*Label 2924*/ 137913, // Rule ID 10276 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_2, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 806:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 65535:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<> => (STLXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10276, GIR_Done, // Label 2924: @137913 GIM_Try, /*On fail goto*//*Label 2925*/ 138015, // Rule ID 10277 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294967295, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_4, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 806:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 4294967295:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<> => (STLXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10277, GIR_Done, // Label 2925: @138015 GIM_Try, /*On fail goto*//*Label 2926*/ 138086, // Rule ID 10264 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_4, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 808:{ *:[iPTR] }, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$val), GPR64sp:{ *:[i64] }:$addr)<> => (STXRW:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10264, GIR_Done, // Label 2926: @138086 GIM_Try, /*On fail goto*//*Label 2927*/ 138157, // Rule ID 10274 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_4, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 806:{ *:[iPTR] }, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$val), GPR64sp:{ *:[i64] }:$addr)<> => (STLXRW:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10274, GIR_Done, // Label 2927: @138157 GIM_Try, /*On fail goto*//*Label 2928*/ 138215, // Rule ID 3487 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prf, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/3, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1075:{ *:[iPTR] }, PPR_3b:{ *:[nxv16i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<>:$prfop) => (PRFB_PRI (timm:{ *:[i32] })<>:$prfop, PPR_3b:{ *:[nxv16i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFB_PRI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // gp GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3487, GIR_Done, // Label 2928: @138215 GIM_Try, /*On fail goto*//*Label 2929*/ 138273, // Rule ID 3490 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prf, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/3, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1075:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<>:$prfop) => (PRFH_PRI (timm:{ *:[i32] })<>:$prfop, PPR_3b:{ *:[nxv8i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFH_PRI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // gp GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3490, GIR_Done, // Label 2929: @138273 GIM_Try, /*On fail goto*//*Label 2930*/ 138331, // Rule ID 3493 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prf, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/3, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1075:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<>:$prfop) => (PRFW_PRI (timm:{ *:[i32] })<>:$prfop, PPR_3b:{ *:[nxv4i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFW_PRI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // gp GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3493, GIR_Done, // Label 2930: @138331 GIM_Try, /*On fail goto*//*Label 2931*/ 138389, // Rule ID 3496 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prf, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/3, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1075:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<>:$prfop) => (PRFD_PRI (timm:{ *:[i32] })<>:$prfop, PPR_3b:{ *:[nxv2i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFD_PRI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // gp GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3496, GIR_Done, // Label 2931: @138389 GIM_Try, /*On fail goto*//*Label 2932*/ 138448, // Rule ID 14 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_space, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i64] } 799:{ *:[iPTR] }, (imm:{ *:[i32] }):$size, GPR64:{ *:[i64] }:$Rn) => (SPACE:{ *:[i64] } (imm:{ *:[i32] }):$size, GPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SPACE, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // size GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 14, GIR_Done, // Label 2932: @138448 GIM_Try, /*On fail goto*//*Label 2933*/ 138504, // Rule ID 75 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::hwasan_check_memaccess, // MIs[0] Operand 1 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64noipRegClassID, // MIs[0] accessinfo GIM_CheckIsImm, /*MI*/0, /*Op*/3, // (intrinsic_void 154:{ *:[iPTR] }, X9:{ *:[i64] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo) => (HWASAN_CHECK_MEMACCESS:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo) GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddRegister, /*InsnID*/1, AArch64::X9, /*AddRegisterRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // X9 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HWASAN_CHECK_MEMACCESS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ptr GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // accessinfo GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 75, GIR_Done, // Label 2933: @138504 GIM_Try, /*On fail goto*//*Label 2934*/ 138560, // Rule ID 76 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::hwasan_check_memaccess_shortgranules, // MIs[0] Operand 1 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64common_and_GPR64noipRegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64noipRegClassID, // MIs[0] accessinfo GIM_CheckIsImm, /*MI*/0, /*Op*/3, // (intrinsic_void 155:{ *:[iPTR] }, X20:{ *:[i64] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo) => (HWASAN_CHECK_MEMACCESS_SHORTGRANULES:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo) GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddRegister, /*InsnID*/1, AArch64::X20, /*AddRegisterRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // X20 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ptr GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // accessinfo GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 76, GIR_Done, // Label 2934: @138560 GIM_Try, /*On fail goto*//*Label 2935*/ 138640, // Rule ID 10258 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_1, // (intrinsic_w_chain:{ *:[i32] } 808:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10258, GIR_Done, // Label 2935: @138640 GIM_Try, /*On fail goto*//*Label 2936*/ 138720, // Rule ID 10259 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_2, // (intrinsic_w_chain:{ *:[i32] } 808:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10259, GIR_Done, // Label 2936: @138720 GIM_Try, /*On fail goto*//*Label 2937*/ 138800, // Rule ID 10260 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_4, // (intrinsic_w_chain:{ *:[i32] } 808:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10260, GIR_Done, // Label 2937: @138800 GIM_Try, /*On fail goto*//*Label 2938*/ 138857, // Rule ID 10261 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_8, // (intrinsic_w_chain:{ *:[i32] } 808:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STXRX:{ *:[i32] } GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10261, GIR_Done, // Label 2938: @138857 GIM_Try, /*On fail goto*//*Label 2939*/ 138937, // Rule ID 10268 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_1, // (intrinsic_w_chain:{ *:[i32] } 806:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STLXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10268, GIR_Done, // Label 2939: @138937 GIM_Try, /*On fail goto*//*Label 2940*/ 139017, // Rule ID 10269 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_2, // (intrinsic_w_chain:{ *:[i32] } 806:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STLXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10269, GIR_Done, // Label 2940: @139017 GIM_Try, /*On fail goto*//*Label 2941*/ 139097, // Rule ID 10270 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_4, // (intrinsic_w_chain:{ *:[i32] } 806:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STLXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10270, GIR_Done, // Label 2941: @139097 GIM_Try, /*On fail goto*//*Label 2942*/ 139154, // Rule ID 10271 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_8, // (intrinsic_w_chain:{ *:[i32] } 806:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STLXRX:{ *:[i32] } GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10271, GIR_Done, // Label 2942: @139154 GIM_Try, /*On fail goto*//*Label 2943*/ 139206, // Rule ID 139 // GIM_CheckFeatures, GIFBS_HasMTE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_irg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_w_chain:{ *:[i64] } 468:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (IRG:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::IRG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 139, GIR_Done, // Label 2943: @139206 GIM_Reject, // Label 2915: @139207 GIM_Try, /*On fail goto*//*Label 2944*/ 140835, GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, GIM_Try, /*On fail goto*//*Label 2945*/ 139287, // Rule ID 7627 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfb_gather_scalar_offset, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, // MIs[1] Operand 1 // No operand predicates // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1077:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR32:{ *:[nxv4i32] }:$Zn, (imm:{ *:[i64] })<>:$imm, (timm:{ *:[i32] })<>:$prfop) => (PRFB_S_PZI (timm:{ *:[i32] })<>:$prfop, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR32:{ *:[nxv4i32] }:$Zn, (imm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFB_S_PZI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Zn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7627, GIR_Done, // Label 2945: @139287 GIM_Try, /*On fail goto*//*Label 2946*/ 139362, // Rule ID 7640 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfb_gather_scalar_offset, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, // MIs[1] Operand 1 // No operand predicates // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1077:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR32:{ *:[nxv2i64] }:$Zn, (imm:{ *:[i64] })<>:$imm, (timm:{ *:[i32] })<>:$prfop) => (PRFB_D_PZI (timm:{ *:[i32] })<>:$prfop, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR32:{ *:[nxv2i64] }:$Zn, (imm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFB_D_PZI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Zn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7640, GIR_Done, // Label 2946: @139362 GIM_Try, /*On fail goto*//*Label 2947*/ 139429, // Rule ID 3499 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfh_gather_uxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1087:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW16:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFH_S_UXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW16:{ *:[nxv4i32] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFH_S_UXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3499, GIR_Done, // Label 2947: @139429 GIM_Try, /*On fail goto*//*Label 2948*/ 139496, // Rule ID 3500 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfh_gather_sxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1086:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW16:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFH_S_SXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW16:{ *:[nxv4i32] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFH_S_SXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3500, GIR_Done, // Label 2948: @139496 GIM_Try, /*On fail goto*//*Label 2949*/ 139563, // Rule ID 3501 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfw_gather_uxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1091:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW32:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFW_S_UXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW32:{ *:[nxv4i32] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFW_S_UXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3501, GIR_Done, // Label 2949: @139563 GIM_Try, /*On fail goto*//*Label 2950*/ 139630, // Rule ID 3502 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfw_gather_sxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1090:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW32:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFW_S_SXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW32:{ *:[nxv4i32] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFW_S_SXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3502, GIR_Done, // Label 2950: @139630 GIM_Try, /*On fail goto*//*Label 2951*/ 139697, // Rule ID 3503 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfd_gather_uxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1083:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW64:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFD_S_UXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW64:{ *:[nxv4i32] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFD_S_UXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3503, GIR_Done, // Label 2951: @139697 GIM_Try, /*On fail goto*//*Label 2952*/ 139764, // Rule ID 3504 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfd_gather_sxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1082:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW64:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFD_S_SXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW64:{ *:[nxv4i32] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFD_S_SXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3504, GIR_Done, // Label 2952: @139764 GIM_Try, /*On fail goto*//*Label 2953*/ 139831, // Rule ID 3505 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfh_gather_uxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1087:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW16:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFH_D_UXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW16:{ *:[nxv2i64] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFH_D_UXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3505, GIR_Done, // Label 2953: @139831 GIM_Try, /*On fail goto*//*Label 2954*/ 139898, // Rule ID 3506 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfh_gather_sxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1086:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW16:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFH_D_SXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW16:{ *:[nxv2i64] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFH_D_SXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3506, GIR_Done, // Label 2954: @139898 GIM_Try, /*On fail goto*//*Label 2955*/ 139965, // Rule ID 3507 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfw_gather_uxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1091:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW32:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFW_D_UXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW32:{ *:[nxv2i64] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFW_D_UXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3507, GIR_Done, // Label 2955: @139965 GIM_Try, /*On fail goto*//*Label 2956*/ 140032, // Rule ID 3508 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfw_gather_sxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1090:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW32:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFW_D_SXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW32:{ *:[nxv2i64] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFW_D_SXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3508, GIR_Done, // Label 2956: @140032 GIM_Try, /*On fail goto*//*Label 2957*/ 140099, // Rule ID 3509 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfd_gather_uxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1083:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW64:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFD_D_UXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW64:{ *:[nxv2i64] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFD_D_UXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3509, GIR_Done, // Label 2957: @140099 GIM_Try, /*On fail goto*//*Label 2958*/ 140166, // Rule ID 3510 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfd_gather_sxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1082:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW64:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFD_D_SXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW64:{ *:[nxv2i64] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFD_D_SXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3510, GIR_Done, // Label 2958: @140166 GIM_Try, /*On fail goto*//*Label 2959*/ 140233, // Rule ID 3511 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfh_gather_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1084:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL16:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFH_D_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL16:{ *:[nxv2i64] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFH_D_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3511, GIR_Done, // Label 2959: @140233 GIM_Try, /*On fail goto*//*Label 2960*/ 140300, // Rule ID 3512 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfw_gather_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1088:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL32:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFW_D_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL32:{ *:[nxv2i64] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFW_D_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3512, GIR_Done, // Label 2960: @140300 GIM_Try, /*On fail goto*//*Label 2961*/ 140367, // Rule ID 3513 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfd_gather_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1080:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL64:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFD_D_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL64:{ *:[nxv2i64] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFD_D_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3513, GIR_Done, // Label 2961: @140367 GIM_Try, /*On fail goto*//*Label 2962*/ 140434, // Rule ID 7625 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfb_gather_uxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1079:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW8Only:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFB_S_UXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW8Only:{ *:[nxv4i32] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFB_S_UXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7625, GIR_Done, // Label 2962: @140434 GIM_Try, /*On fail goto*//*Label 2963*/ 140501, // Rule ID 7626 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfb_gather_sxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1078:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW8Only:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFB_S_SXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW8Only:{ *:[nxv4i32] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFB_S_SXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7626, GIR_Done, // Label 2963: @140501 GIM_Try, /*On fail goto*//*Label 2964*/ 140568, // Rule ID 7637 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfb_gather_uxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1079:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW8Only:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFB_D_UXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW8Only:{ *:[nxv2i64] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFB_D_UXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7637, GIR_Done, // Label 2964: @140568 GIM_Try, /*On fail goto*//*Label 2965*/ 140635, // Rule ID 7638 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfb_gather_sxtw_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1078:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW8Only:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFB_D_SXTW_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW8Only:{ *:[nxv2i64] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFB_D_SXTW_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7638, GIR_Done, // Label 2965: @140635 GIM_Try, /*On fail goto*//*Label 2966*/ 140702, // Rule ID 7639 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_prfb_gather_index, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::PPR_3bRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, // MIs[0] prfop GIM_CheckIsImm, /*MI*/0, /*Op*/4, GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIPFP_I64_Predicate_sve_prfop, // (intrinsic_void 1076:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL8:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<>:$prfop) => (PRFB_D_SCALED (timm:{ *:[i32] })<>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL8:{ *:[nxv2i64] }:$Zm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFB_D_SCALED, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // prfop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Pg GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7639, GIR_Done, // Label 2966: @140702 GIM_Try, /*On fail goto*//*Label 2967*/ 140768, // Rule ID 6776 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/4, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_w_chain:{ *:[i32] } 805:{ *:[iPTR] }, GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr) => (STLXPX:{ *:[i32] } GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXPX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lo GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // hi GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6776, GIR_Done, // Label 2967: @140768 GIM_Try, /*On fail goto*//*Label 2968*/ 140834, // Rule ID 6777 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/4, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_w_chain:{ *:[i32] } 807:{ *:[iPTR] }, GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr) => (STXPX:{ *:[i32] } GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXPX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lo GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // hi GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6777, GIR_Done, // Label 2968: @140834 GIM_Reject, // Label 2944: @140835 GIM_Reject, // Label 32: @140836 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 10, /*)*//*default:*//*Label 2973*/ 141012, /*GILLT_s64*//*Label 2969*/ 140850, 0, 0, /*GILLT_v2s64*//*Label 2970*/ 140910, 0, /*GILLT_v4s32*//*Label 2971*/ 140944, 0, /*GILLT_v8s16*//*Label 2972*/ 140978, // Label 2969: @140850 GIM_Try, /*On fail goto*//*Label 2974*/ 140909, // Rule ID 9615 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 9615, GIR_Done, // Label 2974: @140909 GIM_Reject, // Label 2970: @140910 GIM_Try, /*On fail goto*//*Label 2975*/ 140943, // Rule ID 9489 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn) => (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9489, GIR_Done, // Label 2975: @140943 GIM_Reject, // Label 2971: @140944 GIM_Try, /*On fail goto*//*Label 2976*/ 140977, // Rule ID 9486 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9486, GIR_Done, // Label 2976: @140977 GIM_Reject, // Label 2972: @140978 GIM_Try, /*On fail goto*//*Label 2977*/ 141011, // Rule ID 9483 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn) => (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9483, GIR_Done, // Label 2977: @141011 GIM_Reject, // Label 2973: @141012 GIM_Reject, // Label 33: @141013 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 2982*/ 142020, /*GILLT_s32*//*Label 2978*/ 141027, 0, 0, /*GILLT_v2s32*//*Label 2979*/ 141065, 0, /*GILLT_v4s16*//*Label 2980*/ 141506, 0, /*GILLT_v8s8*//*Label 2981*/ 141763, // Label 2978: @141027 GIM_Try, /*On fail goto*//*Label 2983*/ 141064, // Rule ID 9636 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (trunc:{ *:[i32] } GPR64sp:{ *:[i64] }:$src) => (EXTRACT_SUBREG:{ *:[i32] } GPR64sp:{ *:[i64] }:$src, sub_32:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/15, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32spRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64spRegClassID, // GIR_Coverage, 9636, GIR_Done, // Label 2983: @141064 GIM_Reject, // Label 2979: @141065 GIM_Try, /*On fail goto*//*Label 2984*/ 141505, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2985*/ 141167, // Rule ID 11789 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, AArch64::G_DUP, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/3, /*Op*/1, 2147483648, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // MIs[1] Operand 2 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 32, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (add:{ *:[v2i64] } (AArch64dup:{ *:[v2i64] } 2147483648:{ *:[i64] }), V128:{ *:[v2i64] }:$Vn), 32:{ *:[i32] })) => (RADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vn, (MOVIv2d_ns:{ *:[v2i64] } 0:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVIv2d_ns, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv2i64_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11789, GIR_Done, // Label 2985: @141167 GIM_Try, /*On fail goto*//*Label 2986*/ 141259, // Rule ID 9471 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, AArch64::G_DUP, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/3, /*Op*/1, 2147483648, // MIs[1] Operand 2 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 32, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, (AArch64dup:{ *:[v2i64] } 2147483648:{ *:[i64] })), 32:{ *:[i32] })) => (RADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vn, (MOVIv2d_ns:{ *:[v2i64] } 0:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVIv2d_ns, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv2i64_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9471, GIR_Done, // Label 2986: @141259 GIM_Try, /*On fail goto*//*Label 2987*/ 141323, // Rule ID 8830 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // MIs[1] Operand 2 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 32, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] })) => (ADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv2i64_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8830, GIR_Done, // Label 2987: @141323 GIM_Try, /*On fail goto*//*Label 2988*/ 141387, // Rule ID 8836 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // MIs[1] Operand 2 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 32, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] })) => (SUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv2i64_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8836, GIR_Done, // Label 2988: @141387 GIM_Try, /*On fail goto*//*Label 2989*/ 141439, // Rule ID 2075 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (trunc:{ *:[v2i32] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2075, GIR_Done, // Label 2989: @141439 GIM_Try, /*On fail goto*//*Label 2990*/ 141489, // Rule ID 9477 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9477, GIR_Done, // Label 2990: @141489 GIM_Try, /*On fail goto*//*Label 2991*/ 141504, // Rule ID 1072 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) => (XTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::XTNv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1072, GIR_Done, // Label 2991: @141504 GIM_Reject, // Label 2984: @141505 GIM_Reject, // Label 2980: @141506 GIM_Try, /*On fail goto*//*Label 2992*/ 141762, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2993*/ 141580, // Rule ID 8829 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // MIs[1] Operand 2 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] })) => (ADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv4i32_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8829, GIR_Done, // Label 2993: @141580 GIM_Try, /*On fail goto*//*Label 2994*/ 141644, // Rule ID 8835 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // MIs[1] Operand 2 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] })) => (SUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv4i32_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8835, GIR_Done, // Label 2994: @141644 GIM_Try, /*On fail goto*//*Label 2995*/ 141696, // Rule ID 2074 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (trunc:{ *:[v4i16] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2074, GIR_Done, // Label 2995: @141696 GIM_Try, /*On fail goto*//*Label 2996*/ 141746, // Rule ID 9476 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9476, GIR_Done, // Label 2996: @141746 GIM_Try, /*On fail goto*//*Label 2997*/ 141761, // Rule ID 1071 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) => (XTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::XTNv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1071, GIR_Done, // Label 2997: @141761 GIM_Reject, // Label 2992: @141762 GIM_Reject, // Label 2981: @141763 GIM_Try, /*On fail goto*//*Label 2998*/ 142019, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2999*/ 141837, // Rule ID 8828 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // MIs[1] Operand 2 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 8, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] })) => (ADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv8i16_v8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8828, GIR_Done, // Label 2999: @141837 GIM_Try, /*On fail goto*//*Label 3000*/ 141901, // Rule ID 8834 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // MIs[1] Operand 2 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 8, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] })) => (SUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv8i16_v8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8834, GIR_Done, // Label 3000: @141901 GIM_Try, /*On fail goto*//*Label 3001*/ 141953, // Rule ID 2073 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (trunc:{ *:[v8i8] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2073, GIR_Done, // Label 3001: @141953 GIM_Try, /*On fail goto*//*Label 3002*/ 142003, // Rule ID 9475 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[1] imm GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9475, GIR_Done, // Label 3002: @142003 GIM_Try, /*On fail goto*//*Label 3003*/ 142018, // Rule ID 1070 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) => (XTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::XTNv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1070, GIR_Done, // Label 3003: @142018 GIM_Reject, // Label 2998: @142019 GIM_Reject, // Label 2982: @142020 GIM_Reject, // Label 34: @142021 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 3006*/ 142128, /*GILLT_s32*//*Label 3004*/ 142029, /*GILLT_s64*//*Label 3005*/ 142051, // Label 3004: @142029 GIM_Try, /*On fail goto*//*Label 3007*/ 142050, // Rule ID 83 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Operand 1 // No operand predicates // (imm:{ *:[i32] }):$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MOVi32imm, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 83, GIR_Done, // Label 3007: @142050 GIM_Reject, // Label 3005: @142051 GIM_Try, /*On fail goto*//*Label 3008*/ 142106, // Rule ID 7867 // GIM_CheckFeatures, GIFBS_OptimizedGISelOrOtherSelector, GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, // MIs[0] Operand 1 // No operand predicates // (imm:{ *:[i64] })<>:$src => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$src)), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/0, /*Renderer*/GICR_renderTruncImm, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, // GIR_Coverage, 7867, GIR_Done, // Label 3008: @142106 GIM_Try, /*On fail goto*//*Label 3009*/ 142127, // Rule ID 84 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Operand 1 // No operand predicates // (imm:{ *:[i64] }):$src => (MOVi64imm:{ *:[i64] } (imm:{ *:[i64] }):$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MOVi64imm, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 84, GIR_Done, // Label 3009: @142127 GIM_Reject, // Label 3006: @142128 GIM_Reject, // Label 35: @142129 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 3013*/ 142340, /*GILLT_s16*//*Label 3010*/ 142138, /*GILLT_s32*//*Label 3011*/ 142189, /*GILLT_s64*//*Label 3012*/ 142291, // Label 3010: @142138 GIM_Try, /*On fail goto*//*Label 3014*/ 142161, // Rule ID 487 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, // MIs[0] Operand 1 // No operand predicates // (fpimm:{ *:[f16] })<> => (FMOVH0:{ *:[f16] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVH0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 487, GIR_Done, // Label 3014: @142161 GIM_Try, /*On fail goto*//*Label 3015*/ 142188, // Rule ID 669 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, // MIs[0] Operand 1 // No operand predicates // (fpimm:{ *:[f16] })<><>:$imm => (FMOVHi:{ *:[f16] } (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVHi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderFPImm16, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 669, GIR_Done, // Label 3015: @142188 GIM_Reject, // Label 3011: @142189 GIM_Try, /*On fail goto*//*Label 3016*/ 142210, // Rule ID 488 // GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, // MIs[0] Operand 1 // No operand predicates // (fpimm:{ *:[f32] })<> => (FMOVS0:{ *:[f32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVS0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 488, GIR_Done, // Label 3016: @142210 GIM_Try, /*On fail goto*//*Label 3017*/ 142237, // Rule ID 670 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, // MIs[0] Operand 1 // No operand predicates // (fpimm:{ *:[f32] })<><>:$imm => (FMOVSi:{ *:[f32] } (fpimm32XForm:{ *:[f32] } (fpimm:{ *:[f32] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVSi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderFPImm32, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 670, GIR_Done, // Label 3017: @142237 GIM_Try, /*On fail goto*//*Label 3018*/ 142290, // Rule ID 9211 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm32SIMDModImmType4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, // MIs[0] Operand 1 // No operand predicates // (fpimm:{ *:[f32] })<><>:$in => (EXTRACT_SUBREG:{ *:[f32] } (MOVIv2i32:{ *:[i64] } (fpimm32SIMDModImmType4XForm:{ *:[i32] } f32:{ *:[f32] }:$in), 24:{ *:[i32] }), ssub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVIv2i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/0, /*Renderer*/GICR_renderFPImm32SIMDModImmType4, // in GIR_AddImm, /*InsnID*/1, /*Imm*/24, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR64RegClassID, // GIR_Coverage, 9211, GIR_Done, // Label 3018: @142290 GIM_Reject, // Label 3012: @142291 GIM_Try, /*On fail goto*//*Label 3019*/ 142312, // Rule ID 489 // GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, // MIs[0] Operand 1 // No operand predicates // (fpimm:{ *:[f64] })<> => (FMOVD0:{ *:[f64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVD0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 489, GIR_Done, // Label 3019: @142312 GIM_Try, /*On fail goto*//*Label 3020*/ 142339, // Rule ID 671 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, // MIs[0] Operand 1 // No operand predicates // (fpimm:{ *:[f64] })<><>:$imm => (FMOVDi:{ *:[f64] } (fpimm64XForm:{ *:[f64] } (fpimm:{ *:[f64] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderFPImm64, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 671, GIR_Done, // Label 3020: @142339 GIM_Reject, // Label 3013: @142340 GIM_Reject, // Label 36: @142341 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 10, /*)*//*default:*//*Label 3025*/ 142675, /*GILLT_s64*//*Label 3021*/ 142355, 0, 0, /*GILLT_v2s64*//*Label 3022*/ 142573, 0, /*GILLT_v4s32*//*Label 3023*/ 142607, 0, /*GILLT_v8s16*//*Label 3024*/ 142641, // Label 3021: @142355 GIM_Try, /*On fail goto*//*Label 3026*/ 142572, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3027*/ 142444, // Rule ID 5748 // GIM_CheckFeatures, GIFBS_NotInStreamingSVEMode, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sext:{ *:[i64] } (vector_extract:{ *:[i32] } ZPR:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<>:$index)) => (SMOVvi32to64:{ *:[i64] } (EXTRACT_SUBREG:{ *:[v4i32] } ZPR:{ *:[nxv4i32] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$index) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/37, // vec GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::ZPRRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMOVvi32to64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5748, GIR_Done, // Label 3027: @142444 GIM_Try, /*On fail goto*//*Label 3028*/ 142498, // Rule ID 8988 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<>:$idx)) => (SMOVvi32to64:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMOVvi32to64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8988, GIR_Done, // Label 3028: @142498 GIM_Try, /*On fail goto*//*Label 3029*/ 142571, // Rule ID 9617 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (SBFMXri:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i64] }, 31:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/31, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9617, GIR_Done, // Label 3029: @142571 GIM_Reject, // Label 3026: @142572 GIM_Reject, // Label 3022: @142573 GIM_Try, /*On fail goto*//*Label 3030*/ 142606, // Rule ID 9487 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn) => (SSHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLLv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9487, GIR_Done, // Label 3030: @142606 GIM_Reject, // Label 3023: @142607 GIM_Try, /*On fail goto*//*Label 3031*/ 142640, // Rule ID 9484 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (SSHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLLv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9484, GIR_Done, // Label 3031: @142640 GIM_Reject, // Label 3024: @142641 GIM_Try, /*On fail goto*//*Label 3032*/ 142674, // Rule ID 9481 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn) => (SSHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLLv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9481, GIR_Done, // Label 3032: @142674 GIM_Reject, // Label 3025: @142675 GIM_Reject, // Label 37: @142676 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 10, /*)*//*default:*//*Label 3036*/ 143134, /*GILLT_v2s64*//*Label 3033*/ 142687, 0, /*GILLT_v4s32*//*Label 3034*/ 142836, 0, /*GILLT_v8s16*//*Label 3035*/ 142985, // Label 3033: @142687 GIM_Try, /*On fail goto*//*Label 3037*/ 142835, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 3038*/ 142753, // Rule ID 681 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 614:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 681, GIR_Done, // Label 3038: @142753 GIM_Try, /*On fail goto*//*Label 3039*/ 142809, // Rule ID 1673 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 549:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1673, GIR_Done, // Label 3039: @142809 GIM_Try, /*On fail goto*//*Label 3040*/ 142834, // Rule ID 9488 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn) => (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9488, GIR_Done, // Label 3040: @142834 GIM_Reject, // Label 3037: @142835 GIM_Reject, // Label 3034: @142836 GIM_Try, /*On fail goto*//*Label 3041*/ 142984, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 3042*/ 142902, // Rule ID 677 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 614:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 677, GIR_Done, // Label 3042: @142902 GIM_Try, /*On fail goto*//*Label 3043*/ 142958, // Rule ID 1669 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 549:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1669, GIR_Done, // Label 3043: @142958 GIM_Try, /*On fail goto*//*Label 3044*/ 142983, // Rule ID 9485 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9485, GIR_Done, // Label 3044: @142983 GIM_Reject, // Label 3041: @142984 GIM_Reject, // Label 3035: @142985 GIM_Try, /*On fail goto*//*Label 3045*/ 143133, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 3046*/ 143051, // Rule ID 673 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 614:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 673, GIR_Done, // Label 3046: @143051 GIM_Try, /*On fail goto*//*Label 3047*/ 143107, // Rule ID 1665 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 549:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1665, GIR_Done, // Label 3047: @143107 GIM_Try, /*On fail goto*//*Label 3048*/ 143132, // Rule ID 9482 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn) => (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9482, GIR_Done, // Label 3048: @143132 GIM_Reject, // Label 3045: @143133 GIM_Reject, // Label 3036: @143134 GIM_Reject, // Label 38: @143135 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 3051*/ 143447, /*GILLT_s32*//*Label 3049*/ 143143, /*GILLT_s64*//*Label 3050*/ 143280, // Label 3049: @143143 GIM_Try, /*On fail goto*//*Label 3052*/ 143279, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3053*/ 143200, // Rule ID 7897 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7897, GIR_Done, // Label 3053: @143200 GIM_Try, /*On fail goto*//*Label 3054*/ 143239, // Rule ID 7898 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7898, GIR_Done, // Label 3054: @143239 GIM_Try, /*On fail goto*//*Label 3055*/ 143278, // Rule ID 7896 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7896, GIR_Done, // Label 3055: @143278 GIM_Reject, // Label 3052: @143279 GIM_Reject, // Label 3050: @143280 GIM_Try, /*On fail goto*//*Label 3056*/ 143446, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3057*/ 143365, // Rule ID 7899 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7899, GIR_Done, // Label 3057: @143365 GIM_Try, /*On fail goto*//*Label 3058*/ 143432, // Rule ID 7900 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7900, GIR_Done, // Label 3058: @143432 GIM_Try, /*On fail goto*//*Label 3059*/ 143445, // Rule ID 122 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LSLVXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 122, GIR_Done, // Label 3059: @143445 GIM_Reject, // Label 3056: @143446 GIM_Reject, // Label 3051: @143447 GIM_Reject, // Label 39: @143448 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 3062*/ 143832, /*GILLT_s32*//*Label 3060*/ 143456, /*GILLT_s64*//*Label 3061*/ 143629, // Label 3060: @143456 GIM_Try, /*On fail goto*//*Label 3063*/ 143628, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3064*/ 143510, // Rule ID 7983 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (UBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<>:$imm, 31:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UBFMWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/31, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7983, GIR_Done, // Label 3064: @143510 GIM_Try, /*On fail goto*//*Label 3065*/ 143549, // Rule ID 7903 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7903, GIR_Done, // Label 3065: @143549 GIM_Try, /*On fail goto*//*Label 3066*/ 143588, // Rule ID 7904 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7904, GIR_Done, // Label 3066: @143588 GIM_Try, /*On fail goto*//*Label 3067*/ 143627, // Rule ID 7902 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7902, GIR_Done, // Label 3067: @143627 GIM_Reject, // Label 3063: @143628 GIM_Reject, // Label 3061: @143629 GIM_Try, /*On fail goto*//*Label 3068*/ 143831, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3069*/ 143683, // Rule ID 7984 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_63, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (UBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$imm, 63:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UBFMXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/63, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7984, GIR_Done, // Label 3069: @143683 GIM_Try, /*On fail goto*//*Label 3070*/ 143750, // Rule ID 7905 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7905, GIR_Done, // Label 3070: @143750 GIM_Try, /*On fail goto*//*Label 3071*/ 143817, // Rule ID 7906 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7906, GIR_Done, // Label 3071: @143817 GIM_Try, /*On fail goto*//*Label 3072*/ 143830, // Rule ID 123 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LSRVXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 123, GIR_Done, // Label 3072: @143830 GIM_Reject, // Label 3068: @143831 GIM_Reject, // Label 3062: @143832 GIM_Reject, // Label 40: @143833 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 3075*/ 144327, /*GILLT_s32*//*Label 3073*/ 143841, /*GILLT_s64*//*Label 3074*/ 144014, // Label 3073: @143841 GIM_Try, /*On fail goto*//*Label 3076*/ 144013, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3077*/ 143895, // Rule ID 7981 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<>:$imm, 31:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/31, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7981, GIR_Done, // Label 3077: @143895 GIM_Try, /*On fail goto*//*Label 3078*/ 143934, // Rule ID 6781 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6781, GIR_Done, // Label 3078: @143934 GIM_Try, /*On fail goto*//*Label 3079*/ 143973, // Rule ID 6782 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6782, GIR_Done, // Label 3079: @143973 GIM_Try, /*On fail goto*//*Label 3080*/ 144012, // Rule ID 6780 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6780, GIR_Done, // Label 3080: @144012 GIM_Reject, // Label 3076: @144013 GIM_Reject, // Label 3074: @144014 GIM_Try, /*On fail goto*//*Label 3081*/ 144326, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3082*/ 144126, // Rule ID 9635 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm0_31, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sra:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$imm) => (SBFMXri:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] }), (imm:{ *:[i64] })<>:$imm, 31:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/31, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9635, GIR_Done, // Label 3082: @144126 GIM_Try, /*On fail goto*//*Label 3083*/ 144166, // Rule ID 7982 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_63, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$imm, 63:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/63, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7982, GIR_Done, // Label 3083: @144166 GIM_Try, /*On fail goto*//*Label 3084*/ 144237, // Rule ID 6783 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6783, GIR_Done, // Label 3084: @144237 GIM_Try, /*On fail goto*//*Label 3085*/ 144308, // Rule ID 6784 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6784, GIR_Done, // Label 3085: @144308 GIM_Try, /*On fail goto*//*Label 3086*/ 144325, // Rule ID 121 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ASRVXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 121, GIR_Done, // Label 3086: @144325 GIM_Reject, // Label 3081: @144326 GIM_Reject, // Label 3075: @144327 GIM_Reject, // Label 41: @144328 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 3089*/ 144816, /*GILLT_s32*//*Label 3087*/ 144336, /*GILLT_s64*//*Label 3088*/ 144561, // Label 3087: @144336 GIM_Try, /*On fail goto*//*Label 3090*/ 144560, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3091*/ 144389, // Rule ID 186 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, // (rotr:{ *:[i32] } (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$Rn), 16:{ *:[i64] }) => (REV16Wr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV16Wr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 186, GIR_Done, // Label 3091: @144389 GIM_Try, /*On fail goto*//*Label 3092*/ 144430, // Rule ID 7977 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (EXTRWrri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTRWrri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7977, GIR_Done, // Label 3092: @144430 GIM_Try, /*On fail goto*//*Label 3093*/ 144473, // Rule ID 7909 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (RORVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RORVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7909, GIR_Done, // Label 3093: @144473 GIM_Try, /*On fail goto*//*Label 3094*/ 144516, // Rule ID 7910 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (RORVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RORVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7910, GIR_Done, // Label 3094: @144516 GIM_Try, /*On fail goto*//*Label 3095*/ 144559, // Rule ID 7908 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (RORVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RORVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7908, GIR_Done, // Label 3095: @144559 GIM_Reject, // Label 3090: @144560 GIM_Reject, // Label 3088: @144561 GIM_Try, /*On fail goto*//*Label 3096*/ 144815, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3097*/ 144614, // Rule ID 189 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (rotr:{ *:[i64] } (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$Rn), 32:{ *:[i64] }) => (REV32Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV32Xr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 189, GIR_Done, // Label 3097: @144614 GIM_Try, /*On fail goto*//*Label 3098*/ 144655, // Rule ID 7978 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_63, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (EXTRXrri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTRXrri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7978, GIR_Done, // Label 3098: @144655 GIM_Try, /*On fail goto*//*Label 3099*/ 144726, // Rule ID 7911 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (RORVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RORVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7911, GIR_Done, // Label 3099: @144726 GIM_Try, /*On fail goto*//*Label 3100*/ 144797, // Rule ID 7912 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (RORVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RORVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7912, GIR_Done, // Label 3100: @144797 GIM_Try, /*On fail goto*//*Label 3101*/ 144814, // Rule ID 124 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (RORVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::RORVXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 124, GIR_Done, // Label 3101: @144814 GIM_Reject, // Label 3096: @144815 GIM_Reject, // Label 3089: @144816 GIM_Reject, // Label 42: @144817 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 11, /*)*//*default:*//*Label 3106*/ 145249, /*GILLT_s64*//*Label 3102*/ 144832, 0, 0, 0, 0, /*GILLT_v4s32*//*Label 3103*/ 144862, 0, /*GILLT_v8s16*//*Label 3104*/ 144991, /*GILLT_v16s8*//*Label 3105*/ 145120, // Label 3102: @144832 GIM_Try, /*On fail goto*//*Label 3107*/ 144861, // Rule ID 130 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (mulhu:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UMULHrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMULHrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 130, GIR_Done, // Label 3107: @144861 GIM_Reject, // Label 3103: @144862 GIM_Try, /*On fail goto*//*Label 3108*/ 144990, // Rule ID 9645 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mulhu:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UZP2v4i32:{ *:[v4i32] } (UMULLv2i32_v2i64:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rm, dsub:{ *:[i32] })), (UMULLv4i32_v2i64:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::UMULLv4i32_v2i64, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::UMULLv2i32_v2i64, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9645, GIR_Done, // Label 3108: @144990 GIM_Reject, // Label 3104: @144991 GIM_Try, /*On fail goto*//*Label 3109*/ 145119, // Rule ID 9644 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mulhu:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UZP2v8i16:{ *:[v8i16] } (UMULLv4i16_v4i32:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rm, dsub:{ *:[i32] })), (UMULLv8i16_v4i32:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::UMULLv8i16_v4i32, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::UMULLv4i16_v4i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9644, GIR_Done, // Label 3109: @145119 GIM_Reject, // Label 3105: @145120 GIM_Try, /*On fail goto*//*Label 3110*/ 145248, // Rule ID 9643 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mulhu:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UZP2v16i8:{ *:[v16i8] } (UMULLv8i8_v8i16:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rm, dsub:{ *:[i32] })), (UMULLv16i8_v8i16:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::UMULLv16i8_v8i16, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::UMULLv8i8_v8i16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9643, GIR_Done, // Label 3110: @145248 GIM_Reject, // Label 3106: @145249 GIM_Reject, // Label 43: @145250 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 11, /*)*//*default:*//*Label 3115*/ 145682, /*GILLT_s64*//*Label 3111*/ 145265, 0, 0, 0, 0, /*GILLT_v4s32*//*Label 3112*/ 145295, 0, /*GILLT_v8s16*//*Label 3113*/ 145424, /*GILLT_v16s8*//*Label 3114*/ 145553, // Label 3111: @145265 GIM_Try, /*On fail goto*//*Label 3116*/ 145294, // Rule ID 129 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (mulhs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SMULHrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMULHrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 129, GIR_Done, // Label 3116: @145294 GIM_Reject, // Label 3112: @145295 GIM_Try, /*On fail goto*//*Label 3117*/ 145423, // Rule ID 9642 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mulhs:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UZP2v4i32:{ *:[v4i32] } (SMULLv2i32_v2i64:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rm, dsub:{ *:[i32] })), (SMULLv4i32_v2i64:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SMULLv4i32_v2i64, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SMULLv2i32_v2i64, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9642, GIR_Done, // Label 3117: @145423 GIM_Reject, // Label 3113: @145424 GIM_Try, /*On fail goto*//*Label 3118*/ 145552, // Rule ID 9641 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mulhs:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UZP2v8i16:{ *:[v8i16] } (SMULLv4i16_v4i32:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rm, dsub:{ *:[i32] })), (SMULLv8i16_v4i32:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SMULLv8i16_v4i32, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SMULLv4i16_v4i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9641, GIR_Done, // Label 3118: @145552 GIM_Reject, // Label 3114: @145553 GIM_Try, /*On fail goto*//*Label 3119*/ 145681, // Rule ID 9640 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mulhs:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UZP2v16i8:{ *:[v16i8] } (SMULLv8i8_v8i16:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rm, dsub:{ *:[i32] })), (SMULLv16i8_v8i16:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SMULLv16i8_v8i16, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SMULLv8i8_v8i16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9640, GIR_Done, // Label 3119: @145681 GIM_Reject, // Label 3115: @145682 GIM_Reject, // Label 44: @145683 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 3127*/ 145920, /*GILLT_v2s32*//*Label 3120*/ 145696, /*GILLT_v2s64*//*Label 3121*/ 145728, /*GILLT_v4s16*//*Label 3122*/ 145760, /*GILLT_v4s32*//*Label 3123*/ 145792, /*GILLT_v8s8*//*Label 3124*/ 145824, /*GILLT_v8s16*//*Label 3125*/ 145856, /*GILLT_v16s8*//*Label 3126*/ 145888, // Label 3120: @145696 GIM_Try, /*On fail goto*//*Label 3128*/ 145727, // Rule ID 8622 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (uaddsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (UQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQADDv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8622, GIR_Done, // Label 3128: @145727 GIM_Reject, // Label 3121: @145728 GIM_Try, /*On fail goto*//*Label 3129*/ 145759, // Rule ID 8626 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (uaddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (UQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQADDv2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8626, GIR_Done, // Label 3129: @145759 GIM_Reject, // Label 3122: @145760 GIM_Try, /*On fail goto*//*Label 3130*/ 145791, // Rule ID 8621 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (uaddsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (UQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQADDv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8621, GIR_Done, // Label 3130: @145791 GIM_Reject, // Label 3123: @145792 GIM_Try, /*On fail goto*//*Label 3131*/ 145823, // Rule ID 8625 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (uaddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (UQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQADDv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8625, GIR_Done, // Label 3131: @145823 GIM_Reject, // Label 3124: @145824 GIM_Try, /*On fail goto*//*Label 3132*/ 145855, // Rule ID 8620 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (uaddsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) => (UQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQADDv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8620, GIR_Done, // Label 3132: @145855 GIM_Reject, // Label 3125: @145856 GIM_Try, /*On fail goto*//*Label 3133*/ 145887, // Rule ID 8624 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (uaddsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (UQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQADDv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8624, GIR_Done, // Label 3133: @145887 GIM_Reject, // Label 3126: @145888 GIM_Try, /*On fail goto*//*Label 3134*/ 145919, // Rule ID 8623 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (uaddsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) => (UQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQADDv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8623, GIR_Done, // Label 3134: @145919 GIM_Reject, // Label 3127: @145920 GIM_Reject, // Label 45: @145921 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 3142*/ 146158, /*GILLT_v2s32*//*Label 3135*/ 145934, /*GILLT_v2s64*//*Label 3136*/ 145966, /*GILLT_v4s16*//*Label 3137*/ 145998, /*GILLT_v4s32*//*Label 3138*/ 146030, /*GILLT_v8s8*//*Label 3139*/ 146062, /*GILLT_v8s16*//*Label 3140*/ 146094, /*GILLT_v16s8*//*Label 3141*/ 146126, // Label 3135: @145934 GIM_Try, /*On fail goto*//*Label 3143*/ 145965, // Rule ID 6795 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (saddsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (SQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQADDv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6795, GIR_Done, // Label 3143: @145965 GIM_Reject, // Label 3136: @145966 GIM_Try, /*On fail goto*//*Label 3144*/ 145997, // Rule ID 6799 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (saddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (SQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQADDv2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6799, GIR_Done, // Label 3144: @145997 GIM_Reject, // Label 3137: @145998 GIM_Try, /*On fail goto*//*Label 3145*/ 146029, // Rule ID 6794 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (saddsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (SQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQADDv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6794, GIR_Done, // Label 3145: @146029 GIM_Reject, // Label 3138: @146030 GIM_Try, /*On fail goto*//*Label 3146*/ 146061, // Rule ID 6798 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (saddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (SQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQADDv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6798, GIR_Done, // Label 3146: @146061 GIM_Reject, // Label 3139: @146062 GIM_Try, /*On fail goto*//*Label 3147*/ 146093, // Rule ID 6793 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (saddsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) => (SQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQADDv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6793, GIR_Done, // Label 3147: @146093 GIM_Reject, // Label 3140: @146094 GIM_Try, /*On fail goto*//*Label 3148*/ 146125, // Rule ID 6797 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (saddsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (SQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQADDv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6797, GIR_Done, // Label 3148: @146125 GIM_Reject, // Label 3141: @146126 GIM_Try, /*On fail goto*//*Label 3149*/ 146157, // Rule ID 6796 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (saddsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) => (SQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQADDv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6796, GIR_Done, // Label 3149: @146157 GIM_Reject, // Label 3142: @146158 GIM_Reject, // Label 46: @146159 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 3157*/ 146396, /*GILLT_v2s32*//*Label 3150*/ 146172, /*GILLT_v2s64*//*Label 3151*/ 146204, /*GILLT_v4s16*//*Label 3152*/ 146236, /*GILLT_v4s32*//*Label 3153*/ 146268, /*GILLT_v8s8*//*Label 3154*/ 146300, /*GILLT_v8s16*//*Label 3155*/ 146332, /*GILLT_v16s8*//*Label 3156*/ 146364, // Label 3150: @146172 GIM_Try, /*On fail goto*//*Label 3158*/ 146203, // Rule ID 8636 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (usubsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (UQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQSUBv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8636, GIR_Done, // Label 3158: @146203 GIM_Reject, // Label 3151: @146204 GIM_Try, /*On fail goto*//*Label 3159*/ 146235, // Rule ID 8640 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (usubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (UQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQSUBv2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8640, GIR_Done, // Label 3159: @146235 GIM_Reject, // Label 3152: @146236 GIM_Try, /*On fail goto*//*Label 3160*/ 146267, // Rule ID 8635 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (usubsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (UQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQSUBv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8635, GIR_Done, // Label 3160: @146267 GIM_Reject, // Label 3153: @146268 GIM_Try, /*On fail goto*//*Label 3161*/ 146299, // Rule ID 8639 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (usubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (UQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQSUBv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8639, GIR_Done, // Label 3161: @146299 GIM_Reject, // Label 3154: @146300 GIM_Try, /*On fail goto*//*Label 3162*/ 146331, // Rule ID 8634 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (usubsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) => (UQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQSUBv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8634, GIR_Done, // Label 3162: @146331 GIM_Reject, // Label 3155: @146332 GIM_Try, /*On fail goto*//*Label 3163*/ 146363, // Rule ID 8638 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (usubsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (UQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQSUBv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8638, GIR_Done, // Label 3163: @146363 GIM_Reject, // Label 3156: @146364 GIM_Try, /*On fail goto*//*Label 3164*/ 146395, // Rule ID 8637 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (usubsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) => (UQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQSUBv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8637, GIR_Done, // Label 3164: @146395 GIM_Reject, // Label 3157: @146396 GIM_Reject, // Label 47: @146397 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 3172*/ 146634, /*GILLT_v2s32*//*Label 3165*/ 146410, /*GILLT_v2s64*//*Label 3166*/ 146442, /*GILLT_v4s16*//*Label 3167*/ 146474, /*GILLT_v4s32*//*Label 3168*/ 146506, /*GILLT_v8s8*//*Label 3169*/ 146538, /*GILLT_v8s16*//*Label 3170*/ 146570, /*GILLT_v16s8*//*Label 3171*/ 146602, // Label 3165: @146410 GIM_Try, /*On fail goto*//*Label 3173*/ 146441, // Rule ID 8629 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (ssubsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (SQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQSUBv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8629, GIR_Done, // Label 3173: @146441 GIM_Reject, // Label 3166: @146442 GIM_Try, /*On fail goto*//*Label 3174*/ 146473, // Rule ID 8633 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (ssubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (SQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQSUBv2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8633, GIR_Done, // Label 3174: @146473 GIM_Reject, // Label 3167: @146474 GIM_Try, /*On fail goto*//*Label 3175*/ 146505, // Rule ID 8628 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (ssubsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (SQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQSUBv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8628, GIR_Done, // Label 3175: @146505 GIM_Reject, // Label 3168: @146506 GIM_Try, /*On fail goto*//*Label 3176*/ 146537, // Rule ID 8632 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (ssubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (SQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQSUBv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8632, GIR_Done, // Label 3176: @146537 GIM_Reject, // Label 3169: @146538 GIM_Try, /*On fail goto*//*Label 3177*/ 146569, // Rule ID 8627 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (ssubsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) => (SQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQSUBv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8627, GIR_Done, // Label 3177: @146569 GIM_Reject, // Label 3170: @146570 GIM_Try, /*On fail goto*//*Label 3178*/ 146601, // Rule ID 8631 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (ssubsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (SQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQSUBv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8631, GIR_Done, // Label 3178: @146601 GIM_Reject, // Label 3171: @146602 GIM_Try, /*On fail goto*//*Label 3179*/ 146633, // Rule ID 8630 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (ssubsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) => (SQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQSUBv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8630, GIR_Done, // Label 3179: @146633 GIM_Reject, // Label 3172: @146634 GIM_Reject, // Label 48: @146635 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3188*/ 147552, /*GILLT_s16*//*Label 3180*/ 146651, /*GILLT_s32*//*Label 3181*/ 146865, /*GILLT_s64*//*Label 3182*/ 147209, 0, /*GILLT_v2s32*//*Label 3183*/ 147377, /*GILLT_v2s64*//*Label 3184*/ 147412, /*GILLT_v4s16*//*Label 3185*/ 147447, /*GILLT_v4s32*//*Label 3186*/ 147482, 0, /*GILLT_v8s16*//*Label 3187*/ 147517, // Label 3180: @146651 GIM_Try, /*On fail goto*//*Label 3189*/ 146864, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_Try, /*On fail goto*//*Label 3190*/ 146753, // Rule ID 10123 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i16p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10123, GIR_Done, // Label 3190: @146753 GIM_Try, /*On fail goto*//*Label 3191*/ 146841, // Rule ID 11799 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i16p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11799, GIR_Done, // Label 3191: @146841 GIM_Try, /*On fail goto*//*Label 3192*/ 146863, // Rule ID 565 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (fadd:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FADDHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDHrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 565, GIR_Done, // Label 3192: @146863 GIM_Reject, // Label 3189: @146864 GIM_Reject, // Label 3181: @146865 GIM_Try, /*On fail goto*//*Label 3193*/ 147208, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3194*/ 146944, // Rule ID 6763 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6763, GIR_Done, // Label 3194: @146944 GIM_Try, /*On fail goto*//*Label 3195*/ 147032, // Rule ID 10121 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10121, GIR_Done, // Label 3195: @147032 GIM_Try, /*On fail goto*//*Label 3196*/ 147097, // Rule ID 11486 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11486, GIR_Done, // Label 3196: @147097 GIM_Try, /*On fail goto*//*Label 3197*/ 147185, // Rule ID 11797 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11797, GIR_Done, // Label 3197: @147185 GIM_Try, /*On fail goto*//*Label 3198*/ 147207, // Rule ID 567 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (fadd:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FADDSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDSrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 567, GIR_Done, // Label 3198: @147207 GIM_Reject, // Label 3193: @147208 GIM_Reject, // Label 3182: @147209 GIM_Try, /*On fail goto*//*Label 3199*/ 147376, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3200*/ 147288, // Rule ID 10119 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10119, GIR_Done, // Label 3200: @147288 GIM_Try, /*On fail goto*//*Label 3201*/ 147353, // Rule ID 11795 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11795, GIR_Done, // Label 3201: @147353 GIM_Try, /*On fail goto*//*Label 3202*/ 147375, // Rule ID 569 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fadd:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FADDDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 569, GIR_Done, // Label 3202: @147375 GIM_Reject, // Label 3199: @147376 GIM_Reject, // Label 3183: @147377 GIM_Try, /*On fail goto*//*Label 3203*/ 147411, // Rule ID 1166 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fadd:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1166, GIR_Done, // Label 3203: @147411 GIM_Reject, // Label 3184: @147412 GIM_Try, /*On fail goto*//*Label 3204*/ 147446, // Rule ID 1170 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fadd:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1170, GIR_Done, // Label 3204: @147446 GIM_Reject, // Label 3185: @147447 GIM_Try, /*On fail goto*//*Label 3205*/ 147481, // Rule ID 1162 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fadd:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1162, GIR_Done, // Label 3205: @147481 GIM_Reject, // Label 3186: @147482 GIM_Try, /*On fail goto*//*Label 3206*/ 147516, // Rule ID 1168 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fadd:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1168, GIR_Done, // Label 3206: @147516 GIM_Reject, // Label 3187: @147517 GIM_Try, /*On fail goto*//*Label 3207*/ 147551, // Rule ID 1164 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1164, GIR_Done, // Label 3207: @147551 GIM_Reject, // Label 3188: @147552 GIM_Reject, // Label 49: @147553 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3216*/ 147849, /*GILLT_s16*//*Label 3208*/ 147569, /*GILLT_s32*//*Label 3209*/ 147604, /*GILLT_s64*//*Label 3210*/ 147639, 0, /*GILLT_v2s32*//*Label 3211*/ 147674, /*GILLT_v2s64*//*Label 3212*/ 147709, /*GILLT_v4s16*//*Label 3213*/ 147744, /*GILLT_v4s32*//*Label 3214*/ 147779, 0, /*GILLT_v8s16*//*Label 3215*/ 147814, // Label 3208: @147569 GIM_Try, /*On fail goto*//*Label 3217*/ 147603, // Rule ID 613 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (fsub:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FSUBHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBHrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 613, GIR_Done, // Label 3217: @147603 GIM_Reject, // Label 3209: @147604 GIM_Try, /*On fail goto*//*Label 3218*/ 147638, // Rule ID 615 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (fsub:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FSUBSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBSrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 615, GIR_Done, // Label 3218: @147638 GIM_Reject, // Label 3210: @147639 GIM_Try, /*On fail goto*//*Label 3219*/ 147673, // Rule ID 617 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fsub:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FSUBDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 617, GIR_Done, // Label 3219: @147673 GIM_Reject, // Label 3211: @147674 GIM_Try, /*On fail goto*//*Label 3220*/ 147708, // Rule ID 1306 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fsub:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FSUBv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1306, GIR_Done, // Label 3220: @147708 GIM_Reject, // Label 3212: @147709 GIM_Try, /*On fail goto*//*Label 3221*/ 147743, // Rule ID 1310 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fsub:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FSUBv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1310, GIR_Done, // Label 3221: @147743 GIM_Reject, // Label 3213: @147744 GIM_Try, /*On fail goto*//*Label 3222*/ 147778, // Rule ID 1302 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fsub:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FSUBv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1302, GIR_Done, // Label 3222: @147778 GIM_Reject, // Label 3214: @147779 GIM_Try, /*On fail goto*//*Label 3223*/ 147813, // Rule ID 1308 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fsub:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FSUBv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1308, GIR_Done, // Label 3223: @147813 GIM_Reject, // Label 3215: @147814 GIM_Try, /*On fail goto*//*Label 3224*/ 147848, // Rule ID 1304 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FSUBv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1304, GIR_Done, // Label 3224: @147848 GIM_Reject, // Label 3216: @147849 GIM_Reject, // Label 50: @147850 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3233*/ 150002, /*GILLT_s16*//*Label 3225*/ 147866, /*GILLT_s32*//*Label 3226*/ 148122, /*GILLT_s64*//*Label 3227*/ 148374, 0, /*GILLT_v2s32*//*Label 3228*/ 148626, /*GILLT_v2s64*//*Label 3229*/ 148974, /*GILLT_v4s16*//*Label 3230*/ 149322, /*GILLT_v4s32*//*Label 3231*/ 149488, 0, /*GILLT_v8s16*//*Label 3232*/ 149836, // Label 3225: @147866 GIM_Try, /*On fail goto*//*Label 3234*/ 148121, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_Try, /*On fail goto*//*Label 3235*/ 147944, // Rule ID 10847 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR16Op:{ *:[f16] }:$Rn) => (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10847, GIR_Done, // Label 3235: @147944 GIM_Try, /*On fail goto*//*Label 3236*/ 148008, // Rule ID 1958 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1958, GIR_Done, // Label 3236: @148008 GIM_Try, /*On fail goto*//*Label 3237*/ 148053, // Rule ID 8492 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$a), FPR16:{ *:[f16] }:$b) => (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULHrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8492, GIR_Done, // Label 3237: @148053 GIM_Try, /*On fail goto*//*Label 3238*/ 148098, // Rule ID 11716 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$b, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$a)) => (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULHrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11716, GIR_Done, // Label 3238: @148098 GIM_Try, /*On fail goto*//*Label 3239*/ 148120, // Rule ID 601 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULHrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 601, GIR_Done, // Label 3239: @148120 GIM_Reject, // Label 3234: @148121 GIM_Reject, // Label 3226: @148122 GIM_Try, /*On fail goto*//*Label 3240*/ 148373, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3241*/ 148200, // Rule ID 10849 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32Op:{ *:[f32] }:$Rn) => (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10849, GIR_Done, // Label 3241: @148200 GIM_Try, /*On fail goto*//*Label 3242*/ 148264, // Rule ID 1960 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1960, GIR_Done, // Label 3242: @148264 GIM_Try, /*On fail goto*//*Label 3243*/ 148307, // Rule ID 8493 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$a), FPR32:{ *:[f32] }:$b) => (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULSrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8493, GIR_Done, // Label 3243: @148307 GIM_Try, /*On fail goto*//*Label 3244*/ 148350, // Rule ID 11717 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$b, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$a)) => (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULSrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11717, GIR_Done, // Label 3244: @148350 GIM_Try, /*On fail goto*//*Label 3245*/ 148372, // Rule ID 603 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULSrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 603, GIR_Done, // Label 3245: @148372 GIM_Reject, // Label 3240: @148373 GIM_Reject, // Label 3227: @148374 GIM_Try, /*On fail goto*//*Label 3246*/ 148625, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3247*/ 148452, // Rule ID 10851 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR64Op:{ *:[f64] }:$Rn) => (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10851, GIR_Done, // Label 3247: @148452 GIM_Try, /*On fail goto*//*Label 3248*/ 148516, // Rule ID 1962 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1962, GIR_Done, // Label 3248: @148516 GIM_Try, /*On fail goto*//*Label 3249*/ 148559, // Rule ID 8494 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$a), FPR64:{ *:[f64] }:$b) => (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULDrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8494, GIR_Done, // Label 3249: @148559 GIM_Try, /*On fail goto*//*Label 3250*/ 148602, // Rule ID 11718 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$b, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$a)) => (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULDrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11718, GIR_Done, // Label 3250: @148602 GIM_Try, /*On fail goto*//*Label 3251*/ 148624, // Rule ID 605 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 605, GIR_Done, // Label 3251: @148624 GIM_Reject, // Label 3246: @148625 GIM_Reject, // Label 3228: @148626 GIM_Try, /*On fail goto*//*Label 3252*/ 148973, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3253*/ 148704, // Rule ID 10841 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v2f32] }:$Rn) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10841, GIR_Done, // Label 3253: @148704 GIM_Try, /*On fail goto*//*Label 3254*/ 148768, // Rule ID 1952 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1952, GIR_Done, // Label 3254: @148768 GIM_Try, /*On fail goto*//*Label 3255*/ 148859, // Rule ID 11776 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11776, GIR_Done, // Label 3255: @148859 GIM_Try, /*On fail goto*//*Label 3256*/ 148950, // Rule ID 9395 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm)) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9395, GIR_Done, // Label 3256: @148950 GIM_Try, /*On fail goto*//*Label 3257*/ 148972, // Rule ID 1286 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMULv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1286, GIR_Done, // Label 3257: @148972 GIM_Reject, // Label 3252: @148973 GIM_Reject, // Label 3229: @148974 GIM_Try, /*On fail goto*//*Label 3258*/ 149321, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 3259*/ 149052, // Rule ID 10845 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v2f64] }:$Rn) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10845, GIR_Done, // Label 3259: @149052 GIM_Try, /*On fail goto*//*Label 3260*/ 149116, // Rule ID 1956 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1956, GIR_Done, // Label 3260: @149116 GIM_Try, /*On fail goto*//*Label 3261*/ 149207, // Rule ID 11780 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11780, GIR_Done, // Label 3261: @149207 GIM_Try, /*On fail goto*//*Label 3262*/ 149298, // Rule ID 9399 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm)) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9399, GIR_Done, // Label 3262: @149298 GIM_Try, /*On fail goto*//*Label 3263*/ 149320, // Rule ID 1290 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMULv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1290, GIR_Done, // Label 3263: @149320 GIM_Reject, // Label 3258: @149321 GIM_Reject, // Label 3230: @149322 GIM_Try, /*On fail goto*//*Label 3264*/ 149487, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3265*/ 149400, // Rule ID 10837 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v4f16] }:$Rn) => (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10837, GIR_Done, // Label 3265: @149400 GIM_Try, /*On fail goto*//*Label 3266*/ 149464, // Rule ID 1948 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1948, GIR_Done, // Label 3266: @149464 GIM_Try, /*On fail goto*//*Label 3267*/ 149486, // Rule ID 1282 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMULv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1282, GIR_Done, // Label 3267: @149486 GIM_Reject, // Label 3264: @149487 GIM_Reject, // Label 3231: @149488 GIM_Try, /*On fail goto*//*Label 3268*/ 149835, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 3269*/ 149566, // Rule ID 10843 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v4f32] }:$Rn) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10843, GIR_Done, // Label 3269: @149566 GIM_Try, /*On fail goto*//*Label 3270*/ 149630, // Rule ID 1954 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1954, GIR_Done, // Label 3270: @149630 GIM_Try, /*On fail goto*//*Label 3271*/ 149721, // Rule ID 11778 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11778, GIR_Done, // Label 3271: @149721 GIM_Try, /*On fail goto*//*Label 3272*/ 149812, // Rule ID 9397 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm)) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9397, GIR_Done, // Label 3272: @149812 GIM_Try, /*On fail goto*//*Label 3273*/ 149834, // Rule ID 1288 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMULv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1288, GIR_Done, // Label 3273: @149834 GIM_Reject, // Label 3268: @149835 GIM_Reject, // Label 3232: @149836 GIM_Try, /*On fail goto*//*Label 3274*/ 150001, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 3275*/ 149914, // Rule ID 10839 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v8f16] }:$Rn) => (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10839, GIR_Done, // Label 3275: @149914 GIM_Try, /*On fail goto*//*Label 3276*/ 149978, // Rule ID 1950 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1950, GIR_Done, // Label 3276: @149978 GIM_Try, /*On fail goto*//*Label 3277*/ 150000, // Rule ID 1284 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMULv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1284, GIR_Done, // Label 3277: @150000 GIM_Reject, // Label 3274: @150001 GIM_Reject, // Label 3233: @150002 GIM_Reject, // Label 51: @150003 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3286*/ 160214, /*GILLT_s16*//*Label 3278*/ 150019, /*GILLT_s32*//*Label 3279*/ 150946, /*GILLT_s64*//*Label 3280*/ 152031, 0, /*GILLT_v2s32*//*Label 3281*/ 153116, /*GILLT_v2s64*//*Label 3282*/ 154678, /*GILLT_v4s16*//*Label 3283*/ 156240, /*GILLT_v4s32*//*Label 3284*/ 157446, 0, /*GILLT_v8s16*//*Label 3285*/ 159008, // Label 3278: @150019 GIM_Try, /*On fail goto*//*Label 3287*/ 150945, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_Try, /*On fail goto*//*Label 3288*/ 150122, // Rule ID 9281 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9281, GIR_Done, // Label 3288: @150122 GIM_Try, /*On fail goto*//*Label 3289*/ 150207, // Rule ID 9307 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9307, GIR_Done, // Label 3289: @150207 GIM_Try, /*On fail goto*//*Label 3290*/ 150292, // Rule ID 9333 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9333, GIR_Done, // Label 3290: @150292 GIM_Try, /*On fail goto*//*Label 3291*/ 150377, // Rule ID 9255 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9255, GIR_Done, // Label 3291: @150377 GIM_Try, /*On fail goto*//*Label 3292*/ 150449, // Rule ID 6840 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd) => (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6840, GIR_Done, // Label 3292: @150449 GIM_Try, /*On fail goto*//*Label 3293*/ 150521, // Rule ID 9229 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR16:{ *:[f16] }:$Rd) => (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9229, GIR_Done, // Label 3293: @150521 GIM_Try, /*On fail goto*//*Label 3294*/ 150587, // Rule ID 8502 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8502, GIR_Done, // Label 3294: @150587 GIM_Try, /*On fail goto*//*Label 3295*/ 150653, // Rule ID 11722 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11722, GIR_Done, // Label 3295: @150653 GIM_Try, /*On fail goto*//*Label 3296*/ 150706, // Rule ID 8499 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8499, GIR_Done, // Label 3296: @150706 GIM_Try, /*On fail goto*//*Label 3297*/ 150759, // Rule ID 10693 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10693, GIR_Done, // Label 3297: @150759 GIM_Try, /*On fail goto*//*Label 3298*/ 150812, // Rule ID 625 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 625, GIR_Done, // Label 3298: @150812 GIM_Try, /*On fail goto*//*Label 3299*/ 150865, // Rule ID 11719 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11719, GIR_Done, // Label 3299: @150865 GIM_Try, /*On fail goto*//*Label 3300*/ 150918, // Rule ID 637 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 637, GIR_Done, // Label 3300: @150918 GIM_Try, /*On fail goto*//*Label 3301*/ 150944, // Rule ID 619 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) => (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMADDHrrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 619, GIR_Done, // Label 3301: @150944 GIM_Reject, // Label 3287: @150945 GIM_Reject, // Label 3279: @150946 GIM_Try, /*On fail goto*//*Label 3302*/ 152030, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3303*/ 151047, // Rule ID 9367 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9367, GIR_Done, // Label 3303: @151047 GIM_Try, /*On fail goto*//*Label 3304*/ 151132, // Rule ID 9295 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9295, GIR_Done, // Label 3304: @151132 GIM_Try, /*On fail goto*//*Label 3305*/ 151217, // Rule ID 9321 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9321, GIR_Done, // Label 3305: @151217 GIM_Try, /*On fail goto*//*Label 3306*/ 151302, // Rule ID 9347 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9347, GIR_Done, // Label 3306: @151302 GIM_Try, /*On fail goto*//*Label 3307*/ 151385, // Rule ID 9389 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9389, GIR_Done, // Label 3307: @151385 GIM_Try, /*On fail goto*//*Label 3308*/ 151470, // Rule ID 9269 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9269, GIR_Done, // Label 3308: @151470 GIM_Try, /*On fail goto*//*Label 3309*/ 151542, // Rule ID 6854 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6854, GIR_Done, // Label 3309: @151542 GIM_Try, /*On fail goto*//*Label 3310*/ 151614, // Rule ID 9243 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9243, GIR_Done, // Label 3310: @151614 GIM_Try, /*On fail goto*//*Label 3311*/ 151678, // Rule ID 8503 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8503, GIR_Done, // Label 3311: @151678 GIM_Try, /*On fail goto*//*Label 3312*/ 151742, // Rule ID 11723 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11723, GIR_Done, // Label 3312: @151742 GIM_Try, /*On fail goto*//*Label 3313*/ 151793, // Rule ID 8500 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8500, GIR_Done, // Label 3313: @151793 GIM_Try, /*On fail goto*//*Label 3314*/ 151846, // Rule ID 10695 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10695, GIR_Done, // Label 3314: @151846 GIM_Try, /*On fail goto*//*Label 3315*/ 151899, // Rule ID 627 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 627, GIR_Done, // Label 3315: @151899 GIM_Try, /*On fail goto*//*Label 3316*/ 151950, // Rule ID 11720 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11720, GIR_Done, // Label 3316: @151950 GIM_Try, /*On fail goto*//*Label 3317*/ 152003, // Rule ID 639 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 639, GIR_Done, // Label 3317: @152003 GIM_Try, /*On fail goto*//*Label 3318*/ 152029, // Rule ID 621 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) => (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMADDSrrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 621, GIR_Done, // Label 3318: @152029 GIM_Reject, // Label 3302: @152030 GIM_Reject, // Label 3280: @152031 GIM_Try, /*On fail goto*//*Label 3319*/ 153115, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3320*/ 152132, // Rule ID 9371 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9371, GIR_Done, // Label 3320: @152132 GIM_Try, /*On fail goto*//*Label 3321*/ 152217, // Rule ID 9297 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9297, GIR_Done, // Label 3321: @152217 GIM_Try, /*On fail goto*//*Label 3322*/ 152302, // Rule ID 9323 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9323, GIR_Done, // Label 3322: @152302 GIM_Try, /*On fail goto*//*Label 3323*/ 152387, // Rule ID 9349 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9349, GIR_Done, // Label 3323: @152387 GIM_Try, /*On fail goto*//*Label 3324*/ 152470, // Rule ID 9393 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9393, GIR_Done, // Label 3324: @152470 GIM_Try, /*On fail goto*//*Label 3325*/ 152555, // Rule ID 9271 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9271, GIR_Done, // Label 3325: @152555 GIM_Try, /*On fail goto*//*Label 3326*/ 152627, // Rule ID 6856 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6856, GIR_Done, // Label 3326: @152627 GIM_Try, /*On fail goto*//*Label 3327*/ 152699, // Rule ID 9245 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9245, GIR_Done, // Label 3327: @152699 GIM_Try, /*On fail goto*//*Label 3328*/ 152763, // Rule ID 8504 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8504, GIR_Done, // Label 3328: @152763 GIM_Try, /*On fail goto*//*Label 3329*/ 152827, // Rule ID 11724 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11724, GIR_Done, // Label 3329: @152827 GIM_Try, /*On fail goto*//*Label 3330*/ 152878, // Rule ID 8501 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8501, GIR_Done, // Label 3330: @152878 GIM_Try, /*On fail goto*//*Label 3331*/ 152931, // Rule ID 10697 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10697, GIR_Done, // Label 3331: @152931 GIM_Try, /*On fail goto*//*Label 3332*/ 152984, // Rule ID 629 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 629, GIR_Done, // Label 3332: @152984 GIM_Try, /*On fail goto*//*Label 3333*/ 153035, // Rule ID 11721 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11721, GIR_Done, // Label 3333: @153035 GIM_Try, /*On fail goto*//*Label 3334*/ 153088, // Rule ID 641 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 641, GIR_Done, // Label 3334: @153088 GIM_Try, /*On fail goto*//*Label 3335*/ 153114, // Rule ID 623 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) => (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMADDDrrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 623, GIR_Done, // Label 3335: @153114 GIM_Reject, // Label 3319: @153115 GIM_Reject, // Label 3281: @153116 GIM_Try, /*On fail goto*//*Label 3336*/ 154677, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3337*/ 153217, // Rule ID 9351 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9351, GIR_Done, // Label 3337: @153217 GIM_Try, /*On fail goto*//*Label 3338*/ 153302, // Rule ID 9283 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9283, GIR_Done, // Label 3338: @153302 GIM_Try, /*On fail goto*//*Label 3339*/ 153387, // Rule ID 9309 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9309, GIR_Done, // Label 3339: @153387 GIM_Try, /*On fail goto*//*Label 3340*/ 153472, // Rule ID 9335 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9335, GIR_Done, // Label 3340: @153472 GIM_Try, /*On fail goto*//*Label 3341*/ 153555, // Rule ID 9373 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<>:$idx), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9373, GIR_Done, // Label 3341: @153555 GIM_Try, /*On fail goto*//*Label 3342*/ 153640, // Rule ID 9257 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9257, GIR_Done, // Label 3342: @153640 GIM_Try, /*On fail goto*//*Label 3343*/ 153712, // Rule ID 6842 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6842, GIR_Done, // Label 3343: @153712 GIM_Try, /*On fail goto*//*Label 3344*/ 153784, // Rule ID 9231 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9231, GIR_Done, // Label 3344: @153784 GIM_Try, /*On fail goto*//*Label 3345*/ 153879, // Rule ID 9355 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9355, GIR_Done, // Label 3345: @153879 GIM_Try, /*On fail goto*//*Label 3346*/ 153976, // Rule ID 9285 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9285, GIR_Done, // Label 3346: @153976 GIM_Try, /*On fail goto*//*Label 3347*/ 154073, // Rule ID 9311 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9311, GIR_Done, // Label 3347: @154073 GIM_Try, /*On fail goto*//*Label 3348*/ 154170, // Rule ID 9337 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9337, GIR_Done, // Label 3348: @154170 GIM_Try, /*On fail goto*//*Label 3349*/ 154265, // Rule ID 9377 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9377, GIR_Done, // Label 3349: @154265 GIM_Try, /*On fail goto*//*Label 3350*/ 154362, // Rule ID 9259 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9259, GIR_Done, // Label 3350: @154362 GIM_Try, /*On fail goto*//*Label 3351*/ 154446, // Rule ID 6844 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6844, GIR_Done, // Label 3351: @154446 GIM_Try, /*On fail goto*//*Label 3352*/ 154499, // Rule ID 10727 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10727, GIR_Done, // Label 3352: @154499 GIM_Try, /*On fail goto*//*Label 3353*/ 154583, // Rule ID 9233 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9233, GIR_Done, // Label 3353: @154583 GIM_Try, /*On fail goto*//*Label 3354*/ 154636, // Rule ID 1271 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1271, GIR_Done, // Label 3354: @154636 GIM_Try, /*On fail goto*//*Label 3355*/ 154676, // Rule ID 1261 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1261, GIR_Done, // Label 3355: @154676 GIM_Reject, // Label 3336: @154677 GIM_Reject, // Label 3282: @154678 GIM_Try, /*On fail goto*//*Label 3356*/ 156239, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 3357*/ 154779, // Rule ID 9363 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9363, GIR_Done, // Label 3357: @154779 GIM_Try, /*On fail goto*//*Label 3358*/ 154864, // Rule ID 9291 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9291, GIR_Done, // Label 3358: @154864 GIM_Try, /*On fail goto*//*Label 3359*/ 154949, // Rule ID 9317 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9317, GIR_Done, // Label 3359: @154949 GIM_Try, /*On fail goto*//*Label 3360*/ 155034, // Rule ID 9343 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9343, GIR_Done, // Label 3360: @155034 GIM_Try, /*On fail goto*//*Label 3361*/ 155117, // Rule ID 9385 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<>:$idx), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9385, GIR_Done, // Label 3361: @155117 GIM_Try, /*On fail goto*//*Label 3362*/ 155202, // Rule ID 9265 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9265, GIR_Done, // Label 3362: @155202 GIM_Try, /*On fail goto*//*Label 3363*/ 155274, // Rule ID 6850 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6850, GIR_Done, // Label 3363: @155274 GIM_Try, /*On fail goto*//*Label 3364*/ 155346, // Rule ID 9239 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9239, GIR_Done, // Label 3364: @155346 GIM_Try, /*On fail goto*//*Label 3365*/ 155441, // Rule ID 9365 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9365, GIR_Done, // Label 3365: @155441 GIM_Try, /*On fail goto*//*Label 3366*/ 155538, // Rule ID 9293 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9293, GIR_Done, // Label 3366: @155538 GIM_Try, /*On fail goto*//*Label 3367*/ 155635, // Rule ID 9319 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9319, GIR_Done, // Label 3367: @155635 GIM_Try, /*On fail goto*//*Label 3368*/ 155732, // Rule ID 9345 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9345, GIR_Done, // Label 3368: @155732 GIM_Try, /*On fail goto*//*Label 3369*/ 155827, // Rule ID 9387 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9387, GIR_Done, // Label 3369: @155827 GIM_Try, /*On fail goto*//*Label 3370*/ 155924, // Rule ID 9267 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9267, GIR_Done, // Label 3370: @155924 GIM_Try, /*On fail goto*//*Label 3371*/ 156008, // Rule ID 6852 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6852, GIR_Done, // Label 3371: @156008 GIM_Try, /*On fail goto*//*Label 3372*/ 156061, // Rule ID 10731 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10731, GIR_Done, // Label 3372: @156061 GIM_Try, /*On fail goto*//*Label 3373*/ 156145, // Rule ID 9241 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9241, GIR_Done, // Label 3373: @156145 GIM_Try, /*On fail goto*//*Label 3374*/ 156198, // Rule ID 1275 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1275, GIR_Done, // Label 3374: @156198 GIM_Try, /*On fail goto*//*Label 3375*/ 156238, // Rule ID 1265 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1265, GIR_Done, // Label 3375: @156238 GIM_Reject, // Label 3356: @156239 GIM_Reject, // Label 3283: @156240 GIM_Try, /*On fail goto*//*Label 3376*/ 157445, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3377*/ 156343, // Rule ID 9277 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9277, GIR_Done, // Label 3377: @156343 GIM_Try, /*On fail goto*//*Label 3378*/ 156428, // Rule ID 9303 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9303, GIR_Done, // Label 3378: @156428 GIM_Try, /*On fail goto*//*Label 3379*/ 156513, // Rule ID 9329 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9329, GIR_Done, // Label 3379: @156513 GIM_Try, /*On fail goto*//*Label 3380*/ 156598, // Rule ID 9251 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9251, GIR_Done, // Label 3380: @156598 GIM_Try, /*On fail goto*//*Label 3381*/ 156670, // Rule ID 6836 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6836, GIR_Done, // Label 3381: @156670 GIM_Try, /*On fail goto*//*Label 3382*/ 156742, // Rule ID 9225 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9225, GIR_Done, // Label 3382: @156742 GIM_Try, /*On fail goto*//*Label 3383*/ 156839, // Rule ID 9279 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9279, GIR_Done, // Label 3383: @156839 GIM_Try, /*On fail goto*//*Label 3384*/ 156936, // Rule ID 9305 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9305, GIR_Done, // Label 3384: @156936 GIM_Try, /*On fail goto*//*Label 3385*/ 157033, // Rule ID 9331 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9331, GIR_Done, // Label 3385: @157033 GIM_Try, /*On fail goto*//*Label 3386*/ 157130, // Rule ID 9253 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9253, GIR_Done, // Label 3386: @157130 GIM_Try, /*On fail goto*//*Label 3387*/ 157214, // Rule ID 6838 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6838, GIR_Done, // Label 3387: @157214 GIM_Try, /*On fail goto*//*Label 3388*/ 157267, // Rule ID 10723 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10723, GIR_Done, // Label 3388: @157267 GIM_Try, /*On fail goto*//*Label 3389*/ 157351, // Rule ID 9227 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9227, GIR_Done, // Label 3389: @157351 GIM_Try, /*On fail goto*//*Label 3390*/ 157404, // Rule ID 1267 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1267, GIR_Done, // Label 3390: @157404 GIM_Try, /*On fail goto*//*Label 3391*/ 157444, // Rule ID 1257 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1257, GIR_Done, // Label 3391: @157444 GIM_Reject, // Label 3376: @157445 GIM_Reject, // Label 3284: @157446 GIM_Try, /*On fail goto*//*Label 3392*/ 159007, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 3393*/ 157547, // Rule ID 9357 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9357, GIR_Done, // Label 3393: @157547 GIM_Try, /*On fail goto*//*Label 3394*/ 157632, // Rule ID 9287 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9287, GIR_Done, // Label 3394: @157632 GIM_Try, /*On fail goto*//*Label 3395*/ 157717, // Rule ID 9313 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9313, GIR_Done, // Label 3395: @157717 GIM_Try, /*On fail goto*//*Label 3396*/ 157802, // Rule ID 9339 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9339, GIR_Done, // Label 3396: @157802 GIM_Try, /*On fail goto*//*Label 3397*/ 157885, // Rule ID 9379 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<>:$idx), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9379, GIR_Done, // Label 3397: @157885 GIM_Try, /*On fail goto*//*Label 3398*/ 157970, // Rule ID 9261 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9261, GIR_Done, // Label 3398: @157970 GIM_Try, /*On fail goto*//*Label 3399*/ 158042, // Rule ID 6846 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6846, GIR_Done, // Label 3399: @158042 GIM_Try, /*On fail goto*//*Label 3400*/ 158114, // Rule ID 9235 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9235, GIR_Done, // Label 3400: @158114 GIM_Try, /*On fail goto*//*Label 3401*/ 158209, // Rule ID 9361 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9361, GIR_Done, // Label 3401: @158209 GIM_Try, /*On fail goto*//*Label 3402*/ 158306, // Rule ID 9289 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9289, GIR_Done, // Label 3402: @158306 GIM_Try, /*On fail goto*//*Label 3403*/ 158403, // Rule ID 9315 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9315, GIR_Done, // Label 3403: @158403 GIM_Try, /*On fail goto*//*Label 3404*/ 158500, // Rule ID 9341 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9341, GIR_Done, // Label 3404: @158500 GIM_Try, /*On fail goto*//*Label 3405*/ 158595, // Rule ID 9383 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9383, GIR_Done, // Label 3405: @158595 GIM_Try, /*On fail goto*//*Label 3406*/ 158692, // Rule ID 9263 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9263, GIR_Done, // Label 3406: @158692 GIM_Try, /*On fail goto*//*Label 3407*/ 158776, // Rule ID 6848 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6848, GIR_Done, // Label 3407: @158776 GIM_Try, /*On fail goto*//*Label 3408*/ 158829, // Rule ID 10729 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10729, GIR_Done, // Label 3408: @158829 GIM_Try, /*On fail goto*//*Label 3409*/ 158913, // Rule ID 9237 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9237, GIR_Done, // Label 3409: @158913 GIM_Try, /*On fail goto*//*Label 3410*/ 158966, // Rule ID 1273 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1273, GIR_Done, // Label 3410: @158966 GIM_Try, /*On fail goto*//*Label 3411*/ 159006, // Rule ID 1263 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1263, GIR_Done, // Label 3411: @159006 GIM_Reject, // Label 3392: @159007 GIM_Reject, // Label 3285: @159008 GIM_Try, /*On fail goto*//*Label 3412*/ 160213, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 3413*/ 159111, // Rule ID 9273 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9273, GIR_Done, // Label 3413: @159111 GIM_Try, /*On fail goto*//*Label 3414*/ 159196, // Rule ID 9299 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9299, GIR_Done, // Label 3414: @159196 GIM_Try, /*On fail goto*//*Label 3415*/ 159281, // Rule ID 9325 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9325, GIR_Done, // Label 3415: @159281 GIM_Try, /*On fail goto*//*Label 3416*/ 159366, // Rule ID 9247 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9247, GIR_Done, // Label 3416: @159366 GIM_Try, /*On fail goto*//*Label 3417*/ 159438, // Rule ID 6832 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6832, GIR_Done, // Label 3417: @159438 GIM_Try, /*On fail goto*//*Label 3418*/ 159510, // Rule ID 9221 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9221, GIR_Done, // Label 3418: @159510 GIM_Try, /*On fail goto*//*Label 3419*/ 159607, // Rule ID 9275 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9275, GIR_Done, // Label 3419: @159607 GIM_Try, /*On fail goto*//*Label 3420*/ 159704, // Rule ID 9301 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9301, GIR_Done, // Label 3420: @159704 GIM_Try, /*On fail goto*//*Label 3421*/ 159801, // Rule ID 9327 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9327, GIR_Done, // Label 3421: @159801 GIM_Try, /*On fail goto*//*Label 3422*/ 159898, // Rule ID 9249 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9249, GIR_Done, // Label 3422: @159898 GIM_Try, /*On fail goto*//*Label 3423*/ 159982, // Rule ID 6834 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6834, GIR_Done, // Label 3423: @159982 GIM_Try, /*On fail goto*//*Label 3424*/ 160035, // Rule ID 10725 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10725, GIR_Done, // Label 3424: @160035 GIM_Try, /*On fail goto*//*Label 3425*/ 160119, // Rule ID 9223 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9223, GIR_Done, // Label 3425: @160119 GIM_Try, /*On fail goto*//*Label 3426*/ 160172, // Rule ID 1269 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1269, GIR_Done, // Label 3426: @160172 GIM_Try, /*On fail goto*//*Label 3427*/ 160212, // Rule ID 1259 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1259, GIR_Done, // Label 3427: @160212 GIM_Reject, // Label 3412: @160213 GIM_Reject, // Label 3286: @160214 GIM_Reject, // Label 52: @160215 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3436*/ 160511, /*GILLT_s16*//*Label 3428*/ 160231, /*GILLT_s32*//*Label 3429*/ 160266, /*GILLT_s64*//*Label 3430*/ 160301, 0, /*GILLT_v2s32*//*Label 3431*/ 160336, /*GILLT_v2s64*//*Label 3432*/ 160371, /*GILLT_v4s16*//*Label 3433*/ 160406, /*GILLT_v4s32*//*Label 3434*/ 160441, 0, /*GILLT_v8s16*//*Label 3435*/ 160476, // Label 3428: @160231 GIM_Try, /*On fail goto*//*Label 3437*/ 160265, // Rule ID 571 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (fdiv:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FDIVHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVHrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 571, GIR_Done, // Label 3437: @160265 GIM_Reject, // Label 3429: @160266 GIM_Try, /*On fail goto*//*Label 3438*/ 160300, // Rule ID 573 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FDIVSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVSrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 573, GIR_Done, // Label 3438: @160300 GIM_Reject, // Label 3430: @160301 GIM_Try, /*On fail goto*//*Label 3439*/ 160335, // Rule ID 575 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FDIVDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 575, GIR_Done, // Label 3439: @160335 GIM_Reject, // Label 3431: @160336 GIM_Try, /*On fail goto*//*Label 3440*/ 160370, // Rule ID 1191 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fdiv:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FDIVv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1191, GIR_Done, // Label 3440: @160370 GIM_Reject, // Label 3432: @160371 GIM_Try, /*On fail goto*//*Label 3441*/ 160405, // Rule ID 1195 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fdiv:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FDIVv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1195, GIR_Done, // Label 3441: @160405 GIM_Reject, // Label 3433: @160406 GIM_Try, /*On fail goto*//*Label 3442*/ 160440, // Rule ID 1187 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fdiv:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FDIVv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1187, GIR_Done, // Label 3442: @160440 GIM_Reject, // Label 3434: @160441 GIM_Try, /*On fail goto*//*Label 3443*/ 160475, // Rule ID 1193 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fdiv:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FDIVv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1193, GIR_Done, // Label 3443: @160475 GIM_Reject, // Label 3435: @160476 GIM_Try, /*On fail goto*//*Label 3444*/ 160510, // Rule ID 1189 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FDIVv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1189, GIR_Done, // Label 3444: @160510 GIM_Reject, // Label 3436: @160511 GIM_Reject, // Label 53: @160512 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3453*/ 161389, /*GILLT_s16*//*Label 3445*/ 160528, /*GILLT_s32*//*Label 3446*/ 160775, /*GILLT_s64*//*Label 3447*/ 161022, 0, /*GILLT_v2s32*//*Label 3448*/ 161269, /*GILLT_v2s64*//*Label 3449*/ 161293, /*GILLT_v4s16*//*Label 3450*/ 161317, /*GILLT_v4s32*//*Label 3451*/ 161341, 0, /*GILLT_v8s16*//*Label 3452*/ 161365, // Label 3445: @160528 GIM_Try, /*On fail goto*//*Label 3454*/ 160774, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_Try, /*On fail goto*//*Label 3455*/ 160599, // Rule ID 631 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f16] } (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 631, GIR_Done, // Label 3455: @160599 GIM_Try, /*On fail goto*//*Label 3456*/ 160660, // Rule ID 630 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 630, GIR_Done, // Label 3456: @160660 GIM_Try, /*On fail goto*//*Label 3457*/ 160709, // Rule ID 607 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f16] } (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)) => (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULHrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 607, GIR_Done, // Label 3457: @160709 GIM_Try, /*On fail goto*//*Label 3458*/ 160758, // Rule ID 606 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f16] } (strict_fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)) => (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULHrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 606, GIR_Done, // Label 3458: @160758 GIM_Try, /*On fail goto*//*Label 3459*/ 160773, // Rule ID 505 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FNEGHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 505, GIR_Done, // Label 3459: @160773 GIM_Reject, // Label 3454: @160774 GIM_Reject, // Label 3446: @160775 GIM_Try, /*On fail goto*//*Label 3460*/ 161021, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3461*/ 160846, // Rule ID 633 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f32] } (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 633, GIR_Done, // Label 3461: @160846 GIM_Try, /*On fail goto*//*Label 3462*/ 160907, // Rule ID 632 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 632, GIR_Done, // Label 3462: @160907 GIM_Try, /*On fail goto*//*Label 3463*/ 160956, // Rule ID 609 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f32] } (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)) => (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULSrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 609, GIR_Done, // Label 3463: @160956 GIM_Try, /*On fail goto*//*Label 3464*/ 161005, // Rule ID 608 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f32] } (strict_fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)) => (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULSrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 608, GIR_Done, // Label 3464: @161005 GIM_Try, /*On fail goto*//*Label 3465*/ 161020, // Rule ID 506 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FNEGSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGSr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 506, GIR_Done, // Label 3465: @161020 GIM_Reject, // Label 3460: @161021 GIM_Reject, // Label 3447: @161022 GIM_Try, /*On fail goto*//*Label 3466*/ 161268, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3467*/ 161093, // Rule ID 635 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f64] } (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 635, GIR_Done, // Label 3467: @161093 GIM_Try, /*On fail goto*//*Label 3468*/ 161154, // Rule ID 634 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 634, GIR_Done, // Label 3468: @161154 GIM_Try, /*On fail goto*//*Label 3469*/ 161203, // Rule ID 611 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f64] } (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)) => (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULDrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 611, GIR_Done, // Label 3469: @161203 GIM_Try, /*On fail goto*//*Label 3470*/ 161252, // Rule ID 610 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_STRICT_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f64] } (strict_fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)) => (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULDrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 610, GIR_Done, // Label 3470: @161252 GIM_Try, /*On fail goto*//*Label 3471*/ 161267, // Rule ID 507 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FNEGDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 507, GIR_Done, // Label 3471: @161267 GIM_Reject, // Label 3466: @161268 GIM_Reject, // Label 3448: @161269 GIM_Try, /*On fail goto*//*Label 3472*/ 161292, // Rule ID 833 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FNEGv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 833, GIR_Done, // Label 3472: @161292 GIM_Reject, // Label 3449: @161293 GIM_Try, /*On fail goto*//*Label 3473*/ 161316, // Rule ID 835 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FNEGv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 835, GIR_Done, // Label 3473: @161316 GIM_Reject, // Label 3450: @161317 GIM_Try, /*On fail goto*//*Label 3474*/ 161340, // Rule ID 831 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FNEGv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 831, GIR_Done, // Label 3474: @161340 GIM_Reject, // Label 3451: @161341 GIM_Try, /*On fail goto*//*Label 3475*/ 161364, // Rule ID 834 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FNEGv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 834, GIR_Done, // Label 3475: @161364 GIM_Reject, // Label 3452: @161365 GIM_Try, /*On fail goto*//*Label 3476*/ 161388, // Rule ID 832 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FNEGv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 832, GIR_Done, // Label 3476: @161388 GIM_Reject, // Label 3453: @161389 GIM_Reject, // Label 54: @161390 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 8, /*)*//*default:*//*Label 3481*/ 161533, /*GILLT_s32*//*Label 3477*/ 161403, /*GILLT_s64*//*Label 3478*/ 161430, 0, 0, /*GILLT_v2s64*//*Label 3479*/ 161483, 0, /*GILLT_v4s32*//*Label 3480*/ 161508, // Label 3477: @161403 GIM_Try, /*On fail goto*//*Label 3482*/ 161429, // Rule ID 497 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fpextend:{ *:[f32] } FPR16:{ *:[f16] }:$Rn) => (FCVTSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTSHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 497, GIR_Done, // Label 3482: @161429 GIM_Reject, // Label 3478: @161430 GIM_Try, /*On fail goto*//*Label 3483*/ 161456, // Rule ID 495 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fpextend:{ *:[f64] } FPR16:{ *:[f16] }:$Rn) => (FCVTDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTDHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 495, GIR_Done, // Label 3483: @161456 GIM_Try, /*On fail goto*//*Label 3484*/ 161482, // Rule ID 499 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fpextend:{ *:[f64] } FPR32:{ *:[f32] }:$Rn) => (FCVTDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTDSr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 499, GIR_Done, // Label 3484: @161482 GIM_Reject, // Label 3479: @161483 GIM_Try, /*On fail goto*//*Label 3485*/ 161507, // Rule ID 8524 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fpextend:{ *:[v2f64] } V64:{ *:[v2f32] }:$Rn) => (FCVTLv2i32:{ *:[v2f64] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTLv2i32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8524, GIR_Done, // Label 3485: @161507 GIM_Reject, // Label 3480: @161508 GIM_Try, /*On fail goto*//*Label 3486*/ 161532, // Rule ID 8526 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fpextend:{ *:[v4f32] } V64:{ *:[v4f16] }:$Rn) => (FCVTLv4i16:{ *:[v4f32] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTLv4i16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8526, GIR_Done, // Label 3486: @161532 GIM_Reject, // Label 3481: @161533 GIM_Reject, // Label 55: @161534 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 7, /*)*//*default:*//*Label 3491*/ 161677, /*GILLT_s16*//*Label 3487*/ 161547, /*GILLT_s32*//*Label 3488*/ 161600, 0, 0, /*GILLT_v2s32*//*Label 3489*/ 161627, 0, /*GILLT_v4s16*//*Label 3490*/ 161652, // Label 3487: @161547 GIM_Try, /*On fail goto*//*Label 3492*/ 161573, // Rule ID 491 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fpround:{ *:[f16] } FPR64:{ *:[f64] }:$Rn) => (FCVTHDr:{ *:[f16] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTHDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 491, GIR_Done, // Label 3492: @161573 GIM_Try, /*On fail goto*//*Label 3493*/ 161599, // Rule ID 501 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fpround:{ *:[f16] } FPR32:{ *:[f32] }:$Rn) => (FCVTHSr:{ *:[f16] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTHSr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 501, GIR_Done, // Label 3493: @161599 GIM_Reject, // Label 3488: @161600 GIM_Try, /*On fail goto*//*Label 3494*/ 161626, // Rule ID 493 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) => (FCVTSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTSDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 493, GIR_Done, // Label 3494: @161626 GIM_Reject, // Label 3489: @161627 GIM_Try, /*On fail goto*//*Label 3495*/ 161651, // Rule ID 8530 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fpround:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn) => (FCVTNv2i32:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTNv2i32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8530, GIR_Done, // Label 3495: @161651 GIM_Reject, // Label 3490: @161652 GIM_Try, /*On fail goto*//*Label 3496*/ 161676, // Rule ID 8532 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fpround:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn) => (FCVTNv4i16:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTNv4i16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8532, GIR_Done, // Label 3496: @161676 GIM_Reject, // Label 3491: @161677 GIM_Reject, // Label 56: @161678 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 3504*/ 162698, /*GILLT_s32*//*Label 3497*/ 161693, /*GILLT_s64*//*Label 3498*/ 162084, 0, /*GILLT_v2s32*//*Label 3499*/ 162475, /*GILLT_v2s64*//*Label 3500*/ 162546, /*GILLT_v4s16*//*Label 3501*/ 162617, /*GILLT_v4s32*//*Label 3502*/ 162644, 0, /*GILLT_v8s16*//*Label 3503*/ 162671, // Label 3497: @161693 GIM_Try, /*On fail goto*//*Label 3505*/ 161732, // Rule ID 8375 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8375, GIR_Done, // Label 3505: @161732 GIM_Try, /*On fail goto*//*Label 3506*/ 161771, // Rule ID 8377 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8377, GIR_Done, // Label 3506: @161771 GIM_Try, /*On fail goto*//*Label 3507*/ 161810, // Rule ID 8395 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8395, GIR_Done, // Label 3507: @161810 GIM_Try, /*On fail goto*//*Label 3508*/ 161849, // Rule ID 8397 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8397, GIR_Done, // Label 3508: @161849 GIM_Try, /*On fail goto*//*Label 3509*/ 161888, // Rule ID 8435 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTASUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8435, GIR_Done, // Label 3509: @161888 GIM_Try, /*On fail goto*//*Label 3510*/ 161927, // Rule ID 8437 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTASUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8437, GIR_Done, // Label 3510: @161927 GIM_Try, /*On fail goto*//*Label 3511*/ 161966, // Rule ID 8415 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8415, GIR_Done, // Label 3511: @161966 GIM_Try, /*On fail goto*//*Label 3512*/ 162005, // Rule ID 8417 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8417, GIR_Done, // Label 3512: @162005 GIM_Try, /*On fail goto*//*Label 3513*/ 162031, // Rule ID 392 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fp_to_sint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) => (FCVTZSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUWHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 392, GIR_Done, // Label 3513: @162031 GIM_Try, /*On fail goto*//*Label 3514*/ 162057, // Rule ID 396 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) => (FCVTZSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUWSr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 396, GIR_Done, // Label 3514: @162057 GIM_Try, /*On fail goto*//*Label 3515*/ 162083, // Rule ID 400 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) => (FCVTZSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUWDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 400, GIR_Done, // Label 3515: @162083 GIM_Reject, // Label 3498: @162084 GIM_Try, /*On fail goto*//*Label 3516*/ 162123, // Rule ID 8376 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8376, GIR_Done, // Label 3516: @162123 GIM_Try, /*On fail goto*//*Label 3517*/ 162162, // Rule ID 8378 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8378, GIR_Done, // Label 3517: @162162 GIM_Try, /*On fail goto*//*Label 3518*/ 162201, // Rule ID 8396 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8396, GIR_Done, // Label 3518: @162201 GIM_Try, /*On fail goto*//*Label 3519*/ 162240, // Rule ID 8398 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8398, GIR_Done, // Label 3519: @162240 GIM_Try, /*On fail goto*//*Label 3520*/ 162279, // Rule ID 8436 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTASUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8436, GIR_Done, // Label 3520: @162279 GIM_Try, /*On fail goto*//*Label 3521*/ 162318, // Rule ID 8438 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTASUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8438, GIR_Done, // Label 3521: @162318 GIM_Try, /*On fail goto*//*Label 3522*/ 162357, // Rule ID 8416 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8416, GIR_Done, // Label 3522: @162357 GIM_Try, /*On fail goto*//*Label 3523*/ 162396, // Rule ID 8418 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8418, GIR_Done, // Label 3523: @162396 GIM_Try, /*On fail goto*//*Label 3524*/ 162422, // Rule ID 394 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fp_to_sint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) => (FCVTZSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUXHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 394, GIR_Done, // Label 3524: @162422 GIM_Try, /*On fail goto*//*Label 3525*/ 162448, // Rule ID 398 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fp_to_sint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) => (FCVTZSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUXSr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 398, GIR_Done, // Label 3525: @162448 GIM_Try, /*On fail goto*//*Label 3526*/ 162474, // Rule ID 402 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) => (FCVTZSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUXDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 402, GIR_Done, // Label 3526: @162474 GIM_Reject, // Label 3499: @162475 GIM_Try, /*On fail goto*//*Label 3527*/ 162501, // Rule ID 816 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_sint:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCVTZSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 816, GIR_Done, // Label 3527: @162501 GIM_Try, /*On fail goto*//*Label 3528*/ 162545, // Rule ID 6770 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, // (fp_to_sint:{ *:[v2i32] } v2f64:{ *:[v2f64] }:$src) => (XTNv2i32:{ *:[v2i32] } (FCVTZSv2f64:{ *:[f128] } V128:{ *:[v2f64] }:$src)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FCVTZSv2f64, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XTNv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6770, GIR_Done, // Label 3528: @162545 GIM_Reject, // Label 3500: @162546 GIM_Try, /*On fail goto*//*Label 3529*/ 162572, // Rule ID 820 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fp_to_sint:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCVTZSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 820, GIR_Done, // Label 3529: @162572 GIM_Try, /*On fail goto*//*Label 3530*/ 162616, // Rule ID 6768 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, // (fp_to_sint:{ *:[v2i64] } v2f32:{ *:[v2f32] }:$src) => (FCVTZSv2f64:{ *:[v2i64] } (FCVTLv2i32:{ *:[f128] } V64:{ *:[v2f32] }:$src)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FCVTLv2i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6768, GIR_Done, // Label 3530: @162616 GIM_Reject, // Label 3501: @162617 GIM_Try, /*On fail goto*//*Label 3531*/ 162643, // Rule ID 812 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_sint:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCVTZSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 812, GIR_Done, // Label 3531: @162643 GIM_Reject, // Label 3502: @162644 GIM_Try, /*On fail goto*//*Label 3532*/ 162670, // Rule ID 818 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fp_to_sint:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCVTZSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 818, GIR_Done, // Label 3532: @162670 GIM_Reject, // Label 3503: @162671 GIM_Try, /*On fail goto*//*Label 3533*/ 162697, // Rule ID 814 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fp_to_sint:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCVTZSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 814, GIR_Done, // Label 3533: @162697 GIM_Reject, // Label 3504: @162698 GIM_Reject, // Label 57: @162699 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 3541*/ 163719, /*GILLT_s32*//*Label 3534*/ 162714, /*GILLT_s64*//*Label 3535*/ 163105, 0, /*GILLT_v2s32*//*Label 3536*/ 163496, /*GILLT_v2s64*//*Label 3537*/ 163567, /*GILLT_v4s16*//*Label 3538*/ 163638, /*GILLT_v4s32*//*Label 3539*/ 163665, 0, /*GILLT_v8s16*//*Label 3540*/ 163692, // Label 3534: @162714 GIM_Try, /*On fail goto*//*Label 3542*/ 162753, // Rule ID 8385 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8385, GIR_Done, // Label 3542: @162753 GIM_Try, /*On fail goto*//*Label 3543*/ 162792, // Rule ID 8387 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8387, GIR_Done, // Label 3543: @162792 GIM_Try, /*On fail goto*//*Label 3544*/ 162831, // Rule ID 8405 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8405, GIR_Done, // Label 3544: @162831 GIM_Try, /*On fail goto*//*Label 3545*/ 162870, // Rule ID 8407 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8407, GIR_Done, // Label 3545: @162870 GIM_Try, /*On fail goto*//*Label 3546*/ 162909, // Rule ID 8445 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTAUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8445, GIR_Done, // Label 3546: @162909 GIM_Try, /*On fail goto*//*Label 3547*/ 162948, // Rule ID 8447 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTAUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8447, GIR_Done, // Label 3547: @162948 GIM_Try, /*On fail goto*//*Label 3548*/ 162987, // Rule ID 8425 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8425, GIR_Done, // Label 3548: @162987 GIM_Try, /*On fail goto*//*Label 3549*/ 163026, // Rule ID 8427 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8427, GIR_Done, // Label 3549: @163026 GIM_Try, /*On fail goto*//*Label 3550*/ 163052, // Rule ID 404 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fp_to_uint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) => (FCVTZUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUWHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 404, GIR_Done, // Label 3550: @163052 GIM_Try, /*On fail goto*//*Label 3551*/ 163078, // Rule ID 408 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) => (FCVTZUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUWSr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 408, GIR_Done, // Label 3551: @163078 GIM_Try, /*On fail goto*//*Label 3552*/ 163104, // Rule ID 412 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) => (FCVTZUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUWDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 412, GIR_Done, // Label 3552: @163104 GIM_Reject, // Label 3535: @163105 GIM_Try, /*On fail goto*//*Label 3553*/ 163144, // Rule ID 8386 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8386, GIR_Done, // Label 3553: @163144 GIM_Try, /*On fail goto*//*Label 3554*/ 163183, // Rule ID 8388 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8388, GIR_Done, // Label 3554: @163183 GIM_Try, /*On fail goto*//*Label 3555*/ 163222, // Rule ID 8406 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8406, GIR_Done, // Label 3555: @163222 GIM_Try, /*On fail goto*//*Label 3556*/ 163261, // Rule ID 8408 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8408, GIR_Done, // Label 3556: @163261 GIM_Try, /*On fail goto*//*Label 3557*/ 163300, // Rule ID 8446 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTAUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8446, GIR_Done, // Label 3557: @163300 GIM_Try, /*On fail goto*//*Label 3558*/ 163339, // Rule ID 8448 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTAUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8448, GIR_Done, // Label 3558: @163339 GIM_Try, /*On fail goto*//*Label 3559*/ 163378, // Rule ID 8426 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8426, GIR_Done, // Label 3559: @163378 GIM_Try, /*On fail goto*//*Label 3560*/ 163417, // Rule ID 8428 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8428, GIR_Done, // Label 3560: @163417 GIM_Try, /*On fail goto*//*Label 3561*/ 163443, // Rule ID 406 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fp_to_uint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) => (FCVTZUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUXHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 406, GIR_Done, // Label 3561: @163443 GIM_Try, /*On fail goto*//*Label 3562*/ 163469, // Rule ID 410 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fp_to_uint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) => (FCVTZUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUXSr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 410, GIR_Done, // Label 3562: @163469 GIM_Try, /*On fail goto*//*Label 3563*/ 163495, // Rule ID 414 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) => (FCVTZUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUXDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 414, GIR_Done, // Label 3563: @163495 GIM_Reject, // Label 3536: @163496 GIM_Try, /*On fail goto*//*Label 3564*/ 163522, // Rule ID 826 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_uint:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCVTZUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 826, GIR_Done, // Label 3564: @163522 GIM_Try, /*On fail goto*//*Label 3565*/ 163566, // Rule ID 6771 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, // (fp_to_uint:{ *:[v2i32] } v2f64:{ *:[v2f64] }:$src) => (XTNv2i32:{ *:[v2i32] } (FCVTZUv2f64:{ *:[f128] } V128:{ *:[v2f64] }:$src)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FCVTZUv2f64, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XTNv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6771, GIR_Done, // Label 3565: @163566 GIM_Reject, // Label 3537: @163567 GIM_Try, /*On fail goto*//*Label 3566*/ 163593, // Rule ID 830 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fp_to_uint:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCVTZUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 830, GIR_Done, // Label 3566: @163593 GIM_Try, /*On fail goto*//*Label 3567*/ 163637, // Rule ID 6769 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, // (fp_to_uint:{ *:[v2i64] } v2f32:{ *:[v2f32] }:$src) => (FCVTZUv2f64:{ *:[v2i64] } (FCVTLv2i32:{ *:[f128] } V64:{ *:[v2f32] }:$src)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FCVTLv2i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6769, GIR_Done, // Label 3567: @163637 GIM_Reject, // Label 3538: @163638 GIM_Try, /*On fail goto*//*Label 3568*/ 163664, // Rule ID 822 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_uint:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCVTZUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 822, GIR_Done, // Label 3568: @163664 GIM_Reject, // Label 3539: @163665 GIM_Try, /*On fail goto*//*Label 3569*/ 163691, // Rule ID 828 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fp_to_uint:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCVTZUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 828, GIR_Done, // Label 3569: @163691 GIM_Reject, // Label 3540: @163692 GIM_Try, /*On fail goto*//*Label 3570*/ 163718, // Rule ID 824 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fp_to_uint:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCVTZUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 824, GIR_Done, // Label 3570: @163718 GIM_Reject, // Label 3541: @163719 GIM_Reject, // Label 58: @163720 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3579*/ 166464, /*GILLT_s16*//*Label 3571*/ 163736, /*GILLT_s32*//*Label 3572*/ 163846, /*GILLT_s64*//*Label 3573*/ 164624, 0, /*GILLT_v2s32*//*Label 3574*/ 166238, /*GILLT_v2s64*//*Label 3575*/ 166309, /*GILLT_v4s16*//*Label 3576*/ 166383, /*GILLT_v4s32*//*Label 3577*/ 166410, 0, /*GILLT_v8s16*//*Label 3578*/ 166437, // Label 3571: @163736 GIM_Try, /*On fail goto*//*Label 3580*/ 163793, // Rule ID 8782 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FPTOSI, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sint_to_fp:{ *:[f16] } (fp_to_sint:{ *:[i32] } f16:{ *:[f16] }:$Rn)) => (SCVTFv1i16:{ *:[f16] } (FCVTZSv1f16:{ *:[f16] } f16:{ *:[f16] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FCVTZSv1f16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8782, GIR_Done, // Label 3580: @163793 GIM_Try, /*On fail goto*//*Label 3581*/ 163819, // Rule ID 440 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (sint_to_fp:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) => (SCVTFUWHri:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUWHri, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 440, GIR_Done, // Label 3581: @163819 GIM_Try, /*On fail goto*//*Label 3582*/ 163845, // Rule ID 446 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (sint_to_fp:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) => (SCVTFUXHri:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUXHri, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 446, GIR_Done, // Label 3582: @163845 GIM_Reject, // Label 3572: @163846 GIM_Try, /*On fail goto*//*Label 3583*/ 164015, // Rule ID 9503 // GIM_CheckFeatures, GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext))<><><>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDRHroW, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/2, // ext GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/5, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/3, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv4i16_shift, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/2, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::ssub, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9503, GIR_Done, // Label 3583: @164015 GIM_Try, /*On fail goto*//*Label 3584*/ 164184, // Rule ID 9504 // GIM_CheckFeatures, GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext))<><><>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDRHroX, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/2, // ext GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/5, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/3, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv4i16_shift, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/2, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::ssub, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9504, GIR_Done, // Label 3584: @164184 GIM_Try, /*On fail goto*//*Label 3585*/ 164349, // Rule ID 9505 // GIM_CheckFeatures, GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDRHui, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/5, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/3, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv4i16_shift, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/2, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::ssub, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9505, GIR_Done, // Label 3585: @164349 GIM_Try, /*On fail goto*//*Label 3586*/ 164514, // Rule ID 9506 // GIM_CheckFeatures, GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDURHi, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/5, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/3, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv4i16_shift, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/2, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::ssub, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9506, GIR_Done, // Label 3586: @164514 GIM_Try, /*On fail goto*//*Label 3587*/ 164571, // Rule ID 8770 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FPTOSI, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sint_to_fp:{ *:[f32] } (fp_to_sint:{ *:[i32] } f32:{ *:[f32] }:$Rn)) => (SCVTFv1i32:{ *:[f32] } (FCVTZSv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FCVTZSv1i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8770, GIR_Done, // Label 3587: @164571 GIM_Try, /*On fail goto*//*Label 3588*/ 164597, // Rule ID 442 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (sint_to_fp:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) => (SCVTFUWSri:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUWSri, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 442, GIR_Done, // Label 3588: @164597 GIM_Try, /*On fail goto*//*Label 3589*/ 164623, // Rule ID 448 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (sint_to_fp:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) => (SCVTFUXSri:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUXSri, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 448, GIR_Done, // Label 3589: @164623 GIM_Reject, // Label 3573: @164624 GIM_Try, /*On fail goto*//*Label 3590*/ 164793, // Rule ID 9511 // GIM_CheckFeatures, GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$ext))<><>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$ext), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDRSroW, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/2, // ext GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/5, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/3, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/2, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9511, GIR_Done, // Label 3590: @164793 GIM_Try, /*On fail goto*//*Label 3591*/ 164962, // Rule ID 9512 // GIM_CheckFeatures, GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$ext))<><>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$ext), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDRSroX, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/2, // ext GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/5, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/3, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/2, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9512, GIR_Done, // Label 3591: @164962 GIM_Try, /*On fail goto*//*Label 3592*/ 165173, // Rule ID 9507 // GIM_CheckFeatures, GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext))<><><>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/7, /*Opcode*/AArch64::LDRHroW, GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/2, // ext GIR_MergeMemOperands, /*InsnID*/7, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/7, GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/6, GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/5, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/6, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/5, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SSHLLv4i16_shift, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/4, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, AArch64::dsub, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/2, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9507, GIR_Done, // Label 3592: @165173 GIM_Try, /*On fail goto*//*Label 3593*/ 165384, // Rule ID 9508 // GIM_CheckFeatures, GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext))<><><>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/7, /*Opcode*/AArch64::LDRHroX, GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/2, // ext GIR_MergeMemOperands, /*InsnID*/7, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/7, GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/6, GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/5, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/6, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/5, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SSHLLv4i16_shift, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/4, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, AArch64::dsub, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/2, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9508, GIR_Done, // Label 3593: @165384 GIM_Try, /*On fail goto*//*Label 3594*/ 165549, // Rule ID 9513 // GIM_CheckFeatures, GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDRSui, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/5, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/3, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/2, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9513, GIR_Done, // Label 3594: @165549 GIM_Try, /*On fail goto*//*Label 3595*/ 165714, // Rule ID 9514 // GIM_CheckFeatures, GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDURSi, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/5, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/3, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/2, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9514, GIR_Done, // Label 3595: @165714 GIM_Try, /*On fail goto*//*Label 3596*/ 165921, // Rule ID 9509 // GIM_CheckFeatures, GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/7, /*Opcode*/AArch64::LDRHui, GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/7, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/7, GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/6, GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/5, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/6, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/5, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SSHLLv4i16_shift, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/4, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, AArch64::dsub, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/2, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9509, GIR_Done, // Label 3596: @165921 GIM_Try, /*On fail goto*//*Label 3597*/ 166128, // Rule ID 9510 // GIM_CheckFeatures, GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/7, /*Opcode*/AArch64::LDURHi, GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/7, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/7, GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/6, GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/5, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/6, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/5, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SSHLLv4i16_shift, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/4, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, AArch64::dsub, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/2, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9510, GIR_Done, // Label 3597: @166128 GIM_Try, /*On fail goto*//*Label 3598*/ 166185, // Rule ID 8766 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FPTOSI, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sint_to_fp:{ *:[f64] } (fp_to_sint:{ *:[i64] } f64:{ *:[f64] }:$Rn)) => (SCVTFv1i64:{ *:[f64] } (FCVTZSv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FCVTZSv1i64, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8766, GIR_Done, // Label 3598: @166185 GIM_Try, /*On fail goto*//*Label 3599*/ 166211, // Rule ID 444 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (sint_to_fp:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) => (SCVTFUWDri:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUWDri, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 444, GIR_Done, // Label 3599: @166211 GIM_Try, /*On fail goto*//*Label 3600*/ 166237, // Rule ID 450 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (sint_to_fp:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) => (SCVTFUXDri:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUXDri, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 450, GIR_Done, // Label 3600: @166237 GIM_Reject, // Label 3574: @166238 GIM_Try, /*On fail goto*//*Label 3601*/ 166264, // Rule ID 990 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (sint_to_fp:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) => (SCVTFv2f32:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 990, GIR_Done, // Label 3601: @166264 GIM_Try, /*On fail goto*//*Label 3602*/ 166308, // Rule ID 6766 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, // (sint_to_fp:{ *:[v2f32] } v2i64:{ *:[v2i64] }:$src) => (FCVTNv2i32:{ *:[v2f32] } (SCVTFv2f64:{ *:[f128] } V128:{ *:[v2i64] }:$src)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SCVTFv2f64, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6766, GIR_Done, // Label 3602: @166308 GIM_Reject, // Label 3575: @166309 GIM_Try, /*On fail goto*//*Label 3603*/ 166335, // Rule ID 994 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (sint_to_fp:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) => (SCVTFv2f64:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 994, GIR_Done, // Label 3603: @166335 GIM_Try, /*On fail goto*//*Label 3604*/ 166382, // Rule ID 6764 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, // (sint_to_fp:{ *:[v2f64] } v2i32:{ *:[v2i32] }:$src) => (SCVTFv2f64:{ *:[v2f64] } (SSHLLv2i32_shift:{ *:[f128] } V64:{ *:[v2i32] }:$src, 0:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SSHLLv2i32_shift, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6764, GIR_Done, // Label 3604: @166382 GIM_Reject, // Label 3576: @166383 GIM_Try, /*On fail goto*//*Label 3605*/ 166409, // Rule ID 986 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (sint_to_fp:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) => (SCVTFv4f16:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 986, GIR_Done, // Label 3605: @166409 GIM_Reject, // Label 3577: @166410 GIM_Try, /*On fail goto*//*Label 3606*/ 166436, // Rule ID 992 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (sint_to_fp:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) => (SCVTFv4f32:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 992, GIR_Done, // Label 3606: @166436 GIM_Reject, // Label 3578: @166437 GIM_Try, /*On fail goto*//*Label 3607*/ 166463, // Rule ID 988 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (sint_to_fp:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) => (SCVTFv8f16:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 988, GIR_Done, // Label 3607: @166463 GIM_Reject, // Label 3579: @166464 GIM_Reject, // Label 59: @166465 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3616*/ 168537, /*GILLT_s16*//*Label 3608*/ 166481, /*GILLT_s32*//*Label 3609*/ 166591, /*GILLT_s64*//*Label 3610*/ 167201, 0, /*GILLT_v2s32*//*Label 3611*/ 168311, /*GILLT_v2s64*//*Label 3612*/ 168382, /*GILLT_v4s16*//*Label 3613*/ 168456, /*GILLT_v4s32*//*Label 3614*/ 168483, 0, /*GILLT_v8s16*//*Label 3615*/ 168510, // Label 3608: @166481 GIM_Try, /*On fail goto*//*Label 3617*/ 166538, // Rule ID 8786 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FPTOUI, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckIsSafeToFold, /*InsnID*/1, // (uint_to_fp:{ *:[f16] } (fp_to_uint:{ *:[i32] } f16:{ *:[f16] }:$Rn)) => (UCVTFv1i16:{ *:[f16] } (FCVTZUv1f16:{ *:[f16] } f16:{ *:[f16] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FCVTZUv1f16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8786, GIR_Done, // Label 3617: @166538 GIM_Try, /*On fail goto*//*Label 3618*/ 166564, // Rule ID 464 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (uint_to_fp:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) => (UCVTFUWHri:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUWHri, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 464, GIR_Done, // Label 3618: @166564 GIM_Try, /*On fail goto*//*Label 3619*/ 166590, // Rule ID 470 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (uint_to_fp:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) => (UCVTFUXHri:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUXHri, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 470, GIR_Done, // Label 3619: @166590 GIM_Reject, // Label 3609: @166591 GIM_Try, /*On fail goto*//*Label 3620*/ 166718, // Rule ID 8791 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHroW:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHroW, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8791, GIR_Done, // Label 3620: @166718 GIM_Try, /*On fail goto*//*Label 3621*/ 166845, // Rule ID 8792 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHroX:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHroX, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8792, GIR_Done, // Label 3621: @166845 GIM_Try, /*On fail goto*//*Label 3622*/ 166968, // Rule ID 8793 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHui:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHui, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8793, GIR_Done, // Label 3622: @166968 GIM_Try, /*On fail goto*//*Label 3623*/ 167091, // Rule ID 8794 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDURHi:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDURHi, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8794, GIR_Done, // Label 3623: @167091 GIM_Try, /*On fail goto*//*Label 3624*/ 167148, // Rule ID 8778 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FPTOUI, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (uint_to_fp:{ *:[f32] } (fp_to_uint:{ *:[i32] } f32:{ *:[f32] }:$Rn)) => (UCVTFv1i32:{ *:[f32] } (FCVTZUv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FCVTZUv1i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8778, GIR_Done, // Label 3624: @167148 GIM_Try, /*On fail goto*//*Label 3625*/ 167174, // Rule ID 466 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (uint_to_fp:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) => (UCVTFUWSri:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUWSri, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 466, GIR_Done, // Label 3625: @167174 GIM_Try, /*On fail goto*//*Label 3626*/ 167200, // Rule ID 472 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (uint_to_fp:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) => (UCVTFUXSri:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUXSri, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 472, GIR_Done, // Label 3626: @167200 GIM_Reject, // Label 3610: @167201 GIM_Try, /*On fail goto*//*Label 3627*/ 167328, // Rule ID 8803 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRSroW, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8803, GIR_Done, // Label 3627: @167328 GIM_Try, /*On fail goto*//*Label 3628*/ 167455, // Rule ID 8804 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRSroX, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8804, GIR_Done, // Label 3628: @167455 GIM_Try, /*On fail goto*//*Label 3629*/ 167582, // Rule ID 8799 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHroW, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8799, GIR_Done, // Label 3629: @167582 GIM_Try, /*On fail goto*//*Label 3630*/ 167709, // Rule ID 8800 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHroX, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8800, GIR_Done, // Label 3630: @167709 GIM_Try, /*On fail goto*//*Label 3631*/ 167832, // Rule ID 8805 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRSui, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8805, GIR_Done, // Label 3631: @167832 GIM_Try, /*On fail goto*//*Label 3632*/ 167955, // Rule ID 8806 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), ssub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDURSi, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8806, GIR_Done, // Label 3632: @167955 GIM_Try, /*On fail goto*//*Label 3633*/ 168078, // Rule ID 8801 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHui, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8801, GIR_Done, // Label 3633: @168078 GIM_Try, /*On fail goto*//*Label 3634*/ 168201, // Rule ID 8802 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDURHi, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8802, GIR_Done, // Label 3634: @168201 GIM_Try, /*On fail goto*//*Label 3635*/ 168258, // Rule ID 8774 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FPTOUI, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (uint_to_fp:{ *:[f64] } (fp_to_uint:{ *:[i64] } f64:{ *:[f64] }:$Rn)) => (UCVTFv1i64:{ *:[f64] } (FCVTZUv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FCVTZUv1i64, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8774, GIR_Done, // Label 3635: @168258 GIM_Try, /*On fail goto*//*Label 3636*/ 168284, // Rule ID 468 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (uint_to_fp:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) => (UCVTFUWDri:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUWDri, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 468, GIR_Done, // Label 3636: @168284 GIM_Try, /*On fail goto*//*Label 3637*/ 168310, // Rule ID 474 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (uint_to_fp:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) => (UCVTFUXDri:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUXDri, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 474, GIR_Done, // Label 3637: @168310 GIM_Reject, // Label 3611: @168311 GIM_Try, /*On fail goto*//*Label 3638*/ 168337, // Rule ID 1051 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (uint_to_fp:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) => (UCVTFv2f32:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1051, GIR_Done, // Label 3638: @168337 GIM_Try, /*On fail goto*//*Label 3639*/ 168381, // Rule ID 6767 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, // (uint_to_fp:{ *:[v2f32] } v2i64:{ *:[v2i64] }:$src) => (FCVTNv2i32:{ *:[v2f32] } (UCVTFv2f64:{ *:[f128] } V128:{ *:[v2i64] }:$src)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::UCVTFv2f64, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6767, GIR_Done, // Label 3639: @168381 GIM_Reject, // Label 3612: @168382 GIM_Try, /*On fail goto*//*Label 3640*/ 168408, // Rule ID 1055 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (uint_to_fp:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) => (UCVTFv2f64:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1055, GIR_Done, // Label 3640: @168408 GIM_Try, /*On fail goto*//*Label 3641*/ 168455, // Rule ID 6765 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, // (uint_to_fp:{ *:[v2f64] } v2i32:{ *:[v2i32] }:$src) => (UCVTFv2f64:{ *:[v2f64] } (USHLLv2i32_shift:{ *:[f128] } V64:{ *:[v2i32] }:$src, 0:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::USHLLv2i32_shift, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6765, GIR_Done, // Label 3641: @168455 GIM_Reject, // Label 3613: @168456 GIM_Try, /*On fail goto*//*Label 3642*/ 168482, // Rule ID 1047 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (uint_to_fp:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) => (UCVTFv4f16:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1047, GIR_Done, // Label 3642: @168482 GIM_Reject, // Label 3614: @168483 GIM_Try, /*On fail goto*//*Label 3643*/ 168509, // Rule ID 1053 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (uint_to_fp:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) => (UCVTFv4f32:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1053, GIR_Done, // Label 3643: @168509 GIM_Reject, // Label 3615: @168510 GIM_Try, /*On fail goto*//*Label 3644*/ 168536, // Rule ID 1049 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (uint_to_fp:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) => (UCVTFv8f16:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1049, GIR_Done, // Label 3644: @168536 GIM_Reject, // Label 3616: @168537 GIM_Reject, // Label 60: @168538 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3653*/ 169098, /*GILLT_s16*//*Label 3645*/ 168554, /*GILLT_s32*//*Label 3646*/ 168622, /*GILLT_s64*//*Label 3647*/ 168690, 0, /*GILLT_v2s32*//*Label 3648*/ 168758, /*GILLT_v2s64*//*Label 3649*/ 168826, /*GILLT_v4s16*//*Label 3650*/ 168894, /*GILLT_v4s32*//*Label 3651*/ 168962, 0, /*GILLT_v8s16*//*Label 3652*/ 169030, // Label 3645: @168554 GIM_Try, /*On fail goto*//*Label 3654*/ 168621, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_Try, /*On fail goto*//*Label 3655*/ 168605, // Rule ID 8680 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[f16] } (fsub:{ *:[f16] } f16:{ *:[f16] }:$Rn, f16:{ *:[f16] }:$Rm)) => (FABD16:{ *:[f16] } f16:{ *:[f16] }:$Rn, f16:{ *:[f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8680, GIR_Done, // Label 3655: @168605 GIM_Try, /*On fail goto*//*Label 3656*/ 168620, // Rule ID 502 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fabs:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FABSHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 502, GIR_Done, // Label 3656: @168620 GIM_Reject, // Label 3654: @168621 GIM_Reject, // Label 3646: @168622 GIM_Try, /*On fail goto*//*Label 3657*/ 168689, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3658*/ 168673, // Rule ID 8681 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[f32] } (fsub:{ *:[f32] } f32:{ *:[f32] }:$Rn, f32:{ *:[f32] }:$Rm)) => (FABD32:{ *:[f32] } f32:{ *:[f32] }:$Rn, f32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8681, GIR_Done, // Label 3658: @168673 GIM_Try, /*On fail goto*//*Label 3659*/ 168688, // Rule ID 503 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fabs:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FABSSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSSr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 503, GIR_Done, // Label 3659: @168688 GIM_Reject, // Label 3657: @168689 GIM_Reject, // Label 3647: @168690 GIM_Try, /*On fail goto*//*Label 3660*/ 168757, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3661*/ 168741, // Rule ID 8682 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[f64] } (fsub:{ *:[f64] } f64:{ *:[f64] }:$Rn, f64:{ *:[f64] }:$Rm)) => (FABD64:{ *:[f64] } f64:{ *:[f64] }:$Rn, f64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8682, GIR_Done, // Label 3661: @168741 GIM_Try, /*On fail goto*//*Label 3662*/ 168756, // Rule ID 504 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fabs:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FABSDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 504, GIR_Done, // Label 3662: @168756 GIM_Reject, // Label 3660: @168757 GIM_Reject, // Label 3648: @168758 GIM_Try, /*On fail goto*//*Label 3663*/ 168825, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3664*/ 168809, // Rule ID 8615 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[v2f32] } (fsub:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$Rn, v2f32:{ *:[v2f32] }:$Rm)) => (FABDv2f32:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$Rn, v2f32:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8615, GIR_Done, // Label 3664: @168809 GIM_Try, /*On fail goto*//*Label 3665*/ 168824, // Rule ID 742 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FABSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 742, GIR_Done, // Label 3665: @168824 GIM_Reject, // Label 3663: @168825 GIM_Reject, // Label 3649: @168826 GIM_Try, /*On fail goto*//*Label 3666*/ 168893, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 3667*/ 168877, // Rule ID 8617 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[v2f64] } (fsub:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, v2f64:{ *:[v2f64] }:$Rm)) => (FABDv2f64:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, v2f64:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8617, GIR_Done, // Label 3667: @168877 GIM_Try, /*On fail goto*//*Label 3668*/ 168892, // Rule ID 744 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FABSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 744, GIR_Done, // Label 3668: @168892 GIM_Reject, // Label 3666: @168893 GIM_Reject, // Label 3650: @168894 GIM_Try, /*On fail goto*//*Label 3669*/ 168961, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3670*/ 168945, // Rule ID 8618 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[v4f16] } (fsub:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$Rn, v4f16:{ *:[v4f16] }:$Rm)) => (FABDv4f16:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$Rn, v4f16:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8618, GIR_Done, // Label 3670: @168945 GIM_Try, /*On fail goto*//*Label 3671*/ 168960, // Rule ID 740 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FABSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 740, GIR_Done, // Label 3671: @168960 GIM_Reject, // Label 3669: @168961 GIM_Reject, // Label 3651: @168962 GIM_Try, /*On fail goto*//*Label 3672*/ 169029, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 3673*/ 169013, // Rule ID 8616 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, v4f32:{ *:[v4f32] }:$Rm)) => (FABDv4f32:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, v4f32:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8616, GIR_Done, // Label 3673: @169013 GIM_Try, /*On fail goto*//*Label 3674*/ 169028, // Rule ID 743 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FABSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 743, GIR_Done, // Label 3674: @169028 GIM_Reject, // Label 3672: @169029 GIM_Reject, // Label 3652: @169030 GIM_Try, /*On fail goto*//*Label 3675*/ 169097, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 3676*/ 169081, // Rule ID 8619 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, v8f16:{ *:[v8f16] }:$Rm)) => (FABDv8f16:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, v8f16:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8619, GIR_Done, // Label 3676: @169081 GIM_Try, /*On fail goto*//*Label 3677*/ 169096, // Rule ID 741 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FABSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 741, GIR_Done, // Label 3677: @169096 GIM_Reject, // Label 3675: @169097 GIM_Reject, // Label 3653: @169098 GIM_Reject, // Label 61: @169099 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3686*/ 169410, /*GILLT_s16*//*Label 3678*/ 169115, /*GILLT_s32*//*Label 3679*/ 169150, /*GILLT_s64*//*Label 3680*/ 169185, 0, /*GILLT_v2s32*//*Label 3681*/ 169235, /*GILLT_v2s64*//*Label 3682*/ 169270, /*GILLT_v4s16*//*Label 3683*/ 169305, /*GILLT_v4s32*//*Label 3684*/ 169340, 0, /*GILLT_v8s16*//*Label 3685*/ 169375, // Label 3678: @169115 GIM_Try, /*On fail goto*//*Label 3687*/ 169149, // Rule ID 589 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (fminnum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMINNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMHrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 589, GIR_Done, // Label 3687: @169149 GIM_Reject, // Label 3679: @169150 GIM_Try, /*On fail goto*//*Label 3688*/ 169184, // Rule ID 591 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (fminnum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMINNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMSrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 591, GIR_Done, // Label 3688: @169184 GIM_Reject, // Label 3680: @169185 GIM_Try, /*On fail goto*//*Label 3689*/ 169234, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3690*/ 169221, // Rule ID 593 // GIM_CheckFeatures, GIFBS_HasFPARMv8, // (fminnum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMINNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 593, GIR_Done, // Label 3690: @169221 GIM_Try, /*On fail goto*//*Label 3691*/ 169233, // Rule ID 8498 // // (fminnum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMINNMDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8498, GIR_Done, // Label 3691: @169233 GIM_Reject, // Label 3689: @169234 GIM_Reject, // Label 3681: @169235 GIM_Try, /*On fail goto*//*Label 3692*/ 169269, // Rule ID 1236 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fminnum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1236, GIR_Done, // Label 3692: @169269 GIM_Reject, // Label 3682: @169270 GIM_Try, /*On fail goto*//*Label 3693*/ 169304, // Rule ID 1240 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fminnum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1240, GIR_Done, // Label 3693: @169304 GIM_Reject, // Label 3683: @169305 GIM_Try, /*On fail goto*//*Label 3694*/ 169339, // Rule ID 1232 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fminnum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1232, GIR_Done, // Label 3694: @169339 GIM_Reject, // Label 3684: @169340 GIM_Try, /*On fail goto*//*Label 3695*/ 169374, // Rule ID 1238 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fminnum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1238, GIR_Done, // Label 3695: @169374 GIM_Reject, // Label 3685: @169375 GIM_Try, /*On fail goto*//*Label 3696*/ 169409, // Rule ID 1234 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fminnum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1234, GIR_Done, // Label 3696: @169409 GIM_Reject, // Label 3686: @169410 GIM_Reject, // Label 62: @169411 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3705*/ 169722, /*GILLT_s16*//*Label 3697*/ 169427, /*GILLT_s32*//*Label 3698*/ 169462, /*GILLT_s64*//*Label 3699*/ 169497, 0, /*GILLT_v2s32*//*Label 3700*/ 169547, /*GILLT_v2s64*//*Label 3701*/ 169582, /*GILLT_v4s16*//*Label 3702*/ 169617, /*GILLT_v4s32*//*Label 3703*/ 169652, 0, /*GILLT_v8s16*//*Label 3704*/ 169687, // Label 3697: @169427 GIM_Try, /*On fail goto*//*Label 3706*/ 169461, // Rule ID 577 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (fmaxnum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMAXNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMHrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 577, GIR_Done, // Label 3706: @169461 GIM_Reject, // Label 3698: @169462 GIM_Try, /*On fail goto*//*Label 3707*/ 169496, // Rule ID 579 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (fmaxnum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMAXNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMSrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 579, GIR_Done, // Label 3707: @169496 GIM_Reject, // Label 3699: @169497 GIM_Try, /*On fail goto*//*Label 3708*/ 169546, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3709*/ 169533, // Rule ID 581 // GIM_CheckFeatures, GIFBS_HasFPARMv8, // (fmaxnum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMAXNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 581, GIR_Done, // Label 3709: @169533 GIM_Try, /*On fail goto*//*Label 3710*/ 169545, // Rule ID 8497 // // (fmaxnum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMAXNMDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8497, GIR_Done, // Label 3710: @169545 GIM_Reject, // Label 3708: @169546 GIM_Reject, // Label 3700: @169547 GIM_Try, /*On fail goto*//*Label 3711*/ 169581, // Rule ID 1206 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fmaxnum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1206, GIR_Done, // Label 3711: @169581 GIM_Reject, // Label 3701: @169582 GIM_Try, /*On fail goto*//*Label 3712*/ 169616, // Rule ID 1210 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fmaxnum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1210, GIR_Done, // Label 3712: @169616 GIM_Reject, // Label 3702: @169617 GIM_Try, /*On fail goto*//*Label 3713*/ 169651, // Rule ID 1202 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fmaxnum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1202, GIR_Done, // Label 3713: @169651 GIM_Reject, // Label 3703: @169652 GIM_Try, /*On fail goto*//*Label 3714*/ 169686, // Rule ID 1208 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fmaxnum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1208, GIR_Done, // Label 3714: @169686 GIM_Reject, // Label 3704: @169687 GIM_Try, /*On fail goto*//*Label 3715*/ 169721, // Rule ID 1204 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fmaxnum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1204, GIR_Done, // Label 3715: @169721 GIM_Reject, // Label 3705: @169722 GIM_Reject, // Label 63: @169723 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3724*/ 170034, /*GILLT_s16*//*Label 3716*/ 169739, /*GILLT_s32*//*Label 3717*/ 169774, /*GILLT_s64*//*Label 3718*/ 169809, 0, /*GILLT_v2s32*//*Label 3719*/ 169859, /*GILLT_v2s64*//*Label 3720*/ 169894, /*GILLT_v4s16*//*Label 3721*/ 169929, /*GILLT_v4s32*//*Label 3722*/ 169964, 0, /*GILLT_v8s16*//*Label 3723*/ 169999, // Label 3716: @169739 GIM_Try, /*On fail goto*//*Label 3725*/ 169773, // Rule ID 595 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (fminimum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMINHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINHrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 595, GIR_Done, // Label 3725: @169773 GIM_Reject, // Label 3717: @169774 GIM_Try, /*On fail goto*//*Label 3726*/ 169808, // Rule ID 597 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (fminimum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMINSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINSrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 597, GIR_Done, // Label 3726: @169808 GIM_Reject, // Label 3718: @169809 GIM_Try, /*On fail goto*//*Label 3727*/ 169858, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3728*/ 169845, // Rule ID 599 // GIM_CheckFeatures, GIFBS_HasFPARMv8, // (fminimum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMINDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 599, GIR_Done, // Label 3728: @169845 GIM_Try, /*On fail goto*//*Label 3729*/ 169857, // Rule ID 8496 // // (fminimum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMINDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8496, GIR_Done, // Label 3729: @169857 GIM_Reject, // Label 3727: @169858 GIM_Reject, // Label 3719: @169859 GIM_Try, /*On fail goto*//*Label 3730*/ 169893, // Rule ID 1251 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fminimum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1251, GIR_Done, // Label 3730: @169893 GIM_Reject, // Label 3720: @169894 GIM_Try, /*On fail goto*//*Label 3731*/ 169928, // Rule ID 1255 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fminimum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1255, GIR_Done, // Label 3731: @169928 GIM_Reject, // Label 3721: @169929 GIM_Try, /*On fail goto*//*Label 3732*/ 169963, // Rule ID 1247 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fminimum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1247, GIR_Done, // Label 3732: @169963 GIM_Reject, // Label 3722: @169964 GIM_Try, /*On fail goto*//*Label 3733*/ 169998, // Rule ID 1253 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fminimum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1253, GIR_Done, // Label 3733: @169998 GIM_Reject, // Label 3723: @169999 GIM_Try, /*On fail goto*//*Label 3734*/ 170033, // Rule ID 1249 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fminimum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1249, GIR_Done, // Label 3734: @170033 GIM_Reject, // Label 3724: @170034 GIM_Reject, // Label 64: @170035 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3743*/ 170346, /*GILLT_s16*//*Label 3735*/ 170051, /*GILLT_s32*//*Label 3736*/ 170086, /*GILLT_s64*//*Label 3737*/ 170121, 0, /*GILLT_v2s32*//*Label 3738*/ 170171, /*GILLT_v2s64*//*Label 3739*/ 170206, /*GILLT_v4s16*//*Label 3740*/ 170241, /*GILLT_v4s32*//*Label 3741*/ 170276, 0, /*GILLT_v8s16*//*Label 3742*/ 170311, // Label 3735: @170051 GIM_Try, /*On fail goto*//*Label 3744*/ 170085, // Rule ID 583 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (fmaximum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMAXHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXHrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 583, GIR_Done, // Label 3744: @170085 GIM_Reject, // Label 3736: @170086 GIM_Try, /*On fail goto*//*Label 3745*/ 170120, // Rule ID 585 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (fmaximum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMAXSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXSrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 585, GIR_Done, // Label 3745: @170120 GIM_Reject, // Label 3737: @170121 GIM_Try, /*On fail goto*//*Label 3746*/ 170170, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3747*/ 170157, // Rule ID 587 // GIM_CheckFeatures, GIFBS_HasFPARMv8, // (fmaximum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMAXDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 587, GIR_Done, // Label 3747: @170157 GIM_Try, /*On fail goto*//*Label 3748*/ 170169, // Rule ID 8495 // // (fmaximum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMAXDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8495, GIR_Done, // Label 3748: @170169 GIM_Reject, // Label 3746: @170170 GIM_Reject, // Label 3738: @170171 GIM_Try, /*On fail goto*//*Label 3749*/ 170205, // Rule ID 1221 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fmaximum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1221, GIR_Done, // Label 3749: @170205 GIM_Reject, // Label 3739: @170206 GIM_Try, /*On fail goto*//*Label 3750*/ 170240, // Rule ID 1225 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fmaximum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1225, GIR_Done, // Label 3750: @170240 GIM_Reject, // Label 3740: @170241 GIM_Try, /*On fail goto*//*Label 3751*/ 170275, // Rule ID 1217 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fmaximum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1217, GIR_Done, // Label 3751: @170275 GIM_Reject, // Label 3741: @170276 GIM_Try, /*On fail goto*//*Label 3752*/ 170310, // Rule ID 1223 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fmaximum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1223, GIR_Done, // Label 3752: @170310 GIM_Reject, // Label 3742: @170311 GIM_Try, /*On fail goto*//*Label 3753*/ 170345, // Rule ID 1219 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fmaximum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1219, GIR_Done, // Label 3753: @170345 GIM_Reject, // Label 3743: @170346 GIM_Reject, // Label 65: @170347 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 3762*/ 170695, /*GILLT_s32*//*Label 3754*/ 170363, /*GILLT_s64*//*Label 3755*/ 170433, 0, /*GILLT_v2s32*//*Label 3756*/ 170503, 0, /*GILLT_v4s16*//*Label 3757*/ 170535, /*GILLT_v4s32*//*Label 3758*/ 170567, /*GILLT_v8s8*//*Label 3759*/ 170599, /*GILLT_v8s16*//*Label 3760*/ 170631, /*GILLT_v16s8*//*Label 3761*/ 170663, // Label 3754: @170363 GIM_Try, /*On fail goto*//*Label 3763*/ 170432, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3764*/ 170416, // Rule ID 2241 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm8_32b, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (smin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SMINWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2241, GIR_Done, // Label 3764: @170416 GIM_Try, /*On fail goto*//*Label 3765*/ 170431, // Rule ID 2240 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (smin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SMINWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINWrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2240, GIR_Done, // Label 3765: @170431 GIM_Reject, // Label 3763: @170432 GIM_Reject, // Label 3755: @170433 GIM_Try, /*On fail goto*//*Label 3766*/ 170502, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3767*/ 170486, // Rule ID 2243 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm8_64b, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (smin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (SMINXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2243, GIR_Done, // Label 3767: @170486 GIM_Try, /*On fail goto*//*Label 3768*/ 170501, // Rule ID 2242 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (smin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SMINXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINXrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2242, GIR_Done, // Label 3768: @170501 GIM_Reject, // Label 3766: @170502 GIM_Reject, // Label 3756: @170503 GIM_Try, /*On fail goto*//*Label 3769*/ 170534, // Rule ID 1377 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (smin:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMINv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1377, GIR_Done, // Label 3769: @170534 GIM_Reject, // Label 3757: @170535 GIM_Try, /*On fail goto*//*Label 3770*/ 170566, // Rule ID 1375 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (smin:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMINv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1375, GIR_Done, // Label 3770: @170566 GIM_Reject, // Label 3758: @170567 GIM_Try, /*On fail goto*//*Label 3771*/ 170598, // Rule ID 1378 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (smin:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMINv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1378, GIR_Done, // Label 3771: @170598 GIM_Reject, // Label 3759: @170599 GIM_Try, /*On fail goto*//*Label 3772*/ 170630, // Rule ID 1373 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (smin:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMINv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1373, GIR_Done, // Label 3772: @170630 GIM_Reject, // Label 3760: @170631 GIM_Try, /*On fail goto*//*Label 3773*/ 170662, // Rule ID 1376 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (smin:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMINv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1376, GIR_Done, // Label 3773: @170662 GIM_Reject, // Label 3761: @170663 GIM_Try, /*On fail goto*//*Label 3774*/ 170694, // Rule ID 1374 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (smin:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMINv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1374, GIR_Done, // Label 3774: @170694 GIM_Reject, // Label 3762: @170695 GIM_Reject, // Label 66: @170696 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 3783*/ 171044, /*GILLT_s32*//*Label 3775*/ 170712, /*GILLT_s64*//*Label 3776*/ 170782, 0, /*GILLT_v2s32*//*Label 3777*/ 170852, 0, /*GILLT_v4s16*//*Label 3778*/ 170884, /*GILLT_v4s32*//*Label 3779*/ 170916, /*GILLT_v8s8*//*Label 3780*/ 170948, /*GILLT_v8s16*//*Label 3781*/ 170980, /*GILLT_v16s8*//*Label 3782*/ 171012, // Label 3775: @170712 GIM_Try, /*On fail goto*//*Label 3784*/ 170781, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3785*/ 170765, // Rule ID 2237 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm8_32b, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (smax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SMAXWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2237, GIR_Done, // Label 3785: @170765 GIM_Try, /*On fail goto*//*Label 3786*/ 170780, // Rule ID 2236 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (smax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SMAXWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXWrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2236, GIR_Done, // Label 3786: @170780 GIM_Reject, // Label 3784: @170781 GIM_Reject, // Label 3776: @170782 GIM_Try, /*On fail goto*//*Label 3787*/ 170851, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3788*/ 170835, // Rule ID 2239 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm8_64b, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (smax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (SMAXXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2239, GIR_Done, // Label 3788: @170835 GIM_Try, /*On fail goto*//*Label 3789*/ 170850, // Rule ID 2238 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (smax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SMAXXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXXrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2238, GIR_Done, // Label 3789: @170850 GIM_Reject, // Label 3787: @170851 GIM_Reject, // Label 3777: @170852 GIM_Try, /*On fail goto*//*Label 3790*/ 170883, // Rule ID 1365 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (smax:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMAXv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1365, GIR_Done, // Label 3790: @170883 GIM_Reject, // Label 3778: @170884 GIM_Try, /*On fail goto*//*Label 3791*/ 170915, // Rule ID 1363 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (smax:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMAXv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1363, GIR_Done, // Label 3791: @170915 GIM_Reject, // Label 3779: @170916 GIM_Try, /*On fail goto*//*Label 3792*/ 170947, // Rule ID 1366 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (smax:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMAXv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1366, GIR_Done, // Label 3792: @170947 GIM_Reject, // Label 3780: @170948 GIM_Try, /*On fail goto*//*Label 3793*/ 170979, // Rule ID 1361 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (smax:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMAXv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1361, GIR_Done, // Label 3793: @170979 GIM_Reject, // Label 3781: @170980 GIM_Try, /*On fail goto*//*Label 3794*/ 171011, // Rule ID 1364 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (smax:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMAXv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1364, GIR_Done, // Label 3794: @171011 GIM_Reject, // Label 3782: @171012 GIM_Try, /*On fail goto*//*Label 3795*/ 171043, // Rule ID 1362 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (smax:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMAXv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1362, GIR_Done, // Label 3795: @171043 GIM_Reject, // Label 3783: @171044 GIM_Reject, // Label 67: @171045 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 3804*/ 171393, /*GILLT_s32*//*Label 3796*/ 171061, /*GILLT_s64*//*Label 3797*/ 171131, 0, /*GILLT_v2s32*//*Label 3798*/ 171201, 0, /*GILLT_v4s16*//*Label 3799*/ 171233, /*GILLT_v4s32*//*Label 3800*/ 171265, /*GILLT_v8s8*//*Label 3801*/ 171297, /*GILLT_v8s16*//*Label 3802*/ 171329, /*GILLT_v16s8*//*Label 3803*/ 171361, // Label 3796: @171061 GIM_Try, /*On fail goto*//*Label 3805*/ 171130, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3806*/ 171114, // Rule ID 2249 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimm8_32b, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (umin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UMINWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2249, GIR_Done, // Label 3806: @171114 GIM_Try, /*On fail goto*//*Label 3807*/ 171129, // Rule ID 2248 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (umin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (UMINWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINWrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2248, GIR_Done, // Label 3807: @171129 GIM_Reject, // Label 3805: @171130 GIM_Reject, // Label 3797: @171131 GIM_Try, /*On fail goto*//*Label 3808*/ 171200, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3809*/ 171184, // Rule ID 2251 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimm8_64b, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (umin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (UMINXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2251, GIR_Done, // Label 3809: @171184 GIM_Try, /*On fail goto*//*Label 3810*/ 171199, // Rule ID 2250 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (umin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UMINXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINXrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2250, GIR_Done, // Label 3810: @171199 GIM_Reject, // Label 3808: @171200 GIM_Reject, // Label 3798: @171201 GIM_Try, /*On fail goto*//*Label 3811*/ 171232, // Rule ID 1500 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (umin:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMINv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1500, GIR_Done, // Label 3811: @171232 GIM_Reject, // Label 3799: @171233 GIM_Try, /*On fail goto*//*Label 3812*/ 171264, // Rule ID 1498 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (umin:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMINv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1498, GIR_Done, // Label 3812: @171264 GIM_Reject, // Label 3800: @171265 GIM_Try, /*On fail goto*//*Label 3813*/ 171296, // Rule ID 1501 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (umin:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMINv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1501, GIR_Done, // Label 3813: @171296 GIM_Reject, // Label 3801: @171297 GIM_Try, /*On fail goto*//*Label 3814*/ 171328, // Rule ID 1496 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (umin:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMINv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1496, GIR_Done, // Label 3814: @171328 GIM_Reject, // Label 3802: @171329 GIM_Try, /*On fail goto*//*Label 3815*/ 171360, // Rule ID 1499 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (umin:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMINv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1499, GIR_Done, // Label 3815: @171360 GIM_Reject, // Label 3803: @171361 GIM_Try, /*On fail goto*//*Label 3816*/ 171392, // Rule ID 1497 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (umin:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMINv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1497, GIR_Done, // Label 3816: @171392 GIM_Reject, // Label 3804: @171393 GIM_Reject, // Label 68: @171394 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 3825*/ 171742, /*GILLT_s32*//*Label 3817*/ 171410, /*GILLT_s64*//*Label 3818*/ 171480, 0, /*GILLT_v2s32*//*Label 3819*/ 171550, 0, /*GILLT_v4s16*//*Label 3820*/ 171582, /*GILLT_v4s32*//*Label 3821*/ 171614, /*GILLT_v8s8*//*Label 3822*/ 171646, /*GILLT_v8s16*//*Label 3823*/ 171678, /*GILLT_v16s8*//*Label 3824*/ 171710, // Label 3817: @171410 GIM_Try, /*On fail goto*//*Label 3826*/ 171479, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3827*/ 171463, // Rule ID 2245 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimm8_32b, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (umax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UMAXWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2245, GIR_Done, // Label 3827: @171463 GIM_Try, /*On fail goto*//*Label 3828*/ 171478, // Rule ID 2244 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (umax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (UMAXWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXWrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2244, GIR_Done, // Label 3828: @171478 GIM_Reject, // Label 3826: @171479 GIM_Reject, // Label 3818: @171480 GIM_Try, /*On fail goto*//*Label 3829*/ 171549, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3830*/ 171533, // Rule ID 2247 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimm8_64b, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (umax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (UMAXXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2247, GIR_Done, // Label 3830: @171533 GIM_Try, /*On fail goto*//*Label 3831*/ 171548, // Rule ID 2246 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (umax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UMAXXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXXrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2246, GIR_Done, // Label 3831: @171548 GIM_Reject, // Label 3829: @171549 GIM_Reject, // Label 3819: @171550 GIM_Try, /*On fail goto*//*Label 3832*/ 171581, // Rule ID 1488 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (umax:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMAXv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1488, GIR_Done, // Label 3832: @171581 GIM_Reject, // Label 3820: @171582 GIM_Try, /*On fail goto*//*Label 3833*/ 171613, // Rule ID 1486 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (umax:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMAXv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1486, GIR_Done, // Label 3833: @171613 GIM_Reject, // Label 3821: @171614 GIM_Try, /*On fail goto*//*Label 3834*/ 171645, // Rule ID 1489 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (umax:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMAXv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1489, GIR_Done, // Label 3834: @171645 GIM_Reject, // Label 3822: @171646 GIM_Try, /*On fail goto*//*Label 3835*/ 171677, // Rule ID 1484 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (umax:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMAXv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1484, GIR_Done, // Label 3835: @171677 GIM_Reject, // Label 3823: @171678 GIM_Try, /*On fail goto*//*Label 3836*/ 171709, // Rule ID 1487 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (umax:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMAXv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1487, GIR_Done, // Label 3836: @171709 GIM_Reject, // Label 3824: @171710 GIM_Try, /*On fail goto*//*Label 3837*/ 171741, // Rule ID 1485 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (umax:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMAXv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1485, GIR_Done, // Label 3837: @171741 GIM_Reject, // Label 3825: @171742 GIM_Reject, // Label 69: @171743 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 3847*/ 172244, /*GILLT_s32*//*Label 3838*/ 171759, /*GILLT_s64*//*Label 3839*/ 171783, 0, /*GILLT_v2s32*//*Label 3840*/ 171848, /*GILLT_v2s64*//*Label 3841*/ 171872, /*GILLT_v4s16*//*Label 3842*/ 171972, /*GILLT_v4s32*//*Label 3843*/ 171996, /*GILLT_v8s8*//*Label 3844*/ 172096, /*GILLT_v8s16*//*Label 3845*/ 172120, /*GILLT_v16s8*//*Label 3846*/ 172220, // Label 3838: @171759 GIM_Try, /*On fail goto*//*Label 3848*/ 171782, // Rule ID 2230 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (abs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (ABSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSWr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2230, GIR_Done, // Label 3848: @171782 GIM_Reject, // Label 3839: @171783 GIM_Try, /*On fail goto*//*Label 3849*/ 171847, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 3850*/ 171808, // Rule ID 1617 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (abs:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn) => (ABSv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv1i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1617, GIR_Done, // Label 3850: @171808 GIM_Try, /*On fail goto*//*Label 3851*/ 171827, // Rule ID 2231 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (abs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (ABSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2231, GIR_Done, // Label 3851: @171827 GIM_Try, /*On fail goto*//*Label 3852*/ 171846, // Rule ID 6827 // GIM_CheckFeatures, GIFBS_HasNoCSSC, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (abs:{ *:[i64] } FPR64:{ *:[i64] }:$Rn) => (ABSv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv1i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6827, GIR_Done, // Label 3852: @171846 GIM_Reject, // Label 3849: @171847 GIM_Reject, // Label 3840: @171848 GIM_Try, /*On fail goto*//*Label 3853*/ 171871, // Rule ID 688 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (abs:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) => (ABSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 688, GIR_Done, // Label 3853: @171871 GIM_Reject, // Label 3841: @171872 GIM_Try, /*On fail goto*//*Label 3854*/ 171971, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 3855*/ 171955, // Rule ID 8512 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (abs:{ *:[v2i64] } (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$opA), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$opB))) => (UABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$opA, V64:{ *:[v2i32] }:$opB) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8512, GIR_Done, // Label 3855: @171955 GIM_Try, /*On fail goto*//*Label 3856*/ 171970, // Rule ID 690 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (abs:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) => (ABSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 690, GIR_Done, // Label 3856: @171970 GIM_Reject, // Label 3854: @171971 GIM_Reject, // Label 3842: @171972 GIM_Try, /*On fail goto*//*Label 3857*/ 171995, // Rule ID 686 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (abs:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) => (ABSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 686, GIR_Done, // Label 3857: @171995 GIM_Reject, // Label 3843: @171996 GIM_Try, /*On fail goto*//*Label 3858*/ 172095, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 3859*/ 172079, // Rule ID 8510 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (abs:{ *:[v4i32] } (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$opA), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$opB))) => (UABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$opA, V64:{ *:[v4i16] }:$opB) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8510, GIR_Done, // Label 3859: @172079 GIM_Try, /*On fail goto*//*Label 3860*/ 172094, // Rule ID 689 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (abs:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) => (ABSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 689, GIR_Done, // Label 3860: @172094 GIM_Reject, // Label 3858: @172095 GIM_Reject, // Label 3844: @172096 GIM_Try, /*On fail goto*//*Label 3861*/ 172119, // Rule ID 684 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (abs:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (ABSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 684, GIR_Done, // Label 3861: @172119 GIM_Reject, // Label 3845: @172120 GIM_Try, /*On fail goto*//*Label 3862*/ 172219, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 3863*/ 172203, // Rule ID 8506 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (abs:{ *:[v8i16] } (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opB))) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA, V64:{ *:[v8i8] }:$opB) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8506, GIR_Done, // Label 3863: @172203 GIM_Try, /*On fail goto*//*Label 3864*/ 172218, // Rule ID 687 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (abs:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) => (ABSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 687, GIR_Done, // Label 3864: @172218 GIM_Reject, // Label 3862: @172219 GIM_Reject, // Label 3846: @172220 GIM_Try, /*On fail goto*//*Label 3865*/ 172243, // Rule ID 685 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (abs:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (ABSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 685, GIR_Done, // Label 3865: @172243 GIM_Reject, // Label 3847: @172244 GIM_Reject, // Label 70: @172245 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 3868*/ 172379, /*GILLT_s32*//*Label 3866*/ 172253, /*GILLT_s64*//*Label 3867*/ 172316, // Label 3866: @172253 GIM_Try, /*On fail goto*//*Label 3869*/ 172275, // Rule ID 8456 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // (lround:{ *:[i32] } f16:{ *:[f16] }:$Rn) => (FCVTASUWHr:{ *:[i32] } f16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTASUWHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8456, GIR_Done, // Label 3869: @172275 GIM_Try, /*On fail goto*//*Label 3870*/ 172295, // Rule ID 8462 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // (lround:{ *:[i32] } f32:{ *:[f32] }:$Rn) => (FCVTASUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTASUWSr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8462, GIR_Done, // Label 3870: @172295 GIM_Try, /*On fail goto*//*Label 3871*/ 172315, // Rule ID 8464 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // (lround:{ *:[i32] } f64:{ *:[f64] }:$Rn) => (FCVTASUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTASUWDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8464, GIR_Done, // Label 3871: @172315 GIM_Reject, // Label 3867: @172316 GIM_Try, /*On fail goto*//*Label 3872*/ 172338, // Rule ID 8458 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (lround:{ *:[i64] } f16:{ *:[f16] }:$Rn) => (FCVTASUXHr:{ *:[i64] } f16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTASUXHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8458, GIR_Done, // Label 3872: @172338 GIM_Try, /*On fail goto*//*Label 3873*/ 172358, // Rule ID 8466 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (lround:{ *:[i64] } f32:{ *:[f32] }:$Rn) => (FCVTASUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTASUXSr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8466, GIR_Done, // Label 3873: @172358 GIM_Try, /*On fail goto*//*Label 3874*/ 172378, // Rule ID 8468 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (lround:{ *:[i64] } f64:{ *:[f64] }:$Rn) => (FCVTASUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTASUXDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8468, GIR_Done, // Label 3874: @172378 GIM_Reject, // Label 3868: @172379 GIM_Reject, // Label 71: @172380 GIM_Try, /*On fail goto*//*Label 3875*/ 172449, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/0, 3, /*)*//*default:*//*Label 3879*/ 172448, /*GILLT_s16*//*Label 3876*/ 172395, /*GILLT_s32*//*Label 3877*/ 172414, /*GILLT_s64*//*Label 3878*/ 172431, // Label 3876: @172395 GIM_Try, /*On fail goto*//*Label 3880*/ 172413, // Rule ID 8460 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (llround:{ *:[i64] } f16:{ *:[f16] }:$Rn) => (FCVTASUXHr:{ *:[i64] } f16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTASUXHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8460, GIR_Done, // Label 3880: @172413 GIM_Reject, // Label 3877: @172414 GIM_Try, /*On fail goto*//*Label 3881*/ 172430, // Rule ID 8470 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (llround:{ *:[i64] } f32:{ *:[f32] }:$Rn) => (FCVTASUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTASUXSr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8470, GIR_Done, // Label 3881: @172430 GIM_Reject, // Label 3878: @172431 GIM_Try, /*On fail goto*//*Label 3882*/ 172447, // Rule ID 8472 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (llround:{ *:[i64] } f64:{ *:[f64] }:$Rn) => (FCVTASUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTASUXDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8472, GIR_Done, // Label 3882: @172447 GIM_Reject, // Label 3879: @172448 GIM_Reject, // Label 3875: @172449 GIM_Reject, // Label 72: @172450 GIM_Try, /*On fail goto*//*Label 3883*/ 172462, // Rule ID 223 // // MIs[0] addr GIM_CheckIsMBB, /*MI*/0, /*Op*/0, // (br (bb:{ *:[Other] }):$addr) => (B (bb:{ *:[Other] }):$addr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::B, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 223, GIR_Done, // Label 3883: @172462 GIM_Reject, // Label 73: @172463 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 3887*/ 174720, /*GILLT_s16*//*Label 3884*/ 172472, /*GILLT_s32*//*Label 3885*/ 172934, /*GILLT_s64*//*Label 3886*/ 174207, // Label 3884: @172472 GIM_Try, /*On fail goto*//*Label 3888*/ 172519, // Rule ID 5753 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, // (vector_extract:{ *:[f16] } ZPR:{ *:[nxv8f16] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[f16] } ZPR:{ *:[nxv8f16] }:$Zs, hsub:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/7, // Zs GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR16RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5753, GIR_Done, // Label 3888: @172519 GIM_Try, /*On fail goto*//*Label 3889*/ 172566, // Rule ID 5754 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, // (vector_extract:{ *:[f16] } ZPR:{ *:[nxv4f16] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[f16] } ZPR:{ *:[nxv4f16] }:$Zs, hsub:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/7, // Zs GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR16RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5754, GIR_Done, // Label 3889: @172566 GIM_Try, /*On fail goto*//*Label 3890*/ 172613, // Rule ID 5755 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, // (vector_extract:{ *:[f16] } ZPR:{ *:[nxv2f16] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[f16] } ZPR:{ *:[nxv2f16] }:$Zs, hsub:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/7, // Zs GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR16RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5755, GIR_Done, // Label 3890: @172613 GIM_Try, /*On fail goto*//*Label 3891*/ 172687, // Rule ID 5734 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_sve_elm_idx_extdup_h, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[f16] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<>:$index) => (EXTRACT_SUBREG:{ *:[f16] } (DUP_ZZI_H:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<>:$index), hsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::DUP_ZZI_H, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::hsub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR16RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5734, GIR_Done, // Label 3891: @172687 GIM_Try, /*On fail goto*//*Label 3892*/ 172761, // Rule ID 5735 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_sve_elm_idx_extdup_s, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[f16] } ZPR:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<>:$index) => (EXTRACT_SUBREG:{ *:[f16] } (DUP_ZZI_S:{ *:[nxv16i8] } ZPR:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<>:$index), hsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::DUP_ZZI_S, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::hsub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR16RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5735, GIR_Done, // Label 3892: @172761 GIM_Try, /*On fail goto*//*Label 3893*/ 172835, // Rule ID 5736 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_sve_elm_idx_extdup_d, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[f16] } ZPR:{ *:[nxv2f16] }:$vec, (imm:{ *:[i64] })<>:$index) => (EXTRACT_SUBREG:{ *:[f16] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2f16] }:$vec, (imm:{ *:[i64] })<>:$index), hsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::DUP_ZZI_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::hsub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR16RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5736, GIR_Done, // Label 3893: @172835 GIM_Try, /*On fail goto*//*Label 3894*/ 172884, // Rule ID 9056 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (DUPi16:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9056, GIR_Done, // Label 3894: @172884 GIM_Try, /*On fail goto*//*Label 3895*/ 172933, // Rule ID 9057 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (DUPi16:{ *:[bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9057, GIR_Done, // Label 3895: @172933 GIM_Reject, // Label 3885: @172934 GIM_Try, /*On fail goto*//*Label 3896*/ 172979, // Rule ID 10144 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, // (extractelt:{ *:[i32] } V128:{ *:[v4i32] }:$V, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4i32] }:$V, ssub:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/14, // V GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, // GIR_Coverage, 10144, GIR_Done, // Label 3896: @172979 GIM_Try, /*On fail goto*//*Label 3897*/ 173024, // Rule ID 10145 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, // (extractelt:{ *:[i32] } V64:{ *:[v2i32] }:$V, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i32] } V64:{ *:[v2i32] }:$V, ssub:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/14, // V GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR64RegClassID, // GIR_Coverage, 10145, GIR_Done, // Label 3897: @173024 GIM_Try, /*On fail goto*//*Label 3898*/ 173071, // Rule ID 5749 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, // (vector_extract:{ *:[i32] } ZPR:{ *:[nxv16i8] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i32] } ZPR:{ *:[nxv16i8] }:$Zs, ssub:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/14, // Zs GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5749, GIR_Done, // Label 3898: @173071 GIM_Try, /*On fail goto*//*Label 3899*/ 173118, // Rule ID 5750 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, // (vector_extract:{ *:[i32] } ZPR:{ *:[nxv8i16] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i32] } ZPR:{ *:[nxv8i16] }:$Zs, ssub:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/14, // Zs GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5750, GIR_Done, // Label 3899: @173118 GIM_Try, /*On fail goto*//*Label 3900*/ 173165, // Rule ID 5751 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, // (vector_extract:{ *:[i32] } ZPR:{ *:[nxv4i32] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i32] } ZPR:{ *:[nxv4i32] }:$Zs, ssub:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/14, // Zs GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5751, GIR_Done, // Label 3900: @173165 GIM_Try, /*On fail goto*//*Label 3901*/ 173212, // Rule ID 5756 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, // (vector_extract:{ *:[f32] } ZPR:{ *:[nxv4f32] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[f32] } ZPR:{ *:[nxv4f32] }:$Zs, ssub:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/14, // Zs GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5756, GIR_Done, // Label 3901: @173212 GIM_Try, /*On fail goto*//*Label 3902*/ 173259, // Rule ID 5757 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, // (vector_extract:{ *:[f32] } ZPR:{ *:[nxv2f32] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[f32] } ZPR:{ *:[nxv2f32] }:$Zs, ssub:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/14, // Zs GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5757, GIR_Done, // Label 3902: @173259 GIM_Try, /*On fail goto*//*Label 3903*/ 173333, // Rule ID 5740 // GIM_CheckFeatures, GIFBS_NotInStreamingSVEMode, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i32] } ZPR:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<>:$index) => (UMOVvi8:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v16i8] } ZPR:{ *:[nxv16i8] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$index) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/37, // vec GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::ZPRRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5740, GIR_Done, // Label 3903: @173333 GIM_Try, /*On fail goto*//*Label 3904*/ 173407, // Rule ID 5741 // GIM_CheckFeatures, GIFBS_NotInStreamingSVEMode, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i32] } ZPR:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<>:$index) => (UMOVvi16:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v8i16] } ZPR:{ *:[nxv8i16] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$index) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/37, // vec GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::ZPRRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5741, GIR_Done, // Label 3904: @173407 GIM_Try, /*On fail goto*//*Label 3905*/ 173481, // Rule ID 5742 // GIM_CheckFeatures, GIFBS_NotInStreamingSVEMode, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i32] } ZPR:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<>:$index) => (UMOVvi32:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v4i32] } ZPR:{ *:[nxv4i32] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$index) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/37, // vec GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::ZPRRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5742, GIR_Done, // Label 3905: @173481 GIM_Try, /*On fail goto*//*Label 3906*/ 173532, // Rule ID 1890 // GIM_CheckFeatures, GIFBS_HasNEONorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndex0, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (UMOVvi8_idx0:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi8_idx0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1890, GIR_Done, // Label 3906: @173532 GIM_Try, /*On fail goto*//*Label 3907*/ 173583, // Rule ID 1891 // GIM_CheckFeatures, GIFBS_HasNEONorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndex0, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (UMOVvi16_idx0:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi16_idx0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1891, GIR_Done, // Label 3907: @173583 GIM_Try, /*On fail goto*//*Label 3908*/ 173634, // Rule ID 1892 // GIM_CheckFeatures, GIFBS_HasNEONorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndex0, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (UMOVvi32_idx0:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi32_idx0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1892, GIR_Done, // Label 3908: @173634 GIM_Try, /*On fail goto*//*Label 3909*/ 173685, // Rule ID 1894 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1894, GIR_Done, // Label 3909: @173685 GIM_Try, /*On fail goto*//*Label 3910*/ 173736, // Rule ID 1895 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1895, GIR_Done, // Label 3910: @173736 GIM_Try, /*On fail goto*//*Label 3911*/ 173787, // Rule ID 1896 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (UMOVvi32:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1896, GIR_Done, // Label 3911: @173787 GIM_Try, /*On fail goto*//*Label 3912*/ 173861, // Rule ID 5730 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_sve_elm_idx_extdup_b, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i32] } ZPR:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<>:$index) => (EXTRACT_SUBREG:{ *:[i32] } (DUP_ZZI_B:{ *:[nxv16i8] } ZPR:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<>:$index), ssub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::DUP_ZZI_B, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5730, GIR_Done, // Label 3912: @173861 GIM_Try, /*On fail goto*//*Label 3913*/ 173935, // Rule ID 5731 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_sve_elm_idx_extdup_h, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i32] } ZPR:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<>:$index) => (EXTRACT_SUBREG:{ *:[i32] } (DUP_ZZI_H:{ *:[nxv16i8] } ZPR:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<>:$index), ssub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::DUP_ZZI_H, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5731, GIR_Done, // Label 3913: @173935 GIM_Try, /*On fail goto*//*Label 3914*/ 174009, // Rule ID 5732 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_sve_elm_idx_extdup_s, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i32] } ZPR:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<>:$index) => (EXTRACT_SUBREG:{ *:[i32] } (DUP_ZZI_S:{ *:[nxv16i8] } ZPR:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<>:$index), ssub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::DUP_ZZI_S, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5732, GIR_Done, // Label 3914: @174009 GIM_Try, /*On fail goto*//*Label 3915*/ 174083, // Rule ID 5737 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_sve_elm_idx_extdup_s, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[f32] } ZPR:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<>:$index) => (EXTRACT_SUBREG:{ *:[f32] } (DUP_ZZI_S:{ *:[nxv16i8] } ZPR:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<>:$index), ssub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::DUP_ZZI_S, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5737, GIR_Done, // Label 3915: @174083 GIM_Try, /*On fail goto*//*Label 3916*/ 174157, // Rule ID 5738 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_sve_elm_idx_extdup_d, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[f32] } ZPR:{ *:[nxv2f32] }:$vec, (imm:{ *:[i64] })<>:$index) => (EXTRACT_SUBREG:{ *:[f32] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2f32] }:$vec, (imm:{ *:[i64] })<>:$index), ssub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::DUP_ZZI_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5738, GIR_Done, // Label 3916: @174157 GIM_Try, /*On fail goto*//*Label 3917*/ 174206, // Rule ID 9055 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (DUPi32:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9055, GIR_Done, // Label 3917: @174206 GIM_Reject, // Label 3886: @174207 GIM_Try, /*On fail goto*//*Label 3918*/ 174252, // Rule ID 10143 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, // (extractelt:{ *:[i64] } V128:{ *:[v2i64] }:$V, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2i64] }:$V, dsub:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // V GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, // GIR_Coverage, 10143, GIR_Done, // Label 3918: @174252 GIM_Try, /*On fail goto*//*Label 3919*/ 174299, // Rule ID 5752 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, // (vector_extract:{ *:[i64] } ZPR:{ *:[nxv2i64] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i64] } ZPR:{ *:[nxv2i64] }:$Zs, dsub:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Zs GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5752, GIR_Done, // Label 3919: @174299 GIM_Try, /*On fail goto*//*Label 3920*/ 174346, // Rule ID 5758 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, // (vector_extract:{ *:[f64] } ZPR:{ *:[nxv2f64] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[f64] } ZPR:{ *:[nxv2f64] }:$Zs, dsub:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Zs GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5758, GIR_Done, // Label 3920: @174346 GIM_Try, /*On fail goto*//*Label 3921*/ 174420, // Rule ID 5743 // GIM_CheckFeatures, GIFBS_NotInStreamingSVEMode, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i64] } ZPR:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<>:$index) => (UMOVvi64:{ *:[i64] } (EXTRACT_SUBREG:{ *:[v2i64] } ZPR:{ *:[nxv2i64] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$index) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/37, // vec GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::ZPRRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5743, GIR_Done, // Label 3921: @174420 GIM_Try, /*On fail goto*//*Label 3922*/ 174471, // Rule ID 1893 // GIM_CheckFeatures, GIFBS_HasNEONorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndex0, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (UMOVvi64_idx0:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi64_idx0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1893, GIR_Done, // Label 3922: @174471 GIM_Try, /*On fail goto*//*Label 3923*/ 174522, // Rule ID 1897 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (UMOVvi64:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1897, GIR_Done, // Label 3923: @174522 GIM_Try, /*On fail goto*//*Label 3924*/ 174596, // Rule ID 5733 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_sve_elm_idx_extdup_d, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i64] } ZPR:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<>:$index) => (EXTRACT_SUBREG:{ *:[i64] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<>:$index), dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::DUP_ZZI_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::dsub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5733, GIR_Done, // Label 3924: @174596 GIM_Try, /*On fail goto*//*Label 3925*/ 174670, // Rule ID 5739 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_sve_elm_idx_extdup_d, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[f64] } ZPR:{ *:[nxv2f64] }:$vec, (imm:{ *:[i64] })<>:$index) => (EXTRACT_SUBREG:{ *:[f64] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2f64] }:$vec, (imm:{ *:[i64] })<>:$index), dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::DUP_ZZI_D, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::dsub, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::ZPRRegClassID, // GIR_Coverage, 5739, GIR_Done, // Label 3925: @174670 GIM_Try, /*On fail goto*//*Label 3926*/ 174719, // Rule ID 9054 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (DUPi64:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPi64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9054, GIR_Done, // Label 3926: @174719 GIM_Reject, // Label 3887: @174720 GIM_Reject, // Label 74: @174721 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 3929*/ 174851, /*GILLT_s32*//*Label 3927*/ 174729, /*GILLT_s64*//*Label 3928*/ 174790, // Label 3927: @174729 GIM_Try, /*On fail goto*//*Label 3930*/ 174789, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3931*/ 174754, // Rule ID 2234 // GIM_CheckFeatures, GIFBS_HasCSSC, // (cttz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (CTZWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CTZWr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2234, GIR_Done, // Label 3931: @174754 GIM_Try, /*On fail goto*//*Label 3932*/ 174788, // Rule ID 7966 // // (cttz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (CLZWr:{ *:[i32] } (RBITWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::RBITWr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLZWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7966, GIR_Done, // Label 3932: @174788 GIM_Reject, // Label 3930: @174789 GIM_Reject, // Label 3928: @174790 GIM_Try, /*On fail goto*//*Label 3933*/ 174850, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3934*/ 174815, // Rule ID 2235 // GIM_CheckFeatures, GIFBS_HasCSSC, // (cttz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (CTZXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CTZXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2235, GIR_Done, // Label 3934: @174815 GIM_Try, /*On fail goto*//*Label 3935*/ 174849, // Rule ID 7967 // // (cttz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (CLZXr:{ *:[i64] } (RBITXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::RBITXr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLZXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7967, GIR_Done, // Label 3935: @174849 GIM_Reject, // Label 3933: @174850 GIM_Reject, // Label 3929: @174851 GIM_Reject, // Label 75: @174852 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 3944*/ 175474, /*GILLT_s32*//*Label 3936*/ 174868, /*GILLT_s64*//*Label 3937*/ 175099, 0, /*GILLT_v2s32*//*Label 3938*/ 175330, 0, /*GILLT_v4s16*//*Label 3939*/ 175354, /*GILLT_v4s32*//*Label 3940*/ 175378, /*GILLT_v8s8*//*Label 3941*/ 175402, /*GILLT_v8s16*//*Label 3942*/ 175426, /*GILLT_v16s8*//*Label 3943*/ 175450, // Label 3936: @174868 GIM_Try, /*On fail goto*//*Label 3945*/ 175098, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3946*/ 174981, // Rule ID 7968 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 31, // MIs[3] Rn GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (ctlz:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } (xor:{ *:[i32] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 31:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn), 1:{ *:[i64] }), 1:{ *:[i32] })) => (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7968, GIR_Done, // Label 3946: @174981 GIM_Try, /*On fail goto*//*Label 3947*/ 175084, // Rule ID 11681 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, // MIs[4] Rn GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 31, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (ctlz:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 31:{ *:[i64] })), 1:{ *:[i64] }), 1:{ *:[i32] })) => (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11681, GIR_Done, // Label 3947: @175084 GIM_Try, /*On fail goto*//*Label 3948*/ 175097, // Rule ID 182 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (ctlz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (CLZWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZWr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 182, GIR_Done, // Label 3948: @175097 GIM_Reject, // Label 3945: @175098 GIM_Reject, // Label 3937: @175099 GIM_Try, /*On fail goto*//*Label 3949*/ 175329, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3950*/ 175212, // Rule ID 7969 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 63, // MIs[3] Rn GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (ctlz:{ *:[i64] } (or:{ *:[i64] } (shl:{ *:[i64] } (xor:{ *:[i64] } (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 63:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn), 1:{ *:[i64] }), 1:{ *:[i64] })) => (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7969, GIR_Done, // Label 3950: @175212 GIM_Try, /*On fail goto*//*Label 3951*/ 175315, // Rule ID 11682 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, // MIs[4] Rn GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 63, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (ctlz:{ *:[i64] } (or:{ *:[i64] } (shl:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 63:{ *:[i64] })), 1:{ *:[i64] }), 1:{ *:[i64] })) => (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11682, GIR_Done, // Label 3951: @175315 GIM_Try, /*On fail goto*//*Label 3952*/ 175328, // Rule ID 183 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (ctlz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (CLZXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 183, GIR_Done, // Label 3952: @175328 GIM_Reject, // Label 3949: @175329 GIM_Reject, // Label 3938: @175330 GIM_Try, /*On fail goto*//*Label 3953*/ 175353, // Rule ID 701 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ctlz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) => (CLZv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 701, GIR_Done, // Label 3953: @175353 GIM_Reject, // Label 3939: @175354 GIM_Try, /*On fail goto*//*Label 3954*/ 175377, // Rule ID 699 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ctlz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) => (CLZv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 699, GIR_Done, // Label 3954: @175377 GIM_Reject, // Label 3940: @175378 GIM_Try, /*On fail goto*//*Label 3955*/ 175401, // Rule ID 702 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ctlz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) => (CLZv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 702, GIR_Done, // Label 3955: @175401 GIM_Reject, // Label 3941: @175402 GIM_Try, /*On fail goto*//*Label 3956*/ 175425, // Rule ID 697 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ctlz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (CLZv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 697, GIR_Done, // Label 3956: @175425 GIM_Reject, // Label 3942: @175426 GIM_Try, /*On fail goto*//*Label 3957*/ 175449, // Rule ID 700 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ctlz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) => (CLZv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 700, GIR_Done, // Label 3957: @175449 GIM_Reject, // Label 3943: @175450 GIM_Try, /*On fail goto*//*Label 3958*/ 175473, // Rule ID 698 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ctlz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (CLZv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 698, GIR_Done, // Label 3958: @175473 GIM_Reject, // Label 3944: @175474 GIM_Reject, // Label 76: @175475 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 3963*/ 175587, /*GILLT_s32*//*Label 3959*/ 175491, /*GILLT_s64*//*Label 3960*/ 175515, 0, 0, 0, 0, 0, /*GILLT_v8s8*//*Label 3961*/ 175539, 0, /*GILLT_v16s8*//*Label 3962*/ 175563, // Label 3959: @175491 GIM_Try, /*On fail goto*//*Label 3964*/ 175514, // Rule ID 2232 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (ctpop:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (CNTWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CNTWr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2232, GIR_Done, // Label 3964: @175514 GIM_Reject, // Label 3960: @175515 GIM_Try, /*On fail goto*//*Label 3965*/ 175538, // Rule ID 2233 // GIM_CheckFeatures, GIFBS_HasCSSC, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (ctpop:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (CNTXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CNTXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2233, GIR_Done, // Label 3965: @175538 GIM_Reject, // Label 3961: @175539 GIM_Try, /*On fail goto*//*Label 3966*/ 175562, // Rule ID 738 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ctpop:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (CNTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CNTv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 738, GIR_Done, // Label 3966: @175562 GIM_Reject, // Label 3962: @175563 GIM_Try, /*On fail goto*//*Label 3967*/ 175586, // Rule ID 739 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ctpop:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (CNTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CNTv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 739, GIR_Done, // Label 3967: @175586 GIM_Reject, // Label 3963: @175587 GIM_Reject, // Label 77: @175588 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 3970*/ 175732, /*GILLT_s32*//*Label 3968*/ 175596, /*GILLT_s64*//*Label 3969*/ 175664, // Label 3968: @175596 GIM_Try, /*On fail goto*//*Label 3971*/ 175663, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 3972*/ 175649, // Rule ID 7972 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ROTR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, // (bswap:{ *:[i32] } (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 16:{ *:[i64] })) => (REV16Wr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV16Wr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7972, GIR_Done, // Label 3972: @175649 GIM_Try, /*On fail goto*//*Label 3973*/ 175662, // Rule ID 187 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (REVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REVWr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 187, GIR_Done, // Label 3973: @175662 GIM_Reject, // Label 3971: @175663 GIM_Reject, // Label 3969: @175664 GIM_Try, /*On fail goto*//*Label 3974*/ 175731, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 3975*/ 175717, // Rule ID 7973 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ROTR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (bswap:{ *:[i64] } (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 32:{ *:[i64] })) => (REV32Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV32Xr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 7973, GIR_Done, // Label 3975: @175717 GIM_Try, /*On fail goto*//*Label 3976*/ 175730, // Rule ID 188 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (REVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REVXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 188, GIR_Done, // Label 3976: @175730 GIM_Reject, // Label 3974: @175731 GIM_Reject, // Label 3970: @175732 GIM_Reject, // Label 78: @175733 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 3981*/ 175841, /*GILLT_s32*//*Label 3977*/ 175749, /*GILLT_s64*//*Label 3978*/ 175771, 0, 0, 0, 0, 0, /*GILLT_v8s8*//*Label 3979*/ 175793, 0, /*GILLT_v16s8*//*Label 3980*/ 175817, // Label 3977: @175749 GIM_Try, /*On fail goto*//*Label 3982*/ 175770, // Rule ID 184 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (bitreverse:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (RBITWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::RBITWr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 184, GIR_Done, // Label 3982: @175770 GIM_Reject, // Label 3978: @175771 GIM_Try, /*On fail goto*//*Label 3983*/ 175792, // Rule ID 185 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitreverse:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (RBITXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::RBITXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 185, GIR_Done, // Label 3983: @175792 GIM_Reject, // Label 3979: @175793 GIM_Try, /*On fail goto*//*Label 3984*/ 175816, // Rule ID 947 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitreverse:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (RBITv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::RBITv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 947, GIR_Done, // Label 3984: @175816 GIM_Reject, // Label 3980: @175817 GIM_Try, /*On fail goto*//*Label 3985*/ 175840, // Rule ID 948 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitreverse:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (RBITv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::RBITv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 948, GIR_Done, // Label 3985: @175840 GIM_Reject, // Label 3981: @175841 GIM_Reject, // Label 79: @175842 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3994*/ 176074, /*GILLT_s16*//*Label 3986*/ 175858, /*GILLT_s32*//*Label 3987*/ 175885, /*GILLT_s64*//*Label 3988*/ 175912, 0, /*GILLT_v2s32*//*Label 3989*/ 175939, /*GILLT_v2s64*//*Label 3990*/ 175966, /*GILLT_v4s16*//*Label 3991*/ 175993, /*GILLT_v4s32*//*Label 3992*/ 176020, 0, /*GILLT_v8s16*//*Label 3993*/ 176047, // Label 3986: @175858 GIM_Try, /*On fail goto*//*Label 3995*/ 175884, // Rule ID 533 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fceil:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTPHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 533, GIR_Done, // Label 3995: @175884 GIM_Reject, // Label 3987: @175885 GIM_Try, /*On fail goto*//*Label 3996*/ 175911, // Rule ID 535 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fceil:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTPSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPSr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 535, GIR_Done, // Label 3996: @175911 GIM_Reject, // Label 3988: @175912 GIM_Try, /*On fail goto*//*Label 3997*/ 175938, // Rule ID 537 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fceil:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTPDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 537, GIR_Done, // Label 3997: @175938 GIM_Reject, // Label 3989: @175939 GIM_Try, /*On fail goto*//*Label 3998*/ 175965, // Rule ID 886 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fceil:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 886, GIR_Done, // Label 3998: @175965 GIM_Reject, // Label 3990: @175966 GIM_Try, /*On fail goto*//*Label 3999*/ 175992, // Rule ID 890 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fceil:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 890, GIR_Done, // Label 3999: @175992 GIM_Reject, // Label 3991: @175993 GIM_Try, /*On fail goto*//*Label 4000*/ 176019, // Rule ID 882 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fceil:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 882, GIR_Done, // Label 4000: @176019 GIM_Reject, // Label 3992: @176020 GIM_Try, /*On fail goto*//*Label 4001*/ 176046, // Rule ID 888 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fceil:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 888, GIR_Done, // Label 4001: @176046 GIM_Reject, // Label 3993: @176047 GIM_Try, /*On fail goto*//*Label 4002*/ 176073, // Rule ID 884 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fceil:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 884, GIR_Done, // Label 4002: @176073 GIM_Reject, // Label 3994: @176074 GIM_Reject, // Label 80: @176075 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 4011*/ 176307, /*GILLT_s16*//*Label 4003*/ 176091, /*GILLT_s32*//*Label 4004*/ 176118, /*GILLT_s64*//*Label 4005*/ 176145, 0, /*GILLT_v2s32*//*Label 4006*/ 176172, /*GILLT_v2s64*//*Label 4007*/ 176199, /*GILLT_v4s16*//*Label 4008*/ 176226, /*GILLT_v4s32*//*Label 4009*/ 176253, 0, /*GILLT_v8s16*//*Label 4010*/ 176280, // Label 4003: @176091 GIM_Try, /*On fail goto*//*Label 4012*/ 176117, // Rule ID 551 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FSQRTHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 551, GIR_Done, // Label 4012: @176117 GIM_Reject, // Label 4004: @176118 GIM_Try, /*On fail goto*//*Label 4013*/ 176144, // Rule ID 553 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FSQRTSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTSr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 553, GIR_Done, // Label 4013: @176144 GIM_Reject, // Label 4005: @176145 GIM_Try, /*On fail goto*//*Label 4014*/ 176171, // Rule ID 555 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FSQRTDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 555, GIR_Done, // Label 4014: @176171 GIM_Reject, // Label 4006: @176172 GIM_Try, /*On fail goto*//*Label 4015*/ 176198, // Rule ID 933 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fsqrt:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FSQRTv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 933, GIR_Done, // Label 4015: @176198 GIM_Reject, // Label 4007: @176199 GIM_Try, /*On fail goto*//*Label 4016*/ 176225, // Rule ID 937 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fsqrt:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FSQRTv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 937, GIR_Done, // Label 4016: @176225 GIM_Reject, // Label 4008: @176226 GIM_Try, /*On fail goto*//*Label 4017*/ 176252, // Rule ID 929 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fsqrt:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FSQRTv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 929, GIR_Done, // Label 4017: @176252 GIM_Reject, // Label 4009: @176253 GIM_Try, /*On fail goto*//*Label 4018*/ 176279, // Rule ID 935 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fsqrt:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FSQRTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 935, GIR_Done, // Label 4018: @176279 GIM_Reject, // Label 4010: @176280 GIM_Try, /*On fail goto*//*Label 4019*/ 176306, // Rule ID 931 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fsqrt:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FSQRTv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 931, GIR_Done, // Label 4019: @176306 GIM_Reject, // Label 4011: @176307 GIM_Reject, // Label 81: @176308 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 4028*/ 176540, /*GILLT_s16*//*Label 4020*/ 176324, /*GILLT_s32*//*Label 4021*/ 176351, /*GILLT_s64*//*Label 4022*/ 176378, 0, /*GILLT_v2s32*//*Label 4023*/ 176405, /*GILLT_v2s64*//*Label 4024*/ 176432, /*GILLT_v4s16*//*Label 4025*/ 176459, /*GILLT_v4s32*//*Label 4026*/ 176486, 0, /*GILLT_v8s16*//*Label 4027*/ 176513, // Label 4020: @176324 GIM_Try, /*On fail goto*//*Label 4029*/ 176350, // Rule ID 521 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (ffloor:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTMHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 521, GIR_Done, // Label 4029: @176350 GIM_Reject, // Label 4021: @176351 GIM_Try, /*On fail goto*//*Label 4030*/ 176377, // Rule ID 523 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (ffloor:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTMSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMSr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 523, GIR_Done, // Label 4030: @176377 GIM_Reject, // Label 4022: @176378 GIM_Try, /*On fail goto*//*Label 4031*/ 176404, // Rule ID 525 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ffloor:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTMDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 525, GIR_Done, // Label 4031: @176404 GIM_Reject, // Label 4023: @176405 GIM_Try, /*On fail goto*//*Label 4032*/ 176431, // Rule ID 866 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ffloor:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 866, GIR_Done, // Label 4032: @176431 GIM_Reject, // Label 4024: @176432 GIM_Try, /*On fail goto*//*Label 4033*/ 176458, // Rule ID 870 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ffloor:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 870, GIR_Done, // Label 4033: @176458 GIM_Reject, // Label 4025: @176459 GIM_Try, /*On fail goto*//*Label 4034*/ 176485, // Rule ID 862 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ffloor:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 862, GIR_Done, // Label 4034: @176485 GIM_Reject, // Label 4026: @176486 GIM_Try, /*On fail goto*//*Label 4035*/ 176512, // Rule ID 868 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ffloor:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 868, GIR_Done, // Label 4035: @176512 GIM_Reject, // Label 4027: @176513 GIM_Try, /*On fail goto*//*Label 4036*/ 176539, // Rule ID 864 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ffloor:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 864, GIR_Done, // Label 4036: @176539 GIM_Reject, // Label 4028: @176540 GIM_Reject, // Label 82: @176541 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 4045*/ 176773, /*GILLT_s16*//*Label 4037*/ 176557, /*GILLT_s32*//*Label 4038*/ 176584, /*GILLT_s64*//*Label 4039*/ 176611, 0, /*GILLT_v2s32*//*Label 4040*/ 176638, /*GILLT_v2s64*//*Label 4041*/ 176665, /*GILLT_v4s16*//*Label 4042*/ 176692, /*GILLT_v4s32*//*Label 4043*/ 176719, 0, /*GILLT_v8s16*//*Label 4044*/ 176746, // Label 4037: @176557 GIM_Try, /*On fail goto*//*Label 4046*/ 176583, // Rule ID 539 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (frint:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTXHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 539, GIR_Done, // Label 4046: @176583 GIM_Reject, // Label 4038: @176584 GIM_Try, /*On fail goto*//*Label 4047*/ 176610, // Rule ID 541 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (frint:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTXSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXSr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 541, GIR_Done, // Label 4047: @176610 GIM_Reject, // Label 4039: @176611 GIM_Try, /*On fail goto*//*Label 4048*/ 176637, // Rule ID 543 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (frint:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTXDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 543, GIR_Done, // Label 4048: @176637 GIM_Reject, // Label 4040: @176638 GIM_Try, /*On fail goto*//*Label 4049*/ 176664, // Rule ID 896 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (frint:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 896, GIR_Done, // Label 4049: @176664 GIM_Reject, // Label 4041: @176665 GIM_Try, /*On fail goto*//*Label 4050*/ 176691, // Rule ID 900 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (frint:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 900, GIR_Done, // Label 4050: @176691 GIM_Reject, // Label 4042: @176692 GIM_Try, /*On fail goto*//*Label 4051*/ 176718, // Rule ID 892 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (frint:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 892, GIR_Done, // Label 4051: @176718 GIM_Reject, // Label 4043: @176719 GIM_Try, /*On fail goto*//*Label 4052*/ 176745, // Rule ID 898 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (frint:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 898, GIR_Done, // Label 4052: @176745 GIM_Reject, // Label 4044: @176746 GIM_Try, /*On fail goto*//*Label 4053*/ 176772, // Rule ID 894 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (frint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 894, GIR_Done, // Label 4053: @176772 GIM_Reject, // Label 4045: @176773 GIM_Reject, // Label 83: @176774 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 4062*/ 177006, /*GILLT_s16*//*Label 4054*/ 176790, /*GILLT_s32*//*Label 4055*/ 176817, /*GILLT_s64*//*Label 4056*/ 176844, 0, /*GILLT_v2s32*//*Label 4057*/ 176871, /*GILLT_v2s64*//*Label 4058*/ 176898, /*GILLT_v4s16*//*Label 4059*/ 176925, /*GILLT_v4s32*//*Label 4060*/ 176952, 0, /*GILLT_v8s16*//*Label 4061*/ 176979, // Label 4054: @176790 GIM_Try, /*On fail goto*//*Label 4063*/ 176816, // Rule ID 515 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fnearbyint:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTIHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 515, GIR_Done, // Label 4063: @176816 GIM_Reject, // Label 4055: @176817 GIM_Try, /*On fail goto*//*Label 4064*/ 176843, // Rule ID 517 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fnearbyint:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTISr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTISr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 517, GIR_Done, // Label 4064: @176843 GIM_Reject, // Label 4056: @176844 GIM_Try, /*On fail goto*//*Label 4065*/ 176870, // Rule ID 519 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fnearbyint:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTIDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 519, GIR_Done, // Label 4065: @176870 GIM_Reject, // Label 4057: @176871 GIM_Try, /*On fail goto*//*Label 4066*/ 176897, // Rule ID 856 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fnearbyint:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTIv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 856, GIR_Done, // Label 4066: @176897 GIM_Reject, // Label 4058: @176898 GIM_Try, /*On fail goto*//*Label 4067*/ 176924, // Rule ID 860 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fnearbyint:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTIv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 860, GIR_Done, // Label 4067: @176924 GIM_Reject, // Label 4059: @176925 GIM_Try, /*On fail goto*//*Label 4068*/ 176951, // Rule ID 852 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fnearbyint:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTIv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 852, GIR_Done, // Label 4068: @176951 GIM_Reject, // Label 4060: @176952 GIM_Try, /*On fail goto*//*Label 4069*/ 176978, // Rule ID 858 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fnearbyint:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTIv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 858, GIR_Done, // Label 4069: @176978 GIM_Reject, // Label 4061: @176979 GIM_Try, /*On fail goto*//*Label 4070*/ 177005, // Rule ID 854 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fnearbyint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTIv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 854, GIR_Done, // Label 4070: @177005 GIM_Reject, // Label 4062: @177006 GIM_Reject, // Label 84: @177007 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 4079*/ 177794, /*GILLT_s16*//*Label 4071*/ 177023, /*GILLT_s32*//*Label 4072*/ 177237, /*GILLT_s64*//*Label 4073*/ 177451, 0, /*GILLT_v2s32*//*Label 4074*/ 177619, /*GILLT_v2s64*//*Label 4075*/ 177654, /*GILLT_v4s16*//*Label 4076*/ 177689, /*GILLT_v4s32*//*Label 4077*/ 177724, 0, /*GILLT_v8s16*//*Label 4078*/ 177759, // Label 4071: @177023 GIM_Try, /*On fail goto*//*Label 4080*/ 177236, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_Try, /*On fail goto*//*Label 4081*/ 177125, // Rule ID 10122 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i16p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10122, GIR_Done, // Label 4081: @177125 GIM_Try, /*On fail goto*//*Label 4082*/ 177213, // Rule ID 11798 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i16p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11798, GIR_Done, // Label 4082: @177213 GIM_Try, /*On fail goto*//*Label 4083*/ 177235, // Rule ID 564 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (strict_fadd:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FADDHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDHrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 564, GIR_Done, // Label 4083: @177235 GIM_Reject, // Label 4080: @177236 GIM_Reject, // Label 4072: @177237 GIM_Try, /*On fail goto*//*Label 4084*/ 177450, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_Try, /*On fail goto*//*Label 4085*/ 177339, // Rule ID 10120 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10120, GIR_Done, // Label 4085: @177339 GIM_Try, /*On fail goto*//*Label 4086*/ 177427, // Rule ID 11796 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11796, GIR_Done, // Label 4086: @177427 GIM_Try, /*On fail goto*//*Label 4087*/ 177449, // Rule ID 566 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (strict_fadd:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FADDSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDSrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 566, GIR_Done, // Label 4087: @177449 GIM_Reject, // Label 4084: @177450 GIM_Reject, // Label 4073: @177451 GIM_Try, /*On fail goto*//*Label 4088*/ 177618, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4089*/ 177530, // Rule ID 10118 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10118, GIR_Done, // Label 4089: @177530 GIM_Try, /*On fail goto*//*Label 4090*/ 177595, // Rule ID 11794 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11794, GIR_Done, // Label 4090: @177595 GIM_Try, /*On fail goto*//*Label 4091*/ 177617, // Rule ID 568 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (strict_fadd:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FADDDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 568, GIR_Done, // Label 4091: @177617 GIM_Reject, // Label 4088: @177618 GIM_Reject, // Label 4074: @177619 GIM_Try, /*On fail goto*//*Label 4092*/ 177653, // Rule ID 1165 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (strict_fadd:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1165, GIR_Done, // Label 4092: @177653 GIM_Reject, // Label 4075: @177654 GIM_Try, /*On fail goto*//*Label 4093*/ 177688, // Rule ID 1169 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (strict_fadd:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1169, GIR_Done, // Label 4093: @177688 GIM_Reject, // Label 4076: @177689 GIM_Try, /*On fail goto*//*Label 4094*/ 177723, // Rule ID 1161 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (strict_fadd:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1161, GIR_Done, // Label 4094: @177723 GIM_Reject, // Label 4077: @177724 GIM_Try, /*On fail goto*//*Label 4095*/ 177758, // Rule ID 1167 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (strict_fadd:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1167, GIR_Done, // Label 4095: @177758 GIM_Reject, // Label 4078: @177759 GIM_Try, /*On fail goto*//*Label 4096*/ 177793, // Rule ID 1163 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (strict_fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1163, GIR_Done, // Label 4096: @177793 GIM_Reject, // Label 4079: @177794 GIM_Reject, // Label 85: @177795 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 4105*/ 178091, /*GILLT_s16*//*Label 4097*/ 177811, /*GILLT_s32*//*Label 4098*/ 177846, /*GILLT_s64*//*Label 4099*/ 177881, 0, /*GILLT_v2s32*//*Label 4100*/ 177916, /*GILLT_v2s64*//*Label 4101*/ 177951, /*GILLT_v4s16*//*Label 4102*/ 177986, /*GILLT_v4s32*//*Label 4103*/ 178021, 0, /*GILLT_v8s16*//*Label 4104*/ 178056, // Label 4097: @177811 GIM_Try, /*On fail goto*//*Label 4106*/ 177845, // Rule ID 612 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (strict_fsub:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FSUBHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBHrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 612, GIR_Done, // Label 4106: @177845 GIM_Reject, // Label 4098: @177846 GIM_Try, /*On fail goto*//*Label 4107*/ 177880, // Rule ID 614 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (strict_fsub:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FSUBSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBSrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 614, GIR_Done, // Label 4107: @177880 GIM_Reject, // Label 4099: @177881 GIM_Try, /*On fail goto*//*Label 4108*/ 177915, // Rule ID 616 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (strict_fsub:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FSUBDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 616, GIR_Done, // Label 4108: @177915 GIM_Reject, // Label 4100: @177916 GIM_Try, /*On fail goto*//*Label 4109*/ 177950, // Rule ID 1305 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (strict_fsub:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FSUBv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1305, GIR_Done, // Label 4109: @177950 GIM_Reject, // Label 4101: @177951 GIM_Try, /*On fail goto*//*Label 4110*/ 177985, // Rule ID 1309 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (strict_fsub:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FSUBv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1309, GIR_Done, // Label 4110: @177985 GIM_Reject, // Label 4102: @177986 GIM_Try, /*On fail goto*//*Label 4111*/ 178020, // Rule ID 1301 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (strict_fsub:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FSUBv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1301, GIR_Done, // Label 4111: @178020 GIM_Reject, // Label 4103: @178021 GIM_Try, /*On fail goto*//*Label 4112*/ 178055, // Rule ID 1307 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (strict_fsub:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FSUBv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1307, GIR_Done, // Label 4112: @178055 GIM_Reject, // Label 4104: @178056 GIM_Try, /*On fail goto*//*Label 4113*/ 178090, // Rule ID 1303 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (strict_fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FSUBv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1303, GIR_Done, // Label 4113: @178090 GIM_Reject, // Label 4105: @178091 GIM_Reject, // Label 86: @178092 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 4122*/ 179982, /*GILLT_s16*//*Label 4114*/ 178108, /*GILLT_s32*//*Label 4115*/ 178274, /*GILLT_s64*//*Label 4116*/ 178440, 0, /*GILLT_v2s32*//*Label 4117*/ 178606, /*GILLT_v2s64*//*Label 4118*/ 178954, /*GILLT_v4s16*//*Label 4119*/ 179302, /*GILLT_v4s32*//*Label 4120*/ 179468, 0, /*GILLT_v8s16*//*Label 4121*/ 179816, // Label 4114: @178108 GIM_Try, /*On fail goto*//*Label 4123*/ 178273, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_Try, /*On fail goto*//*Label 4124*/ 178186, // Rule ID 10846 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR16Op:{ *:[f16] }:$Rn) => (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10846, GIR_Done, // Label 4124: @178186 GIM_Try, /*On fail goto*//*Label 4125*/ 178250, // Rule ID 1957 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1957, GIR_Done, // Label 4125: @178250 GIM_Try, /*On fail goto*//*Label 4126*/ 178272, // Rule ID 600 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (strict_fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULHrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 600, GIR_Done, // Label 4126: @178272 GIM_Reject, // Label 4123: @178273 GIM_Reject, // Label 4115: @178274 GIM_Try, /*On fail goto*//*Label 4127*/ 178439, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_Try, /*On fail goto*//*Label 4128*/ 178352, // Rule ID 10848 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32Op:{ *:[f32] }:$Rn) => (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10848, GIR_Done, // Label 4128: @178352 GIM_Try, /*On fail goto*//*Label 4129*/ 178416, // Rule ID 1959 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1959, GIR_Done, // Label 4129: @178416 GIM_Try, /*On fail goto*//*Label 4130*/ 178438, // Rule ID 602 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (strict_fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULSrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 602, GIR_Done, // Label 4130: @178438 GIM_Reject, // Label 4127: @178439 GIM_Reject, // Label 4116: @178440 GIM_Try, /*On fail goto*//*Label 4131*/ 178605, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4132*/ 178518, // Rule ID 10850 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR64Op:{ *:[f64] }:$Rn) => (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10850, GIR_Done, // Label 4132: @178518 GIM_Try, /*On fail goto*//*Label 4133*/ 178582, // Rule ID 1961 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1961, GIR_Done, // Label 4133: @178582 GIM_Try, /*On fail goto*//*Label 4134*/ 178604, // Rule ID 604 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (strict_fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 604, GIR_Done, // Label 4134: @178604 GIM_Reject, // Label 4131: @178605 GIM_Reject, // Label 4117: @178606 GIM_Try, /*On fail goto*//*Label 4135*/ 178953, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4136*/ 178684, // Rule ID 10840 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v2f32] }:$Rn) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10840, GIR_Done, // Label 4136: @178684 GIM_Try, /*On fail goto*//*Label 4137*/ 178748, // Rule ID 1951 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1951, GIR_Done, // Label 4137: @178748 GIM_Try, /*On fail goto*//*Label 4138*/ 178839, // Rule ID 11775 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fmul:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11775, GIR_Done, // Label 4138: @178839 GIM_Try, /*On fail goto*//*Label 4139*/ 178930, // Rule ID 9394 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm)) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9394, GIR_Done, // Label 4139: @178930 GIM_Try, /*On fail goto*//*Label 4140*/ 178952, // Rule ID 1285 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (strict_fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMULv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1285, GIR_Done, // Label 4140: @178952 GIM_Reject, // Label 4135: @178953 GIM_Reject, // Label 4118: @178954 GIM_Try, /*On fail goto*//*Label 4141*/ 179301, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4142*/ 179032, // Rule ID 10844 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v2f64] }:$Rn) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10844, GIR_Done, // Label 4142: @179032 GIM_Try, /*On fail goto*//*Label 4143*/ 179096, // Rule ID 1955 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1955, GIR_Done, // Label 4143: @179096 GIM_Try, /*On fail goto*//*Label 4144*/ 179187, // Rule ID 11779 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fmul:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11779, GIR_Done, // Label 4144: @179187 GIM_Try, /*On fail goto*//*Label 4145*/ 179278, // Rule ID 9398 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm)) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9398, GIR_Done, // Label 4145: @179278 GIM_Try, /*On fail goto*//*Label 4146*/ 179300, // Rule ID 1289 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (strict_fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMULv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1289, GIR_Done, // Label 4146: @179300 GIM_Reject, // Label 4141: @179301 GIM_Reject, // Label 4119: @179302 GIM_Try, /*On fail goto*//*Label 4147*/ 179467, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4148*/ 179380, // Rule ID 10836 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v4f16] }:$Rn) => (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10836, GIR_Done, // Label 4148: @179380 GIM_Try, /*On fail goto*//*Label 4149*/ 179444, // Rule ID 1947 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1947, GIR_Done, // Label 4149: @179444 GIM_Try, /*On fail goto*//*Label 4150*/ 179466, // Rule ID 1281 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (strict_fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMULv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1281, GIR_Done, // Label 4150: @179466 GIM_Reject, // Label 4147: @179467 GIM_Reject, // Label 4120: @179468 GIM_Try, /*On fail goto*//*Label 4151*/ 179815, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4152*/ 179546, // Rule ID 10842 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v4f32] }:$Rn) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10842, GIR_Done, // Label 4152: @179546 GIM_Try, /*On fail goto*//*Label 4153*/ 179610, // Rule ID 1953 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1953, GIR_Done, // Label 4153: @179610 GIM_Try, /*On fail goto*//*Label 4154*/ 179701, // Rule ID 11777 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fmul:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11777, GIR_Done, // Label 4154: @179701 GIM_Try, /*On fail goto*//*Label 4155*/ 179792, // Rule ID 9396 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm)) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9396, GIR_Done, // Label 4155: @179792 GIM_Try, /*On fail goto*//*Label 4156*/ 179814, // Rule ID 1287 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (strict_fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMULv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1287, GIR_Done, // Label 4156: @179814 GIM_Reject, // Label 4151: @179815 GIM_Reject, // Label 4121: @179816 GIM_Try, /*On fail goto*//*Label 4157*/ 179981, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4158*/ 179894, // Rule ID 10838 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v8f16] }:$Rn) => (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10838, GIR_Done, // Label 4158: @179894 GIM_Try, /*On fail goto*//*Label 4159*/ 179958, // Rule ID 1949 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1949, GIR_Done, // Label 4159: @179958 GIM_Try, /*On fail goto*//*Label 4160*/ 179980, // Rule ID 1283 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (strict_fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMULv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1283, GIR_Done, // Label 4160: @179980 GIM_Reject, // Label 4157: @179981 GIM_Reject, // Label 4122: @179982 GIM_Reject, // Label 87: @179983 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 4169*/ 180279, /*GILLT_s16*//*Label 4161*/ 179999, /*GILLT_s32*//*Label 4162*/ 180034, /*GILLT_s64*//*Label 4163*/ 180069, 0, /*GILLT_v2s32*//*Label 4164*/ 180104, /*GILLT_v2s64*//*Label 4165*/ 180139, /*GILLT_v4s16*//*Label 4166*/ 180174, /*GILLT_v4s32*//*Label 4167*/ 180209, 0, /*GILLT_v8s16*//*Label 4168*/ 180244, // Label 4161: @179999 GIM_Try, /*On fail goto*//*Label 4170*/ 180033, // Rule ID 570 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (strict_fdiv:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FDIVHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVHrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 570, GIR_Done, // Label 4170: @180033 GIM_Reject, // Label 4162: @180034 GIM_Try, /*On fail goto*//*Label 4171*/ 180068, // Rule ID 572 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (strict_fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FDIVSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVSrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 572, GIR_Done, // Label 4171: @180068 GIM_Reject, // Label 4163: @180069 GIM_Try, /*On fail goto*//*Label 4172*/ 180103, // Rule ID 574 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (strict_fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FDIVDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVDrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 574, GIR_Done, // Label 4172: @180103 GIM_Reject, // Label 4164: @180104 GIM_Try, /*On fail goto*//*Label 4173*/ 180138, // Rule ID 1190 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (strict_fdiv:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FDIVv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1190, GIR_Done, // Label 4173: @180138 GIM_Reject, // Label 4165: @180139 GIM_Try, /*On fail goto*//*Label 4174*/ 180173, // Rule ID 1194 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (strict_fdiv:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FDIVv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1194, GIR_Done, // Label 4174: @180173 GIM_Reject, // Label 4166: @180174 GIM_Try, /*On fail goto*//*Label 4175*/ 180208, // Rule ID 1186 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (strict_fdiv:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FDIVv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1186, GIR_Done, // Label 4175: @180208 GIM_Reject, // Label 4167: @180209 GIM_Try, /*On fail goto*//*Label 4176*/ 180243, // Rule ID 1192 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (strict_fdiv:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FDIVv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1192, GIR_Done, // Label 4176: @180243 GIM_Reject, // Label 4168: @180244 GIM_Try, /*On fail goto*//*Label 4177*/ 180278, // Rule ID 1188 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (strict_fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FDIVv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1188, GIR_Done, // Label 4177: @180278 GIM_Reject, // Label 4169: @180279 GIM_Reject, // Label 88: @180280 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 4186*/ 189793, /*GILLT_s16*//*Label 4178*/ 180296, /*GILLT_s32*//*Label 4179*/ 180985, /*GILLT_s64*//*Label 4180*/ 181840, 0, /*GILLT_v2s32*//*Label 4181*/ 182695, /*GILLT_v2s64*//*Label 4182*/ 184257, /*GILLT_v4s16*//*Label 4183*/ 185819, /*GILLT_v4s32*//*Label 4184*/ 187025, 0, /*GILLT_v8s16*//*Label 4185*/ 188587, // Label 4178: @180296 GIM_Try, /*On fail goto*//*Label 4187*/ 180984, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_Try, /*On fail goto*//*Label 4188*/ 180399, // Rule ID 9280 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9280, GIR_Done, // Label 4188: @180399 GIM_Try, /*On fail goto*//*Label 4189*/ 180484, // Rule ID 9306 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9306, GIR_Done, // Label 4189: @180484 GIM_Try, /*On fail goto*//*Label 4190*/ 180569, // Rule ID 9332 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9332, GIR_Done, // Label 4190: @180569 GIM_Try, /*On fail goto*//*Label 4191*/ 180654, // Rule ID 9254 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9254, GIR_Done, // Label 4191: @180654 GIM_Try, /*On fail goto*//*Label 4192*/ 180726, // Rule ID 6839 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd) => (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6839, GIR_Done, // Label 4192: @180726 GIM_Try, /*On fail goto*//*Label 4193*/ 180798, // Rule ID 9228 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR16:{ *:[f16] }:$Rd) => (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9228, GIR_Done, // Label 4193: @180798 GIM_Try, /*On fail goto*//*Label 4194*/ 180851, // Rule ID 10692 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10692, GIR_Done, // Label 4194: @180851 GIM_Try, /*On fail goto*//*Label 4195*/ 180904, // Rule ID 624 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 624, GIR_Done, // Label 4195: @180904 GIM_Try, /*On fail goto*//*Label 4196*/ 180957, // Rule ID 636 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 636, GIR_Done, // Label 4196: @180957 GIM_Try, /*On fail goto*//*Label 4197*/ 180983, // Rule ID 618 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) => (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMADDHrrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 618, GIR_Done, // Label 4197: @180983 GIM_Reject, // Label 4187: @180984 GIM_Reject, // Label 4179: @180985 GIM_Try, /*On fail goto*//*Label 4198*/ 181839, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_Try, /*On fail goto*//*Label 4199*/ 181086, // Rule ID 9366 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9366, GIR_Done, // Label 4199: @181086 GIM_Try, /*On fail goto*//*Label 4200*/ 181171, // Rule ID 9294 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9294, GIR_Done, // Label 4200: @181171 GIM_Try, /*On fail goto*//*Label 4201*/ 181256, // Rule ID 9320 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9320, GIR_Done, // Label 4201: @181256 GIM_Try, /*On fail goto*//*Label 4202*/ 181341, // Rule ID 9346 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9346, GIR_Done, // Label 4202: @181341 GIM_Try, /*On fail goto*//*Label 4203*/ 181424, // Rule ID 9388 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9388, GIR_Done, // Label 4203: @181424 GIM_Try, /*On fail goto*//*Label 4204*/ 181509, // Rule ID 9268 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9268, GIR_Done, // Label 4204: @181509 GIM_Try, /*On fail goto*//*Label 4205*/ 181581, // Rule ID 6853 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6853, GIR_Done, // Label 4205: @181581 GIM_Try, /*On fail goto*//*Label 4206*/ 181653, // Rule ID 9242 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9242, GIR_Done, // Label 4206: @181653 GIM_Try, /*On fail goto*//*Label 4207*/ 181706, // Rule ID 10694 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10694, GIR_Done, // Label 4207: @181706 GIM_Try, /*On fail goto*//*Label 4208*/ 181759, // Rule ID 626 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 626, GIR_Done, // Label 4208: @181759 GIM_Try, /*On fail goto*//*Label 4209*/ 181812, // Rule ID 638 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 638, GIR_Done, // Label 4209: @181812 GIM_Try, /*On fail goto*//*Label 4210*/ 181838, // Rule ID 620 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) => (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMADDSrrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 620, GIR_Done, // Label 4210: @181838 GIM_Reject, // Label 4198: @181839 GIM_Reject, // Label 4180: @181840 GIM_Try, /*On fail goto*//*Label 4211*/ 182694, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4212*/ 181941, // Rule ID 9370 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9370, GIR_Done, // Label 4212: @181941 GIM_Try, /*On fail goto*//*Label 4213*/ 182026, // Rule ID 9296 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9296, GIR_Done, // Label 4213: @182026 GIM_Try, /*On fail goto*//*Label 4214*/ 182111, // Rule ID 9322 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9322, GIR_Done, // Label 4214: @182111 GIM_Try, /*On fail goto*//*Label 4215*/ 182196, // Rule ID 9348 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9348, GIR_Done, // Label 4215: @182196 GIM_Try, /*On fail goto*//*Label 4216*/ 182279, // Rule ID 9392 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9392, GIR_Done, // Label 4216: @182279 GIM_Try, /*On fail goto*//*Label 4217*/ 182364, // Rule ID 9270 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9270, GIR_Done, // Label 4217: @182364 GIM_Try, /*On fail goto*//*Label 4218*/ 182436, // Rule ID 6855 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6855, GIR_Done, // Label 4218: @182436 GIM_Try, /*On fail goto*//*Label 4219*/ 182508, // Rule ID 9244 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9244, GIR_Done, // Label 4219: @182508 GIM_Try, /*On fail goto*//*Label 4220*/ 182561, // Rule ID 10696 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10696, GIR_Done, // Label 4220: @182561 GIM_Try, /*On fail goto*//*Label 4221*/ 182614, // Rule ID 628 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 628, GIR_Done, // Label 4221: @182614 GIM_Try, /*On fail goto*//*Label 4222*/ 182667, // Rule ID 640 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 640, GIR_Done, // Label 4222: @182667 GIM_Try, /*On fail goto*//*Label 4223*/ 182693, // Rule ID 622 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) => (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMADDDrrr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 622, GIR_Done, // Label 4223: @182693 GIM_Reject, // Label 4211: @182694 GIM_Reject, // Label 4181: @182695 GIM_Try, /*On fail goto*//*Label 4224*/ 184256, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4225*/ 182796, // Rule ID 9350 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9350, GIR_Done, // Label 4225: @182796 GIM_Try, /*On fail goto*//*Label 4226*/ 182881, // Rule ID 9282 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9282, GIR_Done, // Label 4226: @182881 GIM_Try, /*On fail goto*//*Label 4227*/ 182966, // Rule ID 9308 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9308, GIR_Done, // Label 4227: @182966 GIM_Try, /*On fail goto*//*Label 4228*/ 183051, // Rule ID 9334 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9334, GIR_Done, // Label 4228: @183051 GIM_Try, /*On fail goto*//*Label 4229*/ 183134, // Rule ID 9372 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<>:$idx), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9372, GIR_Done, // Label 4229: @183134 GIM_Try, /*On fail goto*//*Label 4230*/ 183219, // Rule ID 9256 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9256, GIR_Done, // Label 4230: @183219 GIM_Try, /*On fail goto*//*Label 4231*/ 183291, // Rule ID 6841 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6841, GIR_Done, // Label 4231: @183291 GIM_Try, /*On fail goto*//*Label 4232*/ 183363, // Rule ID 9230 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9230, GIR_Done, // Label 4232: @183363 GIM_Try, /*On fail goto*//*Label 4233*/ 183458, // Rule ID 9354 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9354, GIR_Done, // Label 4233: @183458 GIM_Try, /*On fail goto*//*Label 4234*/ 183555, // Rule ID 9284 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9284, GIR_Done, // Label 4234: @183555 GIM_Try, /*On fail goto*//*Label 4235*/ 183652, // Rule ID 9310 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9310, GIR_Done, // Label 4235: @183652 GIM_Try, /*On fail goto*//*Label 4236*/ 183749, // Rule ID 9336 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9336, GIR_Done, // Label 4236: @183749 GIM_Try, /*On fail goto*//*Label 4237*/ 183844, // Rule ID 9376 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9376, GIR_Done, // Label 4237: @183844 GIM_Try, /*On fail goto*//*Label 4238*/ 183941, // Rule ID 9258 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9258, GIR_Done, // Label 4238: @183941 GIM_Try, /*On fail goto*//*Label 4239*/ 184025, // Rule ID 6843 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6843, GIR_Done, // Label 4239: @184025 GIM_Try, /*On fail goto*//*Label 4240*/ 184078, // Rule ID 10726 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10726, GIR_Done, // Label 4240: @184078 GIM_Try, /*On fail goto*//*Label 4241*/ 184162, // Rule ID 9232 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9232, GIR_Done, // Label 4241: @184162 GIM_Try, /*On fail goto*//*Label 4242*/ 184215, // Rule ID 1270 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1270, GIR_Done, // Label 4242: @184215 GIM_Try, /*On fail goto*//*Label 4243*/ 184255, // Rule ID 1260 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1260, GIR_Done, // Label 4243: @184255 GIM_Reject, // Label 4224: @184256 GIM_Reject, // Label 4182: @184257 GIM_Try, /*On fail goto*//*Label 4244*/ 185818, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4245*/ 184358, // Rule ID 9362 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9362, GIR_Done, // Label 4245: @184358 GIM_Try, /*On fail goto*//*Label 4246*/ 184443, // Rule ID 9290 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9290, GIR_Done, // Label 4246: @184443 GIM_Try, /*On fail goto*//*Label 4247*/ 184528, // Rule ID 9316 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9316, GIR_Done, // Label 4247: @184528 GIM_Try, /*On fail goto*//*Label 4248*/ 184613, // Rule ID 9342 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9342, GIR_Done, // Label 4248: @184613 GIM_Try, /*On fail goto*//*Label 4249*/ 184696, // Rule ID 9384 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<>:$idx), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9384, GIR_Done, // Label 4249: @184696 GIM_Try, /*On fail goto*//*Label 4250*/ 184781, // Rule ID 9264 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9264, GIR_Done, // Label 4250: @184781 GIM_Try, /*On fail goto*//*Label 4251*/ 184853, // Rule ID 6849 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6849, GIR_Done, // Label 4251: @184853 GIM_Try, /*On fail goto*//*Label 4252*/ 184925, // Rule ID 9238 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9238, GIR_Done, // Label 4252: @184925 GIM_Try, /*On fail goto*//*Label 4253*/ 185020, // Rule ID 9364 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9364, GIR_Done, // Label 4253: @185020 GIM_Try, /*On fail goto*//*Label 4254*/ 185117, // Rule ID 9292 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9292, GIR_Done, // Label 4254: @185117 GIM_Try, /*On fail goto*//*Label 4255*/ 185214, // Rule ID 9318 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9318, GIR_Done, // Label 4255: @185214 GIM_Try, /*On fail goto*//*Label 4256*/ 185311, // Rule ID 9344 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9344, GIR_Done, // Label 4256: @185311 GIM_Try, /*On fail goto*//*Label 4257*/ 185406, // Rule ID 9386 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9386, GIR_Done, // Label 4257: @185406 GIM_Try, /*On fail goto*//*Label 4258*/ 185503, // Rule ID 9266 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9266, GIR_Done, // Label 4258: @185503 GIM_Try, /*On fail goto*//*Label 4259*/ 185587, // Rule ID 6851 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6851, GIR_Done, // Label 4259: @185587 GIM_Try, /*On fail goto*//*Label 4260*/ 185640, // Rule ID 10730 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10730, GIR_Done, // Label 4260: @185640 GIM_Try, /*On fail goto*//*Label 4261*/ 185724, // Rule ID 9240 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9240, GIR_Done, // Label 4261: @185724 GIM_Try, /*On fail goto*//*Label 4262*/ 185777, // Rule ID 1274 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1274, GIR_Done, // Label 4262: @185777 GIM_Try, /*On fail goto*//*Label 4263*/ 185817, // Rule ID 1264 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1264, GIR_Done, // Label 4263: @185817 GIM_Reject, // Label 4244: @185818 GIM_Reject, // Label 4183: @185819 GIM_Try, /*On fail goto*//*Label 4264*/ 187024, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4265*/ 185922, // Rule ID 9276 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9276, GIR_Done, // Label 4265: @185922 GIM_Try, /*On fail goto*//*Label 4266*/ 186007, // Rule ID 9302 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9302, GIR_Done, // Label 4266: @186007 GIM_Try, /*On fail goto*//*Label 4267*/ 186092, // Rule ID 9328 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9328, GIR_Done, // Label 4267: @186092 GIM_Try, /*On fail goto*//*Label 4268*/ 186177, // Rule ID 9250 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9250, GIR_Done, // Label 4268: @186177 GIM_Try, /*On fail goto*//*Label 4269*/ 186249, // Rule ID 6835 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6835, GIR_Done, // Label 4269: @186249 GIM_Try, /*On fail goto*//*Label 4270*/ 186321, // Rule ID 9224 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9224, GIR_Done, // Label 4270: @186321 GIM_Try, /*On fail goto*//*Label 4271*/ 186418, // Rule ID 9278 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9278, GIR_Done, // Label 4271: @186418 GIM_Try, /*On fail goto*//*Label 4272*/ 186515, // Rule ID 9304 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9304, GIR_Done, // Label 4272: @186515 GIM_Try, /*On fail goto*//*Label 4273*/ 186612, // Rule ID 9330 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9330, GIR_Done, // Label 4273: @186612 GIM_Try, /*On fail goto*//*Label 4274*/ 186709, // Rule ID 9252 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9252, GIR_Done, // Label 4274: @186709 GIM_Try, /*On fail goto*//*Label 4275*/ 186793, // Rule ID 6837 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6837, GIR_Done, // Label 4275: @186793 GIM_Try, /*On fail goto*//*Label 4276*/ 186846, // Rule ID 10722 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10722, GIR_Done, // Label 4276: @186846 GIM_Try, /*On fail goto*//*Label 4277*/ 186930, // Rule ID 9226 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9226, GIR_Done, // Label 4277: @186930 GIM_Try, /*On fail goto*//*Label 4278*/ 186983, // Rule ID 1266 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1266, GIR_Done, // Label 4278: @186983 GIM_Try, /*On fail goto*//*Label 4279*/ 187023, // Rule ID 1256 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1256, GIR_Done, // Label 4279: @187023 GIM_Reject, // Label 4264: @187024 GIM_Reject, // Label 4184: @187025 GIM_Try, /*On fail goto*//*Label 4280*/ 188586, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4281*/ 187126, // Rule ID 9356 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9356, GIR_Done, // Label 4281: @187126 GIM_Try, /*On fail goto*//*Label 4282*/ 187211, // Rule ID 9286 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9286, GIR_Done, // Label 4282: @187211 GIM_Try, /*On fail goto*//*Label 4283*/ 187296, // Rule ID 9312 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9312, GIR_Done, // Label 4283: @187296 GIM_Try, /*On fail goto*//*Label 4284*/ 187381, // Rule ID 9338 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9338, GIR_Done, // Label 4284: @187381 GIM_Try, /*On fail goto*//*Label 4285*/ 187464, // Rule ID 9378 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<>:$idx), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9378, GIR_Done, // Label 4285: @187464 GIM_Try, /*On fail goto*//*Label 4286*/ 187549, // Rule ID 9260 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9260, GIR_Done, // Label 4286: @187549 GIM_Try, /*On fail goto*//*Label 4287*/ 187621, // Rule ID 6845 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6845, GIR_Done, // Label 4287: @187621 GIM_Try, /*On fail goto*//*Label 4288*/ 187693, // Rule ID 9234 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9234, GIR_Done, // Label 4288: @187693 GIM_Try, /*On fail goto*//*Label 4289*/ 187788, // Rule ID 9360 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9360, GIR_Done, // Label 4289: @187788 GIM_Try, /*On fail goto*//*Label 4290*/ 187885, // Rule ID 9288 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9288, GIR_Done, // Label 4290: @187885 GIM_Try, /*On fail goto*//*Label 4291*/ 187982, // Rule ID 9314 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9314, GIR_Done, // Label 4291: @187982 GIM_Try, /*On fail goto*//*Label 4292*/ 188079, // Rule ID 9340 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9340, GIR_Done, // Label 4292: @188079 GIM_Try, /*On fail goto*//*Label 4293*/ 188174, // Rule ID 9382 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9382, GIR_Done, // Label 4293: @188174 GIM_Try, /*On fail goto*//*Label 4294*/ 188271, // Rule ID 9262 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9262, GIR_Done, // Label 4294: @188271 GIM_Try, /*On fail goto*//*Label 4295*/ 188355, // Rule ID 6847 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6847, GIR_Done, // Label 4295: @188355 GIM_Try, /*On fail goto*//*Label 4296*/ 188408, // Rule ID 10728 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10728, GIR_Done, // Label 4296: @188408 GIM_Try, /*On fail goto*//*Label 4297*/ 188492, // Rule ID 9236 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9236, GIR_Done, // Label 4297: @188492 GIM_Try, /*On fail goto*//*Label 4298*/ 188545, // Rule ID 1272 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1272, GIR_Done, // Label 4298: @188545 GIM_Try, /*On fail goto*//*Label 4299*/ 188585, // Rule ID 1262 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1262, GIR_Done, // Label 4299: @188585 GIM_Reject, // Label 4280: @188586 GIM_Reject, // Label 4185: @188587 GIM_Try, /*On fail goto*//*Label 4300*/ 189792, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4301*/ 188690, // Rule ID 9272 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9272, GIR_Done, // Label 4301: @188690 GIM_Try, /*On fail goto*//*Label 4302*/ 188775, // Rule ID 9298 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9298, GIR_Done, // Label 4302: @188775 GIM_Try, /*On fail goto*//*Label 4303*/ 188860, // Rule ID 9324 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9324, GIR_Done, // Label 4303: @188860 GIM_Try, /*On fail goto*//*Label 4304*/ 188945, // Rule ID 9246 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9246, GIR_Done, // Label 4304: @188945 GIM_Try, /*On fail goto*//*Label 4305*/ 189017, // Rule ID 6831 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6831, GIR_Done, // Label 4305: @189017 GIM_Try, /*On fail goto*//*Label 4306*/ 189089, // Rule ID 9220 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9220, GIR_Done, // Label 4306: @189089 GIM_Try, /*On fail goto*//*Label 4307*/ 189186, // Rule ID 9274 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9274, GIR_Done, // Label 4307: @189186 GIM_Try, /*On fail goto*//*Label 4308*/ 189283, // Rule ID 9300 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9300, GIR_Done, // Label 4308: @189283 GIM_Try, /*On fail goto*//*Label 4309*/ 189380, // Rule ID 9326 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9326, GIR_Done, // Label 4309: @189380 GIM_Try, /*On fail goto*//*Label 4310*/ 189477, // Rule ID 9248 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9248, GIR_Done, // Label 4310: @189477 GIM_Try, /*On fail goto*//*Label 4311*/ 189561, // Rule ID 6833 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6833, GIR_Done, // Label 4311: @189561 GIM_Try, /*On fail goto*//*Label 4312*/ 189614, // Rule ID 10724 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10724, GIR_Done, // Label 4312: @189614 GIM_Try, /*On fail goto*//*Label 4313*/ 189698, // Rule ID 9222 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9222, GIR_Done, // Label 4313: @189698 GIM_Try, /*On fail goto*//*Label 4314*/ 189751, // Rule ID 1268 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1268, GIR_Done, // Label 4314: @189751 GIM_Try, /*On fail goto*//*Label 4315*/ 189791, // Rule ID 1258 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1258, GIR_Done, // Label 4315: @189791 GIM_Reject, // Label 4300: @189792 GIM_Reject, // Label 4186: @189793 GIM_Reject, // Label 89: @189794 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 4324*/ 190026, /*GILLT_s16*//*Label 4316*/ 189810, /*GILLT_s32*//*Label 4317*/ 189837, /*GILLT_s64*//*Label 4318*/ 189864, 0, /*GILLT_v2s32*//*Label 4319*/ 189891, /*GILLT_v2s64*//*Label 4320*/ 189918, /*GILLT_v4s16*//*Label 4321*/ 189945, /*GILLT_v4s32*//*Label 4322*/ 189972, 0, /*GILLT_v8s16*//*Label 4323*/ 189999, // Label 4316: @189810 GIM_Try, /*On fail goto*//*Label 4325*/ 189836, // Rule ID 550 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (strict_fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FSQRTHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTHr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 550, GIR_Done, // Label 4325: @189836 GIM_Reject, // Label 4317: @189837 GIM_Try, /*On fail goto*//*Label 4326*/ 189863, // Rule ID 552 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (strict_fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FSQRTSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTSr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 552, GIR_Done, // Label 4326: @189863 GIM_Reject, // Label 4318: @189864 GIM_Try, /*On fail goto*//*Label 4327*/ 189890, // Rule ID 554 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (strict_fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FSQRTDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTDr, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 554, GIR_Done, // Label 4327: @189890 GIM_Reject, // Label 4319: @189891 GIM_Try, /*On fail goto*//*Label 4328*/ 189917, // Rule ID 932 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (strict_fsqrt:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FSQRTv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 932, GIR_Done, // Label 4328: @189917 GIM_Reject, // Label 4320: @189918 GIM_Try, /*On fail goto*//*Label 4329*/ 189944, // Rule ID 936 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (strict_fsqrt:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FSQRTv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 936, GIR_Done, // Label 4329: @189944 GIM_Reject, // Label 4321: @189945 GIM_Try, /*On fail goto*//*Label 4330*/ 189971, // Rule ID 928 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (strict_fsqrt:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FSQRTv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 928, GIR_Done, // Label 4330: @189971 GIM_Reject, // Label 4322: @189972 GIM_Try, /*On fail goto*//*Label 4331*/ 189998, // Rule ID 934 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (strict_fsqrt:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FSQRTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 934, GIR_Done, // Label 4331: @189998 GIM_Reject, // Label 4323: @189999 GIM_Try, /*On fail goto*//*Label 4332*/ 190025, // Rule ID 930 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (strict_fsqrt:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FSQRTv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 930, GIR_Done, // Label 4332: @190025 GIM_Reject, // Label 4324: @190026 GIM_Reject, // Label 90: @190027 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 11, /*)*//*default:*//*Label 4341*/ 190362, /*GILLT_s64*//*Label 4333*/ 190042, 0, /*GILLT_v2s32*//*Label 4334*/ 190082, /*GILLT_v2s64*//*Label 4335*/ 190122, /*GILLT_v4s16*//*Label 4336*/ 190162, /*GILLT_v4s32*//*Label 4337*/ 190202, /*GILLT_v8s8*//*Label 4338*/ 190242, /*GILLT_v8s16*//*Label 4339*/ 190282, /*GILLT_v16s8*//*Label 4340*/ 190322, // Label 4333: @190042 GIM_Try, /*On fail goto*//*Label 4342*/ 190081, // Rule ID 8667 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (AArch64bit:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) => (BITv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::BITv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8667, GIR_Done, // Label 4342: @190081 GIM_Reject, // Label 4334: @190082 GIM_Try, /*On fail goto*//*Label 4343*/ 190121, // Rule ID 8666 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (AArch64bit:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) => (BITv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::BITv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8666, GIR_Done, // Label 4343: @190121 GIM_Reject, // Label 4335: @190122 GIM_Try, /*On fail goto*//*Label 4344*/ 190161, // Rule ID 8670 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (AArch64bit:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) => (BITv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::BITv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8670, GIR_Done, // Label 4344: @190161 GIM_Reject, // Label 4336: @190162 GIM_Try, /*On fail goto*//*Label 4345*/ 190201, // Rule ID 8665 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (AArch64bit:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) => (BITv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::BITv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8665, GIR_Done, // Label 4345: @190201 GIM_Reject, // Label 4337: @190202 GIM_Try, /*On fail goto*//*Label 4346*/ 190241, // Rule ID 8669 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (AArch64bit:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) => (BITv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::BITv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8669, GIR_Done, // Label 4346: @190241 GIM_Reject, // Label 4338: @190242 GIM_Try, /*On fail goto*//*Label 4347*/ 190281, // Rule ID 1570 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (AArch64bit:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (BITv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::BITv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1570, GIR_Done, // Label 4347: @190281 GIM_Reject, // Label 4339: @190282 GIM_Try, /*On fail goto*//*Label 4348*/ 190321, // Rule ID 8668 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (AArch64bit:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) => (BITv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::BITv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8668, GIR_Done, // Label 4348: @190321 GIM_Reject, // Label 4340: @190322 GIM_Try, /*On fail goto*//*Label 4349*/ 190361, // Rule ID 1571 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (AArch64bit:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (BITv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::BITv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1571, GIR_Done, // Label 4349: @190361 GIM_Reject, // Label 4341: @190362 GIM_Reject, // Label 91: @190363 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 11, /*)*//*default:*//*Label 4358*/ 191941, /*GILLT_s64*//*Label 4350*/ 190378, 0, /*GILLT_v2s32*//*Label 4351*/ 190514, /*GILLT_v2s64*//*Label 4352*/ 190705, /*GILLT_v4s16*//*Label 4353*/ 190896, /*GILLT_v4s32*//*Label 4354*/ 191245, /*GILLT_v8s8*//*Label 4355*/ 191436, /*GILLT_v8s16*//*Label 4356*/ 191514, /*GILLT_v16s8*//*Label 4357*/ 191863, // Label 4350: @190378 GIM_Try, /*On fail goto*//*Label 4359*/ 190513, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4360*/ 190435, // Rule ID 9538 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v1i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<><>) => (LD1Rv1d:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv1d, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9538, GIR_Done, // Label 4360: @190435 GIM_Try, /*On fail goto*//*Label 4361*/ 190482, // Rule ID 9542 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v1f64] } (ld:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn)<><>) => (LD1Rv1d:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv1d, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9542, GIR_Done, // Label 4361: @190482 GIM_Try, /*On fail goto*//*Label 4362*/ 190497, // Rule ID 8943 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (AArch64dup:{ *:[v1i64] } GPR64:{ *:[i64] }:$Rn) => (COPY_TO_REGCLASS:{ *:[v1i64] } GPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 8943, GIR_Done, // Label 4362: @190497 GIM_Try, /*On fail goto*//*Label 4363*/ 190512, // Rule ID 8944 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64dup:{ *:[v1f64] } FPR64:{ *:[f64] }:$Rn) => (COPY_TO_REGCLASS:{ *:[v1f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, // GIR_Coverage, 8944, GIR_Done, // Label 4363: @190512 GIM_Reject, // Label 4359: @190513 GIM_Reject, // Label 4351: @190514 GIM_Try, /*On fail goto*//*Label 4364*/ 190704, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4365*/ 190571, // Rule ID 9535 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v2i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<><>) => (LD1Rv2s:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv2s, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9535, GIR_Done, // Label 4365: @190571 GIM_Try, /*On fail goto*//*Label 4366*/ 190618, // Rule ID 9539 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v2f32] } (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<><>) => (LD1Rv2s:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv2s, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9539, GIR_Done, // Label 4366: @190618 GIM_Try, /*On fail goto*//*Label 4367*/ 190633, // Rule ID 1880 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (AArch64dup:{ *:[v2i32] } GPR32:{ *:[i32] }:$Rn) => (DUPv2i32gpr:{ *:[v2i32] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::DUPv2i32gpr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1880, GIR_Done, // Label 4367: @190633 GIM_Try, /*On fail goto*//*Label 4368*/ 190703, // Rule ID 8945 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rn) => (DUPv2i32lane:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rn, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv2i32lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8945, GIR_Done, // Label 4368: @190703 GIM_Reject, // Label 4364: @190704 GIM_Reject, // Label 4352: @190705 GIM_Try, /*On fail goto*//*Label 4369*/ 190895, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4370*/ 190762, // Rule ID 9537 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v2i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<><>) => (LD1Rv2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv2d, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9537, GIR_Done, // Label 4370: @190762 GIM_Try, /*On fail goto*//*Label 4371*/ 190809, // Rule ID 9541 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v2f64] } (ld:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn)<><>) => (LD1Rv2d:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv2d, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9541, GIR_Done, // Label 4371: @190809 GIM_Try, /*On fail goto*//*Label 4372*/ 190824, // Rule ID 1882 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (AArch64dup:{ *:[v2i64] } GPR64:{ *:[i64] }:$Rn) => (DUPv2i64gpr:{ *:[v2i64] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::DUPv2i64gpr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1882, GIR_Done, // Label 4372: @190824 GIM_Try, /*On fail goto*//*Label 4373*/ 190894, // Rule ID 8947 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rn) => (DUPv2i64lane:{ *:[v2f64] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv2i64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8947, GIR_Done, // Label 4373: @190894 GIM_Reject, // Label 4369: @190895 GIM_Reject, // Label 4353: @190896 GIM_Try, /*On fail goto*//*Label 4374*/ 190951, // Rule ID 9543 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v4f16] } (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<><>) => (LD1Rv4h:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv4h, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9543, GIR_Done, // Label 4374: @190951 GIM_Try, /*On fail goto*//*Label 4375*/ 191006, // Rule ID 9545 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v4bf16] } (ld:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn)<><>) => (LD1Rv4h:{ *:[v4bf16] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv4h, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9545, GIR_Done, // Label 4375: @191006 GIM_Try, /*On fail goto*//*Label 4376*/ 191065, // Rule ID 9533 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v4i16] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<><><>) => (LD1Rv4h:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv4h, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9533, GIR_Done, // Label 4376: @191065 GIM_Try, /*On fail goto*//*Label 4377*/ 191088, // Rule ID 1878 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (AArch64dup:{ *:[v4i16] } GPR32:{ *:[i32] }:$Rn) => (DUPv4i16gpr:{ *:[v4i16] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::DUPv4i16gpr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1878, GIR_Done, // Label 4377: @191088 GIM_Try, /*On fail goto*//*Label 4378*/ 191166, // Rule ID 8948 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (AArch64dup:{ *:[v4f16] } FPR16:{ *:[f16] }:$Rn) => (DUPv4i16lane:{ *:[v4f16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i16lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8948, GIR_Done, // Label 4378: @191166 GIM_Try, /*On fail goto*//*Label 4379*/ 191244, // Rule ID 8949 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (AArch64dup:{ *:[v4bf16] } FPR16:{ *:[bf16] }:$Rn) => (DUPv4i16lane:{ *:[v4bf16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[bf16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i16lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8949, GIR_Done, // Label 4379: @191244 GIM_Reject, // Label 4354: @191245 GIM_Try, /*On fail goto*//*Label 4380*/ 191435, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4381*/ 191302, // Rule ID 9536 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v4i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<><>) => (LD1Rv4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv4s, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9536, GIR_Done, // Label 4381: @191302 GIM_Try, /*On fail goto*//*Label 4382*/ 191349, // Rule ID 9540 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v4f32] } (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<><>) => (LD1Rv4s:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv4s, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9540, GIR_Done, // Label 4382: @191349 GIM_Try, /*On fail goto*//*Label 4383*/ 191364, // Rule ID 1881 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (AArch64dup:{ *:[v4i32] } GPR32:{ *:[i32] }:$Rn) => (DUPv4i32gpr:{ *:[v4i32] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::DUPv4i32gpr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1881, GIR_Done, // Label 4383: @191364 GIM_Try, /*On fail goto*//*Label 4384*/ 191434, // Rule ID 8946 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rn) => (DUPv4i32lane:{ *:[v4f32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rn, ssub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i32lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8946, GIR_Done, // Label 4384: @191434 GIM_Reject, // Label 4380: @191435 GIM_Reject, // Label 4355: @191436 GIM_Try, /*On fail goto*//*Label 4385*/ 191513, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4386*/ 191497, // Rule ID 9531 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v8i8] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<><><>) => (LD1Rv8b:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv8b, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9531, GIR_Done, // Label 4386: @191497 GIM_Try, /*On fail goto*//*Label 4387*/ 191512, // Rule ID 1876 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (AArch64dup:{ *:[v8i8] } GPR32:{ *:[i32] }:$Rn) => (DUPv8i8gpr:{ *:[v8i8] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::DUPv8i8gpr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1876, GIR_Done, // Label 4387: @191512 GIM_Reject, // Label 4385: @191513 GIM_Reject, // Label 4356: @191514 GIM_Try, /*On fail goto*//*Label 4388*/ 191569, // Rule ID 9544 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v8f16] } (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<><>) => (LD1Rv8h:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv8h, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9544, GIR_Done, // Label 4388: @191569 GIM_Try, /*On fail goto*//*Label 4389*/ 191624, // Rule ID 9546 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v8bf16] } (ld:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn)<><>) => (LD1Rv8h:{ *:[v8bf16] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv8h, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9546, GIR_Done, // Label 4389: @191624 GIM_Try, /*On fail goto*//*Label 4390*/ 191683, // Rule ID 9534 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v8i16] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<><><>) => (LD1Rv8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv8h, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9534, GIR_Done, // Label 4390: @191683 GIM_Try, /*On fail goto*//*Label 4391*/ 191706, // Rule ID 1879 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (AArch64dup:{ *:[v8i16] } GPR32:{ *:[i32] }:$Rn) => (DUPv8i16gpr:{ *:[v8i16] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::DUPv8i16gpr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1879, GIR_Done, // Label 4391: @191706 GIM_Try, /*On fail goto*//*Label 4392*/ 191784, // Rule ID 8950 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (AArch64dup:{ *:[v8f16] } FPR16:{ *:[f16] }:$Rn) => (DUPv8i16lane:{ *:[v8f16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv8i16lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8950, GIR_Done, // Label 4392: @191784 GIM_Try, /*On fail goto*//*Label 4393*/ 191862, // Rule ID 8951 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (AArch64dup:{ *:[v8bf16] } FPR16:{ *:[bf16] }:$Rn) => (DUPv8i16lane:{ *:[v8bf16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[bf16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv8i16lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8951, GIR_Done, // Label 4393: @191862 GIM_Reject, // Label 4357: @191863 GIM_Try, /*On fail goto*//*Label 4394*/ 191940, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4395*/ 191924, // Rule ID 9532 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, // MIs[1] Rn GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64dup:{ *:[v16i8] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<><><>) => (LD1Rv16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv16b, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9532, GIR_Done, // Label 4395: @191924 GIM_Try, /*On fail goto*//*Label 4396*/ 191939, // Rule ID 1877 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (AArch64dup:{ *:[v16i8] } GPR32:{ *:[i32] }:$Rn) => (DUPv16i8gpr:{ *:[v16i8] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::DUPv16i8gpr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1877, GIR_Done, // Label 4396: @191939 GIM_Reject, // Label 4394: @191940 GIM_Reject, // Label 4358: @191941 GIM_Reject, // Label 92: @191942 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/6, 10, /*)*//*default:*//*Label 4399*/ 192194, /*GILLT_v4s16*//*Label 4397*/ 191952, 0, 0, /*GILLT_v8s16*//*Label 4398*/ 192073, // Label 4397: @191952 GIM_Try, /*On fail goto*//*Label 4400*/ 192072, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4401*/ 192005, // Rule ID 1886 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64duplane16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (DUPv4i16lane:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i16lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1886, GIR_Done, // Label 4401: @192005 GIM_Try, /*On fail goto*//*Label 4402*/ 192038, // Rule ID 8952 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64duplane16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (DUPv4i16lane:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i16lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8952, GIR_Done, // Label 4402: @192038 GIM_Try, /*On fail goto*//*Label 4403*/ 192071, // Rule ID 8954 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64duplane16:{ *:[v4bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (DUPv4i16lane:{ *:[v4bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i16lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8954, GIR_Done, // Label 4403: @192071 GIM_Reject, // Label 4400: @192072 GIM_Reject, // Label 4398: @192073 GIM_Try, /*On fail goto*//*Label 4404*/ 192193, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4405*/ 192126, // Rule ID 1887 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64duplane16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (DUPv8i16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv8i16lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1887, GIR_Done, // Label 4405: @192126 GIM_Try, /*On fail goto*//*Label 4406*/ 192159, // Rule ID 8953 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64duplane16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (DUPv8i16lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv8i16lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8953, GIR_Done, // Label 4406: @192159 GIM_Try, /*On fail goto*//*Label 4407*/ 192192, // Rule ID 8955 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64duplane16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (DUPv8i16lane:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv8i16lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8955, GIR_Done, // Label 4407: @192192 GIM_Reject, // Label 4404: @192193 GIM_Reject, // Label 4399: @192194 GIM_Reject, // Label 93: @192195 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 8, /*)*//*default:*//*Label 4410*/ 192381, /*GILLT_v2s32*//*Label 4408*/ 192205, 0, 0, /*GILLT_v4s32*//*Label 4409*/ 192293, // Label 4408: @192205 GIM_Try, /*On fail goto*//*Label 4411*/ 192292, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4412*/ 192258, // Rule ID 1884 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (DUPv2i32lane:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv2i32lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1884, GIR_Done, // Label 4412: @192258 GIM_Try, /*On fail goto*//*Label 4413*/ 192291, // Rule ID 8956 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (DUPv2i32lane:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv2i32lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8956, GIR_Done, // Label 4413: @192291 GIM_Reject, // Label 4411: @192292 GIM_Reject, // Label 4409: @192293 GIM_Try, /*On fail goto*//*Label 4414*/ 192380, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4415*/ 192346, // Rule ID 1885 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (DUPv4i32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i32lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1885, GIR_Done, // Label 4415: @192346 GIM_Try, /*On fail goto*//*Label 4416*/ 192379, // Rule ID 8957 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (DUPv4i32lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i32lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8957, GIR_Done, // Label 4416: @192379 GIM_Reject, // Label 4414: @192380 GIM_Reject, // Label 4410: @192381 GIM_Reject, // Label 94: @192382 GIM_Try, /*On fail goto*//*Label 4417*/ 192473, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4418*/ 192439, // Rule ID 1883 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64duplane64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (DUPv2i64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv2i64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1883, GIR_Done, // Label 4418: @192439 GIM_Try, /*On fail goto*//*Label 4419*/ 192472, // Rule ID 8958 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (DUPv2i64lane:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv2i64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8958, GIR_Done, // Label 4419: @192472 GIM_Reject, // Label 4417: @192473 GIM_Reject, // Label 95: @192474 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 11, /*)*//*default:*//*Label 4422*/ 192587, /*GILLT_v8s8*//*Label 4420*/ 192483, 0, /*GILLT_v16s8*//*Label 4421*/ 192535, // Label 4420: @192483 GIM_Try, /*On fail goto*//*Label 4423*/ 192534, // Rule ID 1888 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64duplane8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (DUPv8i8lane:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv8i8lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1888, GIR_Done, // Label 4423: @192534 GIM_Reject, // Label 4421: @192535 GIM_Try, /*On fail goto*//*Label 4424*/ 192586, // Rule ID 1889 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64duplane8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (DUPv16i8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv16i8lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1889, GIR_Done, // Label 4424: @192586 GIM_Reject, // Label 4422: @192587 GIM_Reject, // Label 96: @192588 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 11, /*)*//*default:*//*Label 4433*/ 193411, /*GILLT_s64*//*Label 4425*/ 192603, 0, /*GILLT_v2s32*//*Label 4426*/ 192695, /*GILLT_v2s64*//*Label 4427*/ 192787, /*GILLT_v4s16*//*Label 4428*/ 192879, /*GILLT_v4s32*//*Label 4429*/ 193005, /*GILLT_v8s8*//*Label 4430*/ 193097, /*GILLT_v8s16*//*Label 4431*/ 193191, /*GILLT_v16s8*//*Label 4432*/ 193317, // Label 4425: @192603 GIM_Try, /*On fail goto*//*Label 4434*/ 192694, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4435*/ 192659, // Rule ID 8870 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8870, GIR_Done, // Label 4435: @192659 GIM_Try, /*On fail goto*//*Label 4436*/ 192693, // Rule ID 8875 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v1f64] } V64:{ *:[v1f64] }:$Rn, V64:{ *:[v1f64] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v1f64] } V64:{ *:[v1f64] }:$Rn, V64:{ *:[v1f64] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8875, GIR_Done, // Label 4436: @192693 GIM_Reject, // Label 4434: @192694 GIM_Reject, // Label 4426: @192695 GIM_Try, /*On fail goto*//*Label 4437*/ 192786, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4438*/ 192751, // Rule ID 8860 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8860, GIR_Done, // Label 4438: @192751 GIM_Try, /*On fail goto*//*Label 4439*/ 192785, // Rule ID 8865 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8865, GIR_Done, // Label 4439: @192785 GIM_Reject, // Label 4437: @192786 GIM_Reject, // Label 4427: @192787 GIM_Try, /*On fail goto*//*Label 4440*/ 192878, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4441*/ 192843, // Rule ID 8871 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8871, GIR_Done, // Label 4441: @192843 GIM_Try, /*On fail goto*//*Label 4442*/ 192877, // Rule ID 8876 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8876, GIR_Done, // Label 4442: @192877 GIM_Reject, // Label 4440: @192878 GIM_Reject, // Label 4428: @192879 GIM_Try, /*On fail goto*//*Label 4443*/ 193004, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4444*/ 192935, // Rule ID 8845 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8845, GIR_Done, // Label 4444: @192935 GIM_Try, /*On fail goto*//*Label 4445*/ 192969, // Rule ID 8850 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8850, GIR_Done, // Label 4445: @192969 GIM_Try, /*On fail goto*//*Label 4446*/ 193003, // Rule ID 8855 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8855, GIR_Done, // Label 4446: @193003 GIM_Reject, // Label 4443: @193004 GIM_Reject, // Label 4429: @193005 GIM_Try, /*On fail goto*//*Label 4447*/ 193096, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4448*/ 193061, // Rule ID 8861 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8861, GIR_Done, // Label 4448: @193061 GIM_Try, /*On fail goto*//*Label 4449*/ 193095, // Rule ID 8866 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8866, GIR_Done, // Label 4449: @193095 GIM_Reject, // Label 4447: @193096 GIM_Reject, // Label 4430: @193097 GIM_Try, /*On fail goto*//*Label 4450*/ 193190, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4451*/ 193155, // Rule ID 1832 // GIM_CheckFeatures, GIFBS_HasNEON, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1832, GIR_Done, // Label 4451: @193155 GIM_Try, /*On fail goto*//*Label 4452*/ 193189, // Rule ID 8840 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8840, GIR_Done, // Label 4452: @193189 GIM_Reject, // Label 4450: @193190 GIM_Reject, // Label 4431: @193191 GIM_Try, /*On fail goto*//*Label 4453*/ 193316, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4454*/ 193247, // Rule ID 8846 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8846, GIR_Done, // Label 4454: @193247 GIM_Try, /*On fail goto*//*Label 4455*/ 193281, // Rule ID 8851 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8851, GIR_Done, // Label 4455: @193281 GIM_Try, /*On fail goto*//*Label 4456*/ 193315, // Rule ID 8856 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8856, GIR_Done, // Label 4456: @193315 GIM_Reject, // Label 4453: @193316 GIM_Reject, // Label 4432: @193317 GIM_Try, /*On fail goto*//*Label 4457*/ 193410, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4458*/ 193375, // Rule ID 1833 // GIM_CheckFeatures, GIFBS_HasNEON, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1833, GIR_Done, // Label 4458: @193375 GIM_Try, /*On fail goto*//*Label 4459*/ 193409, // Rule ID 8841 // // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64ext:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8841, GIR_Done, // Label 4459: @193409 GIM_Reject, // Label 4457: @193410 GIM_Reject, // Label 4433: @193411 GIM_Reject, // Label 97: @193412 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 4467*/ 193689, /*GILLT_s32*//*Label 4460*/ 193427, /*GILLT_s64*//*Label 4461*/ 193462, 0, /*GILLT_v2s32*//*Label 4462*/ 193514, /*GILLT_v2s64*//*Label 4463*/ 193549, /*GILLT_v4s16*//*Label 4464*/ 193584, /*GILLT_v4s32*//*Label 4465*/ 193619, 0, /*GILLT_v8s16*//*Label 4466*/ 193654, // Label 4460: @193427 GIM_Try, /*On fail goto*//*Label 4468*/ 193461, // Rule ID 1587 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (AArch64fcmeq:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FCMEQ32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMEQ32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1587, GIR_Done, // Label 4468: @193461 GIM_Reject, // Label 4461: @193462 GIM_Try, /*On fail goto*//*Label 4469*/ 193513, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4470*/ 193498, // Rule ID 1586 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64fcmeq:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FCMEQ64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMEQ64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1586, GIR_Done, // Label 4470: @193498 GIM_Try, /*On fail goto*//*Label 4471*/ 193512, // Rule ID 8684 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64fcmeq:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FCMEQ64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMEQ64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8684, GIR_Done, // Label 4471: @193512 GIM_Reject, // Label 4469: @193513 GIM_Reject, // Label 4462: @193514 GIM_Try, /*On fail goto*//*Label 4472*/ 193548, // Rule ID 1173 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmeq:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCMEQv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMEQv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1173, GIR_Done, // Label 4472: @193548 GIM_Reject, // Label 4463: @193549 GIM_Try, /*On fail goto*//*Label 4473*/ 193583, // Rule ID 1175 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmeq:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCMEQv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMEQv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1175, GIR_Done, // Label 4473: @193583 GIM_Reject, // Label 4464: @193584 GIM_Try, /*On fail goto*//*Label 4474*/ 193618, // Rule ID 1171 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmeq:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCMEQv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMEQv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1171, GIR_Done, // Label 4474: @193618 GIM_Reject, // Label 4465: @193619 GIM_Try, /*On fail goto*//*Label 4475*/ 193653, // Rule ID 1174 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmeq:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCMEQv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMEQv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1174, GIR_Done, // Label 4475: @193653 GIM_Reject, // Label 4466: @193654 GIM_Try, /*On fail goto*//*Label 4476*/ 193688, // Rule ID 1172 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmeq:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCMEQv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMEQv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1172, GIR_Done, // Label 4476: @193688 GIM_Reject, // Label 4467: @193689 GIM_Reject, // Label 98: @193690 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 10, /*)*//*default:*//*Label 4483*/ 193866, /*GILLT_s64*//*Label 4477*/ 193704, 0, /*GILLT_v2s32*//*Label 4478*/ 193731, /*GILLT_v2s64*//*Label 4479*/ 193758, /*GILLT_v4s16*//*Label 4480*/ 193785, /*GILLT_v4s32*//*Label 4481*/ 193812, 0, /*GILLT_v8s16*//*Label 4482*/ 193839, // Label 4477: @193704 GIM_Try, /*On fail goto*//*Label 4484*/ 193730, // Rule ID 6826 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmeqz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) => (FCMEQv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMEQv1i64rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6826, GIR_Done, // Label 4484: @193730 GIM_Reject, // Label 4478: @193731 GIM_Try, /*On fail goto*//*Label 4485*/ 193757, // Rule ID 747 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmeqz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCMEQv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMEQv2i32rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 747, GIR_Done, // Label 4485: @193757 GIM_Reject, // Label 4479: @193758 GIM_Try, /*On fail goto*//*Label 4486*/ 193784, // Rule ID 749 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmeqz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCMEQv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMEQv2i64rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 749, GIR_Done, // Label 4486: @193784 GIM_Reject, // Label 4480: @193785 GIM_Try, /*On fail goto*//*Label 4487*/ 193811, // Rule ID 745 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmeqz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCMEQv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMEQv4i16rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 745, GIR_Done, // Label 4487: @193811 GIM_Reject, // Label 4481: @193812 GIM_Try, /*On fail goto*//*Label 4488*/ 193838, // Rule ID 748 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmeqz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCMEQv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMEQv4i32rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 748, GIR_Done, // Label 4488: @193838 GIM_Reject, // Label 4482: @193839 GIM_Try, /*On fail goto*//*Label 4489*/ 193865, // Rule ID 746 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmeqz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCMEQv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMEQv8i16rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 746, GIR_Done, // Label 4489: @193865 GIM_Reject, // Label 4483: @193866 GIM_Reject, // Label 99: @193867 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 4497*/ 194144, /*GILLT_s32*//*Label 4490*/ 193882, /*GILLT_s64*//*Label 4491*/ 193917, 0, /*GILLT_v2s32*//*Label 4492*/ 193969, /*GILLT_v2s64*//*Label 4493*/ 194004, /*GILLT_v4s16*//*Label 4494*/ 194039, /*GILLT_v4s32*//*Label 4495*/ 194074, 0, /*GILLT_v8s16*//*Label 4496*/ 194109, // Label 4490: @193882 GIM_Try, /*On fail goto*//*Label 4498*/ 193916, // Rule ID 1589 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (AArch64fcmge:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FCMGE32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGE32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1589, GIR_Done, // Label 4498: @193916 GIM_Reject, // Label 4491: @193917 GIM_Try, /*On fail goto*//*Label 4499*/ 193968, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4500*/ 193953, // Rule ID 1588 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64fcmge:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FCMGE64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGE64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1588, GIR_Done, // Label 4500: @193953 GIM_Try, /*On fail goto*//*Label 4501*/ 193967, // Rule ID 8685 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64fcmge:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FCMGE64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGE64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8685, GIR_Done, // Label 4501: @193967 GIM_Reject, // Label 4499: @193968 GIM_Reject, // Label 4492: @193969 GIM_Try, /*On fail goto*//*Label 4502*/ 194003, // Rule ID 1178 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmge:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCMGEv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGEv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1178, GIR_Done, // Label 4502: @194003 GIM_Reject, // Label 4493: @194004 GIM_Try, /*On fail goto*//*Label 4503*/ 194038, // Rule ID 1180 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmge:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCMGEv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGEv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1180, GIR_Done, // Label 4503: @194038 GIM_Reject, // Label 4494: @194039 GIM_Try, /*On fail goto*//*Label 4504*/ 194073, // Rule ID 1176 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmge:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCMGEv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGEv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1176, GIR_Done, // Label 4504: @194073 GIM_Reject, // Label 4495: @194074 GIM_Try, /*On fail goto*//*Label 4505*/ 194108, // Rule ID 1179 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmge:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCMGEv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGEv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1179, GIR_Done, // Label 4505: @194108 GIM_Reject, // Label 4496: @194109 GIM_Try, /*On fail goto*//*Label 4506*/ 194143, // Rule ID 1177 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmge:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCMGEv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGEv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1177, GIR_Done, // Label 4506: @194143 GIM_Reject, // Label 4497: @194144 GIM_Reject, // Label 100: @194145 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 10, /*)*//*default:*//*Label 4513*/ 194321, /*GILLT_s64*//*Label 4507*/ 194159, 0, /*GILLT_v2s32*//*Label 4508*/ 194186, /*GILLT_v2s64*//*Label 4509*/ 194213, /*GILLT_v4s16*//*Label 4510*/ 194240, /*GILLT_v4s32*//*Label 4511*/ 194267, 0, /*GILLT_v8s16*//*Label 4512*/ 194294, // Label 4507: @194159 GIM_Try, /*On fail goto*//*Label 4514*/ 194185, // Rule ID 8712 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmgez:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) => (FCMGEv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGEv1i64rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8712, GIR_Done, // Label 4514: @194185 GIM_Reject, // Label 4508: @194186 GIM_Try, /*On fail goto*//*Label 4515*/ 194212, // Rule ID 752 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmgez:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCMGEv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGEv2i32rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 752, GIR_Done, // Label 4515: @194212 GIM_Reject, // Label 4509: @194213 GIM_Try, /*On fail goto*//*Label 4516*/ 194239, // Rule ID 754 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmgez:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCMGEv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGEv2i64rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 754, GIR_Done, // Label 4516: @194239 GIM_Reject, // Label 4510: @194240 GIM_Try, /*On fail goto*//*Label 4517*/ 194266, // Rule ID 750 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmgez:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCMGEv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGEv4i16rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 750, GIR_Done, // Label 4517: @194266 GIM_Reject, // Label 4511: @194267 GIM_Try, /*On fail goto*//*Label 4518*/ 194293, // Rule ID 753 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmgez:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCMGEv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGEv4i32rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 753, GIR_Done, // Label 4518: @194293 GIM_Reject, // Label 4512: @194294 GIM_Try, /*On fail goto*//*Label 4519*/ 194320, // Rule ID 751 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmgez:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCMGEv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGEv8i16rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 751, GIR_Done, // Label 4519: @194320 GIM_Reject, // Label 4513: @194321 GIM_Reject, // Label 101: @194322 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 4527*/ 194599, /*GILLT_s32*//*Label 4520*/ 194337, /*GILLT_s64*//*Label 4521*/ 194372, 0, /*GILLT_v2s32*//*Label 4522*/ 194424, /*GILLT_v2s64*//*Label 4523*/ 194459, /*GILLT_v4s16*//*Label 4524*/ 194494, /*GILLT_v4s32*//*Label 4525*/ 194529, 0, /*GILLT_v8s16*//*Label 4526*/ 194564, // Label 4520: @194337 GIM_Try, /*On fail goto*//*Label 4528*/ 194371, // Rule ID 1591 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (AArch64fcmgt:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FCMGT32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGT32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1591, GIR_Done, // Label 4528: @194371 GIM_Reject, // Label 4521: @194372 GIM_Try, /*On fail goto*//*Label 4529*/ 194423, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4530*/ 194408, // Rule ID 1590 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64fcmgt:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FCMGT64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGT64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1590, GIR_Done, // Label 4530: @194408 GIM_Try, /*On fail goto*//*Label 4531*/ 194422, // Rule ID 8686 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64fcmgt:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FCMGT64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGT64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8686, GIR_Done, // Label 4531: @194422 GIM_Reject, // Label 4529: @194423 GIM_Reject, // Label 4522: @194424 GIM_Try, /*On fail goto*//*Label 4532*/ 194458, // Rule ID 1183 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmgt:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCMGTv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGTv2f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1183, GIR_Done, // Label 4532: @194458 GIM_Reject, // Label 4523: @194459 GIM_Try, /*On fail goto*//*Label 4533*/ 194493, // Rule ID 1185 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmgt:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCMGTv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGTv2f64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1185, GIR_Done, // Label 4533: @194493 GIM_Reject, // Label 4524: @194494 GIM_Try, /*On fail goto*//*Label 4534*/ 194528, // Rule ID 1181 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmgt:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCMGTv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGTv4f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1181, GIR_Done, // Label 4534: @194528 GIM_Reject, // Label 4525: @194529 GIM_Try, /*On fail goto*//*Label 4535*/ 194563, // Rule ID 1184 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmgt:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCMGTv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGTv4f32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1184, GIR_Done, // Label 4535: @194563 GIM_Reject, // Label 4526: @194564 GIM_Try, /*On fail goto*//*Label 4536*/ 194598, // Rule ID 1182 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmgt:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCMGTv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGTv8f16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1182, GIR_Done, // Label 4536: @194598 GIM_Reject, // Label 4527: @194599 GIM_Reject, // Label 102: @194600 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 10, /*)*//*default:*//*Label 4543*/ 194776, /*GILLT_s64*//*Label 4537*/ 194614, 0, /*GILLT_v2s32*//*Label 4538*/ 194641, /*GILLT_v2s64*//*Label 4539*/ 194668, /*GILLT_v4s16*//*Label 4540*/ 194695, /*GILLT_v4s32*//*Label 4541*/ 194722, 0, /*GILLT_v8s16*//*Label 4542*/ 194749, // Label 4537: @194614 GIM_Try, /*On fail goto*//*Label 4544*/ 194640, // Rule ID 8713 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmgtz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) => (FCMGTv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGTv1i64rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8713, GIR_Done, // Label 4544: @194640 GIM_Reject, // Label 4538: @194641 GIM_Try, /*On fail goto*//*Label 4545*/ 194667, // Rule ID 757 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmgtz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCMGTv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGTv2i32rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 757, GIR_Done, // Label 4545: @194667 GIM_Reject, // Label 4539: @194668 GIM_Try, /*On fail goto*//*Label 4546*/ 194694, // Rule ID 759 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmgtz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCMGTv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGTv2i64rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 759, GIR_Done, // Label 4546: @194694 GIM_Reject, // Label 4540: @194695 GIM_Try, /*On fail goto*//*Label 4547*/ 194721, // Rule ID 755 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmgtz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCMGTv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGTv4i16rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 755, GIR_Done, // Label 4547: @194721 GIM_Reject, // Label 4541: @194722 GIM_Try, /*On fail goto*//*Label 4548*/ 194748, // Rule ID 758 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmgtz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCMGTv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGTv4i32rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 758, GIR_Done, // Label 4548: @194748 GIM_Reject, // Label 4542: @194749 GIM_Try, /*On fail goto*//*Label 4549*/ 194775, // Rule ID 756 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmgtz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCMGTv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMGTv8i16rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 756, GIR_Done, // Label 4549: @194775 GIM_Reject, // Label 4543: @194776 GIM_Reject, // Label 103: @194777 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 10, /*)*//*default:*//*Label 4556*/ 194953, /*GILLT_s64*//*Label 4550*/ 194791, 0, /*GILLT_v2s32*//*Label 4551*/ 194818, /*GILLT_v2s64*//*Label 4552*/ 194845, /*GILLT_v4s16*//*Label 4553*/ 194872, /*GILLT_v4s32*//*Label 4554*/ 194899, 0, /*GILLT_v8s16*//*Label 4555*/ 194926, // Label 4550: @194791 GIM_Try, /*On fail goto*//*Label 4557*/ 194817, // Rule ID 8714 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmlez:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) => (FCMLEv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMLEv1i64rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8714, GIR_Done, // Label 4557: @194817 GIM_Reject, // Label 4551: @194818 GIM_Try, /*On fail goto*//*Label 4558*/ 194844, // Rule ID 762 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmlez:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCMLEv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMLEv2i32rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 762, GIR_Done, // Label 4558: @194844 GIM_Reject, // Label 4552: @194845 GIM_Try, /*On fail goto*//*Label 4559*/ 194871, // Rule ID 764 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmlez:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCMLEv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMLEv2i64rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 764, GIR_Done, // Label 4559: @194871 GIM_Reject, // Label 4553: @194872 GIM_Try, /*On fail goto*//*Label 4560*/ 194898, // Rule ID 760 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmlez:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCMLEv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMLEv4i16rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 760, GIR_Done, // Label 4560: @194898 GIM_Reject, // Label 4554: @194899 GIM_Try, /*On fail goto*//*Label 4561*/ 194925, // Rule ID 763 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmlez:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCMLEv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMLEv4i32rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 763, GIR_Done, // Label 4561: @194925 GIM_Reject, // Label 4555: @194926 GIM_Try, /*On fail goto*//*Label 4562*/ 194952, // Rule ID 761 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmlez:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCMLEv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMLEv8i16rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 761, GIR_Done, // Label 4562: @194952 GIM_Reject, // Label 4556: @194953 GIM_Reject, // Label 104: @194954 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 10, /*)*//*default:*//*Label 4569*/ 195130, /*GILLT_s64*//*Label 4563*/ 194968, 0, /*GILLT_v2s32*//*Label 4564*/ 194995, /*GILLT_v2s64*//*Label 4565*/ 195022, /*GILLT_v4s16*//*Label 4566*/ 195049, /*GILLT_v4s32*//*Label 4567*/ 195076, 0, /*GILLT_v8s16*//*Label 4568*/ 195103, // Label 4563: @194968 GIM_Try, /*On fail goto*//*Label 4570*/ 194994, // Rule ID 8715 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmltz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) => (FCMLTv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMLTv1i64rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8715, GIR_Done, // Label 4570: @194994 GIM_Reject, // Label 4564: @194995 GIM_Try, /*On fail goto*//*Label 4571*/ 195021, // Rule ID 767 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmltz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMLTv2i32rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 767, GIR_Done, // Label 4571: @195021 GIM_Reject, // Label 4565: @195022 GIM_Try, /*On fail goto*//*Label 4572*/ 195048, // Rule ID 769 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmltz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMLTv2i64rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 769, GIR_Done, // Label 4572: @195048 GIM_Reject, // Label 4566: @195049 GIM_Try, /*On fail goto*//*Label 4573*/ 195075, // Rule ID 765 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64fcmltz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMLTv4i16rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 765, GIR_Done, // Label 4573: @195075 GIM_Reject, // Label 4567: @195076 GIM_Try, /*On fail goto*//*Label 4574*/ 195102, // Rule ID 768 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmltz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMLTv4i32rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 768, GIR_Done, // Label 4574: @195102 GIM_Reject, // Label 4568: @195103 GIM_Try, /*On fail goto*//*Label 4575*/ 195129, // Rule ID 766 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64fcmltz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCMLTv8i16rz, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 766, GIR_Done, // Label 4575: @195129 GIM_Reject, // Label 4569: @195130 GIM_Reject, // Label 105: @195131 GIM_Try, /*On fail goto*//*Label 4576*/ 195257, GIM_CheckIsImm, /*MI*/0, /*Op*/0, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_Try, /*On fail goto*//*Label 4577*/ 195171, // Rule ID 254 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)) => (PRFMroW (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFMroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 254, GIR_Done, // Label 4577: @195171 GIM_Try, /*On fail goto*//*Label 4578*/ 195202, // Rule ID 255 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)) => (PRFMroX (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFMroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 255, GIR_Done, // Label 4578: @195202 GIM_Try, /*On fail goto*//*Label 4579*/ 195229, // Rule ID 270 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)) => (PRFMui (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFMui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 270, GIR_Done, // Label 4579: @195229 GIM_Try, /*On fail goto*//*Label 4580*/ 195256, // Rule ID 291 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset)) => (PRFUMi (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PRFUMi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 291, GIR_Done, // Label 4580: @195256 GIM_Reject, // Label 4576: @195257 GIM_Reject, // Label 106: @195258 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 11, /*)*//*default:*//*Label 4583*/ 195315, /*GILLT_v8s8*//*Label 4581*/ 195267, 0, /*GILLT_v16s8*//*Label 4582*/ 195291, // Label 4581: @195267 GIM_Try, /*On fail goto*//*Label 4584*/ 195290, // Rule ID 949 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64rev16:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (REV16v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 949, GIR_Done, // Label 4584: @195290 GIM_Reject, // Label 4582: @195291 GIM_Try, /*On fail goto*//*Label 4585*/ 195314, // Rule ID 950 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64rev16:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (REV16v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 950, GIR_Done, // Label 4585: @195314 GIM_Reject, // Label 4583: @195315 GIM_Reject, // Label 107: @195316 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/6, 11, /*)*//*default:*//*Label 4590*/ 195465, /*GILLT_v4s16*//*Label 4586*/ 195327, 0, /*GILLT_v8s8*//*Label 4587*/ 195372, /*GILLT_v8s16*//*Label 4588*/ 195396, /*GILLT_v16s8*//*Label 4589*/ 195441, // Label 4586: @195327 GIM_Try, /*On fail goto*//*Label 4591*/ 195371, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4592*/ 195352, // Rule ID 953 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64rev32:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) => (REV32v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 953, GIR_Done, // Label 4592: @195352 GIM_Try, /*On fail goto*//*Label 4593*/ 195361, // Rule ID 8570 // // (AArch64rev32:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (REV32v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8570, GIR_Done, // Label 4593: @195361 GIM_Try, /*On fail goto*//*Label 4594*/ 195370, // Rule ID 8572 // // (AArch64rev32:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn) => (REV32v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8572, GIR_Done, // Label 4594: @195370 GIM_Reject, // Label 4591: @195371 GIM_Reject, // Label 4587: @195372 GIM_Try, /*On fail goto*//*Label 4595*/ 195395, // Rule ID 951 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64rev32:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (REV32v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 951, GIR_Done, // Label 4595: @195395 GIM_Reject, // Label 4588: @195396 GIM_Try, /*On fail goto*//*Label 4596*/ 195440, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4597*/ 195421, // Rule ID 954 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64rev32:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) => (REV32v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 954, GIR_Done, // Label 4597: @195421 GIM_Try, /*On fail goto*//*Label 4598*/ 195430, // Rule ID 8574 // // (AArch64rev32:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (REV32v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8574, GIR_Done, // Label 4598: @195430 GIM_Try, /*On fail goto*//*Label 4599*/ 195439, // Rule ID 8576 // // (AArch64rev32:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (REV32v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8576, GIR_Done, // Label 4599: @195439 GIM_Reject, // Label 4596: @195440 GIM_Reject, // Label 4589: @195441 GIM_Try, /*On fail goto*//*Label 4600*/ 195464, // Rule ID 952 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64rev32:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (REV32v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 952, GIR_Done, // Label 4600: @195464 GIM_Reject, // Label 4590: @195465 GIM_Reject, // Label 108: @195466 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 4607*/ 195689, /*GILLT_v2s32*//*Label 4601*/ 195479, 0, /*GILLT_v4s16*//*Label 4602*/ 195515, /*GILLT_v4s32*//*Label 4603*/ 195560, /*GILLT_v8s8*//*Label 4604*/ 195596, /*GILLT_v8s16*//*Label 4605*/ 195620, /*GILLT_v16s8*//*Label 4606*/ 195665, // Label 4601: @195479 GIM_Try, /*On fail goto*//*Label 4608*/ 195514, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4609*/ 195504, // Rule ID 959 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64rev64:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) => (REV64v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 959, GIR_Done, // Label 4609: @195504 GIM_Try, /*On fail goto*//*Label 4610*/ 195513, // Rule ID 8578 // // (AArch64rev64:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (REV64v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8578, GIR_Done, // Label 4610: @195513 GIM_Reject, // Label 4608: @195514 GIM_Reject, // Label 4602: @195515 GIM_Try, /*On fail goto*//*Label 4611*/ 195559, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4612*/ 195540, // Rule ID 957 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64rev64:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) => (REV64v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 957, GIR_Done, // Label 4612: @195540 GIM_Try, /*On fail goto*//*Label 4613*/ 195549, // Rule ID 8571 // // (AArch64rev64:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (REV64v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8571, GIR_Done, // Label 4613: @195549 GIM_Try, /*On fail goto*//*Label 4614*/ 195558, // Rule ID 8573 // // (AArch64rev64:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn) => (REV64v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8573, GIR_Done, // Label 4614: @195558 GIM_Reject, // Label 4611: @195559 GIM_Reject, // Label 4603: @195560 GIM_Try, /*On fail goto*//*Label 4615*/ 195595, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4616*/ 195585, // Rule ID 960 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64rev64:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) => (REV64v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 960, GIR_Done, // Label 4616: @195585 GIM_Try, /*On fail goto*//*Label 4617*/ 195594, // Rule ID 8579 // // (AArch64rev64:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (REV64v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8579, GIR_Done, // Label 4617: @195594 GIM_Reject, // Label 4615: @195595 GIM_Reject, // Label 4604: @195596 GIM_Try, /*On fail goto*//*Label 4618*/ 195619, // Rule ID 955 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64rev64:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (REV64v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 955, GIR_Done, // Label 4618: @195619 GIM_Reject, // Label 4605: @195620 GIM_Try, /*On fail goto*//*Label 4619*/ 195664, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4620*/ 195645, // Rule ID 958 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64rev64:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) => (REV64v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 958, GIR_Done, // Label 4620: @195645 GIM_Try, /*On fail goto*//*Label 4621*/ 195654, // Rule ID 8575 // // (AArch64rev64:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (REV64v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8575, GIR_Done, // Label 4621: @195654 GIM_Try, /*On fail goto*//*Label 4622*/ 195663, // Rule ID 8577 // // (AArch64rev64:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (REV64v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8577, GIR_Done, // Label 4622: @195663 GIM_Reject, // Label 4619: @195664 GIM_Reject, // Label 4606: @195665 GIM_Try, /*On fail goto*//*Label 4623*/ 195688, // Rule ID 956 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (AArch64rev64:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (REV64v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 956, GIR_Done, // Label 4623: @195688 GIM_Reject, // Label 4607: @195689 GIM_Reject, // Label 109: @195690 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 4627*/ 195780, /*GILLT_s16*//*Label 4624*/ 195699, /*GILLT_s32*//*Label 4625*/ 195726, /*GILLT_s64*//*Label 4626*/ 195753, // Label 4624: @195699 GIM_Try, /*On fail goto*//*Label 4628*/ 195725, // Rule ID 1622 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (AArch64sitof:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (SCVTFv1i16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv1i16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1622, GIR_Done, // Label 4628: @195725 GIM_Reject, // Label 4625: @195726 GIM_Try, /*On fail goto*//*Label 4629*/ 195752, // Rule ID 1621 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (AArch64sitof:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (SCVTFv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv1i32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1621, GIR_Done, // Label 4629: @195752 GIM_Reject, // Label 4626: @195753 GIM_Try, /*On fail goto*//*Label 4630*/ 195779, // Rule ID 1620 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64sitof:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (SCVTFv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1620, GIR_Done, // Label 4630: @195779 GIM_Reject, // Label 4627: @195780 GIM_Reject, // Label 110: @195781 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 22, /*)*//*default:*//*Label 4639*/ 196145, /*GILLT_v2s32*//*Label 4631*/ 195805, /*GILLT_v2s64*//*Label 4632*/ 195851, /*GILLT_v4s16*//*Label 4633*/ 195897, /*GILLT_v4s32*//*Label 4634*/ 195954, /*GILLT_v8s8*//*Label 4635*/ 196000, /*GILLT_v8s16*//*Label 4636*/ 196032, /*GILLT_v16s8*//*Label 4637*/ 196089, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*GILLT_nxv16s1*//*Label 4638*/ 196121, // Label 4631: @195805 GIM_Try, /*On fail goto*//*Label 4640*/ 195850, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4641*/ 195838, // Rule ID 1838 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn1:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (TRN1v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1838, GIR_Done, // Label 4641: @195838 GIM_Try, /*On fail goto*//*Label 4642*/ 195849, // Rule ID 6818 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn1:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (TRN1v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6818, GIR_Done, // Label 4642: @195849 GIM_Reject, // Label 4640: @195850 GIM_Reject, // Label 4632: @195851 GIM_Try, /*On fail goto*//*Label 4643*/ 195896, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4644*/ 195884, // Rule ID 1840 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (TRN1v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1840, GIR_Done, // Label 4644: @195884 GIM_Try, /*On fail goto*//*Label 4645*/ 195895, // Rule ID 6820 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn1:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (TRN1v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6820, GIR_Done, // Label 4645: @195895 GIM_Reject, // Label 4643: @195896 GIM_Reject, // Label 4633: @195897 GIM_Try, /*On fail goto*//*Label 4646*/ 195953, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4647*/ 195930, // Rule ID 1836 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn1:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (TRN1v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1836, GIR_Done, // Label 4647: @195930 GIM_Try, /*On fail goto*//*Label 4648*/ 195941, // Rule ID 6814 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn1:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (TRN1v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6814, GIR_Done, // Label 4648: @195941 GIM_Try, /*On fail goto*//*Label 4649*/ 195952, // Rule ID 6815 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn1:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) => (TRN1v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6815, GIR_Done, // Label 4649: @195952 GIM_Reject, // Label 4646: @195953 GIM_Reject, // Label 4634: @195954 GIM_Try, /*On fail goto*//*Label 4650*/ 195999, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4651*/ 195987, // Rule ID 1839 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (TRN1v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1839, GIR_Done, // Label 4651: @195987 GIM_Try, /*On fail goto*//*Label 4652*/ 195998, // Rule ID 6819 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn1:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (TRN1v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6819, GIR_Done, // Label 4652: @195998 GIM_Reject, // Label 4650: @195999 GIM_Reject, // Label 4635: @196000 GIM_Try, /*On fail goto*//*Label 4653*/ 196031, // Rule ID 1834 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (AArch64trn1:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (TRN1v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1834, GIR_Done, // Label 4653: @196031 GIM_Reject, // Label 4636: @196032 GIM_Try, /*On fail goto*//*Label 4654*/ 196088, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4655*/ 196065, // Rule ID 1837 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn1:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (TRN1v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1837, GIR_Done, // Label 4655: @196065 GIM_Try, /*On fail goto*//*Label 4656*/ 196076, // Rule ID 6816 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn1:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (TRN1v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6816, GIR_Done, // Label 4656: @196076 GIM_Try, /*On fail goto*//*Label 4657*/ 196087, // Rule ID 6817 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn1:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (TRN1v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 6817, GIR_Done, // Label 4657: @196087 GIM_Reject, // Label 4654: @196088 GIM_Reject, // Label 4637: @196089 GIM_Try, /*On fail goto*//*Label 4658*/ 196120, // Rule ID 1835 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (AArch64trn1:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (TRN1v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1835, GIR_Done, // Label 4658: @196120 GIM_Reject, // Label 4638: @196121 GIM_Try, /*On fail goto*//*Label 4659*/ 196144, // Rule ID 2282 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (AArch64trn1:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN1_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1_PPP_B, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2282, GIR_Done, // Label 4659: @196144 GIM_Reject, // Label 4639: @196145 GIM_Reject, // Label 111: @196146 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 22, /*)*//*default:*//*Label 4668*/ 196510, /*GILLT_v2s32*//*Label 4660*/ 196170, /*GILLT_v2s64*//*Label 4661*/ 196216, /*GILLT_v4s16*//*Label 4662*/ 196262, /*GILLT_v4s32*//*Label 4663*/ 196319, /*GILLT_v8s8*//*Label 4664*/ 196365, /*GILLT_v8s16*//*Label 4665*/ 196397, /*GILLT_v16s8*//*Label 4666*/ 196454, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*GILLT_nxv16s1*//*Label 4667*/ 196486, // Label 4660: @196170 GIM_Try, /*On fail goto*//*Label 4669*/ 196215, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4670*/ 196203, // Rule ID 1845 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn2:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (TRN2v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1845, GIR_Done, // Label 4670: @196203 GIM_Try, /*On fail goto*//*Label 4671*/ 196214, // Rule ID 8884 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn2:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (TRN2v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8884, GIR_Done, // Label 4671: @196214 GIM_Reject, // Label 4669: @196215 GIM_Reject, // Label 4661: @196216 GIM_Try, /*On fail goto*//*Label 4672*/ 196261, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4673*/ 196249, // Rule ID 1847 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (TRN2v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1847, GIR_Done, // Label 4673: @196249 GIM_Try, /*On fail goto*//*Label 4674*/ 196260, // Rule ID 8886 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn2:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (TRN2v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8886, GIR_Done, // Label 4674: @196260 GIM_Reject, // Label 4672: @196261 GIM_Reject, // Label 4662: @196262 GIM_Try, /*On fail goto*//*Label 4675*/ 196318, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4676*/ 196295, // Rule ID 1843 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn2:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (TRN2v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1843, GIR_Done, // Label 4676: @196295 GIM_Try, /*On fail goto*//*Label 4677*/ 196306, // Rule ID 8880 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn2:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (TRN2v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8880, GIR_Done, // Label 4677: @196306 GIM_Try, /*On fail goto*//*Label 4678*/ 196317, // Rule ID 8881 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn2:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) => (TRN2v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8881, GIR_Done, // Label 4678: @196317 GIM_Reject, // Label 4675: @196318 GIM_Reject, // Label 4663: @196319 GIM_Try, /*On fail goto*//*Label 4679*/ 196364, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4680*/ 196352, // Rule ID 1846 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (TRN2v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1846, GIR_Done, // Label 4680: @196352 GIM_Try, /*On fail goto*//*Label 4681*/ 196363, // Rule ID 8885 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn2:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (TRN2v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8885, GIR_Done, // Label 4681: @196363 GIM_Reject, // Label 4679: @196364 GIM_Reject, // Label 4664: @196365 GIM_Try, /*On fail goto*//*Label 4682*/ 196396, // Rule ID 1841 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (AArch64trn2:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (TRN2v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1841, GIR_Done, // Label 4682: @196396 GIM_Reject, // Label 4665: @196397 GIM_Try, /*On fail goto*//*Label 4683*/ 196453, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4684*/ 196430, // Rule ID 1844 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn2:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (TRN2v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1844, GIR_Done, // Label 4684: @196430 GIM_Try, /*On fail goto*//*Label 4685*/ 196441, // Rule ID 8882 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn2:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (TRN2v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8882, GIR_Done, // Label 4685: @196441 GIM_Try, /*On fail goto*//*Label 4686*/ 196452, // Rule ID 8883 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64trn2:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (TRN2v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8883, GIR_Done, // Label 4686: @196452 GIM_Reject, // Label 4683: @196453 GIM_Reject, // Label 4666: @196454 GIM_Try, /*On fail goto*//*Label 4687*/ 196485, // Rule ID 1842 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (AArch64trn2:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (TRN2v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1842, GIR_Done, // Label 4687: @196485 GIM_Reject, // Label 4667: @196486 GIM_Try, /*On fail goto*//*Label 4688*/ 196509, // Rule ID 2286 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (AArch64trn2:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN2_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2_PPP_B, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2286, GIR_Done, // Label 4688: @196509 GIM_Reject, // Label 4668: @196510 GIM_Reject, // Label 112: @196511 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 4692*/ 196601, /*GILLT_s16*//*Label 4689*/ 196520, /*GILLT_s32*//*Label 4690*/ 196547, /*GILLT_s64*//*Label 4691*/ 196574, // Label 4689: @196520 GIM_Try, /*On fail goto*//*Label 4693*/ 196546, // Rule ID 1633 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (AArch64uitof:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (UCVTFv1i16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv1i16, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1633, GIR_Done, // Label 4693: @196546 GIM_Reject, // Label 4690: @196547 GIM_Try, /*On fail goto*//*Label 4694*/ 196573, // Rule ID 1632 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (AArch64uitof:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (UCVTFv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv1i32, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1632, GIR_Done, // Label 4694: @196573 GIM_Reject, // Label 4691: @196574 GIM_Try, /*On fail goto*//*Label 4695*/ 196600, // Rule ID 1631 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (AArch64uitof:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (UCVTFv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_AddImplicitUse, /*InsnID*/0, AArch64::FPCR, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1631, GIR_Done, // Label 4695: @196600 GIM_Reject, // Label 4692: @196601 GIM_Reject, // Label 113: @196602 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 22, /*)*//*default:*//*Label 4704*/ 196966, /*GILLT_v2s32*//*Label 4696*/ 196626, /*GILLT_v2s64*//*Label 4697*/ 196672, /*GILLT_v4s16*//*Label 4698*/ 196718, /*GILLT_v4s32*//*Label 4699*/ 196775, /*GILLT_v8s8*//*Label 4700*/ 196821, /*GILLT_v8s16*//*Label 4701*/ 196853, /*GILLT_v16s8*//*Label 4702*/ 196910, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*GILLT_nxv16s1*//*Label 4703*/ 196942, // Label 4696: @196626 GIM_Try, /*On fail goto*//*Label 4705*/ 196671, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4706*/ 196659, // Rule ID 1852 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp1:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UZP1v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1852, GIR_Done, // Label 4706: @196659 GIM_Try, /*On fail goto*//*Label 4707*/ 196670, // Rule ID 8891 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp1:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (UZP1v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8891, GIR_Done, // Label 4707: @196670 GIM_Reject, // Label 4705: @196671 GIM_Reject, // Label 4697: @196672 GIM_Try, /*On fail goto*//*Label 4708*/ 196717, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4709*/ 196705, // Rule ID 1854 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UZP1v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1854, GIR_Done, // Label 4709: @196705 GIM_Try, /*On fail goto*//*Label 4710*/ 196716, // Rule ID 8893 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp1:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (UZP1v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8893, GIR_Done, // Label 4710: @196716 GIM_Reject, // Label 4708: @196717 GIM_Reject, // Label 4698: @196718 GIM_Try, /*On fail goto*//*Label 4711*/ 196774, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4712*/ 196751, // Rule ID 1850 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp1:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UZP1v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1850, GIR_Done, // Label 4712: @196751 GIM_Try, /*On fail goto*//*Label 4713*/ 196762, // Rule ID 8887 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp1:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (UZP1v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8887, GIR_Done, // Label 4713: @196762 GIM_Try, /*On fail goto*//*Label 4714*/ 196773, // Rule ID 8888 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp1:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) => (UZP1v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8888, GIR_Done, // Label 4714: @196773 GIM_Reject, // Label 4711: @196774 GIM_Reject, // Label 4699: @196775 GIM_Try, /*On fail goto*//*Label 4715*/ 196820, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4716*/ 196808, // Rule ID 1853 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UZP1v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1853, GIR_Done, // Label 4716: @196808 GIM_Try, /*On fail goto*//*Label 4717*/ 196819, // Rule ID 8892 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp1:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (UZP1v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8892, GIR_Done, // Label 4717: @196819 GIM_Reject, // Label 4715: @196820 GIM_Reject, // Label 4700: @196821 GIM_Try, /*On fail goto*//*Label 4718*/ 196852, // Rule ID 1848 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (AArch64uzp1:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UZP1v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1848, GIR_Done, // Label 4718: @196852 GIM_Reject, // Label 4701: @196853 GIM_Try, /*On fail goto*//*Label 4719*/ 196909, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4720*/ 196886, // Rule ID 1851 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp1:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UZP1v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1851, GIR_Done, // Label 4720: @196886 GIM_Try, /*On fail goto*//*Label 4721*/ 196897, // Rule ID 8889 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp1:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (UZP1v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8889, GIR_Done, // Label 4721: @196897 GIM_Try, /*On fail goto*//*Label 4722*/ 196908, // Rule ID 8890 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp1:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (UZP1v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8890, GIR_Done, // Label 4722: @196908 GIM_Reject, // Label 4719: @196909 GIM_Reject, // Label 4702: @196910 GIM_Try, /*On fail goto*//*Label 4723*/ 196941, // Rule ID 1849 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (AArch64uzp1:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UZP1v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1849, GIR_Done, // Label 4723: @196941 GIM_Reject, // Label 4703: @196942 GIM_Try, /*On fail goto*//*Label 4724*/ 196965, // Rule ID 2274 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (AArch64uzp1:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP1_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1_PPP_B, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2274, GIR_Done, // Label 4724: @196965 GIM_Reject, // Label 4704: @196966 GIM_Reject, // Label 114: @196967 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 22, /*)*//*default:*//*Label 4733*/ 197331, /*GILLT_v2s32*//*Label 4725*/ 196991, /*GILLT_v2s64*//*Label 4726*/ 197037, /*GILLT_v4s16*//*Label 4727*/ 197083, /*GILLT_v4s32*//*Label 4728*/ 197140, /*GILLT_v8s8*//*Label 4729*/ 197186, /*GILLT_v8s16*//*Label 4730*/ 197218, /*GILLT_v16s8*//*Label 4731*/ 197275, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*GILLT_nxv16s1*//*Label 4732*/ 197307, // Label 4725: @196991 GIM_Try, /*On fail goto*//*Label 4734*/ 197036, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4735*/ 197024, // Rule ID 1859 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp2:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UZP2v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1859, GIR_Done, // Label 4735: @197024 GIM_Try, /*On fail goto*//*Label 4736*/ 197035, // Rule ID 8898 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp2:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (UZP2v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8898, GIR_Done, // Label 4736: @197035 GIM_Reject, // Label 4734: @197036 GIM_Reject, // Label 4726: @197037 GIM_Try, /*On fail goto*//*Label 4737*/ 197082, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4738*/ 197070, // Rule ID 1861 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UZP2v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1861, GIR_Done, // Label 4738: @197070 GIM_Try, /*On fail goto*//*Label 4739*/ 197081, // Rule ID 8900 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp2:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (UZP2v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8900, GIR_Done, // Label 4739: @197081 GIM_Reject, // Label 4737: @197082 GIM_Reject, // Label 4727: @197083 GIM_Try, /*On fail goto*//*Label 4740*/ 197139, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4741*/ 197116, // Rule ID 1857 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp2:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UZP2v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1857, GIR_Done, // Label 4741: @197116 GIM_Try, /*On fail goto*//*Label 4742*/ 197127, // Rule ID 8894 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp2:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (UZP2v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8894, GIR_Done, // Label 4742: @197127 GIM_Try, /*On fail goto*//*Label 4743*/ 197138, // Rule ID 8895 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp2:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) => (UZP2v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8895, GIR_Done, // Label 4743: @197138 GIM_Reject, // Label 4740: @197139 GIM_Reject, // Label 4728: @197140 GIM_Try, /*On fail goto*//*Label 4744*/ 197185, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4745*/ 197173, // Rule ID 1860 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UZP2v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1860, GIR_Done, // Label 4745: @197173 GIM_Try, /*On fail goto*//*Label 4746*/ 197184, // Rule ID 8899 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp2:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (UZP2v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8899, GIR_Done, // Label 4746: @197184 GIM_Reject, // Label 4744: @197185 GIM_Reject, // Label 4729: @197186 GIM_Try, /*On fail goto*//*Label 4747*/ 197217, // Rule ID 1855 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (AArch64uzp2:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UZP2v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1855, GIR_Done, // Label 4747: @197217 GIM_Reject, // Label 4730: @197218 GIM_Try, /*On fail goto*//*Label 4748*/ 197274, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4749*/ 197251, // Rule ID 1858 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp2:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UZP2v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1858, GIR_Done, // Label 4749: @197251 GIM_Try, /*On fail goto*//*Label 4750*/ 197262, // Rule ID 8896 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp2:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (UZP2v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8896, GIR_Done, // Label 4750: @197262 GIM_Try, /*On fail goto*//*Label 4751*/ 197273, // Rule ID 8897 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64uzp2:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (UZP2v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8897, GIR_Done, // Label 4751: @197273 GIM_Reject, // Label 4748: @197274 GIM_Reject, // Label 4731: @197275 GIM_Try, /*On fail goto*//*Label 4752*/ 197306, // Rule ID 1856 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (AArch64uzp2:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UZP2v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1856, GIR_Done, // Label 4752: @197306 GIM_Reject, // Label 4732: @197307 GIM_Try, /*On fail goto*//*Label 4753*/ 197330, // Rule ID 2278 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (AArch64uzp2:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP2_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2_PPP_B, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2278, GIR_Done, // Label 4753: @197330 GIM_Reject, // Label 4733: @197331 GIM_Reject, // Label 115: @197332 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 11, /*)*//*default:*//*Label 4762*/ 197966, /*GILLT_s64*//*Label 4754*/ 197347, 0, /*GILLT_v2s32*//*Label 4755*/ 197455, /*GILLT_v2s64*//*Label 4756*/ 197528, /*GILLT_v4s16*//*Label 4757*/ 197601, /*GILLT_v4s32*//*Label 4758*/ 197674, /*GILLT_v8s8*//*Label 4759*/ 197747, /*GILLT_v8s16*//*Label 4760*/ 197820, /*GILLT_v16s8*//*Label 4761*/ 197893, // Label 4754: @197347 GIM_Try, /*On fail goto*//*Label 4763*/ 197454, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4764*/ 197383, // Rule ID 8719 // // MIs[0] Operand 2 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, 63, // (AArch64vashr:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, 63:{ *:[i32] }) => (CMLTv1i64rz:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CMLTv1i64rz, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8719, GIR_Done, // Label 4764: @197383 GIM_Try, /*On fail goto*//*Label 4765*/ 197418, // Rule ID 2036 // GIM_CheckFeatures, GIFBS_HasNEON, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vashr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SSHRd:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2036, GIR_Done, // Label 4765: @197418 GIM_Try, /*On fail goto*//*Label 4766*/ 197453, // Rule ID 9437 // GIM_CheckFeatures, GIFBS_HasNEON, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SSHRd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9437, GIR_Done, // Label 4766: @197453 GIM_Reject, // Label 4763: @197454 GIM_Reject, // Label 4755: @197455 GIM_Try, /*On fail goto*//*Label 4767*/ 197527, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4768*/ 197491, // Rule ID 8516 // // MIs[0] Operand 2 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, 31, // (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, 31:{ *:[i32] }) => (CMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CMLTv2i32rz, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8516, GIR_Done, // Label 4768: @197491 GIM_Try, /*On fail goto*//*Label 4769*/ 197526, // Rule ID 2140 // GIM_CheckFeatures, GIFBS_HasNEON, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SSHRv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2140, GIR_Done, // Label 4769: @197526 GIM_Reject, // Label 4767: @197527 GIM_Reject, // Label 4756: @197528 GIM_Try, /*On fail goto*//*Label 4770*/ 197600, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4771*/ 197564, // Rule ID 8520 // // MIs[0] Operand 2 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, 63, // (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, 63:{ *:[i32] }) => (CMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CMLTv2i64rz, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8520, GIR_Done, // Label 4771: @197564 GIM_Try, /*On fail goto*//*Label 4772*/ 197599, // Rule ID 2142 // GIM_CheckFeatures, GIFBS_HasNEON, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SSHRv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2142, GIR_Done, // Label 4772: @197599 GIM_Reject, // Label 4770: @197600 GIM_Reject, // Label 4757: @197601 GIM_Try, /*On fail goto*//*Label 4773*/ 197673, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4774*/ 197637, // Rule ID 8515 // // MIs[0] Operand 2 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, 15, // (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, 15:{ *:[i32] }) => (CMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CMLTv4i16rz, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8515, GIR_Done, // Label 4774: @197637 GIM_Try, /*On fail goto*//*Label 4775*/ 197672, // Rule ID 2138 // GIM_CheckFeatures, GIFBS_HasNEON, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SSHRv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2138, GIR_Done, // Label 4775: @197672 GIM_Reject, // Label 4773: @197673 GIM_Reject, // Label 4758: @197674 GIM_Try, /*On fail goto*//*Label 4776*/ 197746, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4777*/ 197710, // Rule ID 8519 // // MIs[0] Operand 2 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, 31, // (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, 31:{ *:[i32] }) => (CMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CMLTv4i32rz, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8519, GIR_Done, // Label 4777: @197710 GIM_Try, /*On fail goto*//*Label 4778*/ 197745, // Rule ID 2141 // GIM_CheckFeatures, GIFBS_HasNEON, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SSHRv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2141, GIR_Done, // Label 4778: @197745 GIM_Reject, // Label 4776: @197746 GIM_Reject, // Label 4759: @197747 GIM_Try, /*On fail goto*//*Label 4779*/ 197819, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4780*/ 197783, // Rule ID 8514 // // MIs[0] Operand 2 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, 7, // (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, 7:{ *:[i32] }) => (CMLTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CMLTv8i8rz, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8514, GIR_Done, // Label 4780: @197783 GIM_Try, /*On fail goto*//*Label 4781*/ 197818, // Rule ID 2136 // GIM_CheckFeatures, GIFBS_HasNEON, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SSHRv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2136, GIR_Done, // Label 4781: @197818 GIM_Reject, // Label 4779: @197819 GIM_Reject, // Label 4760: @197820 GIM_Try, /*On fail goto*//*Label 4782*/ 197892, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4783*/ 197856, // Rule ID 8518 // // MIs[0] Operand 2 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, 15, // (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, 15:{ *:[i32] }) => (CMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CMLTv8i16rz, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8518, GIR_Done, // Label 4783: @197856 GIM_Try, /*On fail goto*//*Label 4784*/ 197891, // Rule ID 2139 // GIM_CheckFeatures, GIFBS_HasNEON, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SSHRv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2139, GIR_Done, // Label 4784: @197891 GIM_Reject, // Label 4782: @197892 GIM_Reject, // Label 4761: @197893 GIM_Try, /*On fail goto*//*Label 4785*/ 197965, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4786*/ 197929, // Rule ID 8517 // // MIs[0] Operand 2 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, 7, // (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, 7:{ *:[i32] }) => (CMLTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CMLTv16i8rz, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8517, GIR_Done, // Label 4786: @197929 GIM_Try, /*On fail goto*//*Label 4787*/ 197964, // Rule ID 2137 // GIM_CheckFeatures, GIFBS_HasNEON, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SSHRv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2137, GIR_Done, // Label 4787: @197964 GIM_Reject, // Label 4785: @197965 GIM_Reject, // Label 4762: @197966 GIM_Reject, // Label 116: @197967 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 11, /*)*//*default:*//*Label 4796*/ 198404, /*GILLT_s64*//*Label 4788*/ 197982, 0, /*GILLT_v2s32*//*Label 4789*/ 198068, /*GILLT_v2s64*//*Label 4790*/ 198116, /*GILLT_v4s16*//*Label 4791*/ 198164, /*GILLT_v4s32*//*Label 4792*/ 198212, /*GILLT_v8s8*//*Label 4793*/ 198260, /*GILLT_v8s16*//*Label 4794*/ 198308, /*GILLT_v16s8*//*Label 4795*/ 198356, // Label 4788: @197982 GIM_Try, /*On fail goto*//*Label 4797*/ 198067, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4798*/ 198031, // Rule ID 2045 // GIM_CheckFeatures, GIFBS_HasNEON, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vlshr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (USHRd:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2045, GIR_Done, // Label 4798: @198031 GIM_Try, /*On fail goto*//*Label 4799*/ 198066, // Rule ID 9443 // GIM_CheckFeatures, GIFBS_HasNEON, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (USHRd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 9443, GIR_Done, // Label 4799: @198066 GIM_Reject, // Label 4797: @198067 GIM_Reject, // Label 4789: @198068 GIM_Try, /*On fail goto*//*Label 4800*/ 198115, // Rule ID 2199 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (USHRv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2199, GIR_Done, // Label 4800: @198115 GIM_Reject, // Label 4790: @198116 GIM_Try, /*On fail goto*//*Label 4801*/ 198163, // Rule ID 2201 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (USHRv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2201, GIR_Done, // Label 4801: @198163 GIM_Reject, // Label 4791: @198164 GIM_Try, /*On fail goto*//*Label 4802*/ 198211, // Rule ID 2197 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (USHRv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2197, GIR_Done, // Label 4802: @198211 GIM_Reject, // Label 4792: @198212 GIM_Try, /*On fail goto*//*Label 4803*/ 198259, // Rule ID 2200 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (USHRv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2200, GIR_Done, // Label 4803: @198259 GIM_Reject, // Label 4793: @198260 GIM_Try, /*On fail goto*//*Label 4804*/ 198307, // Rule ID 2195 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (USHRv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2195, GIR_Done, // Label 4804: @198307 GIM_Reject, // Label 4794: @198308 GIM_Try, /*On fail goto*//*Label 4805*/ 198355, // Rule ID 2198 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (USHRv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2198, GIR_Done, // Label 4805: @198355 GIM_Reject, // Label 4795: @198356 GIM_Try, /*On fail goto*//*Label 4806*/ 198403, // Rule ID 2196 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // MIs[0] imm GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (USHRv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2196, GIR_Done, // Label 4806: @198403 GIM_Reject, // Label 4796: @198404 GIM_Reject, // Label 117: @198405 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 22, /*)*//*default:*//*Label 4815*/ 198769, /*GILLT_v2s32*//*Label 4807*/ 198429, /*GILLT_v2s64*//*Label 4808*/ 198475, /*GILLT_v4s16*//*Label 4809*/ 198521, /*GILLT_v4s32*//*Label 4810*/ 198578, /*GILLT_v8s8*//*Label 4811*/ 198624, /*GILLT_v8s16*//*Label 4812*/ 198656, /*GILLT_v16s8*//*Label 4813*/ 198713, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*GILLT_nxv16s1*//*Label 4814*/ 198745, // Label 4807: @198429 GIM_Try, /*On fail goto*//*Label 4816*/ 198474, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4817*/ 198462, // Rule ID 1866 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip1:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ZIP1v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1866, GIR_Done, // Label 4817: @198462 GIM_Try, /*On fail goto*//*Label 4818*/ 198473, // Rule ID 8905 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip1:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (ZIP1v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8905, GIR_Done, // Label 4818: @198473 GIM_Reject, // Label 4816: @198474 GIM_Reject, // Label 4808: @198475 GIM_Try, /*On fail goto*//*Label 4819*/ 198520, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4820*/ 198508, // Rule ID 1868 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ZIP1v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1868, GIR_Done, // Label 4820: @198508 GIM_Try, /*On fail goto*//*Label 4821*/ 198519, // Rule ID 8907 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip1:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (ZIP1v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8907, GIR_Done, // Label 4821: @198519 GIM_Reject, // Label 4819: @198520 GIM_Reject, // Label 4809: @198521 GIM_Try, /*On fail goto*//*Label 4822*/ 198577, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4823*/ 198554, // Rule ID 1864 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip1:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ZIP1v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1864, GIR_Done, // Label 4823: @198554 GIM_Try, /*On fail goto*//*Label 4824*/ 198565, // Rule ID 8901 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip1:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (ZIP1v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8901, GIR_Done, // Label 4824: @198565 GIM_Try, /*On fail goto*//*Label 4825*/ 198576, // Rule ID 8902 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip1:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) => (ZIP1v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8902, GIR_Done, // Label 4825: @198576 GIM_Reject, // Label 4822: @198577 GIM_Reject, // Label 4810: @198578 GIM_Try, /*On fail goto*//*Label 4826*/ 198623, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4827*/ 198611, // Rule ID 1867 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ZIP1v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1867, GIR_Done, // Label 4827: @198611 GIM_Try, /*On fail goto*//*Label 4828*/ 198622, // Rule ID 8906 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip1:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (ZIP1v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8906, GIR_Done, // Label 4828: @198622 GIM_Reject, // Label 4826: @198623 GIM_Reject, // Label 4811: @198624 GIM_Try, /*On fail goto*//*Label 4829*/ 198655, // Rule ID 1862 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (AArch64zip1:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ZIP1v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1862, GIR_Done, // Label 4829: @198655 GIM_Reject, // Label 4812: @198656 GIM_Try, /*On fail goto*//*Label 4830*/ 198712, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4831*/ 198689, // Rule ID 1865 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip1:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ZIP1v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1865, GIR_Done, // Label 4831: @198689 GIM_Try, /*On fail goto*//*Label 4832*/ 198700, // Rule ID 8903 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip1:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (ZIP1v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8903, GIR_Done, // Label 4832: @198700 GIM_Try, /*On fail goto*//*Label 4833*/ 198711, // Rule ID 8904 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip1:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (ZIP1v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8904, GIR_Done, // Label 4833: @198711 GIM_Reject, // Label 4830: @198712 GIM_Reject, // Label 4813: @198713 GIM_Try, /*On fail goto*//*Label 4834*/ 198744, // Rule ID 1863 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (AArch64zip1:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ZIP1v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1863, GIR_Done, // Label 4834: @198744 GIM_Reject, // Label 4814: @198745 GIM_Try, /*On fail goto*//*Label 4835*/ 198768, // Rule ID 2266 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (AArch64zip1:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP1_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1_PPP_B, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2266, GIR_Done, // Label 4835: @198768 GIM_Reject, // Label 4815: @198769 GIM_Reject, // Label 118: @198770 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 22, /*)*//*default:*//*Label 4844*/ 199134, /*GILLT_v2s32*//*Label 4836*/ 198794, /*GILLT_v2s64*//*Label 4837*/ 198840, /*GILLT_v4s16*//*Label 4838*/ 198886, /*GILLT_v4s32*//*Label 4839*/ 198943, /*GILLT_v8s8*//*Label 4840*/ 198989, /*GILLT_v8s16*//*Label 4841*/ 199021, /*GILLT_v16s8*//*Label 4842*/ 199078, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*GILLT_nxv16s1*//*Label 4843*/ 199110, // Label 4836: @198794 GIM_Try, /*On fail goto*//*Label 4845*/ 198839, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4846*/ 198827, // Rule ID 1873 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip2:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ZIP2v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1873, GIR_Done, // Label 4846: @198827 GIM_Try, /*On fail goto*//*Label 4847*/ 198838, // Rule ID 8912 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip2:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (ZIP2v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8912, GIR_Done, // Label 4847: @198838 GIM_Reject, // Label 4845: @198839 GIM_Reject, // Label 4837: @198840 GIM_Try, /*On fail goto*//*Label 4848*/ 198885, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4849*/ 198873, // Rule ID 1875 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ZIP2v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1875, GIR_Done, // Label 4849: @198873 GIM_Try, /*On fail goto*//*Label 4850*/ 198884, // Rule ID 8914 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip2:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (ZIP2v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8914, GIR_Done, // Label 4850: @198884 GIM_Reject, // Label 4848: @198885 GIM_Reject, // Label 4838: @198886 GIM_Try, /*On fail goto*//*Label 4851*/ 198942, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 4852*/ 198919, // Rule ID 1871 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip2:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ZIP2v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1871, GIR_Done, // Label 4852: @198919 GIM_Try, /*On fail goto*//*Label 4853*/ 198930, // Rule ID 8908 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip2:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (ZIP2v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8908, GIR_Done, // Label 4853: @198930 GIM_Try, /*On fail goto*//*Label 4854*/ 198941, // Rule ID 8909 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip2:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) => (ZIP2v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8909, GIR_Done, // Label 4854: @198941 GIM_Reject, // Label 4851: @198942 GIM_Reject, // Label 4839: @198943 GIM_Try, /*On fail goto*//*Label 4855*/ 198988, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4856*/ 198976, // Rule ID 1874 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ZIP2v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1874, GIR_Done, // Label 4856: @198976 GIM_Try, /*On fail goto*//*Label 4857*/ 198987, // Rule ID 8913 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip2:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (ZIP2v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8913, GIR_Done, // Label 4857: @198987 GIM_Reject, // Label 4855: @198988 GIM_Reject, // Label 4840: @198989 GIM_Try, /*On fail goto*//*Label 4858*/ 199020, // Rule ID 1869 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (AArch64zip2:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ZIP2v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1869, GIR_Done, // Label 4858: @199020 GIM_Reject, // Label 4841: @199021 GIM_Try, /*On fail goto*//*Label 4859*/ 199077, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 4860*/ 199054, // Rule ID 1872 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip2:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ZIP2v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1872, GIR_Done, // Label 4860: @199054 GIM_Try, /*On fail goto*//*Label 4861*/ 199065, // Rule ID 8910 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip2:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (ZIP2v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8910, GIR_Done, // Label 4861: @199065 GIM_Try, /*On fail goto*//*Label 4862*/ 199076, // Rule ID 8911 // GIM_CheckFeatures, GIFBS_HasNEON, // (AArch64zip2:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (ZIP2v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 8911, GIR_Done, // Label 4862: @199076 GIM_Reject, // Label 4859: @199077 GIM_Reject, // Label 4842: @199078 GIM_Try, /*On fail goto*//*Label 4863*/ 199109, // Rule ID 1870 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (AArch64zip2:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ZIP2v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1870, GIR_Done, // Label 4863: @199109 GIM_Reject, // Label 4843: @199110 GIM_Try, /*On fail goto*//*Label 4864*/ 199133, // Rule ID 2270 // GIM_CheckFeatures, GIFBS_HasSVEorSME, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::PPRRegClassID, // (AArch64zip2:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP2_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2_PPP_B, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2270, GIR_Done, // Label 4864: @199133 GIM_Reject, // Label 4844: @199134 GIM_Reject, // Label 119: @199135 GIM_Reject, }; return MatchTable0; } #endif // ifdef GET_GLOBALISEL_IMPL #ifdef GET_GLOBALISEL_PREDICATES_DECL PredicateBitset AvailableModuleFeatures; mutable PredicateBitset AvailableFunctionFeatures; PredicateBitset getAvailableFeatures() const { return AvailableModuleFeatures | AvailableFunctionFeatures; } PredicateBitset computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const; PredicateBitset computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, const MachineFunction *MF) const; void setupGeneratedPerFunctionState(MachineFunction &MF) override; #endif // ifdef GET_GLOBALISEL_PREDICATES_DECL #ifdef GET_GLOBALISEL_PREDICATES_INIT AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), AvailableFunctionFeatures() #endif // ifdef GET_GLOBALISEL_PREDICATES_INIT