/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM namespace llvm { namespace Mips { enum { PHI = 0, INLINEASM = 1, INLINEASM_BR = 2, CFI_INSTRUCTION = 3, EH_LABEL = 4, GC_LABEL = 5, ANNOTATION_LABEL = 6, KILL = 7, EXTRACT_SUBREG = 8, INSERT_SUBREG = 9, IMPLICIT_DEF = 10, SUBREG_TO_REG = 11, COPY_TO_REGCLASS = 12, DBG_VALUE = 13, DBG_VALUE_LIST = 14, DBG_INSTR_REF = 15, DBG_PHI = 16, DBG_LABEL = 17, REG_SEQUENCE = 18, COPY = 19, BUNDLE = 20, LIFETIME_START = 21, LIFETIME_END = 22, PSEUDO_PROBE = 23, ARITH_FENCE = 24, STACKMAP = 25, FENTRY_CALL = 26, PATCHPOINT = 27, LOAD_STACK_GUARD = 28, PREALLOCATED_SETUP = 29, PREALLOCATED_ARG = 30, STATEPOINT = 31, LOCAL_ESCAPE = 32, FAULTING_OP = 33, PATCHABLE_OP = 34, PATCHABLE_FUNCTION_ENTER = 35, PATCHABLE_RET = 36, PATCHABLE_FUNCTION_EXIT = 37, PATCHABLE_TAIL_CALL = 38, PATCHABLE_EVENT_CALL = 39, PATCHABLE_TYPED_EVENT_CALL = 40, ICALL_BRANCH_FUNNEL = 41, MEMBARRIER = 42, G_ASSERT_SEXT = 43, G_ASSERT_ZEXT = 44, G_ASSERT_ALIGN = 45, G_ADD = 46, G_SUB = 47, G_MUL = 48, G_SDIV = 49, G_UDIV = 50, G_SREM = 51, G_UREM = 52, G_SDIVREM = 53, G_UDIVREM = 54, G_AND = 55, G_OR = 56, G_XOR = 57, G_IMPLICIT_DEF = 58, G_PHI = 59, G_FRAME_INDEX = 60, G_GLOBAL_VALUE = 61, G_EXTRACT = 62, G_UNMERGE_VALUES = 63, G_INSERT = 64, G_MERGE_VALUES = 65, G_BUILD_VECTOR = 66, G_BUILD_VECTOR_TRUNC = 67, G_CONCAT_VECTORS = 68, G_PTRTOINT = 69, G_INTTOPTR = 70, G_BITCAST = 71, G_FREEZE = 72, G_INTRINSIC_FPTRUNC_ROUND = 73, G_INTRINSIC_TRUNC = 74, G_INTRINSIC_ROUND = 75, G_INTRINSIC_LRINT = 76, G_INTRINSIC_ROUNDEVEN = 77, G_READCYCLECOUNTER = 78, G_LOAD = 79, G_SEXTLOAD = 80, G_ZEXTLOAD = 81, G_INDEXED_LOAD = 82, G_INDEXED_SEXTLOAD = 83, G_INDEXED_ZEXTLOAD = 84, G_STORE = 85, G_INDEXED_STORE = 86, G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87, G_ATOMIC_CMPXCHG = 88, G_ATOMICRMW_XCHG = 89, G_ATOMICRMW_ADD = 90, G_ATOMICRMW_SUB = 91, G_ATOMICRMW_AND = 92, G_ATOMICRMW_NAND = 93, G_ATOMICRMW_OR = 94, G_ATOMICRMW_XOR = 95, G_ATOMICRMW_MAX = 96, G_ATOMICRMW_MIN = 97, G_ATOMICRMW_UMAX = 98, G_ATOMICRMW_UMIN = 99, G_ATOMICRMW_FADD = 100, G_ATOMICRMW_FSUB = 101, G_ATOMICRMW_FMAX = 102, G_ATOMICRMW_FMIN = 103, G_ATOMICRMW_UINC_WRAP = 104, G_ATOMICRMW_UDEC_WRAP = 105, G_FENCE = 106, G_BRCOND = 107, G_BRINDIRECT = 108, G_INVOKE_REGION_START = 109, G_INTRINSIC = 110, G_INTRINSIC_W_SIDE_EFFECTS = 111, G_ANYEXT = 112, G_TRUNC = 113, G_CONSTANT = 114, G_FCONSTANT = 115, G_VASTART = 116, G_VAARG = 117, G_SEXT = 118, G_SEXT_INREG = 119, G_ZEXT = 120, G_SHL = 121, G_LSHR = 122, G_ASHR = 123, G_FSHL = 124, G_FSHR = 125, G_ROTR = 126, G_ROTL = 127, G_ICMP = 128, G_FCMP = 129, G_SELECT = 130, G_UADDO = 131, G_UADDE = 132, G_USUBO = 133, G_USUBE = 134, G_SADDO = 135, G_SADDE = 136, G_SSUBO = 137, G_SSUBE = 138, G_UMULO = 139, G_SMULO = 140, G_UMULH = 141, G_SMULH = 142, G_UADDSAT = 143, G_SADDSAT = 144, G_USUBSAT = 145, G_SSUBSAT = 146, G_USHLSAT = 147, G_SSHLSAT = 148, G_SMULFIX = 149, G_UMULFIX = 150, G_SMULFIXSAT = 151, G_UMULFIXSAT = 152, G_SDIVFIX = 153, G_UDIVFIX = 154, G_SDIVFIXSAT = 155, G_UDIVFIXSAT = 156, G_FADD = 157, G_FSUB = 158, G_FMUL = 159, G_FMA = 160, G_FMAD = 161, G_FDIV = 162, G_FREM = 163, G_FPOW = 164, G_FPOWI = 165, G_FEXP = 166, G_FEXP2 = 167, G_FLOG = 168, G_FLOG2 = 169, G_FLOG10 = 170, G_FNEG = 171, G_FPEXT = 172, G_FPTRUNC = 173, G_FPTOSI = 174, G_FPTOUI = 175, G_SITOFP = 176, G_UITOFP = 177, G_FABS = 178, G_FCOPYSIGN = 179, G_IS_FPCLASS = 180, G_FCANONICALIZE = 181, G_FMINNUM = 182, G_FMAXNUM = 183, G_FMINNUM_IEEE = 184, G_FMAXNUM_IEEE = 185, G_FMINIMUM = 186, G_FMAXIMUM = 187, G_PTR_ADD = 188, G_PTRMASK = 189, G_SMIN = 190, G_SMAX = 191, G_UMIN = 192, G_UMAX = 193, G_ABS = 194, G_LROUND = 195, G_LLROUND = 196, G_BR = 197, G_BRJT = 198, G_INSERT_VECTOR_ELT = 199, G_EXTRACT_VECTOR_ELT = 200, G_SHUFFLE_VECTOR = 201, G_CTTZ = 202, G_CTTZ_ZERO_UNDEF = 203, G_CTLZ = 204, G_CTLZ_ZERO_UNDEF = 205, G_CTPOP = 206, G_BSWAP = 207, G_BITREVERSE = 208, G_FCEIL = 209, G_FCOS = 210, G_FSIN = 211, G_FSQRT = 212, G_FFLOOR = 213, G_FRINT = 214, G_FNEARBYINT = 215, G_ADDRSPACE_CAST = 216, G_BLOCK_ADDR = 217, G_JUMP_TABLE = 218, G_DYN_STACKALLOC = 219, G_STRICT_FADD = 220, G_STRICT_FSUB = 221, G_STRICT_FMUL = 222, G_STRICT_FDIV = 223, G_STRICT_FREM = 224, G_STRICT_FMA = 225, G_STRICT_FSQRT = 226, G_READ_REGISTER = 227, G_WRITE_REGISTER = 228, G_MEMCPY = 229, G_MEMCPY_INLINE = 230, G_MEMMOVE = 231, G_MEMSET = 232, G_BZERO = 233, G_VECREDUCE_SEQ_FADD = 234, G_VECREDUCE_SEQ_FMUL = 235, G_VECREDUCE_FADD = 236, G_VECREDUCE_FMUL = 237, G_VECREDUCE_FMAX = 238, G_VECREDUCE_FMIN = 239, G_VECREDUCE_ADD = 240, G_VECREDUCE_MUL = 241, G_VECREDUCE_AND = 242, G_VECREDUCE_OR = 243, G_VECREDUCE_XOR = 244, G_VECREDUCE_SMAX = 245, G_VECREDUCE_SMIN = 246, G_VECREDUCE_UMAX = 247, G_VECREDUCE_UMIN = 248, G_SBFX = 249, G_UBFX = 250, ABSMacro = 251, ADJCALLSTACKDOWN = 252, ADJCALLSTACKUP = 253, AND_V_D_PSEUDO = 254, AND_V_H_PSEUDO = 255, AND_V_W_PSEUDO = 256, ATOMIC_CMP_SWAP_I16 = 257, ATOMIC_CMP_SWAP_I16_POSTRA = 258, ATOMIC_CMP_SWAP_I32 = 259, ATOMIC_CMP_SWAP_I32_POSTRA = 260, ATOMIC_CMP_SWAP_I64 = 261, ATOMIC_CMP_SWAP_I64_POSTRA = 262, ATOMIC_CMP_SWAP_I8 = 263, ATOMIC_CMP_SWAP_I8_POSTRA = 264, ATOMIC_LOAD_ADD_I16 = 265, ATOMIC_LOAD_ADD_I16_POSTRA = 266, ATOMIC_LOAD_ADD_I32 = 267, ATOMIC_LOAD_ADD_I32_POSTRA = 268, ATOMIC_LOAD_ADD_I64 = 269, ATOMIC_LOAD_ADD_I64_POSTRA = 270, ATOMIC_LOAD_ADD_I8 = 271, ATOMIC_LOAD_ADD_I8_POSTRA = 272, ATOMIC_LOAD_AND_I16 = 273, ATOMIC_LOAD_AND_I16_POSTRA = 274, ATOMIC_LOAD_AND_I32 = 275, ATOMIC_LOAD_AND_I32_POSTRA = 276, ATOMIC_LOAD_AND_I64 = 277, ATOMIC_LOAD_AND_I64_POSTRA = 278, ATOMIC_LOAD_AND_I8 = 279, ATOMIC_LOAD_AND_I8_POSTRA = 280, ATOMIC_LOAD_MAX_I16 = 281, ATOMIC_LOAD_MAX_I16_POSTRA = 282, ATOMIC_LOAD_MAX_I32 = 283, ATOMIC_LOAD_MAX_I32_POSTRA = 284, ATOMIC_LOAD_MAX_I64 = 285, ATOMIC_LOAD_MAX_I64_POSTRA = 286, ATOMIC_LOAD_MAX_I8 = 287, ATOMIC_LOAD_MAX_I8_POSTRA = 288, ATOMIC_LOAD_MIN_I16 = 289, ATOMIC_LOAD_MIN_I16_POSTRA = 290, ATOMIC_LOAD_MIN_I32 = 291, ATOMIC_LOAD_MIN_I32_POSTRA = 292, ATOMIC_LOAD_MIN_I64 = 293, ATOMIC_LOAD_MIN_I64_POSTRA = 294, ATOMIC_LOAD_MIN_I8 = 295, ATOMIC_LOAD_MIN_I8_POSTRA = 296, ATOMIC_LOAD_NAND_I16 = 297, ATOMIC_LOAD_NAND_I16_POSTRA = 298, ATOMIC_LOAD_NAND_I32 = 299, ATOMIC_LOAD_NAND_I32_POSTRA = 300, ATOMIC_LOAD_NAND_I64 = 301, ATOMIC_LOAD_NAND_I64_POSTRA = 302, ATOMIC_LOAD_NAND_I8 = 303, ATOMIC_LOAD_NAND_I8_POSTRA = 304, ATOMIC_LOAD_OR_I16 = 305, ATOMIC_LOAD_OR_I16_POSTRA = 306, ATOMIC_LOAD_OR_I32 = 307, ATOMIC_LOAD_OR_I32_POSTRA = 308, ATOMIC_LOAD_OR_I64 = 309, ATOMIC_LOAD_OR_I64_POSTRA = 310, ATOMIC_LOAD_OR_I8 = 311, ATOMIC_LOAD_OR_I8_POSTRA = 312, ATOMIC_LOAD_SUB_I16 = 313, ATOMIC_LOAD_SUB_I16_POSTRA = 314, ATOMIC_LOAD_SUB_I32 = 315, ATOMIC_LOAD_SUB_I32_POSTRA = 316, ATOMIC_LOAD_SUB_I64 = 317, ATOMIC_LOAD_SUB_I64_POSTRA = 318, ATOMIC_LOAD_SUB_I8 = 319, ATOMIC_LOAD_SUB_I8_POSTRA = 320, ATOMIC_LOAD_UMAX_I16 = 321, ATOMIC_LOAD_UMAX_I16_POSTRA = 322, ATOMIC_LOAD_UMAX_I32 = 323, ATOMIC_LOAD_UMAX_I32_POSTRA = 324, ATOMIC_LOAD_UMAX_I64 = 325, ATOMIC_LOAD_UMAX_I64_POSTRA = 326, ATOMIC_LOAD_UMAX_I8 = 327, ATOMIC_LOAD_UMAX_I8_POSTRA = 328, ATOMIC_LOAD_UMIN_I16 = 329, ATOMIC_LOAD_UMIN_I16_POSTRA = 330, ATOMIC_LOAD_UMIN_I32 = 331, ATOMIC_LOAD_UMIN_I32_POSTRA = 332, ATOMIC_LOAD_UMIN_I64 = 333, ATOMIC_LOAD_UMIN_I64_POSTRA = 334, ATOMIC_LOAD_UMIN_I8 = 335, ATOMIC_LOAD_UMIN_I8_POSTRA = 336, ATOMIC_LOAD_XOR_I16 = 337, ATOMIC_LOAD_XOR_I16_POSTRA = 338, ATOMIC_LOAD_XOR_I32 = 339, ATOMIC_LOAD_XOR_I32_POSTRA = 340, ATOMIC_LOAD_XOR_I64 = 341, ATOMIC_LOAD_XOR_I64_POSTRA = 342, ATOMIC_LOAD_XOR_I8 = 343, ATOMIC_LOAD_XOR_I8_POSTRA = 344, ATOMIC_SWAP_I16 = 345, ATOMIC_SWAP_I16_POSTRA = 346, ATOMIC_SWAP_I32 = 347, ATOMIC_SWAP_I32_POSTRA = 348, ATOMIC_SWAP_I64 = 349, ATOMIC_SWAP_I64_POSTRA = 350, ATOMIC_SWAP_I8 = 351, ATOMIC_SWAP_I8_POSTRA = 352, B = 353, BAL_BR = 354, BAL_BR_MM = 355, BEQLImmMacro = 356, BGE = 357, BGEImmMacro = 358, BGEL = 359, BGELImmMacro = 360, BGEU = 361, BGEUImmMacro = 362, BGEUL = 363, BGEULImmMacro = 364, BGT = 365, BGTImmMacro = 366, BGTL = 367, BGTLImmMacro = 368, BGTU = 369, BGTUImmMacro = 370, BGTUL = 371, BGTULImmMacro = 372, BLE = 373, BLEImmMacro = 374, BLEL = 375, BLELImmMacro = 376, BLEU = 377, BLEUImmMacro = 378, BLEUL = 379, BLEULImmMacro = 380, BLT = 381, BLTImmMacro = 382, BLTL = 383, BLTLImmMacro = 384, BLTU = 385, BLTUImmMacro = 386, BLTUL = 387, BLTULImmMacro = 388, BNELImmMacro = 389, BPOSGE32_PSEUDO = 390, BSEL_D_PSEUDO = 391, BSEL_FD_PSEUDO = 392, BSEL_FW_PSEUDO = 393, BSEL_H_PSEUDO = 394, BSEL_W_PSEUDO = 395, B_MM = 396, B_MMR6_Pseudo = 397, B_MM_Pseudo = 398, BeqImm = 399, BneImm = 400, BteqzT8CmpX16 = 401, BteqzT8CmpiX16 = 402, BteqzT8SltX16 = 403, BteqzT8SltiX16 = 404, BteqzT8SltiuX16 = 405, BteqzT8SltuX16 = 406, BtnezT8CmpX16 = 407, BtnezT8CmpiX16 = 408, BtnezT8SltX16 = 409, BtnezT8SltiX16 = 410, BtnezT8SltiuX16 = 411, BtnezT8SltuX16 = 412, BuildPairF64 = 413, BuildPairF64_64 = 414, CFTC1 = 415, CONSTPOOL_ENTRY = 416, COPY_FD_PSEUDO = 417, COPY_FW_PSEUDO = 418, CTTC1 = 419, Constant32 = 420, DMULImmMacro = 421, DMULMacro = 422, DMULOMacro = 423, DMULOUMacro = 424, DROL = 425, DROLImm = 426, DROR = 427, DRORImm = 428, DSDivIMacro = 429, DSDivMacro = 430, DSRemIMacro = 431, DSRemMacro = 432, DUDivIMacro = 433, DUDivMacro = 434, DURemIMacro = 435, DURemMacro = 436, ERet = 437, ExtractElementF64 = 438, ExtractElementF64_64 = 439, FABS_D = 440, FABS_W = 441, FEXP2_D_1_PSEUDO = 442, FEXP2_W_1_PSEUDO = 443, FILL_FD_PSEUDO = 444, FILL_FW_PSEUDO = 445, GotPrologue16 = 446, INSERT_B_VIDX64_PSEUDO = 447, INSERT_B_VIDX_PSEUDO = 448, INSERT_D_VIDX64_PSEUDO = 449, INSERT_D_VIDX_PSEUDO = 450, INSERT_FD_PSEUDO = 451, INSERT_FD_VIDX64_PSEUDO = 452, INSERT_FD_VIDX_PSEUDO = 453, INSERT_FW_PSEUDO = 454, INSERT_FW_VIDX64_PSEUDO = 455, INSERT_FW_VIDX_PSEUDO = 456, INSERT_H_VIDX64_PSEUDO = 457, INSERT_H_VIDX_PSEUDO = 458, INSERT_W_VIDX64_PSEUDO = 459, INSERT_W_VIDX_PSEUDO = 460, JALR64Pseudo = 461, JALRHB64Pseudo = 462, JALRHBPseudo = 463, JALRPseudo = 464, JAL_MMR6 = 465, JalOneReg = 466, JalTwoReg = 467, LDMacro = 468, LDR_D = 469, LDR_W = 470, LD_F16 = 471, LOAD_ACC128 = 472, LOAD_ACC64 = 473, LOAD_ACC64DSP = 474, LOAD_CCOND_DSP = 475, LONG_BRANCH_ADDiu = 476, LONG_BRANCH_ADDiu2Op = 477, LONG_BRANCH_DADDiu = 478, LONG_BRANCH_DADDiu2Op = 479, LONG_BRANCH_LUi = 480, LONG_BRANCH_LUi2Op = 481, LONG_BRANCH_LUi2Op_64 = 482, LWM_MM = 483, LoadAddrImm32 = 484, LoadAddrImm64 = 485, LoadAddrReg32 = 486, LoadAddrReg64 = 487, LoadImm32 = 488, LoadImm64 = 489, LoadImmDoubleFGR = 490, LoadImmDoubleFGR_32 = 491, LoadImmDoubleGPR = 492, LoadImmSingleFGR = 493, LoadImmSingleGPR = 494, LwConstant32 = 495, MFTACX = 496, MFTC0 = 497, MFTC1 = 498, MFTDSP = 499, MFTGPR = 500, MFTHC1 = 501, MFTHI = 502, MFTLO = 503, MIPSeh_return32 = 504, MIPSeh_return64 = 505, MSA_FP_EXTEND_D_PSEUDO = 506, MSA_FP_EXTEND_W_PSEUDO = 507, MSA_FP_ROUND_D_PSEUDO = 508, MSA_FP_ROUND_W_PSEUDO = 509, MTTACX = 510, MTTC0 = 511, MTTC1 = 512, MTTDSP = 513, MTTGPR = 514, MTTHC1 = 515, MTTHI = 516, MTTLO = 517, MULImmMacro = 518, MULOMacro = 519, MULOUMacro = 520, MultRxRy16 = 521, MultRxRyRz16 = 522, MultuRxRy16 = 523, MultuRxRyRz16 = 524, NOP = 525, NORImm = 526, NORImm64 = 527, NOR_V_D_PSEUDO = 528, NOR_V_H_PSEUDO = 529, NOR_V_W_PSEUDO = 530, OR_V_D_PSEUDO = 531, OR_V_H_PSEUDO = 532, OR_V_W_PSEUDO = 533, PseudoCMPU_EQ_QB = 534, PseudoCMPU_LE_QB = 535, PseudoCMPU_LT_QB = 536, PseudoCMP_EQ_PH = 537, PseudoCMP_LE_PH = 538, PseudoCMP_LT_PH = 539, PseudoCVT_D32_W = 540, PseudoCVT_D64_L = 541, PseudoCVT_D64_W = 542, PseudoCVT_S_L = 543, PseudoCVT_S_W = 544, PseudoDMULT = 545, PseudoDMULTu = 546, PseudoDSDIV = 547, PseudoDUDIV = 548, PseudoD_SELECT_I = 549, PseudoD_SELECT_I64 = 550, PseudoIndirectBranch = 551, PseudoIndirectBranch64 = 552, PseudoIndirectBranch64R6 = 553, PseudoIndirectBranchR6 = 554, PseudoIndirectBranch_MM = 555, PseudoIndirectBranch_MMR6 = 556, PseudoIndirectHazardBranch = 557, PseudoIndirectHazardBranch64 = 558, PseudoIndrectHazardBranch64R6 = 559, PseudoIndrectHazardBranchR6 = 560, PseudoMADD = 561, PseudoMADDU = 562, PseudoMADDU_MM = 563, PseudoMADD_MM = 564, PseudoMFHI = 565, PseudoMFHI64 = 566, PseudoMFHI_MM = 567, PseudoMFLO = 568, PseudoMFLO64 = 569, PseudoMFLO_MM = 570, PseudoMSUB = 571, PseudoMSUBU = 572, PseudoMSUBU_MM = 573, PseudoMSUB_MM = 574, PseudoMTLOHI = 575, PseudoMTLOHI64 = 576, PseudoMTLOHI_DSP = 577, PseudoMTLOHI_MM = 578, PseudoMULT = 579, PseudoMULT_MM = 580, PseudoMULTu = 581, PseudoMULTu_MM = 582, PseudoPICK_PH = 583, PseudoPICK_QB = 584, PseudoReturn = 585, PseudoReturn64 = 586, PseudoSDIV = 587, PseudoSELECTFP_F_D32 = 588, PseudoSELECTFP_F_D64 = 589, PseudoSELECTFP_F_I = 590, PseudoSELECTFP_F_I64 = 591, PseudoSELECTFP_F_S = 592, PseudoSELECTFP_T_D32 = 593, PseudoSELECTFP_T_D64 = 594, PseudoSELECTFP_T_I = 595, PseudoSELECTFP_T_I64 = 596, PseudoSELECTFP_T_S = 597, PseudoSELECT_D32 = 598, PseudoSELECT_D64 = 599, PseudoSELECT_I = 600, PseudoSELECT_I64 = 601, PseudoSELECT_S = 602, PseudoTRUNC_W_D = 603, PseudoTRUNC_W_D32 = 604, PseudoTRUNC_W_S = 605, PseudoUDIV = 606, ROL = 607, ROLImm = 608, ROR = 609, RORImm = 610, RetRA = 611, RetRA16 = 612, SDC1_M1 = 613, SDIV_MM_Pseudo = 614, SDMacro = 615, SDivIMacro = 616, SDivMacro = 617, SEQIMacro = 618, SEQMacro = 619, SGE = 620, SGEImm = 621, SGEImm64 = 622, SGEU = 623, SGEUImm = 624, SGEUImm64 = 625, SGTImm = 626, SGTImm64 = 627, SGTUImm = 628, SGTUImm64 = 629, SLE = 630, SLEImm = 631, SLEImm64 = 632, SLEU = 633, SLEUImm = 634, SLEUImm64 = 635, SLTImm64 = 636, SLTUImm64 = 637, SNEIMacro = 638, SNEMacro = 639, SNZ_B_PSEUDO = 640, SNZ_D_PSEUDO = 641, SNZ_H_PSEUDO = 642, SNZ_V_PSEUDO = 643, SNZ_W_PSEUDO = 644, SRemIMacro = 645, SRemMacro = 646, STORE_ACC128 = 647, STORE_ACC64 = 648, STORE_ACC64DSP = 649, STORE_CCOND_DSP = 650, STR_D = 651, STR_W = 652, ST_F16 = 653, SWM_MM = 654, SZ_B_PSEUDO = 655, SZ_D_PSEUDO = 656, SZ_H_PSEUDO = 657, SZ_V_PSEUDO = 658, SZ_W_PSEUDO = 659, SaaAddr = 660, SaadAddr = 661, SelBeqZ = 662, SelBneZ = 663, SelTBteqZCmp = 664, SelTBteqZCmpi = 665, SelTBteqZSlt = 666, SelTBteqZSlti = 667, SelTBteqZSltiu = 668, SelTBteqZSltu = 669, SelTBtneZCmp = 670, SelTBtneZCmpi = 671, SelTBtneZSlt = 672, SelTBtneZSlti = 673, SelTBtneZSltiu = 674, SelTBtneZSltu = 675, SltCCRxRy16 = 676, SltiCCRxImmX16 = 677, SltiuCCRxImmX16 = 678, SltuCCRxRy16 = 679, SltuRxRyRz16 = 680, TAILCALL = 681, TAILCALL64R6REG = 682, TAILCALLHB64R6REG = 683, TAILCALLHBR6REG = 684, TAILCALLR6REG = 685, TAILCALLREG = 686, TAILCALLREG64 = 687, TAILCALLREGHB = 688, TAILCALLREGHB64 = 689, TAILCALLREG_MM = 690, TAILCALLREG_MMR6 = 691, TAILCALL_MM = 692, TAILCALL_MMR6 = 693, TRAP = 694, TRAP_MM = 695, UDIV_MM_Pseudo = 696, UDivIMacro = 697, UDivMacro = 698, URemIMacro = 699, URemMacro = 700, Ulh = 701, Ulhu = 702, Ulw = 703, Ush = 704, Usw = 705, XOR_V_D_PSEUDO = 706, XOR_V_H_PSEUDO = 707, XOR_V_W_PSEUDO = 708, ABSQ_S_PH = 709, ABSQ_S_PH_MM = 710, ABSQ_S_QB = 711, ABSQ_S_QB_MMR2 = 712, ABSQ_S_W = 713, ABSQ_S_W_MM = 714, ADD = 715, ADDIUPC = 716, ADDIUPC_MM = 717, ADDIUPC_MMR6 = 718, ADDIUR1SP_MM = 719, ADDIUR2_MM = 720, ADDIUS5_MM = 721, ADDIUSP_MM = 722, ADDIU_MMR6 = 723, ADDQH_PH = 724, ADDQH_PH_MMR2 = 725, ADDQH_R_PH = 726, ADDQH_R_PH_MMR2 = 727, ADDQH_R_W = 728, ADDQH_R_W_MMR2 = 729, ADDQH_W = 730, ADDQH_W_MMR2 = 731, ADDQ_PH = 732, ADDQ_PH_MM = 733, ADDQ_S_PH = 734, ADDQ_S_PH_MM = 735, ADDQ_S_W = 736, ADDQ_S_W_MM = 737, ADDR_PS64 = 738, ADDSC = 739, ADDSC_MM = 740, ADDS_A_B = 741, ADDS_A_D = 742, ADDS_A_H = 743, ADDS_A_W = 744, ADDS_S_B = 745, ADDS_S_D = 746, ADDS_S_H = 747, ADDS_S_W = 748, ADDS_U_B = 749, ADDS_U_D = 750, ADDS_U_H = 751, ADDS_U_W = 752, ADDU16_MM = 753, ADDU16_MMR6 = 754, ADDUH_QB = 755, ADDUH_QB_MMR2 = 756, ADDUH_R_QB = 757, ADDUH_R_QB_MMR2 = 758, ADDU_MMR6 = 759, ADDU_PH = 760, ADDU_PH_MMR2 = 761, ADDU_QB = 762, ADDU_QB_MM = 763, ADDU_S_PH = 764, ADDU_S_PH_MMR2 = 765, ADDU_S_QB = 766, ADDU_S_QB_MM = 767, ADDVI_B = 768, ADDVI_D = 769, ADDVI_H = 770, ADDVI_W = 771, ADDV_B = 772, ADDV_D = 773, ADDV_H = 774, ADDV_W = 775, ADDWC = 776, ADDWC_MM = 777, ADD_A_B = 778, ADD_A_D = 779, ADD_A_H = 780, ADD_A_W = 781, ADD_MM = 782, ADD_MMR6 = 783, ADDi = 784, ADDi_MM = 785, ADDiu = 786, ADDiu_MM = 787, ADDu = 788, ADDu_MM = 789, ALIGN = 790, ALIGN_MMR6 = 791, ALUIPC = 792, ALUIPC_MMR6 = 793, AND = 794, AND16_MM = 795, AND16_MMR6 = 796, AND64 = 797, ANDI16_MM = 798, ANDI16_MMR6 = 799, ANDI_B = 800, ANDI_MMR6 = 801, AND_MM = 802, AND_MMR6 = 803, AND_V = 804, ANDi = 805, ANDi64 = 806, ANDi_MM = 807, APPEND = 808, APPEND_MMR2 = 809, ASUB_S_B = 810, ASUB_S_D = 811, ASUB_S_H = 812, ASUB_S_W = 813, ASUB_U_B = 814, ASUB_U_D = 815, ASUB_U_H = 816, ASUB_U_W = 817, AUI = 818, AUIPC = 819, AUIPC_MMR6 = 820, AUI_MMR6 = 821, AVER_S_B = 822, AVER_S_D = 823, AVER_S_H = 824, AVER_S_W = 825, AVER_U_B = 826, AVER_U_D = 827, AVER_U_H = 828, AVER_U_W = 829, AVE_S_B = 830, AVE_S_D = 831, AVE_S_H = 832, AVE_S_W = 833, AVE_U_B = 834, AVE_U_D = 835, AVE_U_H = 836, AVE_U_W = 837, AddiuRxImmX16 = 838, AddiuRxPcImmX16 = 839, AddiuRxRxImm16 = 840, AddiuRxRxImmX16 = 841, AddiuRxRyOffMemX16 = 842, AddiuSpImm16 = 843, AddiuSpImmX16 = 844, AdduRxRyRz16 = 845, AndRxRxRy16 = 846, B16_MM = 847, BADDu = 848, BAL = 849, BALC = 850, BALC_MMR6 = 851, BALIGN = 852, BALIGN_MMR2 = 853, BBIT0 = 854, BBIT032 = 855, BBIT1 = 856, BBIT132 = 857, BC = 858, BC16_MMR6 = 859, BC1EQZ = 860, BC1EQZC_MMR6 = 861, BC1F = 862, BC1FL = 863, BC1F_MM = 864, BC1NEZ = 865, BC1NEZC_MMR6 = 866, BC1T = 867, BC1TL = 868, BC1T_MM = 869, BC2EQZ = 870, BC2EQZC_MMR6 = 871, BC2NEZ = 872, BC2NEZC_MMR6 = 873, BCLRI_B = 874, BCLRI_D = 875, BCLRI_H = 876, BCLRI_W = 877, BCLR_B = 878, BCLR_D = 879, BCLR_H = 880, BCLR_W = 881, BC_MMR6 = 882, BEQ = 883, BEQ64 = 884, BEQC = 885, BEQC64 = 886, BEQC_MMR6 = 887, BEQL = 888, BEQZ16_MM = 889, BEQZALC = 890, BEQZALC_MMR6 = 891, BEQZC = 892, BEQZC16_MMR6 = 893, BEQZC64 = 894, BEQZC_MM = 895, BEQZC_MMR6 = 896, BEQ_MM = 897, BGEC = 898, BGEC64 = 899, BGEC_MMR6 = 900, BGEUC = 901, BGEUC64 = 902, BGEUC_MMR6 = 903, BGEZ = 904, BGEZ64 = 905, BGEZAL = 906, BGEZALC = 907, BGEZALC_MMR6 = 908, BGEZALL = 909, BGEZALS_MM = 910, BGEZAL_MM = 911, BGEZC = 912, BGEZC64 = 913, BGEZC_MMR6 = 914, BGEZL = 915, BGEZ_MM = 916, BGTZ = 917, BGTZ64 = 918, BGTZALC = 919, BGTZALC_MMR6 = 920, BGTZC = 921, BGTZC64 = 922, BGTZC_MMR6 = 923, BGTZL = 924, BGTZ_MM = 925, BINSLI_B = 926, BINSLI_D = 927, BINSLI_H = 928, BINSLI_W = 929, BINSL_B = 930, BINSL_D = 931, BINSL_H = 932, BINSL_W = 933, BINSRI_B = 934, BINSRI_D = 935, BINSRI_H = 936, BINSRI_W = 937, BINSR_B = 938, BINSR_D = 939, BINSR_H = 940, BINSR_W = 941, BITREV = 942, BITREV_MM = 943, BITSWAP = 944, BITSWAP_MMR6 = 945, BLEZ = 946, BLEZ64 = 947, BLEZALC = 948, BLEZALC_MMR6 = 949, BLEZC = 950, BLEZC64 = 951, BLEZC_MMR6 = 952, BLEZL = 953, BLEZ_MM = 954, BLTC = 955, BLTC64 = 956, BLTC_MMR6 = 957, BLTUC = 958, BLTUC64 = 959, BLTUC_MMR6 = 960, BLTZ = 961, BLTZ64 = 962, BLTZAL = 963, BLTZALC = 964, BLTZALC_MMR6 = 965, BLTZALL = 966, BLTZALS_MM = 967, BLTZAL_MM = 968, BLTZC = 969, BLTZC64 = 970, BLTZC_MMR6 = 971, BLTZL = 972, BLTZ_MM = 973, BMNZI_B = 974, BMNZ_V = 975, BMZI_B = 976, BMZ_V = 977, BNE = 978, BNE64 = 979, BNEC = 980, BNEC64 = 981, BNEC_MMR6 = 982, BNEGI_B = 983, BNEGI_D = 984, BNEGI_H = 985, BNEGI_W = 986, BNEG_B = 987, BNEG_D = 988, BNEG_H = 989, BNEG_W = 990, BNEL = 991, BNEZ16_MM = 992, BNEZALC = 993, BNEZALC_MMR6 = 994, BNEZC = 995, BNEZC16_MMR6 = 996, BNEZC64 = 997, BNEZC_MM = 998, BNEZC_MMR6 = 999, BNE_MM = 1000, BNVC = 1001, BNVC_MMR6 = 1002, BNZ_B = 1003, BNZ_D = 1004, BNZ_H = 1005, BNZ_V = 1006, BNZ_W = 1007, BOVC = 1008, BOVC_MMR6 = 1009, BPOSGE32 = 1010, BPOSGE32C_MMR3 = 1011, BPOSGE32_MM = 1012, BREAK = 1013, BREAK16_MM = 1014, BREAK16_MMR6 = 1015, BREAK_MM = 1016, BREAK_MMR6 = 1017, BSELI_B = 1018, BSEL_V = 1019, BSETI_B = 1020, BSETI_D = 1021, BSETI_H = 1022, BSETI_W = 1023, BSET_B = 1024, BSET_D = 1025, BSET_H = 1026, BSET_W = 1027, BZ_B = 1028, BZ_D = 1029, BZ_H = 1030, BZ_V = 1031, BZ_W = 1032, BeqzRxImm16 = 1033, BeqzRxImmX16 = 1034, Bimm16 = 1035, BimmX16 = 1036, BnezRxImm16 = 1037, BnezRxImmX16 = 1038, Break16 = 1039, Bteqz16 = 1040, BteqzX16 = 1041, Btnez16 = 1042, BtnezX16 = 1043, CACHE = 1044, CACHEE = 1045, CACHEE_MM = 1046, CACHE_MM = 1047, CACHE_MMR6 = 1048, CACHE_R6 = 1049, CEIL_L_D64 = 1050, CEIL_L_D_MMR6 = 1051, CEIL_L_S = 1052, CEIL_L_S_MMR6 = 1053, CEIL_W_D32 = 1054, CEIL_W_D64 = 1055, CEIL_W_D_MMR6 = 1056, CEIL_W_MM = 1057, CEIL_W_S = 1058, CEIL_W_S_MM = 1059, CEIL_W_S_MMR6 = 1060, CEQI_B = 1061, CEQI_D = 1062, CEQI_H = 1063, CEQI_W = 1064, CEQ_B = 1065, CEQ_D = 1066, CEQ_H = 1067, CEQ_W = 1068, CFC1 = 1069, CFC1_MM = 1070, CFC2_MM = 1071, CFCMSA = 1072, CINS = 1073, CINS32 = 1074, CINS64_32 = 1075, CINS_i32 = 1076, CLASS_D = 1077, CLASS_D_MMR6 = 1078, CLASS_S = 1079, CLASS_S_MMR6 = 1080, CLEI_S_B = 1081, CLEI_S_D = 1082, CLEI_S_H = 1083, CLEI_S_W = 1084, CLEI_U_B = 1085, CLEI_U_D = 1086, CLEI_U_H = 1087, CLEI_U_W = 1088, CLE_S_B = 1089, CLE_S_D = 1090, CLE_S_H = 1091, CLE_S_W = 1092, CLE_U_B = 1093, CLE_U_D = 1094, CLE_U_H = 1095, CLE_U_W = 1096, CLO = 1097, CLO_MM = 1098, CLO_MMR6 = 1099, CLO_R6 = 1100, CLTI_S_B = 1101, CLTI_S_D = 1102, CLTI_S_H = 1103, CLTI_S_W = 1104, CLTI_U_B = 1105, CLTI_U_D = 1106, CLTI_U_H = 1107, CLTI_U_W = 1108, CLT_S_B = 1109, CLT_S_D = 1110, CLT_S_H = 1111, CLT_S_W = 1112, CLT_U_B = 1113, CLT_U_D = 1114, CLT_U_H = 1115, CLT_U_W = 1116, CLZ = 1117, CLZ_MM = 1118, CLZ_MMR6 = 1119, CLZ_R6 = 1120, CMPGDU_EQ_QB = 1121, CMPGDU_EQ_QB_MMR2 = 1122, CMPGDU_LE_QB = 1123, CMPGDU_LE_QB_MMR2 = 1124, CMPGDU_LT_QB = 1125, CMPGDU_LT_QB_MMR2 = 1126, CMPGU_EQ_QB = 1127, CMPGU_EQ_QB_MM = 1128, CMPGU_LE_QB = 1129, CMPGU_LE_QB_MM = 1130, CMPGU_LT_QB = 1131, CMPGU_LT_QB_MM = 1132, CMPU_EQ_QB = 1133, CMPU_EQ_QB_MM = 1134, CMPU_LE_QB = 1135, CMPU_LE_QB_MM = 1136, CMPU_LT_QB = 1137, CMPU_LT_QB_MM = 1138, CMP_AF_D_MMR6 = 1139, CMP_AF_S_MMR6 = 1140, CMP_EQ_D = 1141, CMP_EQ_D_MMR6 = 1142, CMP_EQ_PH = 1143, CMP_EQ_PH_MM = 1144, CMP_EQ_S = 1145, CMP_EQ_S_MMR6 = 1146, CMP_F_D = 1147, CMP_F_S = 1148, CMP_LE_D = 1149, CMP_LE_D_MMR6 = 1150, CMP_LE_PH = 1151, CMP_LE_PH_MM = 1152, CMP_LE_S = 1153, CMP_LE_S_MMR6 = 1154, CMP_LT_D = 1155, CMP_LT_D_MMR6 = 1156, CMP_LT_PH = 1157, CMP_LT_PH_MM = 1158, CMP_LT_S = 1159, CMP_LT_S_MMR6 = 1160, CMP_SAF_D = 1161, CMP_SAF_D_MMR6 = 1162, CMP_SAF_S = 1163, CMP_SAF_S_MMR6 = 1164, CMP_SEQ_D = 1165, CMP_SEQ_D_MMR6 = 1166, CMP_SEQ_S = 1167, CMP_SEQ_S_MMR6 = 1168, CMP_SLE_D = 1169, CMP_SLE_D_MMR6 = 1170, CMP_SLE_S = 1171, CMP_SLE_S_MMR6 = 1172, CMP_SLT_D = 1173, CMP_SLT_D_MMR6 = 1174, CMP_SLT_S = 1175, CMP_SLT_S_MMR6 = 1176, CMP_SUEQ_D = 1177, CMP_SUEQ_D_MMR6 = 1178, CMP_SUEQ_S = 1179, CMP_SUEQ_S_MMR6 = 1180, CMP_SULE_D = 1181, CMP_SULE_D_MMR6 = 1182, CMP_SULE_S = 1183, CMP_SULE_S_MMR6 = 1184, CMP_SULT_D = 1185, CMP_SULT_D_MMR6 = 1186, CMP_SULT_S = 1187, CMP_SULT_S_MMR6 = 1188, CMP_SUN_D = 1189, CMP_SUN_D_MMR6 = 1190, CMP_SUN_S = 1191, CMP_SUN_S_MMR6 = 1192, CMP_UEQ_D = 1193, CMP_UEQ_D_MMR6 = 1194, CMP_UEQ_S = 1195, CMP_UEQ_S_MMR6 = 1196, CMP_ULE_D = 1197, CMP_ULE_D_MMR6 = 1198, CMP_ULE_S = 1199, CMP_ULE_S_MMR6 = 1200, CMP_ULT_D = 1201, CMP_ULT_D_MMR6 = 1202, CMP_ULT_S = 1203, CMP_ULT_S_MMR6 = 1204, CMP_UN_D = 1205, CMP_UN_D_MMR6 = 1206, CMP_UN_S = 1207, CMP_UN_S_MMR6 = 1208, COPY_S_B = 1209, COPY_S_D = 1210, COPY_S_H = 1211, COPY_S_W = 1212, COPY_U_B = 1213, COPY_U_H = 1214, COPY_U_W = 1215, CRC32B = 1216, CRC32CB = 1217, CRC32CD = 1218, CRC32CH = 1219, CRC32CW = 1220, CRC32D = 1221, CRC32H = 1222, CRC32W = 1223, CTC1 = 1224, CTC1_MM = 1225, CTC2_MM = 1226, CTCMSA = 1227, CVT_D32_S = 1228, CVT_D32_S_MM = 1229, CVT_D32_W = 1230, CVT_D32_W_MM = 1231, CVT_D64_L = 1232, CVT_D64_S = 1233, CVT_D64_S_MM = 1234, CVT_D64_W = 1235, CVT_D64_W_MM = 1236, CVT_D_L_MMR6 = 1237, CVT_L_D64 = 1238, CVT_L_D64_MM = 1239, CVT_L_D_MMR6 = 1240, CVT_L_S = 1241, CVT_L_S_MM = 1242, CVT_L_S_MMR6 = 1243, CVT_PS_PW64 = 1244, CVT_PS_S64 = 1245, CVT_PW_PS64 = 1246, CVT_S_D32 = 1247, CVT_S_D32_MM = 1248, CVT_S_D64 = 1249, CVT_S_D64_MM = 1250, CVT_S_L = 1251, CVT_S_L_MMR6 = 1252, CVT_S_PL64 = 1253, CVT_S_PU64 = 1254, CVT_S_W = 1255, CVT_S_W_MM = 1256, CVT_S_W_MMR6 = 1257, CVT_W_D32 = 1258, CVT_W_D32_MM = 1259, CVT_W_D64 = 1260, CVT_W_D64_MM = 1261, CVT_W_S = 1262, CVT_W_S_MM = 1263, CVT_W_S_MMR6 = 1264, C_EQ_D32 = 1265, C_EQ_D32_MM = 1266, C_EQ_D64 = 1267, C_EQ_D64_MM = 1268, C_EQ_S = 1269, C_EQ_S_MM = 1270, C_F_D32 = 1271, C_F_D32_MM = 1272, C_F_D64 = 1273, C_F_D64_MM = 1274, C_F_S = 1275, C_F_S_MM = 1276, C_LE_D32 = 1277, C_LE_D32_MM = 1278, C_LE_D64 = 1279, C_LE_D64_MM = 1280, C_LE_S = 1281, C_LE_S_MM = 1282, C_LT_D32 = 1283, C_LT_D32_MM = 1284, C_LT_D64 = 1285, C_LT_D64_MM = 1286, C_LT_S = 1287, C_LT_S_MM = 1288, C_NGE_D32 = 1289, C_NGE_D32_MM = 1290, C_NGE_D64 = 1291, C_NGE_D64_MM = 1292, C_NGE_S = 1293, C_NGE_S_MM = 1294, C_NGLE_D32 = 1295, C_NGLE_D32_MM = 1296, C_NGLE_D64 = 1297, C_NGLE_D64_MM = 1298, C_NGLE_S = 1299, C_NGLE_S_MM = 1300, C_NGL_D32 = 1301, C_NGL_D32_MM = 1302, C_NGL_D64 = 1303, C_NGL_D64_MM = 1304, C_NGL_S = 1305, C_NGL_S_MM = 1306, C_NGT_D32 = 1307, C_NGT_D32_MM = 1308, C_NGT_D64 = 1309, C_NGT_D64_MM = 1310, C_NGT_S = 1311, C_NGT_S_MM = 1312, C_OLE_D32 = 1313, C_OLE_D32_MM = 1314, C_OLE_D64 = 1315, C_OLE_D64_MM = 1316, C_OLE_S = 1317, C_OLE_S_MM = 1318, C_OLT_D32 = 1319, C_OLT_D32_MM = 1320, C_OLT_D64 = 1321, C_OLT_D64_MM = 1322, C_OLT_S = 1323, C_OLT_S_MM = 1324, C_SEQ_D32 = 1325, C_SEQ_D32_MM = 1326, C_SEQ_D64 = 1327, C_SEQ_D64_MM = 1328, C_SEQ_S = 1329, C_SEQ_S_MM = 1330, C_SF_D32 = 1331, C_SF_D32_MM = 1332, C_SF_D64 = 1333, C_SF_D64_MM = 1334, C_SF_S = 1335, C_SF_S_MM = 1336, C_UEQ_D32 = 1337, C_UEQ_D32_MM = 1338, C_UEQ_D64 = 1339, C_UEQ_D64_MM = 1340, C_UEQ_S = 1341, C_UEQ_S_MM = 1342, C_ULE_D32 = 1343, C_ULE_D32_MM = 1344, C_ULE_D64 = 1345, C_ULE_D64_MM = 1346, C_ULE_S = 1347, C_ULE_S_MM = 1348, C_ULT_D32 = 1349, C_ULT_D32_MM = 1350, C_ULT_D64 = 1351, C_ULT_D64_MM = 1352, C_ULT_S = 1353, C_ULT_S_MM = 1354, C_UN_D32 = 1355, C_UN_D32_MM = 1356, C_UN_D64 = 1357, C_UN_D64_MM = 1358, C_UN_S = 1359, C_UN_S_MM = 1360, CmpRxRy16 = 1361, CmpiRxImm16 = 1362, CmpiRxImmX16 = 1363, DADD = 1364, DADDi = 1365, DADDiu = 1366, DADDu = 1367, DAHI = 1368, DALIGN = 1369, DATI = 1370, DAUI = 1371, DBITSWAP = 1372, DCLO = 1373, DCLO_R6 = 1374, DCLZ = 1375, DCLZ_R6 = 1376, DDIV = 1377, DDIVU = 1378, DERET = 1379, DERET_MM = 1380, DERET_MMR6 = 1381, DEXT = 1382, DEXT64_32 = 1383, DEXTM = 1384, DEXTU = 1385, DI = 1386, DINS = 1387, DINSM = 1388, DINSU = 1389, DIV = 1390, DIVU = 1391, DIVU_MMR6 = 1392, DIV_MMR6 = 1393, DIV_S_B = 1394, DIV_S_D = 1395, DIV_S_H = 1396, DIV_S_W = 1397, DIV_U_B = 1398, DIV_U_D = 1399, DIV_U_H = 1400, DIV_U_W = 1401, DI_MM = 1402, DI_MMR6 = 1403, DLSA = 1404, DLSA_R6 = 1405, DMFC0 = 1406, DMFC1 = 1407, DMFC2 = 1408, DMFC2_OCTEON = 1409, DMFGC0 = 1410, DMOD = 1411, DMODU = 1412, DMT = 1413, DMTC0 = 1414, DMTC1 = 1415, DMTC2 = 1416, DMTC2_OCTEON = 1417, DMTGC0 = 1418, DMUH = 1419, DMUHU = 1420, DMUL = 1421, DMULT = 1422, DMULTu = 1423, DMULU = 1424, DMUL_R6 = 1425, DOTP_S_D = 1426, DOTP_S_H = 1427, DOTP_S_W = 1428, DOTP_U_D = 1429, DOTP_U_H = 1430, DOTP_U_W = 1431, DPADD_S_D = 1432, DPADD_S_H = 1433, DPADD_S_W = 1434, DPADD_U_D = 1435, DPADD_U_H = 1436, DPADD_U_W = 1437, DPAQX_SA_W_PH = 1438, DPAQX_SA_W_PH_MMR2 = 1439, DPAQX_S_W_PH = 1440, DPAQX_S_W_PH_MMR2 = 1441, DPAQ_SA_L_W = 1442, DPAQ_SA_L_W_MM = 1443, DPAQ_S_W_PH = 1444, DPAQ_S_W_PH_MM = 1445, DPAU_H_QBL = 1446, DPAU_H_QBL_MM = 1447, DPAU_H_QBR = 1448, DPAU_H_QBR_MM = 1449, DPAX_W_PH = 1450, DPAX_W_PH_MMR2 = 1451, DPA_W_PH = 1452, DPA_W_PH_MMR2 = 1453, DPOP = 1454, DPSQX_SA_W_PH = 1455, DPSQX_SA_W_PH_MMR2 = 1456, DPSQX_S_W_PH = 1457, DPSQX_S_W_PH_MMR2 = 1458, DPSQ_SA_L_W = 1459, DPSQ_SA_L_W_MM = 1460, DPSQ_S_W_PH = 1461, DPSQ_S_W_PH_MM = 1462, DPSUB_S_D = 1463, DPSUB_S_H = 1464, DPSUB_S_W = 1465, DPSUB_U_D = 1466, DPSUB_U_H = 1467, DPSUB_U_W = 1468, DPSU_H_QBL = 1469, DPSU_H_QBL_MM = 1470, DPSU_H_QBR = 1471, DPSU_H_QBR_MM = 1472, DPSX_W_PH = 1473, DPSX_W_PH_MMR2 = 1474, DPS_W_PH = 1475, DPS_W_PH_MMR2 = 1476, DROTR = 1477, DROTR32 = 1478, DROTRV = 1479, DSBH = 1480, DSDIV = 1481, DSHD = 1482, DSLL = 1483, DSLL32 = 1484, DSLL64_32 = 1485, DSLLV = 1486, DSRA = 1487, DSRA32 = 1488, DSRAV = 1489, DSRL = 1490, DSRL32 = 1491, DSRLV = 1492, DSUB = 1493, DSUBu = 1494, DUDIV = 1495, DVP = 1496, DVPE = 1497, DVP_MMR6 = 1498, DivRxRy16 = 1499, DivuRxRy16 = 1500, EHB = 1501, EHB_MM = 1502, EHB_MMR6 = 1503, EI = 1504, EI_MM = 1505, EI_MMR6 = 1506, EMT = 1507, ERET = 1508, ERETNC = 1509, ERETNC_MMR6 = 1510, ERET_MM = 1511, ERET_MMR6 = 1512, EVP = 1513, EVPE = 1514, EVP_MMR6 = 1515, EXT = 1516, EXTP = 1517, EXTPDP = 1518, EXTPDPV = 1519, EXTPDPV_MM = 1520, EXTPDP_MM = 1521, EXTPV = 1522, EXTPV_MM = 1523, EXTP_MM = 1524, EXTRV_RS_W = 1525, EXTRV_RS_W_MM = 1526, EXTRV_R_W = 1527, EXTRV_R_W_MM = 1528, EXTRV_S_H = 1529, EXTRV_S_H_MM = 1530, EXTRV_W = 1531, EXTRV_W_MM = 1532, EXTR_RS_W = 1533, EXTR_RS_W_MM = 1534, EXTR_R_W = 1535, EXTR_R_W_MM = 1536, EXTR_S_H = 1537, EXTR_S_H_MM = 1538, EXTR_W = 1539, EXTR_W_MM = 1540, EXTS = 1541, EXTS32 = 1542, EXT_MM = 1543, EXT_MMR6 = 1544, FABS_D32 = 1545, FABS_D32_MM = 1546, FABS_D64 = 1547, FABS_D64_MM = 1548, FABS_S = 1549, FABS_S_MM = 1550, FADD_D = 1551, FADD_D32 = 1552, FADD_D32_MM = 1553, FADD_D64 = 1554, FADD_D64_MM = 1555, FADD_PS64 = 1556, FADD_S = 1557, FADD_S_MM = 1558, FADD_S_MMR6 = 1559, FADD_W = 1560, FCAF_D = 1561, FCAF_W = 1562, FCEQ_D = 1563, FCEQ_W = 1564, FCLASS_D = 1565, FCLASS_W = 1566, FCLE_D = 1567, FCLE_W = 1568, FCLT_D = 1569, FCLT_W = 1570, FCMP_D32 = 1571, FCMP_D32_MM = 1572, FCMP_D64 = 1573, FCMP_S32 = 1574, FCMP_S32_MM = 1575, FCNE_D = 1576, FCNE_W = 1577, FCOR_D = 1578, FCOR_W = 1579, FCUEQ_D = 1580, FCUEQ_W = 1581, FCULE_D = 1582, FCULE_W = 1583, FCULT_D = 1584, FCULT_W = 1585, FCUNE_D = 1586, FCUNE_W = 1587, FCUN_D = 1588, FCUN_W = 1589, FDIV_D = 1590, FDIV_D32 = 1591, FDIV_D32_MM = 1592, FDIV_D64 = 1593, FDIV_D64_MM = 1594, FDIV_S = 1595, FDIV_S_MM = 1596, FDIV_S_MMR6 = 1597, FDIV_W = 1598, FEXDO_H = 1599, FEXDO_W = 1600, FEXP2_D = 1601, FEXP2_W = 1602, FEXUPL_D = 1603, FEXUPL_W = 1604, FEXUPR_D = 1605, FEXUPR_W = 1606, FFINT_S_D = 1607, FFINT_S_W = 1608, FFINT_U_D = 1609, FFINT_U_W = 1610, FFQL_D = 1611, FFQL_W = 1612, FFQR_D = 1613, FFQR_W = 1614, FILL_B = 1615, FILL_D = 1616, FILL_H = 1617, FILL_W = 1618, FLOG2_D = 1619, FLOG2_W = 1620, FLOOR_L_D64 = 1621, FLOOR_L_D_MMR6 = 1622, FLOOR_L_S = 1623, FLOOR_L_S_MMR6 = 1624, FLOOR_W_D32 = 1625, FLOOR_W_D64 = 1626, FLOOR_W_D_MMR6 = 1627, FLOOR_W_MM = 1628, FLOOR_W_S = 1629, FLOOR_W_S_MM = 1630, FLOOR_W_S_MMR6 = 1631, FMADD_D = 1632, FMADD_W = 1633, FMAX_A_D = 1634, FMAX_A_W = 1635, FMAX_D = 1636, FMAX_W = 1637, FMIN_A_D = 1638, FMIN_A_W = 1639, FMIN_D = 1640, FMIN_W = 1641, FMOV_D32 = 1642, FMOV_D32_MM = 1643, FMOV_D64 = 1644, FMOV_D64_MM = 1645, FMOV_D_MMR6 = 1646, FMOV_S = 1647, FMOV_S_MM = 1648, FMOV_S_MMR6 = 1649, FMSUB_D = 1650, FMSUB_W = 1651, FMUL_D = 1652, FMUL_D32 = 1653, FMUL_D32_MM = 1654, FMUL_D64 = 1655, FMUL_D64_MM = 1656, FMUL_PS64 = 1657, FMUL_S = 1658, FMUL_S_MM = 1659, FMUL_S_MMR6 = 1660, FMUL_W = 1661, FNEG_D32 = 1662, FNEG_D32_MM = 1663, FNEG_D64 = 1664, FNEG_D64_MM = 1665, FNEG_S = 1666, FNEG_S_MM = 1667, FNEG_S_MMR6 = 1668, FORK = 1669, FRCP_D = 1670, FRCP_W = 1671, FRINT_D = 1672, FRINT_W = 1673, FRSQRT_D = 1674, FRSQRT_W = 1675, FSAF_D = 1676, FSAF_W = 1677, FSEQ_D = 1678, FSEQ_W = 1679, FSLE_D = 1680, FSLE_W = 1681, FSLT_D = 1682, FSLT_W = 1683, FSNE_D = 1684, FSNE_W = 1685, FSOR_D = 1686, FSOR_W = 1687, FSQRT_D = 1688, FSQRT_D32 = 1689, FSQRT_D32_MM = 1690, FSQRT_D64 = 1691, FSQRT_D64_MM = 1692, FSQRT_S = 1693, FSQRT_S_MM = 1694, FSQRT_W = 1695, FSUB_D = 1696, FSUB_D32 = 1697, FSUB_D32_MM = 1698, FSUB_D64 = 1699, FSUB_D64_MM = 1700, FSUB_PS64 = 1701, FSUB_S = 1702, FSUB_S_MM = 1703, FSUB_S_MMR6 = 1704, FSUB_W = 1705, FSUEQ_D = 1706, FSUEQ_W = 1707, FSULE_D = 1708, FSULE_W = 1709, FSULT_D = 1710, FSULT_W = 1711, FSUNE_D = 1712, FSUNE_W = 1713, FSUN_D = 1714, FSUN_W = 1715, FTINT_S_D = 1716, FTINT_S_W = 1717, FTINT_U_D = 1718, FTINT_U_W = 1719, FTQ_H = 1720, FTQ_W = 1721, FTRUNC_S_D = 1722, FTRUNC_S_W = 1723, FTRUNC_U_D = 1724, FTRUNC_U_W = 1725, GINVI = 1726, GINVI_MMR6 = 1727, GINVT = 1728, GINVT_MMR6 = 1729, HADD_S_D = 1730, HADD_S_H = 1731, HADD_S_W = 1732, HADD_U_D = 1733, HADD_U_H = 1734, HADD_U_W = 1735, HSUB_S_D = 1736, HSUB_S_H = 1737, HSUB_S_W = 1738, HSUB_U_D = 1739, HSUB_U_H = 1740, HSUB_U_W = 1741, HYPCALL = 1742, HYPCALL_MM = 1743, ILVEV_B = 1744, ILVEV_D = 1745, ILVEV_H = 1746, ILVEV_W = 1747, ILVL_B = 1748, ILVL_D = 1749, ILVL_H = 1750, ILVL_W = 1751, ILVOD_B = 1752, ILVOD_D = 1753, ILVOD_H = 1754, ILVOD_W = 1755, ILVR_B = 1756, ILVR_D = 1757, ILVR_H = 1758, ILVR_W = 1759, INS = 1760, INSERT_B = 1761, INSERT_D = 1762, INSERT_H = 1763, INSERT_W = 1764, INSV = 1765, INSVE_B = 1766, INSVE_D = 1767, INSVE_H = 1768, INSVE_W = 1769, INSV_MM = 1770, INS_MM = 1771, INS_MMR6 = 1772, J = 1773, JAL = 1774, JALR = 1775, JALR16_MM = 1776, JALR64 = 1777, JALRC16_MMR6 = 1778, JALRC_HB_MMR6 = 1779, JALRC_MMR6 = 1780, JALRS16_MM = 1781, JALRS_MM = 1782, JALR_HB = 1783, JALR_HB64 = 1784, JALR_MM = 1785, JALS_MM = 1786, JALX = 1787, JALX_MM = 1788, JAL_MM = 1789, JIALC = 1790, JIALC64 = 1791, JIALC_MMR6 = 1792, JIC = 1793, JIC64 = 1794, JIC_MMR6 = 1795, JR = 1796, JR16_MM = 1797, JR64 = 1798, JRADDIUSP = 1799, JRC16_MM = 1800, JRC16_MMR6 = 1801, JRCADDIUSP_MMR6 = 1802, JR_HB = 1803, JR_HB64 = 1804, JR_HB64_R6 = 1805, JR_HB_R6 = 1806, JR_MM = 1807, J_MM = 1808, Jal16 = 1809, JalB16 = 1810, JrRa16 = 1811, JrcRa16 = 1812, JrcRx16 = 1813, JumpLinkReg16 = 1814, LB = 1815, LB64 = 1816, LBE = 1817, LBE_MM = 1818, LBU16_MM = 1819, LBUX = 1820, LBUX_MM = 1821, LBU_MMR6 = 1822, LB_MM = 1823, LB_MMR6 = 1824, LBu = 1825, LBu64 = 1826, LBuE = 1827, LBuE_MM = 1828, LBu_MM = 1829, LD = 1830, LDC1 = 1831, LDC164 = 1832, LDC1_D64_MMR6 = 1833, LDC1_MM_D32 = 1834, LDC1_MM_D64 = 1835, LDC2 = 1836, LDC2_MMR6 = 1837, LDC2_R6 = 1838, LDC3 = 1839, LDI_B = 1840, LDI_D = 1841, LDI_H = 1842, LDI_W = 1843, LDL = 1844, LDPC = 1845, LDR = 1846, LDXC1 = 1847, LDXC164 = 1848, LD_B = 1849, LD_D = 1850, LD_H = 1851, LD_W = 1852, LEA_ADDiu = 1853, LEA_ADDiu64 = 1854, LEA_ADDiu_MM = 1855, LH = 1856, LH64 = 1857, LHE = 1858, LHE_MM = 1859, LHU16_MM = 1860, LHX = 1861, LHX_MM = 1862, LH_MM = 1863, LHu = 1864, LHu64 = 1865, LHuE = 1866, LHuE_MM = 1867, LHu_MM = 1868, LI16_MM = 1869, LI16_MMR6 = 1870, LL = 1871, LL64 = 1872, LL64_R6 = 1873, LLD = 1874, LLD_R6 = 1875, LLE = 1876, LLE_MM = 1877, LL_MM = 1878, LL_MMR6 = 1879, LL_R6 = 1880, LSA = 1881, LSA_MMR6 = 1882, LSA_R6 = 1883, LUI_MMR6 = 1884, LUXC1 = 1885, LUXC164 = 1886, LUXC1_MM = 1887, LUi = 1888, LUi64 = 1889, LUi_MM = 1890, LW = 1891, LW16_MM = 1892, LW64 = 1893, LWC1 = 1894, LWC1_MM = 1895, LWC2 = 1896, LWC2_MMR6 = 1897, LWC2_R6 = 1898, LWC3 = 1899, LWDSP = 1900, LWDSP_MM = 1901, LWE = 1902, LWE_MM = 1903, LWGP_MM = 1904, LWL = 1905, LWL64 = 1906, LWLE = 1907, LWLE_MM = 1908, LWL_MM = 1909, LWM16_MM = 1910, LWM16_MMR6 = 1911, LWM32_MM = 1912, LWPC = 1913, LWPC_MMR6 = 1914, LWP_MM = 1915, LWR = 1916, LWR64 = 1917, LWRE = 1918, LWRE_MM = 1919, LWR_MM = 1920, LWSP_MM = 1921, LWUPC = 1922, LWU_MM = 1923, LWX = 1924, LWXC1 = 1925, LWXC1_MM = 1926, LWXS_MM = 1927, LWX_MM = 1928, LW_MM = 1929, LW_MMR6 = 1930, LWu = 1931, LbRxRyOffMemX16 = 1932, LbuRxRyOffMemX16 = 1933, LhRxRyOffMemX16 = 1934, LhuRxRyOffMemX16 = 1935, LiRxImm16 = 1936, LiRxImmAlignX16 = 1937, LiRxImmX16 = 1938, LwRxPcTcp16 = 1939, LwRxPcTcpX16 = 1940, LwRxRyOffMemX16 = 1941, LwRxSpImmX16 = 1942, MADD = 1943, MADDF_D = 1944, MADDF_D_MMR6 = 1945, MADDF_S = 1946, MADDF_S_MMR6 = 1947, MADDR_Q_H = 1948, MADDR_Q_W = 1949, MADDU = 1950, MADDU_DSP = 1951, MADDU_DSP_MM = 1952, MADDU_MM = 1953, MADDV_B = 1954, MADDV_D = 1955, MADDV_H = 1956, MADDV_W = 1957, MADD_D32 = 1958, MADD_D32_MM = 1959, MADD_D64 = 1960, MADD_DSP = 1961, MADD_DSP_MM = 1962, MADD_MM = 1963, MADD_Q_H = 1964, MADD_Q_W = 1965, MADD_S = 1966, MADD_S_MM = 1967, MAQ_SA_W_PHL = 1968, MAQ_SA_W_PHL_MM = 1969, MAQ_SA_W_PHR = 1970, MAQ_SA_W_PHR_MM = 1971, MAQ_S_W_PHL = 1972, MAQ_S_W_PHL_MM = 1973, MAQ_S_W_PHR = 1974, MAQ_S_W_PHR_MM = 1975, MAXA_D = 1976, MAXA_D_MMR6 = 1977, MAXA_S = 1978, MAXA_S_MMR6 = 1979, MAXI_S_B = 1980, MAXI_S_D = 1981, MAXI_S_H = 1982, MAXI_S_W = 1983, MAXI_U_B = 1984, MAXI_U_D = 1985, MAXI_U_H = 1986, MAXI_U_W = 1987, MAX_A_B = 1988, MAX_A_D = 1989, MAX_A_H = 1990, MAX_A_W = 1991, MAX_D = 1992, MAX_D_MMR6 = 1993, MAX_S = 1994, MAX_S_B = 1995, MAX_S_D = 1996, MAX_S_H = 1997, MAX_S_MMR6 = 1998, MAX_S_W = 1999, MAX_U_B = 2000, MAX_U_D = 2001, MAX_U_H = 2002, MAX_U_W = 2003, MFC0 = 2004, MFC0_MMR6 = 2005, MFC1 = 2006, MFC1_D64 = 2007, MFC1_MM = 2008, MFC1_MMR6 = 2009, MFC2 = 2010, MFC2_MMR6 = 2011, MFGC0 = 2012, MFGC0_MM = 2013, MFHC0_MMR6 = 2014, MFHC1_D32 = 2015, MFHC1_D32_MM = 2016, MFHC1_D64 = 2017, MFHC1_D64_MM = 2018, MFHC2_MMR6 = 2019, MFHGC0 = 2020, MFHGC0_MM = 2021, MFHI = 2022, MFHI16_MM = 2023, MFHI64 = 2024, MFHI_DSP = 2025, MFHI_DSP_MM = 2026, MFHI_MM = 2027, MFLO = 2028, MFLO16_MM = 2029, MFLO64 = 2030, MFLO_DSP = 2031, MFLO_DSP_MM = 2032, MFLO_MM = 2033, MFTR = 2034, MINA_D = 2035, MINA_D_MMR6 = 2036, MINA_S = 2037, MINA_S_MMR6 = 2038, MINI_S_B = 2039, MINI_S_D = 2040, MINI_S_H = 2041, MINI_S_W = 2042, MINI_U_B = 2043, MINI_U_D = 2044, MINI_U_H = 2045, MINI_U_W = 2046, MIN_A_B = 2047, MIN_A_D = 2048, MIN_A_H = 2049, MIN_A_W = 2050, MIN_D = 2051, MIN_D_MMR6 = 2052, MIN_S = 2053, MIN_S_B = 2054, MIN_S_D = 2055, MIN_S_H = 2056, MIN_S_MMR6 = 2057, MIN_S_W = 2058, MIN_U_B = 2059, MIN_U_D = 2060, MIN_U_H = 2061, MIN_U_W = 2062, MOD = 2063, MODSUB = 2064, MODSUB_MM = 2065, MODU = 2066, MODU_MMR6 = 2067, MOD_MMR6 = 2068, MOD_S_B = 2069, MOD_S_D = 2070, MOD_S_H = 2071, MOD_S_W = 2072, MOD_U_B = 2073, MOD_U_D = 2074, MOD_U_H = 2075, MOD_U_W = 2076, MOVE16_MM = 2077, MOVE16_MMR6 = 2078, MOVEP_MM = 2079, MOVEP_MMR6 = 2080, MOVE_V = 2081, MOVF_D32 = 2082, MOVF_D32_MM = 2083, MOVF_D64 = 2084, MOVF_I = 2085, MOVF_I64 = 2086, MOVF_I_MM = 2087, MOVF_S = 2088, MOVF_S_MM = 2089, MOVN_I64_D64 = 2090, MOVN_I64_I = 2091, MOVN_I64_I64 = 2092, MOVN_I64_S = 2093, MOVN_I_D32 = 2094, MOVN_I_D32_MM = 2095, MOVN_I_D64 = 2096, MOVN_I_I = 2097, MOVN_I_I64 = 2098, MOVN_I_MM = 2099, MOVN_I_S = 2100, MOVN_I_S_MM = 2101, MOVT_D32 = 2102, MOVT_D32_MM = 2103, MOVT_D64 = 2104, MOVT_I = 2105, MOVT_I64 = 2106, MOVT_I_MM = 2107, MOVT_S = 2108, MOVT_S_MM = 2109, MOVZ_I64_D64 = 2110, MOVZ_I64_I = 2111, MOVZ_I64_I64 = 2112, MOVZ_I64_S = 2113, MOVZ_I_D32 = 2114, MOVZ_I_D32_MM = 2115, MOVZ_I_D64 = 2116, MOVZ_I_I = 2117, MOVZ_I_I64 = 2118, MOVZ_I_MM = 2119, MOVZ_I_S = 2120, MOVZ_I_S_MM = 2121, MSUB = 2122, MSUBF_D = 2123, MSUBF_D_MMR6 = 2124, MSUBF_S = 2125, MSUBF_S_MMR6 = 2126, MSUBR_Q_H = 2127, MSUBR_Q_W = 2128, MSUBU = 2129, MSUBU_DSP = 2130, MSUBU_DSP_MM = 2131, MSUBU_MM = 2132, MSUBV_B = 2133, MSUBV_D = 2134, MSUBV_H = 2135, MSUBV_W = 2136, MSUB_D32 = 2137, MSUB_D32_MM = 2138, MSUB_D64 = 2139, MSUB_DSP = 2140, MSUB_DSP_MM = 2141, MSUB_MM = 2142, MSUB_Q_H = 2143, MSUB_Q_W = 2144, MSUB_S = 2145, MSUB_S_MM = 2146, MTC0 = 2147, MTC0_MMR6 = 2148, MTC1 = 2149, MTC1_D64 = 2150, MTC1_D64_MM = 2151, MTC1_MM = 2152, MTC1_MMR6 = 2153, MTC2 = 2154, MTC2_MMR6 = 2155, MTGC0 = 2156, MTGC0_MM = 2157, MTHC0_MMR6 = 2158, MTHC1_D32 = 2159, MTHC1_D32_MM = 2160, MTHC1_D64 = 2161, MTHC1_D64_MM = 2162, MTHC2_MMR6 = 2163, MTHGC0 = 2164, MTHGC0_MM = 2165, MTHI = 2166, MTHI64 = 2167, MTHI_DSP = 2168, MTHI_DSP_MM = 2169, MTHI_MM = 2170, MTHLIP = 2171, MTHLIP_MM = 2172, MTLO = 2173, MTLO64 = 2174, MTLO_DSP = 2175, MTLO_DSP_MM = 2176, MTLO_MM = 2177, MTM0 = 2178, MTM1 = 2179, MTM2 = 2180, MTP0 = 2181, MTP1 = 2182, MTP2 = 2183, MTTR = 2184, MUH = 2185, MUHU = 2186, MUHU_MMR6 = 2187, MUH_MMR6 = 2188, MUL = 2189, MULEQ_S_W_PHL = 2190, MULEQ_S_W_PHL_MM = 2191, MULEQ_S_W_PHR = 2192, MULEQ_S_W_PHR_MM = 2193, MULEU_S_PH_QBL = 2194, MULEU_S_PH_QBL_MM = 2195, MULEU_S_PH_QBR = 2196, MULEU_S_PH_QBR_MM = 2197, MULQ_RS_PH = 2198, MULQ_RS_PH_MM = 2199, MULQ_RS_W = 2200, MULQ_RS_W_MMR2 = 2201, MULQ_S_PH = 2202, MULQ_S_PH_MMR2 = 2203, MULQ_S_W = 2204, MULQ_S_W_MMR2 = 2205, MULR_PS64 = 2206, MULR_Q_H = 2207, MULR_Q_W = 2208, MULSAQ_S_W_PH = 2209, MULSAQ_S_W_PH_MM = 2210, MULSA_W_PH = 2211, MULSA_W_PH_MMR2 = 2212, MULT = 2213, MULTU_DSP = 2214, MULTU_DSP_MM = 2215, MULT_DSP = 2216, MULT_DSP_MM = 2217, MULT_MM = 2218, MULTu = 2219, MULTu_MM = 2220, MULU = 2221, MULU_MMR6 = 2222, MULV_B = 2223, MULV_D = 2224, MULV_H = 2225, MULV_W = 2226, MUL_MM = 2227, MUL_MMR6 = 2228, MUL_PH = 2229, MUL_PH_MMR2 = 2230, MUL_Q_H = 2231, MUL_Q_W = 2232, MUL_R6 = 2233, MUL_S_PH = 2234, MUL_S_PH_MMR2 = 2235, Mfhi16 = 2236, Mflo16 = 2237, Move32R16 = 2238, MoveR3216 = 2239, NLOC_B = 2240, NLOC_D = 2241, NLOC_H = 2242, NLOC_W = 2243, NLZC_B = 2244, NLZC_D = 2245, NLZC_H = 2246, NLZC_W = 2247, NMADD_D32 = 2248, NMADD_D32_MM = 2249, NMADD_D64 = 2250, NMADD_S = 2251, NMADD_S_MM = 2252, NMSUB_D32 = 2253, NMSUB_D32_MM = 2254, NMSUB_D64 = 2255, NMSUB_S = 2256, NMSUB_S_MM = 2257, NOR = 2258, NOR64 = 2259, NORI_B = 2260, NOR_MM = 2261, NOR_MMR6 = 2262, NOR_V = 2263, NOT16_MM = 2264, NOT16_MMR6 = 2265, NegRxRy16 = 2266, NotRxRy16 = 2267, OR = 2268, OR16_MM = 2269, OR16_MMR6 = 2270, OR64 = 2271, ORI_B = 2272, ORI_MMR6 = 2273, OR_MM = 2274, OR_MMR6 = 2275, OR_V = 2276, ORi = 2277, ORi64 = 2278, ORi_MM = 2279, OrRxRxRy16 = 2280, PACKRL_PH = 2281, PACKRL_PH_MM = 2282, PAUSE = 2283, PAUSE_MM = 2284, PAUSE_MMR6 = 2285, PCKEV_B = 2286, PCKEV_D = 2287, PCKEV_H = 2288, PCKEV_W = 2289, PCKOD_B = 2290, PCKOD_D = 2291, PCKOD_H = 2292, PCKOD_W = 2293, PCNT_B = 2294, PCNT_D = 2295, PCNT_H = 2296, PCNT_W = 2297, PICK_PH = 2298, PICK_PH_MM = 2299, PICK_QB = 2300, PICK_QB_MM = 2301, PLL_PS64 = 2302, PLU_PS64 = 2303, POP = 2304, PRECEQU_PH_QBL = 2305, PRECEQU_PH_QBLA = 2306, PRECEQU_PH_QBLA_MM = 2307, PRECEQU_PH_QBL_MM = 2308, PRECEQU_PH_QBR = 2309, PRECEQU_PH_QBRA = 2310, PRECEQU_PH_QBRA_MM = 2311, PRECEQU_PH_QBR_MM = 2312, PRECEQ_W_PHL = 2313, PRECEQ_W_PHL_MM = 2314, PRECEQ_W_PHR = 2315, PRECEQ_W_PHR_MM = 2316, PRECEU_PH_QBL = 2317, PRECEU_PH_QBLA = 2318, PRECEU_PH_QBLA_MM = 2319, PRECEU_PH_QBL_MM = 2320, PRECEU_PH_QBR = 2321, PRECEU_PH_QBRA = 2322, PRECEU_PH_QBRA_MM = 2323, PRECEU_PH_QBR_MM = 2324, PRECRQU_S_QB_PH = 2325, PRECRQU_S_QB_PH_MM = 2326, PRECRQ_PH_W = 2327, PRECRQ_PH_W_MM = 2328, PRECRQ_QB_PH = 2329, PRECRQ_QB_PH_MM = 2330, PRECRQ_RS_PH_W = 2331, PRECRQ_RS_PH_W_MM = 2332, PRECR_QB_PH = 2333, PRECR_QB_PH_MMR2 = 2334, PRECR_SRA_PH_W = 2335, PRECR_SRA_PH_W_MMR2 = 2336, PRECR_SRA_R_PH_W = 2337, PRECR_SRA_R_PH_W_MMR2 = 2338, PREF = 2339, PREFE = 2340, PREFE_MM = 2341, PREFX_MM = 2342, PREF_MM = 2343, PREF_MMR6 = 2344, PREF_R6 = 2345, PREPEND = 2346, PREPEND_MMR2 = 2347, PUL_PS64 = 2348, PUU_PS64 = 2349, RADDU_W_QB = 2350, RADDU_W_QB_MM = 2351, RDDSP = 2352, RDDSP_MM = 2353, RDHWR = 2354, RDHWR64 = 2355, RDHWR_MM = 2356, RDHWR_MMR6 = 2357, RDPGPR_MMR6 = 2358, RECIP_D32 = 2359, RECIP_D32_MM = 2360, RECIP_D64 = 2361, RECIP_D64_MM = 2362, RECIP_S = 2363, RECIP_S_MM = 2364, REPLV_PH = 2365, REPLV_PH_MM = 2366, REPLV_QB = 2367, REPLV_QB_MM = 2368, REPL_PH = 2369, REPL_PH_MM = 2370, REPL_QB = 2371, REPL_QB_MM = 2372, RINT_D = 2373, RINT_D_MMR6 = 2374, RINT_S = 2375, RINT_S_MMR6 = 2376, ROTR = 2377, ROTRV = 2378, ROTRV_MM = 2379, ROTR_MM = 2380, ROUND_L_D64 = 2381, ROUND_L_D_MMR6 = 2382, ROUND_L_S = 2383, ROUND_L_S_MMR6 = 2384, ROUND_W_D32 = 2385, ROUND_W_D64 = 2386, ROUND_W_D_MMR6 = 2387, ROUND_W_MM = 2388, ROUND_W_S = 2389, ROUND_W_S_MM = 2390, ROUND_W_S_MMR6 = 2391, RSQRT_D32 = 2392, RSQRT_D32_MM = 2393, RSQRT_D64 = 2394, RSQRT_D64_MM = 2395, RSQRT_S = 2396, RSQRT_S_MM = 2397, Restore16 = 2398, RestoreX16 = 2399, SAA = 2400, SAAD = 2401, SAT_S_B = 2402, SAT_S_D = 2403, SAT_S_H = 2404, SAT_S_W = 2405, SAT_U_B = 2406, SAT_U_D = 2407, SAT_U_H = 2408, SAT_U_W = 2409, SB = 2410, SB16_MM = 2411, SB16_MMR6 = 2412, SB64 = 2413, SBE = 2414, SBE_MM = 2415, SB_MM = 2416, SB_MMR6 = 2417, SC = 2418, SC64 = 2419, SC64_R6 = 2420, SCD = 2421, SCD_R6 = 2422, SCE = 2423, SCE_MM = 2424, SC_MM = 2425, SC_MMR6 = 2426, SC_R6 = 2427, SD = 2428, SDBBP = 2429, SDBBP16_MM = 2430, SDBBP16_MMR6 = 2431, SDBBP_MM = 2432, SDBBP_MMR6 = 2433, SDBBP_R6 = 2434, SDC1 = 2435, SDC164 = 2436, SDC1_D64_MMR6 = 2437, SDC1_MM_D32 = 2438, SDC1_MM_D64 = 2439, SDC2 = 2440, SDC2_MMR6 = 2441, SDC2_R6 = 2442, SDC3 = 2443, SDIV = 2444, SDIV_MM = 2445, SDL = 2446, SDR = 2447, SDXC1 = 2448, SDXC164 = 2449, SEB = 2450, SEB64 = 2451, SEB_MM = 2452, SEH = 2453, SEH64 = 2454, SEH_MM = 2455, SELEQZ = 2456, SELEQZ64 = 2457, SELEQZ_D = 2458, SELEQZ_D_MMR6 = 2459, SELEQZ_MMR6 = 2460, SELEQZ_S = 2461, SELEQZ_S_MMR6 = 2462, SELNEZ = 2463, SELNEZ64 = 2464, SELNEZ_D = 2465, SELNEZ_D_MMR6 = 2466, SELNEZ_MMR6 = 2467, SELNEZ_S = 2468, SELNEZ_S_MMR6 = 2469, SEL_D = 2470, SEL_D_MMR6 = 2471, SEL_S = 2472, SEL_S_MMR6 = 2473, SEQ = 2474, SEQi = 2475, SH = 2476, SH16_MM = 2477, SH16_MMR6 = 2478, SH64 = 2479, SHE = 2480, SHE_MM = 2481, SHF_B = 2482, SHF_H = 2483, SHF_W = 2484, SHILO = 2485, SHILOV = 2486, SHILOV_MM = 2487, SHILO_MM = 2488, SHLLV_PH = 2489, SHLLV_PH_MM = 2490, SHLLV_QB = 2491, SHLLV_QB_MM = 2492, SHLLV_S_PH = 2493, SHLLV_S_PH_MM = 2494, SHLLV_S_W = 2495, SHLLV_S_W_MM = 2496, SHLL_PH = 2497, SHLL_PH_MM = 2498, SHLL_QB = 2499, SHLL_QB_MM = 2500, SHLL_S_PH = 2501, SHLL_S_PH_MM = 2502, SHLL_S_W = 2503, SHLL_S_W_MM = 2504, SHRAV_PH = 2505, SHRAV_PH_MM = 2506, SHRAV_QB = 2507, SHRAV_QB_MMR2 = 2508, SHRAV_R_PH = 2509, SHRAV_R_PH_MM = 2510, SHRAV_R_QB = 2511, SHRAV_R_QB_MMR2 = 2512, SHRAV_R_W = 2513, SHRAV_R_W_MM = 2514, SHRA_PH = 2515, SHRA_PH_MM = 2516, SHRA_QB = 2517, SHRA_QB_MMR2 = 2518, SHRA_R_PH = 2519, SHRA_R_PH_MM = 2520, SHRA_R_QB = 2521, SHRA_R_QB_MMR2 = 2522, SHRA_R_W = 2523, SHRA_R_W_MM = 2524, SHRLV_PH = 2525, SHRLV_PH_MMR2 = 2526, SHRLV_QB = 2527, SHRLV_QB_MM = 2528, SHRL_PH = 2529, SHRL_PH_MMR2 = 2530, SHRL_QB = 2531, SHRL_QB_MM = 2532, SH_MM = 2533, SH_MMR6 = 2534, SIGRIE = 2535, SIGRIE_MMR6 = 2536, SLDI_B = 2537, SLDI_D = 2538, SLDI_H = 2539, SLDI_W = 2540, SLD_B = 2541, SLD_D = 2542, SLD_H = 2543, SLD_W = 2544, SLL = 2545, SLL16_MM = 2546, SLL16_MMR6 = 2547, SLL64_32 = 2548, SLL64_64 = 2549, SLLI_B = 2550, SLLI_D = 2551, SLLI_H = 2552, SLLI_W = 2553, SLLV = 2554, SLLV_MM = 2555, SLL_B = 2556, SLL_D = 2557, SLL_H = 2558, SLL_MM = 2559, SLL_MMR6 = 2560, SLL_W = 2561, SLT = 2562, SLT64 = 2563, SLT_MM = 2564, SLTi = 2565, SLTi64 = 2566, SLTi_MM = 2567, SLTiu = 2568, SLTiu64 = 2569, SLTiu_MM = 2570, SLTu = 2571, SLTu64 = 2572, SLTu_MM = 2573, SNE = 2574, SNEi = 2575, SPLATI_B = 2576, SPLATI_D = 2577, SPLATI_H = 2578, SPLATI_W = 2579, SPLAT_B = 2580, SPLAT_D = 2581, SPLAT_H = 2582, SPLAT_W = 2583, SRA = 2584, SRAI_B = 2585, SRAI_D = 2586, SRAI_H = 2587, SRAI_W = 2588, SRARI_B = 2589, SRARI_D = 2590, SRARI_H = 2591, SRARI_W = 2592, SRAR_B = 2593, SRAR_D = 2594, SRAR_H = 2595, SRAR_W = 2596, SRAV = 2597, SRAV_MM = 2598, SRA_B = 2599, SRA_D = 2600, SRA_H = 2601, SRA_MM = 2602, SRA_W = 2603, SRL = 2604, SRL16_MM = 2605, SRL16_MMR6 = 2606, SRLI_B = 2607, SRLI_D = 2608, SRLI_H = 2609, SRLI_W = 2610, SRLRI_B = 2611, SRLRI_D = 2612, SRLRI_H = 2613, SRLRI_W = 2614, SRLR_B = 2615, SRLR_D = 2616, SRLR_H = 2617, SRLR_W = 2618, SRLV = 2619, SRLV_MM = 2620, SRL_B = 2621, SRL_D = 2622, SRL_H = 2623, SRL_MM = 2624, SRL_W = 2625, SSNOP = 2626, SSNOP_MM = 2627, SSNOP_MMR6 = 2628, ST_B = 2629, ST_D = 2630, ST_H = 2631, ST_W = 2632, SUB = 2633, SUBQH_PH = 2634, SUBQH_PH_MMR2 = 2635, SUBQH_R_PH = 2636, SUBQH_R_PH_MMR2 = 2637, SUBQH_R_W = 2638, SUBQH_R_W_MMR2 = 2639, SUBQH_W = 2640, SUBQH_W_MMR2 = 2641, SUBQ_PH = 2642, SUBQ_PH_MM = 2643, SUBQ_S_PH = 2644, SUBQ_S_PH_MM = 2645, SUBQ_S_W = 2646, SUBQ_S_W_MM = 2647, SUBSUS_U_B = 2648, SUBSUS_U_D = 2649, SUBSUS_U_H = 2650, SUBSUS_U_W = 2651, SUBSUU_S_B = 2652, SUBSUU_S_D = 2653, SUBSUU_S_H = 2654, SUBSUU_S_W = 2655, SUBS_S_B = 2656, SUBS_S_D = 2657, SUBS_S_H = 2658, SUBS_S_W = 2659, SUBS_U_B = 2660, SUBS_U_D = 2661, SUBS_U_H = 2662, SUBS_U_W = 2663, SUBU16_MM = 2664, SUBU16_MMR6 = 2665, SUBUH_QB = 2666, SUBUH_QB_MMR2 = 2667, SUBUH_R_QB = 2668, SUBUH_R_QB_MMR2 = 2669, SUBU_MMR6 = 2670, SUBU_PH = 2671, SUBU_PH_MMR2 = 2672, SUBU_QB = 2673, SUBU_QB_MM = 2674, SUBU_S_PH = 2675, SUBU_S_PH_MMR2 = 2676, SUBU_S_QB = 2677, SUBU_S_QB_MM = 2678, SUBVI_B = 2679, SUBVI_D = 2680, SUBVI_H = 2681, SUBVI_W = 2682, SUBV_B = 2683, SUBV_D = 2684, SUBV_H = 2685, SUBV_W = 2686, SUB_MM = 2687, SUB_MMR6 = 2688, SUBu = 2689, SUBu_MM = 2690, SUXC1 = 2691, SUXC164 = 2692, SUXC1_MM = 2693, SW = 2694, SW16_MM = 2695, SW16_MMR6 = 2696, SW64 = 2697, SWC1 = 2698, SWC1_MM = 2699, SWC2 = 2700, SWC2_MMR6 = 2701, SWC2_R6 = 2702, SWC3 = 2703, SWDSP = 2704, SWDSP_MM = 2705, SWE = 2706, SWE_MM = 2707, SWL = 2708, SWL64 = 2709, SWLE = 2710, SWLE_MM = 2711, SWL_MM = 2712, SWM16_MM = 2713, SWM16_MMR6 = 2714, SWM32_MM = 2715, SWP_MM = 2716, SWR = 2717, SWR64 = 2718, SWRE = 2719, SWRE_MM = 2720, SWR_MM = 2721, SWSP_MM = 2722, SWSP_MMR6 = 2723, SWXC1 = 2724, SWXC1_MM = 2725, SW_MM = 2726, SW_MMR6 = 2727, SYNC = 2728, SYNCI = 2729, SYNCI_MM = 2730, SYNCI_MMR6 = 2731, SYNC_MM = 2732, SYNC_MMR6 = 2733, SYSCALL = 2734, SYSCALL_MM = 2735, Save16 = 2736, SaveX16 = 2737, SbRxRyOffMemX16 = 2738, SebRx16 = 2739, SehRx16 = 2740, ShRxRyOffMemX16 = 2741, SllX16 = 2742, SllvRxRy16 = 2743, SltRxRy16 = 2744, SltiRxImm16 = 2745, SltiRxImmX16 = 2746, SltiuRxImm16 = 2747, SltiuRxImmX16 = 2748, SltuRxRy16 = 2749, SraX16 = 2750, SravRxRy16 = 2751, SrlX16 = 2752, SrlvRxRy16 = 2753, SubuRxRyRz16 = 2754, SwRxRyOffMemX16 = 2755, SwRxSpImmX16 = 2756, TEQ = 2757, TEQI = 2758, TEQI_MM = 2759, TEQ_MM = 2760, TGE = 2761, TGEI = 2762, TGEIU = 2763, TGEIU_MM = 2764, TGEI_MM = 2765, TGEU = 2766, TGEU_MM = 2767, TGE_MM = 2768, TLBGINV = 2769, TLBGINVF = 2770, TLBGINVF_MM = 2771, TLBGINV_MM = 2772, TLBGP = 2773, TLBGP_MM = 2774, TLBGR = 2775, TLBGR_MM = 2776, TLBGWI = 2777, TLBGWI_MM = 2778, TLBGWR = 2779, TLBGWR_MM = 2780, TLBINV = 2781, TLBINVF = 2782, TLBINVF_MMR6 = 2783, TLBINV_MMR6 = 2784, TLBP = 2785, TLBP_MM = 2786, TLBR = 2787, TLBR_MM = 2788, TLBWI = 2789, TLBWI_MM = 2790, TLBWR = 2791, TLBWR_MM = 2792, TLT = 2793, TLTI = 2794, TLTIU_MM = 2795, TLTI_MM = 2796, TLTU = 2797, TLTU_MM = 2798, TLT_MM = 2799, TNE = 2800, TNEI = 2801, TNEI_MM = 2802, TNE_MM = 2803, TRUNC_L_D64 = 2804, TRUNC_L_D_MMR6 = 2805, TRUNC_L_S = 2806, TRUNC_L_S_MMR6 = 2807, TRUNC_W_D32 = 2808, TRUNC_W_D64 = 2809, TRUNC_W_D_MMR6 = 2810, TRUNC_W_MM = 2811, TRUNC_W_S = 2812, TRUNC_W_S_MM = 2813, TRUNC_W_S_MMR6 = 2814, TTLTIU = 2815, UDIV = 2816, UDIV_MM = 2817, V3MULU = 2818, VMM0 = 2819, VMULU = 2820, VSHF_B = 2821, VSHF_D = 2822, VSHF_H = 2823, VSHF_W = 2824, WAIT = 2825, WAIT_MM = 2826, WAIT_MMR6 = 2827, WRDSP = 2828, WRDSP_MM = 2829, WRPGPR_MMR6 = 2830, WSBH = 2831, WSBH_MM = 2832, WSBH_MMR6 = 2833, XOR = 2834, XOR16_MM = 2835, XOR16_MMR6 = 2836, XOR64 = 2837, XORI_B = 2838, XORI_MMR6 = 2839, XOR_MM = 2840, XOR_MMR6 = 2841, XOR_V = 2842, XORi = 2843, XORi64 = 2844, XORi_MM = 2845, XorRxRxRy16 = 2846, YIELD = 2847, INSTRUCTION_LIST_END = 2848 }; } // end namespace Mips } // end namespace llvm #endif // GET_INSTRINFO_ENUM #ifdef GET_INSTRINFO_SCHED_ENUM #undef GET_INSTRINFO_SCHED_ENUM namespace llvm { namespace Mips { namespace Sched { enum { NoInstrModel = 0, IIPseudo = 1, II_B = 2, II_BCCZAL = 3, II_MTC1 = 4, II_MFC1 = 5, II_JALR = 6, II_JAL = 7, II_CVT = 8, II_DMULT = 9, II_DMULTU = 10, II_DDIV = 11, II_DDIVU = 12, II_IndirectBranchPseudo = 13, II_MADD = 14, II_MADDU = 15, II_MFHI_MFLO = 16, II_MSUB = 17, II_MSUBU = 18, II_MTHI_MTLO = 19, II_MULT = 20, II_MULTU = 21, II_ReturnPseudo = 22, II_DIV = 23, II_DIVU = 24, II_J = 25, II_JR = 26, II_TRAP = 27, II_ADD = 28, II_ADDIUPC = 29, II_ADDIU = 30, II_ADDR_PS = 31, II_ADDU = 32, II_ADDI = 33, II_ALIGN = 34, II_ALUIPC = 35, II_AND = 36, II_ANDI = 37, II_AUI = 38, II_AUIPC = 39, IIM16Alu = 40, II_BADDU = 41, II_BC = 42, II_BALC = 43, II_BBIT = 44, II_BC1CCZ = 45, II_BC1F = 46, II_BC1FL = 47, II_BC1T = 48, II_BC1TL = 49, II_BC2CCZ = 50, II_BCC = 51, II_BCCC = 52, II_BCCZ = 53, II_BCCZC = 54, II_BCCZALS = 55, II_BITSWAP = 56, II_BREAK = 57, II_CACHE = 58, II_CACHEE = 59, II_CEIL = 60, II_CFC1 = 61, II_CFC2 = 62, II_INS = 63, II_CLASS_D = 64, II_CLASS_S = 65, II_CLO = 66, II_CLZ = 67, II_CMP_CC_D = 68, II_CMP_CC_S = 69, II_CRC32B = 70, II_CRC32CB = 71, II_CRC32CD = 72, II_CRC32CH = 73, II_CRC32CW = 74, II_CRC32D = 75, II_CRC32H = 76, II_CRC32W = 77, II_CTC1 = 78, II_CTC2 = 79, II_C_CC_D = 80, II_C_CC_S = 81, II_DADD = 82, II_DADDI = 83, II_DADDIU = 84, II_DADDU = 85, II_DAHI = 86, II_DALIGN = 87, II_DATI = 88, II_DAUI = 89, II_DBITSWAP = 90, II_DCLO = 91, II_DCLZ = 92, II_DERET = 93, II_EXT = 94, II_DI = 95, II_DLSA = 96, II_DMFC0 = 97, II_DMFC1 = 98, II_DMFC2 = 99, II_DMFGC0 = 100, II_DMOD = 101, II_DMODU = 102, II_DMT = 103, II_DMTC0 = 104, II_DMTC1 = 105, II_DMTC2 = 106, II_DMTGC0 = 107, II_DMUH = 108, II_DMUHU = 109, II_DMUL = 110, II_POP = 111, II_DROTR = 112, II_DROTR32 = 113, II_DROTRV = 114, II_DSBH = 115, II_DSHD = 116, II_DSLL = 117, II_DSLL32 = 118, II_DSLLV = 119, II_DSRA = 120, II_DSRA32 = 121, II_DSRAV = 122, II_DSRL = 123, II_DSRL32 = 124, II_DSRLV = 125, II_DSUB = 126, II_DSUBU = 127, II_DVP = 128, II_DVPE = 129, II_EHB = 130, II_EI = 131, II_EMT = 132, II_ERET = 133, II_ERETNC = 134, II_EVP = 135, II_EVPE = 136, II_ABS = 137, II_SQRT_D = 138, II_ADD_D = 139, II_ADD_PS = 140, II_ADD_S = 141, II_DIV_D = 142, II_DIV_S = 143, II_FLOOR = 144, II_MOV_D = 145, II_MOV_S = 146, II_MUL_D = 147, II_MUL_PS = 148, II_MUL_S = 149, II_NEG = 150, II_FORK = 151, II_SQRT_S = 152, II_SUB_D = 153, II_SUB_PS = 154, II_SUB_S = 155, II_GINVI = 156, II_GINVT = 157, II_HYPCALL = 158, II_JALR_HB = 159, II_JALRC = 160, II_JALRS = 161, II_JALS = 162, II_JIALC = 163, II_JIC = 164, II_JRADDIUSP = 165, II_JRC = 166, II_JR_HB = 167, II_LB = 168, II_LBE = 169, II_LBU = 170, II_LBUE = 171, II_LD = 172, II_LDC1 = 173, II_LDC2 = 174, II_LDC3 = 175, II_LDL = 176, II_LDPC = 177, II_LDR = 178, II_LDXC1 = 179, II_LH = 180, II_LHE = 181, II_LHU = 182, II_LHUE = 183, II_LI = 184, II_LL = 185, II_LLD = 186, II_LLE = 187, II_LSA = 188, II_LUI = 189, II_LUXC1 = 190, II_LW = 191, II_LWC1 = 192, II_LWC2 = 193, II_LWC3 = 194, II_LWE = 195, II_LWL = 196, II_LWLE = 197, II_LWM = 198, II_LWPC = 199, II_LWP = 200, II_LWR = 201, II_LWRE = 202, II_LWUPC = 203, II_LWU = 204, II_LWXC1 = 205, II_LWXS = 206, II_MADDF_D = 207, II_MADDF_S = 208, II_MADD_D = 209, II_MADD_S = 210, II_MAX_D = 211, II_MAXA_D = 212, II_MAX_S = 213, II_MAXA_S = 214, II_MFC0 = 215, II_MFC2 = 216, II_MFGC0 = 217, II_MFHC0 = 218, II_MFHC1 = 219, II_MFHGC0 = 220, II_MFTR = 221, II_MIN_S = 222, II_MINA_D = 223, II_MIN_D = 224, II_MINA_S = 225, II_MOD = 226, II_MODU = 227, II_MOVE = 228, II_MOVF_D = 229, II_MOVF = 230, II_MOVF_S = 231, II_MOVN_D = 232, II_MOVN = 233, II_MOVN_S = 234, II_MOVT_D = 235, II_MOVT = 236, II_MOVT_S = 237, II_MOVZ_D = 238, II_MOVZ = 239, II_MOVZ_S = 240, II_MSUBF_D = 241, II_MSUBF_S = 242, II_MSUB_D = 243, II_MSUB_S = 244, II_MTC0 = 245, II_MTC2 = 246, II_MTGC0 = 247, II_MTHC0 = 248, II_MTHC1 = 249, II_MTHGC0 = 250, II_MTTR = 251, II_MUH = 252, II_MUHU = 253, II_MUL = 254, II_MULR_PS = 255, II_MULU = 256, II_NMADD_D = 257, II_NMADD_S = 258, II_NMSUB_D = 259, II_NMSUB_S = 260, II_NOR = 261, II_NOT = 262, II_OR = 263, II_ORI = 264, II_PAUSE = 265, II_PREF = 266, II_PREFE = 267, II_RDHWR = 268, II_RDPGPR = 269, II_RECIP_D = 270, II_RECIP_S = 271, II_RINT_D = 272, II_RINT_S = 273, II_ROTR = 274, II_ROTRV = 275, II_ROUND = 276, II_RSQRT_D = 277, II_RSQRT_S = 278, II_RESTORE = 279, II_SB = 280, II_SBE = 281, II_SC = 282, II_SCD = 283, II_SCE = 284, II_SD = 285, II_SDBBP = 286, II_SDC1 = 287, II_SDC2 = 288, II_SDC3 = 289, II_SDL = 290, II_SDR = 291, II_SDXC1 = 292, II_SEB = 293, II_SEH = 294, II_SELCCZ = 295, II_SELCCZ_D = 296, II_SELCCZ_S = 297, II_SEL_D = 298, II_SEL_S = 299, II_SEQ_SNE = 300, II_SEQI_SNEI = 301, II_SH = 302, II_SHE = 303, II_SIGRIE = 304, II_SLL = 305, II_SLLV = 306, II_SLT_SLTU = 307, II_SLTI_SLTIU = 308, II_SRA = 309, II_SRAV = 310, II_SRL = 311, II_SRLV = 312, II_SSNOP = 313, II_SUB = 314, II_SUBU = 315, II_SUXC1 = 316, II_SW = 317, II_SWC1 = 318, II_SWC2 = 319, II_SWC3 = 320, II_SWE = 321, II_SWL = 322, II_SWLE = 323, II_SWM = 324, II_SWP = 325, II_SWR = 326, II_SWRE = 327, II_SWXC1 = 328, II_SYNC = 329, II_SYNCI = 330, II_SYSCALL = 331, II_SAVE = 332, II_TEQ = 333, II_TEQI = 334, II_TGE = 335, II_TGEI = 336, II_TGEIU = 337, II_TGEU = 338, II_TLBGINV = 339, II_TLBGINVF = 340, II_TLBGP = 341, II_TLBGR = 342, II_TLBGWI = 343, II_TLBGWR = 344, II_TLBINV = 345, II_TLBINVF = 346, II_TLBP = 347, II_TLBR = 348, II_TLBWI = 349, II_TLBWR = 350, II_TLT = 351, II_TLTI = 352, II_TTLTIU = 353, II_TLTU = 354, II_TNE = 355, II_TNEI = 356, II_TRUNC = 357, II_WAIT = 358, II_WRPGPR = 359, II_WSBH = 360, II_XOR = 361, II_XORI = 362, II_YIELD = 363, AND = 364, LUi = 365, NOR = 366, OR = 367, SLTi_SLTiu = 368, SUB = 369, SUBu = 370, XOR = 371, SSNOP = 372, NOP = 373, B = 374, BAL = 375, BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 376, BEQ_BEQL_BNE_BNEL = 377, BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 378, BREAK = 379, DERET = 380, ERET = 381, ERet_RetRA = 382, ERETNC = 383, J_TAILCALL = 384, JR_TAILCALLREG_TAILCALLREGHB = 385, JR_HB = 386, PseudoIndirectBranch_PseudoIndirectHazardBranch = 387, PseudoReturn = 388, SDBBP = 389, SYSCALL = 390, TEQ = 391, TEQI = 392, TGE = 393, TGEI = 394, TGEIU = 395, TGEU = 396, TLT = 397, TLTI = 398, TLTU = 399, TNE = 400, TNEI = 401, TRAP = 402, TTLTIU = 403, WAIT = 404, PAUSE = 405, JAL = 406, JALR_JALRHBPseudo_JALRPseudo = 407, JALR_HB = 408, JALX = 409, TLBINV = 410, TLBINVF = 411, TLBP = 412, TLBR = 413, TLBWI = 414, TLBWR = 415, MFC0 = 416, MTC0 = 417, MFC2 = 418, MTC2 = 419, HYPCALL = 420, MFGC0 = 421, MFHGC0 = 422, MTGC0 = 423, MTHGC0 = 424, TLBGINV = 425, TLBGINVF = 426, TLBGP = 427, TLBGR = 428, TLBGWI = 429, TLBGWR = 430, LB = 431, LBu = 432, LH = 433, LHu = 434, LW = 435, LL = 436, LWC2 = 437, LWC3 = 438, LDC2 = 439, LDC3 = 440, LBE = 441, LBuE = 442, LHE = 443, LHuE = 444, LWE = 445, LLE = 446, LWPC = 447, LWL = 448, LWR = 449, LWLE = 450, LWRE = 451, SB = 452, SH = 453, SW = 454, SWC2 = 455, SWC3 = 456, SDC2 = 457, SDC3 = 458, SC = 459, SBE = 460, SHE = 461, SWE = 462, SCE = 463, SWL = 464, SWR = 465, SWLE = 466, SWRE = 467, PREF = 468, PREFE = 469, CACHE = 470, CACHEE = 471, SYNC = 472, SYNCI = 473, CLO = 474, CLZ = 475, DI = 476, EI = 477, MFHI_MFLO_PseudoMFHI_PseudoMFLO = 478, EHB = 479, RDHWR = 480, WSBH = 481, MOVN_I_I = 482, MOVZ_I_I = 483, DIV_PseudoSDIV_SDIV = 484, DIVU_PseudoUDIV_UDIV = 485, MUL = 486, MULT_PseudoMULT = 487, MULTu_PseudoMULTu = 488, MADD_PseudoMADD = 489, MADDU_PseudoMADDU = 490, MSUB_PseudoMSUB = 491, MSUBU_PseudoMSUBU = 492, MTHI_MTLO_PseudoMTLOHI = 493, EXT = 494, INS = 495, ADD = 496, ADDi = 497, ADDiu = 498, ANDi = 499, ORi = 500, ROTR = 501, SEB = 502, SEH = 503, SLT_SLTu = 504, SLL = 505, SRA = 506, SRL = 507, XORi = 508, ADDu = 509, SLLV = 510, SRAV = 511, SRLV = 512, LSA = 513, COPY = 514, VSHF_B_VSHF_D_VSHF_H_VSHF_W = 515, BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 516, BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 517, INSERT_B_INSERT_D_INSERT_H_INSERT_W = 518, SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 519, BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 520, BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 521, BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 522, BSELI_B_BSEL_V = 523, BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 524, BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 525, PCNT_B_PCNT_D_PCNT_H_PCNT_W = 526, SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 527, BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 528, CFCMSA_CTCMSA = 529, FABS_S_FABS_D32_FABS_D64 = 530, MOVF_D32_MOVF_D64 = 531, MOVF_S = 532, MOVT_D32_MOVT_D64 = 533, MOVT_S = 534, FMOV_D32_FMOV_D64 = 535, FMOV_S = 536, FNEG_S_FNEG_D32_FNEG_D64 = 537, ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 538, ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 539, ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 540, ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 541, AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 542, SHF_B_SHF_H_SHF_W = 543, FILL_B_FILL_D_FILL_H_FILL_W = 544, SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 545, MOVE_V = 546, LDI_B_LDI_D_LDI_H_LDI_W = 547, AND_V_NOR_V_OR_V_XOR_V = 548, ANDI_B_NORI_B_ORI_B_XORI_B = 549, AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO_NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO_OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO_XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 550, FILL_FD_PSEUDO_FILL_FW_PSEUDO = 551, INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 552, FEXP2_D_FEXP2_W = 553, CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 554, CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 555, CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 556, CMP_UN_D = 557, CMP_UN_S = 558, CMP_UEQ_D = 559, CMP_UEQ_S = 560, CMP_EQ_D = 561, CMP_EQ_S = 562, CMP_LT_D = 563, CMP_LT_S = 564, CMP_ULT_D = 565, CMP_ULT_S = 566, CMP_LE_D = 567, CMP_LE_S = 568, CMP_ULE_D = 569, CMP_ULE_S = 570, FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 571, FSUEQ_D_FSUEQ_W = 572, FSULE_D_FSULE_W = 573, FSULT_D_FSULT_W = 574, FSUNE_D_FSUNE_W = 575, FSUN_D_FSUN_W = 576, FCAF_D_FCAF_W = 577, FCEQ_D_FCEQ_W = 578, FCLE_D_FCLE_W = 579, FCLT_D_FCLT_W = 580, FCNE_D_FCNE_W = 581, FCOR_D_FCOR_W = 582, FCUEQ_D_FCUEQ_W = 583, FCULE_D_FCULE_W = 584, FCULT_D_FCULT_W = 585, FCUNE_D_FCUNE_W = 586, FCUN_D_FCUN_W = 587, FABS_D_FABS_W = 588, FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 589, FFQL_D_FFQL_W = 590, FFQR_D_FFQR_W = 591, FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 592, FRINT_D_FRINT_W = 593, FTQ_H_FTQ_W = 594, FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 595, FEXDO_H_FEXDO_W = 596, FEXUPL_D_FEXUPL_W = 597, FEXUPR_D_FEXUPR_W = 598, FCLASS_D_FCLASS_W = 599, FMAX_A_D_FMAX_A_W = 600, FMAX_D_FMAX_W = 601, FMIN_A_D_FMIN_A_W = 602, FMIN_D_FMIN_W = 603, FLOG2_D_FLOG2_W = 604, ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 605, ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 606, INSVE_B_INSVE_D_INSVE_H_INSVE_W = 607, SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 608, SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 609, SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 610, SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 611, SUBV_B_SUBV_D_SUBV_H_SUBV_W = 612, MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 613, DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 614, HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 615, HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 616, MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 617, MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 618, MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 619, MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 620, SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 621, SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 622, SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 623, SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 624, SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 625, PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 626, NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 627, FADD_D32_FADD_D64 = 628, FADD_PS64 = 629, FADD_S = 630, FMUL_D32_FMUL_D64 = 631, FMUL_PS64 = 632, FMUL_S = 633, FSUB_D32_FSUB_D64 = 634, FSUB_PS64 = 635, FSUB_S = 636, TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 637, CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 638, CVT_PS_S64_CVT_S_PL64_CVT_S_PU64 = 639, C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 640, C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 641, FCMP_D32_FCMP_D64 = 642, FCMP_S32 = 643, PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 644, PLL_PS64_PLU_PS64_PUL_PS64_PUU_PS64 = 645, FDIV_S = 646, FDIV_D32_FDIV_D64 = 647, FSQRT_S = 648, FSQRT_D32_FSQRT_D64 = 649, FRCP_D_FRCP_W = 650, FRSQRT_D_FRSQRT_W = 651, RECIP_D32_RECIP_D64 = 652, RSQRT_D32_RSQRT_D64 = 653, RECIP_S = 654, RSQRT_S = 655, FMADD_D_FMADD_W = 656, FMSUB_D_FMSUB_W = 657, FDIV_W = 658, FDIV_D = 659, FSQRT_W = 660, FSQRT_D = 661, FMUL_D_FMUL_W = 662, FADD_D_FADD_W = 663, FSUB_D_FSUB_W = 664, DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 665, DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 666, DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 667, MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 668, MADDV_B_MADDV_D_MADDV_H_MADDV_W = 669, MULV_B_MULV_D_MULV_H_MULV_W = 670, MADDR_Q_H_MADDR_Q_W = 671, MADD_Q_H_MADD_Q_W = 672, MSUBR_Q_H_MSUBR_Q_W = 673, MSUB_Q_H_MSUB_Q_W = 674, MULR_Q_H_MULR_Q_W = 675, MUL_Q_H_MUL_Q_W = 676, MADD_D32_MADD_D64 = 677, MADD_S = 678, MSUB_D32_MSUB_D64 = 679, MSUB_S = 680, NMADD_D32_NMADD_D64 = 681, NMADD_S = 682, NMSUB_D32_NMSUB_D64 = 683, NMSUB_S = 684, CTC1 = 685, MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 686, MTHC1_D32_MTHC1_D64 = 687, COPY_U_B_COPY_U_H_COPY_U_W = 688, COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 689, BC1F = 690, BC1FL = 691, BC1T = 692, BC1TL = 693, CFC1 = 694, MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 695, MFHC1_D32_MFHC1_D64 = 696, MOVF_I = 697, MOVT_I = 698, SDC1_SDC164 = 699, SDXC1_SDXC164 = 700, SWC1 = 701, SWXC1 = 702, SUXC1_SUXC164 = 703, ST_B_ST_D_ST_H_ST_W = 704, ST_F16 = 705, MOVN_I_D32_MOVN_I_D64 = 706, MOVN_I_S = 707, MOVZ_I_D32_MOVZ_I_D64 = 708, MOVZ_I_S = 709, LDC1_LDC164 = 710, LDXC1_LDXC164 = 711, LWC1 = 712, LWXC1 = 713, LUXC1_LUXC164 = 714, LD_B_LD_D_LD_H_LD_W = 715, LD_F16 = 716, CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 717, FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 718, ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 719, ROTRV = 720, ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 721, ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 722, ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 723, LEA_ADDiu = 724, ADDIUPC = 725, ALIGN = 726, ALUIPC = 727, AUI = 728, AUIPC = 729, BITSWAP = 730, CLO_R6 = 731, CLZ_R6 = 732, LSA_R6 = 733, SELEQZ_SELNEZ = 734, AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 735, SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 736, Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 737, ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 738, ADDU16_MM_ADDu_MM = 739, ADD_MM = 740, ADDi_MM = 741, AND16_MM_ANDI16_MM_AND_MM = 742, ANDi_MM = 743, CLO_MM = 744, CLZ_MM = 745, EXT_MM = 746, INS_MM = 747, LI16_MM = 748, LUi_MM = 749, MOVE16_MM = 750, MOVEP_MM = 751, NOR_MM = 752, NOT16_MM = 753, OR16_MM_OR_MM = 754, ORi_MM = 755, ROTRV_MM = 756, ROTR_MM = 757, SEB_MM = 758, SEH_MM = 759, SLL16_MM_SLL_MM = 760, SLLV_MM = 761, SLT_MM_SLTu_MM = 762, SLTi_MM_SLTiu_MM = 763, SRAV_MM = 764, SRA_MM = 765, SRL16_MM_SRL_MM = 766, SRLV_MM = 767, SSNOP_MM = 768, SUBU16_MM_SUBu_MM = 769, SUB_MM = 770, WSBH_MM = 771, XOR16_MM_XOR_MM = 772, XORi_MM = 773, ADDIUPC_MMR6 = 774, ADDIU_MMR6 = 775, ADDU16_MMR6_ADDU_MMR6 = 776, ADD_MMR6 = 777, ALIGN_MMR6 = 778, ALUIPC_MMR6 = 779, AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 780, ANDI_MMR6 = 781, AUIPC_MMR6 = 782, AUI_MMR6 = 783, BITSWAP_MMR6 = 784, CLO_MMR6 = 785, CLZ_MMR6 = 786, EXT_MMR6 = 787, INS_MMR6 = 788, LI16_MMR6 = 789, LSA_MMR6 = 790, LUI_MMR6 = 791, MOVE16_MMR6 = 792, NOR_MMR6 = 793, NOT16_MMR6 = 794, OR16_MMR6_OR_MMR6 = 795, ORI_MMR6 = 796, SELEQZ_MMR6_SELNEZ_MMR6 = 797, SLL16_MMR6_SLL_MMR6 = 798, SRL16_MMR6 = 799, SSNOP_MMR6 = 800, SUBU16_MMR6_SUBU_MMR6 = 801, SUB_MMR6 = 802, WSBH_MMR6 = 803, XOR16_MMR6_XOR_MMR6 = 804, XORI_MMR6 = 805, AND64_ANDi64 = 806, DEXT64_32 = 807, DSLL64_32 = 808, ORi64 = 809, SEB64 = 810, SEH64 = 811, SLL64_32_SLL64_64 = 812, SLT64_SLTu64 = 813, SLTi64_SLTiu64 = 814, XOR64_XORi64 = 815, DADD = 816, DADDi = 817, DADDiu = 818, DADDu = 819, DCLO = 820, DCLZ = 821, DEXT_DEXTM_DEXTU = 822, DINS_DINSM_DINSU = 823, DROTR = 824, DROTR32 = 825, DROTRV = 826, DSBH = 827, DSHD = 828, DSLL = 829, DSLL32 = 830, DSLLV = 831, DSRA = 832, DSRA32 = 833, DSRAV = 834, DSRL = 835, DSRL32 = 836, DSRLV = 837, DSUB = 838, DSUBu = 839, LEA_ADDiu64 = 840, LUi64 = 841, NOR64 = 842, OR64 = 843, DALIGN = 844, DAHI = 845, DATI = 846, DAUI = 847, DCLO_R6 = 848, DCLZ_R6 = 849, DBITSWAP = 850, DLSA_DLSA_R6 = 851, SELEQZ64_SELNEZ64 = 852, MADD = 853, MADDU = 854, MSUB = 855, MSUBU = 856, PseudoMADD_MM = 857, PseudoMADDU_MM = 858, PseudoMSUB_MM = 859, PseudoMSUBU_MM = 860, PseudoMULT_MM = 861, PseudoMULTu_MM = 862, PseudoMULT = 863, PseudoMULTu = 864, PseudoSDIV_SDIV = 865, PseudoUDIV_UDIV = 866, PseudoMFHI_MM_PseudoMFLO_MM = 867, PseudoMTLOHI_MM = 868, MUH = 869, MUHU = 870, MULU = 871, MUL_R6 = 872, MOD = 873, MODU = 874, MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 875, DivRxRy16 = 876, DivuRxRy16 = 877, MULT_MM = 878, MULTu_MM = 879, MADD_MM = 880, MADDU_MM = 881, MSUB_MM = 882, MSUBU_MM = 883, MUL_MM = 884, SDIV_MM_SDIV_MM_Pseudo = 885, UDIV_MM_UDIV_MM_Pseudo = 886, MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 887, MOVF_I_MM = 888, MOVT_I_MM = 889, MTHI_MM_MTLO_MM = 890, RDHWR_MM = 891, MUHU_MMR6 = 892, MUH_MMR6 = 893, MULU_MMR6 = 894, MUL_MMR6 = 895, MODU_MMR6 = 896, MOD_MMR6 = 897, DIVU_MMR6 = 898, DIV_MMR6 = 899, RDHWR_MMR6 = 900, DMULU = 901, DMULT_PseudoDMULT = 902, DMULTu_PseudoDMULTu = 903, DSDIV_PseudoDSDIV = 904, DUDIV_PseudoDUDIV = 905, MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 906, PseudoMTLOHI64 = 907, MTHI64_MTLO64 = 908, RDHWR64 = 909, MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 910, MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 911, DMUH = 912, DMUHU = 913, DMUL_R6 = 914, DDIV = 915, DMOD = 916, DDIVU = 917, DMODU = 918, BAL_BR_BLTZAL = 919, BEQ_BNE = 920, BGTZ_BGEZ_BLEZ_BLTZ = 921, J = 922, JR = 923, ERet = 924, BGEZAL = 925, BALC = 926, BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 927, JIALC = 928, BC = 929, BC2EQZ_BC2NEZ = 930, BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 931, BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 932, JIC = 933, JR_HB_R6 = 934, SIGRIE = 935, PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 936, TAILCALLR6REG_TAILCALLHBR6REG = 937, SDBBP_R6 = 938, Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 939, BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 940, Jal16_JalB16 = 941, JumpLinkReg16 = 942, Break16 = 943, SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 944, B16_MM_B_MM = 945, BAL_BR_MM = 946, BC1F_MM = 947, BC1T_MM = 948, BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 949, BEQZC_MM_BNEZC_MM = 950, BEQ_MM_BNE_MM = 951, DERET_MM = 952, ERET_MM = 953, JR16_MM_JR_MM = 954, J_MM = 955, B_MM_Pseudo = 956, BGEZALS_MM_BLTZALS_MM = 957, BGEZAL_MM_BLTZAL_MM = 958, JALR16_MM_JALR_MM = 959, JALRS16_MM_JALRS_MM = 960, JALS_MM = 961, JALX_MM_JAL_MM = 962, TAILCALLREG_MM = 963, TAILCALL_MM = 964, PseudoIndirectBranch_MM = 965, BREAK16_MM_BREAK_MM = 966, SDBBP16_MM_SDBBP_MM = 967, SYSCALL_MM = 968, TEQI_MM = 969, TEQ_MM = 970, TGEIU_MM = 971, TGEI_MM = 972, TGEU_MM = 973, TGE_MM = 974, TLTIU_MM = 975, TLTI_MM = 976, TLTU_MM = 977, TLT_MM = 978, TNEI_MM = 979, TNE_MM = 980, TRAP_MM = 981, BC16_MMR6_BC_MMR6 = 982, BC1EQZC_MMR6_BC1NEZC_MMR6 = 983, BC2EQZC_MMR6_BC2NEZC_MMR6 = 984, BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 985, BEQZC16_MMR6_BNEZC16_MMR6 = 986, BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 987, DERET_MMR6 = 988, ERETNC_MMR6 = 989, JAL_MMR6 = 990, ERET_MMR6 = 991, JIC_MMR6 = 992, JRADDIUSP_JRCADDIUSP_MMR6 = 993, JRC16_MM = 994, JRC16_MMR6 = 995, SIGRIE_MMR6 = 996, B_MMR6_Pseudo = 997, PseudoIndirectBranch_MMR6 = 998, BALC_MMR6 = 999, BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 1000, JALRC16_MMR6 = 1001, JALRC_HB_MMR6 = 1002, JALRC_MMR6 = 1003, JIALC_MMR6 = 1004, TAILCALLREG_MMR6 = 1005, TAILCALL_MMR6 = 1006, BREAK16_MMR6_BREAK_MMR6 = 1007, SDBBP_MMR6_SDBBP16_MMR6 = 1008, BEQ64_BNE64 = 1009, BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 1010, JR64 = 1011, JALR64_JALR64Pseudo_JALRHB64Pseudo = 1012, JALR_HB64 = 1013, JR_HB64 = 1014, TAILCALLREG64_TAILCALLREGHB64 = 1015, PseudoReturn64 = 1016, BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64 = 1017, BEQZC64_BGEZC64_BGTZC64_BLEZC64_BLTZC64_BNEZC64 = 1018, JIC64 = 1019, PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1020, JIALC64 = 1021, JR_HB64_R6 = 1022, TAILCALL64R6REG_TAILCALLHB64R6REG = 1023, PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6 = 1024, EVP = 1025, DVP = 1026, TLBP_MM = 1027, TLBR_MM = 1028, TLBWI_MM = 1029, TLBWR_MM = 1030, DI_MM = 1031, EI_MM = 1032, EHB_MM = 1033, PAUSE_MM = 1034, WAIT_MM = 1035, RDPGPR_MMR6 = 1036, WRPGPR_MMR6 = 1037, TLBINV_MMR6 = 1038, TLBINVF_MMR6 = 1039, MFHC0_MMR6 = 1040, MFC0_MMR6 = 1041, MFHC2_MMR6_MFC2_MMR6 = 1042, MTHC0_MMR6 = 1043, MTC0_MMR6 = 1044, MTHC2_MMR6_MTC2_MMR6 = 1045, EVP_MMR6 = 1046, DVP_MMR6 = 1047, DI_MMR6 = 1048, EI_MMR6 = 1049, EHB_MMR6 = 1050, PAUSE_MMR6 = 1051, WAIT_MMR6 = 1052, DMFC0 = 1053, DMTC0 = 1054, DMFC2 = 1055, DMTC2 = 1056, CFC2_MM = 1057, CTC2_MM = 1058, DMT = 1059, DVPE = 1060, EMT = 1061, EVPE = 1062, MFTR = 1063, MTTR = 1064, YIELD = 1065, FORK = 1066, DMFGC0 = 1067, DMTGC0 = 1068, HYPCALL_MM = 1069, TLBGINVF_MM = 1070, TLBGINV_MM = 1071, TLBGP_MM = 1072, TLBGR_MM = 1073, TLBGWI_MM = 1074, TLBGWR_MM = 1075, MFGC0_MM = 1076, MFHGC0_MM = 1077, MTGC0_MM = 1078, MTHGC0_MM = 1079, SC_MMR6 = 1080, LDC2_R6 = 1081, LL_R6 = 1082, LWC2_R6 = 1083, SWC2_R6 = 1084, SDC2_R6 = 1085, SC_R6 = 1086, PREF_R6 = 1087, CACHE_R6 = 1088, GINVI = 1089, GINVT = 1090, LBE_MM = 1091, LBuE_MM = 1092, LHE_MM = 1093, LHuE_MM = 1094, LWE_MM = 1095, LWLE_MM = 1096, LWRE_MM = 1097, LLE_MM = 1098, SBE_MM = 1099, SB_MM = 1100, SHE_MM = 1101, SWE_MM = 1102, SWLE_MM = 1103, SWRE_MM = 1104, SCE_MM = 1105, PREFE_MM = 1106, CACHEE_MM = 1107, Restore16_RestoreX16 = 1108, LbRxRyOffMemX16 = 1109, LbuRxRyOffMemX16 = 1110, LhRxRyOffMemX16 = 1111, LhuRxRyOffMemX16 = 1112, LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1113, Save16_SaveX16 = 1114, SbRxRyOffMemX16 = 1115, ShRxRyOffMemX16 = 1116, SwRxRyOffMemX16_SwRxSpImmX16 = 1117, LBU16_MM_LBu_MM = 1118, LB_MM = 1119, LHU16_MM_LHu_MM = 1120, LH_MM = 1121, LL_MM = 1122, LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1123, LWL_MM = 1124, LWM16_MM_LWM32_MM = 1125, LWP_MM = 1126, LWR_MM = 1127, LWU_MM = 1128, LWXS_MM = 1129, SB16_MM = 1130, SC_MM = 1131, SH16_MM_SH_MM = 1132, SW16_MM_SWSP_MM_SW_MM = 1133, SWL_MM = 1134, SWM16_MM_SWM32_MM = 1135, SWM_MM = 1136, SWP_MM = 1137, SWR_MM = 1138, PREF_MM_PREFX_MM = 1139, CACHE_MM = 1140, SYNC_MM = 1141, SYNCI_MM = 1142, GINVI_MMR6 = 1143, GINVT_MMR6 = 1144, LBU_MMR6 = 1145, LB_MMR6 = 1146, LDC2_MMR6 = 1147, LL_MMR6 = 1148, LWM16_MMR6 = 1149, LWC2_MMR6 = 1150, LWPC_MMR6 = 1151, LW_MMR6 = 1152, SB16_MMR6_SB_MMR6 = 1153, SDC2_MMR6 = 1154, SH16_MMR6_SH_MMR6 = 1155, SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1156, SWC2_MMR6 = 1157, SWM16_MMR6 = 1158, SYNC_MMR6 = 1159, SYNCI_MMR6 = 1160, PREF_MMR6 = 1161, CACHE_MMR6 = 1162, LD = 1163, LL64_LLD = 1164, LWu = 1165, LB64 = 1166, LBu64 = 1167, LH64 = 1168, LHu64 = 1169, LW64 = 1170, LWL64 = 1171, LWR64 = 1172, LDL = 1173, LDR = 1174, SD = 1175, SC64_SCD = 1176, SB64 = 1177, SH64 = 1178, SW64 = 1179, SWL64 = 1180, SWR64 = 1181, SDL = 1182, SDR = 1183, LWUPC = 1184, LDPC = 1185, LLD_R6 = 1186, LL64_R6 = 1187, SC64_R6 = 1188, SCD_R6 = 1189, CRC32B = 1190, CRC32H = 1191, CRC32W = 1192, CRC32CB = 1193, CRC32CH = 1194, CRC32CW = 1195, CRC32D = 1196, CRC32CD = 1197, BADDu = 1198, BBIT0_BBIT032_BBIT1_BBIT132 = 1199, CINS_CINS32_CINS64_32_CINS_i32 = 1200, DMFC2_OCTEON = 1201, DMTC2_OCTEON = 1202, DPOP_POP = 1203, EXTS_EXTS32 = 1204, MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1205, SEQ_SNE = 1206, SEQi_SNEi = 1207, V3MULU_VMM0_VMULU = 1208, DMUL = 1209, SAA_SAAD = 1210, ADDR_PS64 = 1211, CVT_PS_PW64_CVT_PW_PS64 = 1212, MULR_PS64 = 1213, PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 1214, MOVT_I64 = 1215, MOVF_I64 = 1216, MOVZ_I64_S = 1217, MOVN_I64_D64 = 1218, MOVN_I64_S = 1219, MOVZ_I64_D64 = 1220, SELEQZ_S_SELNEZ_S = 1221, SELEQZ_D_SELNEZ_D = 1222, MAX_S_MAXA_S = 1223, MAX_D_MAXA_D = 1224, MIN_S_MINA_D = 1225, MIN_D_MINA_S = 1226, CLASS_S = 1227, CLASS_D = 1228, RINT_S = 1229, RINT_D = 1230, BC1EQZ_BC1NEZ = 1231, SEL_D = 1232, SEL_S = 1233, MADDF_S = 1234, MSUBF_S = 1235, MADDF_D = 1236, MSUBF_D = 1237, MOVF_D32_MM = 1238, MOVF_S_MM = 1239, MOVN_I_D32_MM = 1240, MOVN_I_S_MM = 1241, MOVT_D32_MM = 1242, MOVT_S_MM = 1243, MOVZ_I_D32_MM = 1244, MOVZ_I_S_MM = 1245, CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1246, CEIL_W_MM_CEIL_W_S_MM = 1247, FLOOR_W_MM_FLOOR_W_S_MM = 1248, NMADD_S_MM = 1249, NMADD_D32_MM = 1250, NMSUB_S_MM = 1251, NMSUB_D32_MM = 1252, MADD_S_MM = 1253, MADD_D32_MM = 1254, ROUND_W_MM_ROUND_W_S_MM = 1255, TRUNC_W_MM_TRUNC_W_S_MM = 1256, C_F_D32_MM_C_F_D64_MM = 1257, C_F_S_MM = 1258, C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1259, C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1260, C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1261, C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1262, C_NGLE_D32_MM_C_NGLE_D64_MM = 1263, C_NGLE_S_MM = 1264, FCMP_S32_MM = 1265, FCMP_D32_MM = 1266, MFC1_MM = 1267, MFHC1_D32_MM_MFHC1_D64_MM = 1268, MTC1_MM_MTC1_D64_MM = 1269, MTHC1_D32_MM_MTHC1_D64_MM = 1270, FABS_D32_MM_FABS_D64_MM = 1271, FABS_S_MM = 1272, FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1273, FADD_D32_MM_FADD_D64_MM = 1274, FADD_S_MM = 1275, FMOV_D32_MM_FMOV_D64_MM = 1276, FMOV_S_MM = 1277, FMUL_D32_MM_FMUL_D64_MM = 1278, FMUL_S_MM = 1279, FSUB_D32_MM_FSUB_D64_MM = 1280, FSUB_S_MM = 1281, MSUB_S_MM = 1282, MSUB_D32_MM = 1283, FDIV_S_MM = 1284, FDIV_D32_MM_FDIV_D64_MM = 1285, FSQRT_S_MM = 1286, FSQRT_D32_MM_FSQRT_D64_MM = 1287, RECIP_S_MM_RSQRT_S_MM = 1288, RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1289, SDC1_MM_D32_SDC1_MM_D64 = 1290, SWC1_MM = 1291, SUXC1_MM = 1292, SWXC1_MM = 1293, CFC1_MM = 1294, CTC1_MM = 1295, LDC1_MM_D32_LDC1_MM_D64 = 1296, LUXC1_MM = 1297, LWC1_MM = 1298, LWXC1_MM = 1299, FNEG_S_MMR6 = 1300, CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1301, CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1302, CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1303, CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1304, CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1305, CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1306, CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1307, TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1308, ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1309, FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1310, CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1311, MFC1_MMR6 = 1312, MTC1_MMR6 = 1313, CLASS_S_MMR6_CLASS_D_MMR6 = 1314, FADD_S_MMR6 = 1315, MAX_D_MMR6 = 1316, MAX_S_MMR6 = 1317, MIN_D_MMR6 = 1318, MIN_S_MMR6 = 1319, MAXA_D_MMR6 = 1320, MAXA_S_MMR6 = 1321, MINA_D_MMR6 = 1322, MINA_S_MMR6 = 1323, SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1324, SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1325, SEL_D_MMR6 = 1326, SEL_S_MMR6 = 1327, RINT_S_MMR6_RINT_D_MMR6 = 1328, MADDF_D_MMR6 = 1329, MADDF_S_MMR6 = 1330, MSUBF_D_MMR6 = 1331, MSUBF_S_MMR6 = 1332, FMOV_S_MMR6 = 1333, FMUL_S_MMR6 = 1334, FSUB_S_MMR6 = 1335, FMOV_D_MMR6 = 1336, FDIV_S_MMR6 = 1337, SDC1_D64_MMR6 = 1338, LDC1_D64_MMR6 = 1339, DMFC1 = 1340, DMTC1 = 1341, SWDSP = 1342, LWDSP = 1343, PseudoMTLOHI_DSP = 1344, EXTRV_RS_W = 1345, EXTRV_R_W = 1346, EXTRV_S_H = 1347, EXTRV_W = 1348, EXTR_RS_W = 1349, EXTR_R_W = 1350, EXTR_S_H = 1351, EXTR_W = 1352, INSV = 1353, MTHLIP = 1354, MTHI_DSP = 1355, MTLO_DSP = 1356, ABSQ_S_PH = 1357, ABSQ_S_W = 1358, ADDQ_PH = 1359, ADDQ_S_PH = 1360, ADDQ_S_W = 1361, ADDSC = 1362, ADDU_QB = 1363, ADDU_S_QB = 1364, ADDWC = 1365, BITREV = 1366, BPOSGE32 = 1367, CMPGU_EQ_QB = 1368, CMPGU_LE_QB = 1369, CMPGU_LT_QB = 1370, CMPU_EQ_QB = 1371, CMPU_LE_QB = 1372, CMPU_LT_QB = 1373, CMP_EQ_PH = 1374, CMP_LE_PH = 1375, CMP_LT_PH = 1376, DPAQ_SA_L_W = 1377, DPAQ_S_W_PH = 1378, DPAU_H_QBL = 1379, DPAU_H_QBR = 1380, DPSQ_SA_L_W = 1381, DPSQ_S_W_PH = 1382, DPSU_H_QBL = 1383, DPSU_H_QBR = 1384, EXTPDPV = 1385, EXTPDP = 1386, EXTPV = 1387, EXTP = 1388, LBUX = 1389, LHX = 1390, LWX = 1391, MADDU_DSP = 1392, MADD_DSP = 1393, MAQ_SA_W_PHL = 1394, MAQ_SA_W_PHR = 1395, MAQ_S_W_PHL = 1396, MAQ_S_W_PHR = 1397, MFHI_DSP = 1398, MFLO_DSP = 1399, MODSUB = 1400, MSUBU_DSP = 1401, MSUB_DSP = 1402, MULEQ_S_W_PHL = 1403, MULEQ_S_W_PHR = 1404, MULEU_S_PH_QBL = 1405, MULEU_S_PH_QBR = 1406, MULQ_RS_PH = 1407, MULSAQ_S_W_PH = 1408, MULTU_DSP = 1409, MULT_DSP = 1410, PACKRL_PH = 1411, PICK_PH = 1412, PICK_QB = 1413, PRECEQU_PH_QBLA = 1414, PRECEQU_PH_QBL = 1415, PRECEQU_PH_QBRA = 1416, PRECEQU_PH_QBR = 1417, PRECEQ_W_PHL = 1418, PRECEQ_W_PHR = 1419, PRECEU_PH_QBLA = 1420, PRECEU_PH_QBL = 1421, PRECEU_PH_QBRA = 1422, PRECEU_PH_QBR = 1423, PRECRQU_S_QB_PH = 1424, PRECRQ_PH_W = 1425, PRECRQ_QB_PH = 1426, PRECRQ_RS_PH_W = 1427, RADDU_W_QB = 1428, RDDSP = 1429, REPLV_PH = 1430, REPLV_QB = 1431, REPL_PH = 1432, REPL_QB = 1433, SHILOV = 1434, SHILO = 1435, SHLLV_PH = 1436, SHLLV_QB = 1437, SHLLV_S_PH = 1438, SHLLV_S_W = 1439, SHLL_PH = 1440, SHLL_QB = 1441, SHLL_S_PH = 1442, SHLL_S_W = 1443, SHRAV_PH = 1444, SHRAV_R_PH = 1445, SHRAV_R_W = 1446, SHRA_PH = 1447, SHRA_R_PH = 1448, SHRA_R_W = 1449, SHRLV_QB = 1450, SHRL_QB = 1451, SUBQ_PH = 1452, SUBQ_S_PH = 1453, SUBQ_S_W = 1454, SUBU_QB = 1455, SUBU_S_QB = 1456, WRDSP = 1457, PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1458, PseudoPICK_PH_PseudoPICK_QB = 1459, ABSQ_S_QB = 1460, ADDQH_PH = 1461, ADDQH_R_PH = 1462, ADDQH_R_W = 1463, ADDQH_W = 1464, ADDUH_QB = 1465, ADDUH_R_QB = 1466, ADDU_PH = 1467, ADDU_S_PH = 1468, APPEND = 1469, BALIGN = 1470, CMPGDU_EQ_QB = 1471, CMPGDU_LE_QB = 1472, CMPGDU_LT_QB = 1473, DPA_W_PH = 1474, DPAQX_SA_W_PH = 1475, DPAQX_S_W_PH = 1476, DPAX_W_PH = 1477, DPS_W_PH = 1478, DPSQX_S_W_PH = 1479, DPSQX_SA_W_PH = 1480, DPSX_W_PH = 1481, MUL_PH = 1482, MUL_S_PH = 1483, MULQ_RS_W = 1484, MULQ_S_PH = 1485, MULQ_S_W = 1486, MULSA_W_PH = 1487, PRECR_QB_PH = 1488, PRECR_SRA_PH_W = 1489, PRECR_SRA_R_PH_W = 1490, PREPEND = 1491, SHRA_QB = 1492, SHRA_R_QB = 1493, SHRAV_QB = 1494, SHRAV_R_QB = 1495, SHRL_PH = 1496, SHRLV_PH = 1497, SUBQH_PH = 1498, SUBQH_R_PH = 1499, SUBQH_W = 1500, SUBQH_R_W = 1501, SUBU_PH = 1502, SUBU_S_PH = 1503, SUBUH_QB = 1504, SUBUH_R_QB = 1505, LWDSP_MM = 1506, SWDSP_MM = 1507, ABSQ_S_PH_MM = 1508, ABSQ_S_W_MM = 1509, ADDQ_PH_MM = 1510, ADDQ_S_PH_MM = 1511, ADDQ_S_W_MM = 1512, ADDSC_MM = 1513, ADDU_QB_MM = 1514, ADDU_S_QB_MM = 1515, ADDWC_MM = 1516, BITREV_MM = 1517, BPOSGE32_MM = 1518, CMPGU_EQ_QB_MM = 1519, CMPGU_LE_QB_MM = 1520, CMPGU_LT_QB_MM = 1521, CMPU_EQ_QB_MM = 1522, CMPU_LE_QB_MM = 1523, CMPU_LT_QB_MM = 1524, CMP_EQ_PH_MM = 1525, CMP_LE_PH_MM = 1526, CMP_LT_PH_MM = 1527, DPAQ_SA_L_W_MM = 1528, DPAQ_S_W_PH_MM = 1529, DPAU_H_QBL_MM = 1530, DPAU_H_QBR_MM = 1531, DPSQ_SA_L_W_MM = 1532, DPSQ_S_W_PH_MM = 1533, DPSU_H_QBL_MM = 1534, DPSU_H_QBR_MM = 1535, EXTPDPV_MM = 1536, EXTPDP_MM = 1537, EXTPV_MM = 1538, EXTP_MM = 1539, EXTRV_RS_W_MM = 1540, EXTRV_R_W_MM = 1541, EXTRV_S_H_MM = 1542, EXTRV_W_MM = 1543, EXTR_RS_W_MM = 1544, EXTR_R_W_MM = 1545, EXTR_S_H_MM = 1546, EXTR_W_MM = 1547, INSV_MM = 1548, LBUX_MM = 1549, LHX_MM = 1550, LWX_MM = 1551, MADDU_DSP_MM = 1552, MADD_DSP_MM = 1553, MAQ_SA_W_PHL_MM = 1554, MAQ_SA_W_PHR_MM = 1555, MAQ_S_W_PHL_MM = 1556, MAQ_S_W_PHR_MM = 1557, MFHI_DSP_MM = 1558, MFLO_DSP_MM = 1559, MODSUB_MM = 1560, MOVEP_MMR6 = 1561, MOVN_I_MM = 1562, MOVZ_I_MM = 1563, MSUBU_DSP_MM = 1564, MSUB_DSP_MM = 1565, MTHI_DSP_MM = 1566, MTHLIP_MM = 1567, MTLO_DSP_MM = 1568, MULEQ_S_W_PHL_MM = 1569, MULEQ_S_W_PHR_MM = 1570, MULEU_S_PH_QBL_MM = 1571, MULEU_S_PH_QBR_MM = 1572, MULQ_RS_PH_MM = 1573, MULSAQ_S_W_PH_MM = 1574, MULTU_DSP_MM = 1575, MULT_DSP_MM = 1576, PACKRL_PH_MM = 1577, PICK_PH_MM = 1578, PICK_QB_MM = 1579, PRECEQU_PH_QBLA_MM = 1580, PRECEQU_PH_QBL_MM = 1581, PRECEQU_PH_QBRA_MM = 1582, PRECEQU_PH_QBR_MM = 1583, PRECEQ_W_PHL_MM = 1584, PRECEQ_W_PHR_MM = 1585, PRECEU_PH_QBLA_MM = 1586, PRECEU_PH_QBL_MM = 1587, PRECEU_PH_QBRA_MM = 1588, PRECEU_PH_QBR_MM = 1589, PRECRQU_S_QB_PH_MM = 1590, PRECRQ_PH_W_MM = 1591, PRECRQ_QB_PH_MM = 1592, PRECRQ_RS_PH_W_MM = 1593, RADDU_W_QB_MM = 1594, RDDSP_MM = 1595, REPLV_PH_MM = 1596, REPLV_QB_MM = 1597, REPL_PH_MM = 1598, REPL_QB_MM = 1599, SHILOV_MM = 1600, SHILO_MM = 1601, SHLLV_PH_MM = 1602, SHLLV_QB_MM = 1603, SHLLV_S_PH_MM = 1604, SHLLV_S_W_MM = 1605, SHLL_PH_MM = 1606, SHLL_QB_MM = 1607, SHLL_S_PH_MM = 1608, SHLL_S_W_MM = 1609, SHRAV_PH_MM = 1610, SHRAV_R_PH_MM = 1611, SHRAV_R_W_MM = 1612, SHRA_PH_MM = 1613, SHRA_R_PH_MM = 1614, SHRA_R_W_MM = 1615, SHRLV_QB_MM = 1616, SHRL_QB_MM = 1617, SUBQ_PH_MM = 1618, SUBQ_S_PH_MM = 1619, SUBQ_S_W_MM = 1620, SUBU_QB_MM = 1621, SUBU_S_QB_MM = 1622, WRDSP_MM = 1623, ABSQ_S_QB_MMR2 = 1624, ADDQH_PH_MMR2 = 1625, ADDQH_R_PH_MMR2 = 1626, ADDQH_R_W_MMR2 = 1627, ADDQH_W_MMR2 = 1628, ADDUH_QB_MMR2 = 1629, ADDUH_R_QB_MMR2 = 1630, ADDU_PH_MMR2 = 1631, ADDU_S_PH_MMR2 = 1632, APPEND_MMR2 = 1633, BALIGN_MMR2 = 1634, CMPGDU_EQ_QB_MMR2 = 1635, CMPGDU_LE_QB_MMR2 = 1636, CMPGDU_LT_QB_MMR2 = 1637, DPA_W_PH_MMR2 = 1638, DPAQX_SA_W_PH_MMR2 = 1639, DPAQX_S_W_PH_MMR2 = 1640, DPAX_W_PH_MMR2 = 1641, DPS_W_PH_MMR2 = 1642, DPSQX_S_W_PH_MMR2 = 1643, DPSQX_SA_W_PH_MMR2 = 1644, DPSX_W_PH_MMR2 = 1645, MUL_PH_MMR2 = 1646, MUL_S_PH_MMR2 = 1647, MULQ_RS_W_MMR2 = 1648, MULQ_S_PH_MMR2 = 1649, MULQ_S_W_MMR2 = 1650, MULSA_W_PH_MMR2 = 1651, PRECR_QB_PH_MMR2 = 1652, PRECR_SRA_PH_W_MMR2 = 1653, PRECR_SRA_R_PH_W_MMR2 = 1654, PREPEND_MMR2 = 1655, SHRA_QB_MMR2 = 1656, SHRA_R_QB_MMR2 = 1657, SHRAV_QB_MMR2 = 1658, SHRAV_R_QB_MMR2 = 1659, SHRL_PH_MMR2 = 1660, SHRLV_PH_MMR2 = 1661, SUBQH_PH_MMR2 = 1662, SUBQH_R_PH_MMR2 = 1663, SUBQH_W_MMR2 = 1664, SUBQH_R_W_MMR2 = 1665, SUBU_PH_MMR2 = 1666, SUBU_S_PH_MMR2 = 1667, SUBUH_QB_MMR2 = 1668, SUBUH_R_QB_MMR2 = 1669, BPOSGE32C_MMR3 = 1670, CMP_F_D = 1671, CMP_F_S = 1672, CMP_SAF_D = 1673, CMP_SAF_S = 1674, CMP_SEQ_D = 1675, CMP_SEQ_S = 1676, CMP_SLE_D = 1677, CMP_SLE_S = 1678, CMP_SLT_D = 1679, CMP_SLT_S = 1680, CMP_SUEQ_D = 1681, CMP_SUEQ_S = 1682, CMP_SULE_D = 1683, CMP_SULE_S = 1684, CMP_SULT_D = 1685, CMP_SULT_S = 1686, CMP_SUN_D = 1687, CMP_SUN_S = 1688, SCHED_LIST_END = 1689 }; } // end namespace Sched } // end namespace Mips } // end namespace llvm #endif // GET_INSTRINFO_SCHED_ENUM #ifdef GET_INSTRINFO_MC_DESC #undef GET_INSTRINFO_MC_DESC namespace llvm { static const MCPhysReg ImplicitList1[] = { Mips::SP, Mips::SP }; static const MCPhysReg ImplicitList2[] = { Mips::AT }; static const MCPhysReg ImplicitList3[] = { Mips::RA }; static const MCPhysReg ImplicitList4[] = { Mips::DSPPos }; static const MCPhysReg ImplicitList5[] = { Mips::V0, Mips::V1 }; static const MCPhysReg ImplicitList6[] = { Mips::HI0, Mips::LO0 }; static const MCPhysReg ImplicitList7[] = { Mips::T8 }; static const MCPhysReg ImplicitList8[] = { Mips::DSPOutFlag20 }; static const MCPhysReg ImplicitList9[] = { Mips::DSPCarry }; static const MCPhysReg ImplicitList10[] = { Mips::DSPCarry, Mips::DSPOutFlag20 }; static const MCPhysReg ImplicitList11[] = { Mips::DSPCCond }; static const MCPhysReg ImplicitList12[] = { Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2 }; static const MCPhysReg ImplicitList13[] = { Mips::HI0_64, Mips::LO0_64 }; static const MCPhysReg ImplicitList14[] = { Mips::DSPOutFlag16_19 }; static const MCPhysReg ImplicitList15[] = { Mips::DSPPos, Mips::DSPEFI }; static const MCPhysReg ImplicitList16[] = { Mips::DSPPos, Mips::DSPPos, Mips::DSPEFI }; static const MCPhysReg ImplicitList17[] = { Mips::DSPOutFlag23 }; static const MCPhysReg ImplicitList18[] = { Mips::FCC0 }; static const MCPhysReg ImplicitList19[] = { Mips::DSPPos, Mips::DSPSCount }; static const MCPhysReg ImplicitList20[] = { Mips::HI0, Mips::LO0, Mips::HI0, Mips::LO0 }; static const MCPhysReg ImplicitList21[] = { Mips::AC0 }; static const MCPhysReg ImplicitList22[] = { Mips::AC0_64 }; static const MCPhysReg ImplicitList23[] = { Mips::HI0 }; static const MCPhysReg ImplicitList24[] = { Mips::HI0_64 }; static const MCPhysReg ImplicitList25[] = { Mips::LO0 }; static const MCPhysReg ImplicitList26[] = { Mips::LO0_64 }; static const MCPhysReg ImplicitList27[] = { Mips::MPL0, Mips::P0, Mips::P1, Mips::P2 }; static const MCPhysReg ImplicitList28[] = { Mips::MPL1, Mips::P0, Mips::P1, Mips::P2 }; static const MCPhysReg ImplicitList29[] = { Mips::MPL2, Mips::P0, Mips::P1, Mips::P2 }; static const MCPhysReg ImplicitList30[] = { Mips::P0 }; static const MCPhysReg ImplicitList31[] = { Mips::P1 }; static const MCPhysReg ImplicitList32[] = { Mips::P2 }; static const MCPhysReg ImplicitList33[] = { Mips::DSPOutFlag21 }; static const MCPhysReg ImplicitList34[] = { Mips::DSPOutFlag22 }; static const MCPhysReg ImplicitList35[] = { Mips::P0, Mips::P1, Mips::P2 }; static const MCPhysReg ImplicitList36[] = { Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2 }; static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, }; static const MCOperandInfo OperandInfo10[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo11[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<InitMCInstrInfo(MipsInsts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2848); } } // end namespace llvm #endif // GET_INSTRINFO_MC_DESC #ifdef GET_INSTRINFO_HEADER #undef GET_INSTRINFO_HEADER namespace llvm { struct MipsGenInstrInfo : public TargetInstrInfo { explicit MipsGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); ~MipsGenInstrInfo() override = default; }; } // end namespace llvm #endif // GET_INSTRINFO_HEADER #ifdef GET_INSTRINFO_HELPER_DECLS #undef GET_INSTRINFO_HELPER_DECLS #endif // GET_INSTRINFO_HELPER_DECLS #ifdef GET_INSTRINFO_HELPERS #undef GET_INSTRINFO_HELPERS #endif // GET_INSTRINFO_HELPERS #ifdef GET_INSTRINFO_CTOR_DTOR #undef GET_INSTRINFO_CTOR_DTOR namespace llvm { extern const MCInstrDesc MipsInsts[]; extern const unsigned MipsInstrNameIndices[]; extern const char MipsInstrNameData[]; MipsGenInstrInfo::MipsGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { InitMCInstrInfo(MipsInsts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2848); } } // end namespace llvm #endif // GET_INSTRINFO_CTOR_DTOR #ifdef GET_INSTRINFO_OPERAND_ENUM #undef GET_INSTRINFO_OPERAND_ENUM namespace llvm { namespace Mips { namespace OpName { enum { OPERAND_LAST }; } // end namespace OpName } // end namespace Mips } // end namespace llvm #endif //GET_INSTRINFO_OPERAND_ENUM #ifdef GET_INSTRINFO_NAMED_OPS #undef GET_INSTRINFO_NAMED_OPS namespace llvm { namespace Mips { LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { return -1; } } // end namespace Mips } // end namespace llvm #endif //GET_INSTRINFO_NAMED_OPS #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM #undef GET_INSTRINFO_OPERAND_TYPES_ENUM namespace llvm { namespace Mips { namespace OpTypes { enum OperandType { InvertedImOperand = 0, InvertedImOperand64 = 1, PtrRC = 2, brtarget = 3, brtarget10_mm = 4, brtarget1SImm16 = 5, brtarget21 = 6, brtarget21_mm = 7, brtarget26 = 8, brtarget26_mm = 9, brtarget7_mm = 10, brtarget_lsl2_mm = 11, brtarget_mm = 12, brtargetr6 = 13, calloffset16 = 14, calltarget = 15, calltarget_mm = 16, condcode = 17, cpinst_operand = 18, f32imm = 19, f64imm = 20, i16imm = 21, i1imm = 22, i32imm = 23, i64imm = 24, i8imm = 25, imm64 = 26, jmpoffset16 = 27, jmptarget = 28, jmptarget_mm = 29, li16_imm = 30, mem = 31, mem16 = 32, mem16_ea = 33, mem16sp = 34, mem_ea = 35, mem_mm_11 = 36, mem_mm_12 = 37, mem_mm_16 = 38, mem_mm_4 = 39, mem_mm_4_lsl1 = 40, mem_mm_4_lsl2 = 41, mem_mm_4sp = 42, mem_mm_9 = 43, mem_mm_gp_simm7_lsl2 = 44, mem_mm_sp_imm5_lsl2 = 45, mem_msa = 46, mem_simm10 = 47, mem_simm10_lsl1 = 48, mem_simm10_lsl2 = 49, mem_simm10_lsl3 = 50, mem_simm11 = 51, mem_simm12 = 52, mem_simm16 = 53, mem_simm9 = 54, mem_simm9_exp = 55, mem_simmptr = 56, pcrel16 = 57, ptype0 = 58, ptype1 = 59, ptype2 = 60, ptype3 = 61, ptype4 = 62, ptype5 = 63, reglist = 64, reglist16 = 65, simm10 = 66, simm10_64 = 67, simm10_lsl1 = 68, simm10_lsl2 = 69, simm10_lsl3 = 70, simm11 = 71, simm12 = 72, simm16 = 73, simm16_64 = 74, simm16_relaxed = 75, simm18_lsl3 = 76, simm19_lsl2 = 77, simm23_lsl2 = 78, simm32 = 79, simm32_relaxed = 80, simm3_lsa2 = 81, simm4 = 82, simm5 = 83, simm6 = 84, simm7_lsl2 = 85, simm9 = 86, simm9_addiusp = 87, size_ins = 88, type0 = 89, type1 = 90, type2 = 91, type3 = 92, type4 = 93, type5 = 94, uimm1 = 95, uimm10 = 96, uimm16 = 97, uimm16_64 = 98, uimm16_64_relaxed = 99, uimm16_altrelaxed = 100, uimm16_relaxed = 101, uimm1_ptr = 102, uimm2 = 103, uimm20 = 104, uimm26 = 105, uimm2_plus1 = 106, uimm2_ptr = 107, uimm3 = 108, uimm32_coerced = 109, uimm3_ptr = 110, uimm3_shift = 111, uimm4 = 112, uimm4_andi = 113, uimm4_ptr = 114, uimm5 = 115, uimm5_64 = 116, uimm5_64_report_uimm6 = 117, uimm5_inssize_plus1 = 118, uimm5_lsl2 = 119, uimm5_plus1 = 120, uimm5_plus1_report_uimm6 = 121, uimm5_plus32 = 122, uimm5_plus32_normalize = 123, uimm5_plus32_normalize_64 = 124, uimm5_plus33 = 125, uimm5_report_uimm6 = 126, uimm6 = 127, uimm6_lsl2 = 128, uimm7 = 129, uimm8 = 130, uimm_range_2_64 = 131, uimmz = 132, untyped_imm_0 = 133, vsplat_simm10 = 134, vsplat_simm5 = 135, vsplat_uimm1 = 136, vsplat_uimm2 = 137, vsplat_uimm3 = 138, vsplat_uimm4 = 139, vsplat_uimm5 = 140, vsplat_uimm6 = 141, vsplat_uimm8 = 142, ACC64DSPOpnd = 143, AFGR64Opnd = 144, CCROpnd = 145, COP0Opnd = 146, COP2Opnd = 147, COP3Opnd = 148, DSPROpnd = 149, FCCRegsOpnd = 150, FGR32Opnd = 151, FGR64Opnd = 152, FGRCCOpnd = 153, GPR32NonZeroOpnd = 154, GPR32Opnd = 155, GPR32ZeroOpnd = 156, GPR64Opnd = 157, GPRMM16Opnd = 158, GPRMM16OpndMoveP = 159, GPRMM16OpndMovePPairFirst = 160, GPRMM16OpndMovePPairSecond = 161, GPRMM16OpndZero = 162, HI32DSPOpnd = 163, HWRegsOpnd = 164, LO32DSPOpnd = 165, MSA128BOpnd = 166, MSA128CROpnd = 167, MSA128DOpnd = 168, MSA128F16Opnd = 169, MSA128HOpnd = 170, MSA128WOpnd = 171, StrictlyAFGR64Opnd = 172, StrictlyFGR32Opnd = 173, StrictlyFGR64Opnd = 174, ACC128 = 175, ACC64 = 176, ACC64DSP = 177, AFGR64 = 178, CCR = 179, COP0 = 180, COP2 = 181, COP3 = 182, CPU16Regs = 183, CPU16RegsPlusSP = 184, CPURAReg = 185, CPUSPReg = 186, DSPCC = 187, DSPR = 188, FCC = 189, FGR32 = 190, FGR64 = 191, FGRCC = 192, GP32 = 193, GP64 = 194, GPR32 = 195, GPR32NONZERO = 196, GPR32ZERO = 197, GPR64 = 198, GPRMM16 = 199, GPRMM16MoveP = 200, GPRMM16MovePPairFirst = 201, GPRMM16MovePPairSecond = 202, GPRMM16Zero = 203, HI32 = 204, HI32DSP = 205, HI64 = 206, HWRegs = 207, LO32 = 208, LO32DSP = 209, LO64 = 210, MSA128B = 211, MSA128D = 212, MSA128F16 = 213, MSA128H = 214, MSA128W = 215, MSA128WEvens = 216, MSACtrl = 217, OCTEON_MPL = 218, OCTEON_P = 219, SP32 = 220, SP64 = 221, OPERAND_TYPE_LIST_END }; } // end namespace OpTypes } // end namespace Mips } // end namespace llvm #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM #ifdef GET_INSTRINFO_OPERAND_TYPE #undef GET_INSTRINFO_OPERAND_TYPE namespace llvm { namespace Mips { LLVM_READONLY static int getOperandType(uint16_t Opcode, uint16_t OpIdx) { const uint16_t Offsets[] = { /* PHI */ 0, /* INLINEASM */ 1, /* INLINEASM_BR */ 1, /* CFI_INSTRUCTION */ 1, /* EH_LABEL */ 2, /* GC_LABEL */ 3, /* ANNOTATION_LABEL */ 4, /* KILL */ 5, /* EXTRACT_SUBREG */ 5, /* INSERT_SUBREG */ 8, /* IMPLICIT_DEF */ 12, /* SUBREG_TO_REG */ 13, /* COPY_TO_REGCLASS */ 17, /* DBG_VALUE */ 20, /* DBG_VALUE_LIST */ 20, /* DBG_INSTR_REF */ 20, /* DBG_PHI */ 20, /* DBG_LABEL */ 20, /* REG_SEQUENCE */ 21, /* COPY */ 23, /* BUNDLE */ 25, /* LIFETIME_START */ 25, /* LIFETIME_END */ 26, /* PSEUDO_PROBE */ 27, /* ARITH_FENCE */ 31, /* STACKMAP */ 33, /* FENTRY_CALL */ 35, /* PATCHPOINT */ 35, /* LOAD_STACK_GUARD */ 41, /* PREALLOCATED_SETUP */ 42, /* PREALLOCATED_ARG */ 43, /* STATEPOINT */ 46, /* LOCAL_ESCAPE */ 46, /* FAULTING_OP */ 48, /* PATCHABLE_OP */ 49, /* PATCHABLE_FUNCTION_ENTER */ 49, /* PATCHABLE_RET */ 49, /* PATCHABLE_FUNCTION_EXIT */ 49, /* PATCHABLE_TAIL_CALL */ 49, /* PATCHABLE_EVENT_CALL */ 49, /* PATCHABLE_TYPED_EVENT_CALL */ 51, /* ICALL_BRANCH_FUNNEL */ 54, /* MEMBARRIER */ 54, /* G_ASSERT_SEXT */ 54, /* G_ASSERT_ZEXT */ 57, /* G_ASSERT_ALIGN */ 60, /* G_ADD */ 63, /* G_SUB */ 66, /* G_MUL */ 69, /* G_SDIV */ 72, /* G_UDIV */ 75, /* G_SREM */ 78, /* G_UREM */ 81, /* G_SDIVREM */ 84, /* G_UDIVREM */ 88, /* G_AND */ 92, /* G_OR */ 95, /* G_XOR */ 98, /* G_IMPLICIT_DEF */ 101, /* G_PHI */ 102, /* G_FRAME_INDEX */ 103, /* G_GLOBAL_VALUE */ 105, /* G_EXTRACT */ 107, /* G_UNMERGE_VALUES */ 110, /* G_INSERT */ 112, /* G_MERGE_VALUES */ 116, /* G_BUILD_VECTOR */ 118, /* G_BUILD_VECTOR_TRUNC */ 120, /* G_CONCAT_VECTORS */ 122, /* G_PTRTOINT */ 124, /* G_INTTOPTR */ 126, /* G_BITCAST */ 128, /* G_FREEZE */ 130, /* G_INTRINSIC_FPTRUNC_ROUND */ 132, /* G_INTRINSIC_TRUNC */ 135, /* G_INTRINSIC_ROUND */ 137, /* G_INTRINSIC_LRINT */ 139, /* G_INTRINSIC_ROUNDEVEN */ 141, /* G_READCYCLECOUNTER */ 143, /* G_LOAD */ 144, /* G_SEXTLOAD */ 146, /* G_ZEXTLOAD */ 148, /* G_INDEXED_LOAD */ 150, /* G_INDEXED_SEXTLOAD */ 155, /* G_INDEXED_ZEXTLOAD */ 160, /* G_STORE */ 165, /* G_INDEXED_STORE */ 167, /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ 172, /* G_ATOMIC_CMPXCHG */ 177, /* G_ATOMICRMW_XCHG */ 181, /* G_ATOMICRMW_ADD */ 184, /* G_ATOMICRMW_SUB */ 187, /* G_ATOMICRMW_AND */ 190, /* G_ATOMICRMW_NAND */ 193, /* G_ATOMICRMW_OR */ 196, /* G_ATOMICRMW_XOR */ 199, /* G_ATOMICRMW_MAX */ 202, /* G_ATOMICRMW_MIN */ 205, /* G_ATOMICRMW_UMAX */ 208, /* G_ATOMICRMW_UMIN */ 211, /* G_ATOMICRMW_FADD */ 214, /* G_ATOMICRMW_FSUB */ 217, /* G_ATOMICRMW_FMAX */ 220, /* G_ATOMICRMW_FMIN */ 223, /* G_ATOMICRMW_UINC_WRAP */ 226, /* G_ATOMICRMW_UDEC_WRAP */ 229, /* G_FENCE */ 232, /* G_BRCOND */ 234, /* G_BRINDIRECT */ 236, /* G_INVOKE_REGION_START */ 237, /* G_INTRINSIC */ 237, /* G_INTRINSIC_W_SIDE_EFFECTS */ 238, /* G_ANYEXT */ 239, /* G_TRUNC */ 241, /* G_CONSTANT */ 243, /* G_FCONSTANT */ 245, /* G_VASTART */ 247, /* G_VAARG */ 248, /* G_SEXT */ 251, /* G_SEXT_INREG */ 253, /* G_ZEXT */ 256, /* G_SHL */ 258, /* G_LSHR */ 261, /* G_ASHR */ 264, /* G_FSHL */ 267, /* G_FSHR */ 271, /* G_ROTR */ 275, /* G_ROTL */ 278, /* G_ICMP */ 281, /* G_FCMP */ 285, /* G_SELECT */ 289, /* G_UADDO */ 293, /* G_UADDE */ 297, /* G_USUBO */ 302, /* G_USUBE */ 306, /* G_SADDO */ 311, /* G_SADDE */ 315, /* G_SSUBO */ 320, /* G_SSUBE */ 324, /* G_UMULO */ 329, /* G_SMULO */ 333, /* G_UMULH */ 337, /* G_SMULH */ 340, /* G_UADDSAT */ 343, /* G_SADDSAT */ 346, /* G_USUBSAT */ 349, /* G_SSUBSAT */ 352, /* G_USHLSAT */ 355, /* G_SSHLSAT */ 358, /* G_SMULFIX */ 361, /* G_UMULFIX */ 365, /* G_SMULFIXSAT */ 369, /* G_UMULFIXSAT */ 373, /* G_SDIVFIX */ 377, /* G_UDIVFIX */ 381, /* G_SDIVFIXSAT */ 385, /* G_UDIVFIXSAT */ 389, /* G_FADD */ 393, /* G_FSUB */ 396, /* G_FMUL */ 399, /* G_FMA */ 402, /* G_FMAD */ 406, /* G_FDIV */ 410, /* G_FREM */ 413, /* G_FPOW */ 416, /* G_FPOWI */ 419, /* G_FEXP */ 422, /* G_FEXP2 */ 424, /* G_FLOG */ 426, /* G_FLOG2 */ 428, /* G_FLOG10 */ 430, /* G_FNEG */ 432, /* G_FPEXT */ 434, /* G_FPTRUNC */ 436, /* G_FPTOSI */ 438, /* G_FPTOUI */ 440, /* G_SITOFP */ 442, /* G_UITOFP */ 444, /* G_FABS */ 446, /* G_FCOPYSIGN */ 448, /* G_IS_FPCLASS */ 451, /* G_FCANONICALIZE */ 454, /* G_FMINNUM */ 456, /* G_FMAXNUM */ 459, /* G_FMINNUM_IEEE */ 462, /* G_FMAXNUM_IEEE */ 465, /* G_FMINIMUM */ 468, /* G_FMAXIMUM */ 471, /* G_PTR_ADD */ 474, /* G_PTRMASK */ 477, /* G_SMIN */ 480, /* G_SMAX */ 483, /* G_UMIN */ 486, /* G_UMAX */ 489, /* G_ABS */ 492, /* G_LROUND */ 494, /* G_LLROUND */ 496, /* G_BR */ 498, /* G_BRJT */ 499, /* G_INSERT_VECTOR_ELT */ 502, /* G_EXTRACT_VECTOR_ELT */ 506, /* G_SHUFFLE_VECTOR */ 509, /* G_CTTZ */ 513, /* G_CTTZ_ZERO_UNDEF */ 515, /* G_CTLZ */ 517, /* G_CTLZ_ZERO_UNDEF */ 519, /* G_CTPOP */ 521, /* G_BSWAP */ 523, /* G_BITREVERSE */ 525, /* G_FCEIL */ 527, /* G_FCOS */ 529, /* G_FSIN */ 531, /* G_FSQRT */ 533, /* G_FFLOOR */ 535, /* G_FRINT */ 537, /* G_FNEARBYINT */ 539, /* G_ADDRSPACE_CAST */ 541, /* G_BLOCK_ADDR */ 543, /* G_JUMP_TABLE */ 545, /* G_DYN_STACKALLOC */ 547, /* G_STRICT_FADD */ 550, /* G_STRICT_FSUB */ 553, /* G_STRICT_FMUL */ 556, /* G_STRICT_FDIV */ 559, /* G_STRICT_FREM */ 562, /* G_STRICT_FMA */ 565, /* G_STRICT_FSQRT */ 569, /* G_READ_REGISTER */ 571, /* G_WRITE_REGISTER */ 573, /* G_MEMCPY */ 575, /* G_MEMCPY_INLINE */ 579, /* G_MEMMOVE */ 582, /* G_MEMSET */ 586, /* G_BZERO */ 590, /* G_VECREDUCE_SEQ_FADD */ 593, /* G_VECREDUCE_SEQ_FMUL */ 596, /* G_VECREDUCE_FADD */ 599, /* G_VECREDUCE_FMUL */ 601, /* G_VECREDUCE_FMAX */ 603, /* G_VECREDUCE_FMIN */ 605, /* G_VECREDUCE_ADD */ 607, /* G_VECREDUCE_MUL */ 609, /* G_VECREDUCE_AND */ 611, /* G_VECREDUCE_OR */ 613, /* G_VECREDUCE_XOR */ 615, /* G_VECREDUCE_SMAX */ 617, /* G_VECREDUCE_SMIN */ 619, /* G_VECREDUCE_UMAX */ 621, /* G_VECREDUCE_UMIN */ 623, /* G_SBFX */ 625, /* G_UBFX */ 629, /* ABSMacro */ 633, /* ADJCALLSTACKDOWN */ 635, /* ADJCALLSTACKUP */ 637, /* AND_V_D_PSEUDO */ 639, /* AND_V_H_PSEUDO */ 642, /* AND_V_W_PSEUDO */ 645, /* ATOMIC_CMP_SWAP_I16 */ 648, /* ATOMIC_CMP_SWAP_I16_POSTRA */ 652, /* ATOMIC_CMP_SWAP_I32 */ 659, /* ATOMIC_CMP_SWAP_I32_POSTRA */ 663, /* ATOMIC_CMP_SWAP_I64 */ 667, /* ATOMIC_CMP_SWAP_I64_POSTRA */ 671, /* ATOMIC_CMP_SWAP_I8 */ 675, /* ATOMIC_CMP_SWAP_I8_POSTRA */ 679, /* ATOMIC_LOAD_ADD_I16 */ 686, /* ATOMIC_LOAD_ADD_I16_POSTRA */ 689, /* ATOMIC_LOAD_ADD_I32 */ 695, /* ATOMIC_LOAD_ADD_I32_POSTRA */ 698, /* ATOMIC_LOAD_ADD_I64 */ 701, /* ATOMIC_LOAD_ADD_I64_POSTRA */ 704, /* ATOMIC_LOAD_ADD_I8 */ 707, /* ATOMIC_LOAD_ADD_I8_POSTRA */ 710, /* ATOMIC_LOAD_AND_I16 */ 716, /* ATOMIC_LOAD_AND_I16_POSTRA */ 719, /* ATOMIC_LOAD_AND_I32 */ 725, /* ATOMIC_LOAD_AND_I32_POSTRA */ 728, /* ATOMIC_LOAD_AND_I64 */ 731, /* ATOMIC_LOAD_AND_I64_POSTRA */ 734, /* ATOMIC_LOAD_AND_I8 */ 737, /* ATOMIC_LOAD_AND_I8_POSTRA */ 740, /* ATOMIC_LOAD_MAX_I16 */ 746, /* ATOMIC_LOAD_MAX_I16_POSTRA */ 749, /* ATOMIC_LOAD_MAX_I32 */ 755, /* ATOMIC_LOAD_MAX_I32_POSTRA */ 758, /* ATOMIC_LOAD_MAX_I64 */ 761, /* ATOMIC_LOAD_MAX_I64_POSTRA */ 764, /* ATOMIC_LOAD_MAX_I8 */ 767, /* ATOMIC_LOAD_MAX_I8_POSTRA */ 770, /* ATOMIC_LOAD_MIN_I16 */ 776, /* ATOMIC_LOAD_MIN_I16_POSTRA */ 779, /* ATOMIC_LOAD_MIN_I32 */ 785, /* ATOMIC_LOAD_MIN_I32_POSTRA */ 788, /* ATOMIC_LOAD_MIN_I64 */ 791, /* ATOMIC_LOAD_MIN_I64_POSTRA */ 794, /* ATOMIC_LOAD_MIN_I8 */ 797, /* ATOMIC_LOAD_MIN_I8_POSTRA */ 800, /* ATOMIC_LOAD_NAND_I16 */ 806, /* ATOMIC_LOAD_NAND_I16_POSTRA */ 809, /* ATOMIC_LOAD_NAND_I32 */ 815, /* ATOMIC_LOAD_NAND_I32_POSTRA */ 818, /* ATOMIC_LOAD_NAND_I64 */ 821, /* ATOMIC_LOAD_NAND_I64_POSTRA */ 824, /* ATOMIC_LOAD_NAND_I8 */ 827, /* ATOMIC_LOAD_NAND_I8_POSTRA */ 830, /* ATOMIC_LOAD_OR_I16 */ 836, /* ATOMIC_LOAD_OR_I16_POSTRA */ 839, /* ATOMIC_LOAD_OR_I32 */ 845, /* ATOMIC_LOAD_OR_I32_POSTRA */ 848, /* ATOMIC_LOAD_OR_I64 */ 851, /* ATOMIC_LOAD_OR_I64_POSTRA */ 854, /* ATOMIC_LOAD_OR_I8 */ 857, /* ATOMIC_LOAD_OR_I8_POSTRA */ 860, /* ATOMIC_LOAD_SUB_I16 */ 866, /* ATOMIC_LOAD_SUB_I16_POSTRA */ 869, /* ATOMIC_LOAD_SUB_I32 */ 875, /* ATOMIC_LOAD_SUB_I32_POSTRA */ 878, /* ATOMIC_LOAD_SUB_I64 */ 881, /* ATOMIC_LOAD_SUB_I64_POSTRA */ 884, /* ATOMIC_LOAD_SUB_I8 */ 887, /* ATOMIC_LOAD_SUB_I8_POSTRA */ 890, /* ATOMIC_LOAD_UMAX_I16 */ 896, /* ATOMIC_LOAD_UMAX_I16_POSTRA */ 899, /* ATOMIC_LOAD_UMAX_I32 */ 905, /* ATOMIC_LOAD_UMAX_I32_POSTRA */ 908, /* ATOMIC_LOAD_UMAX_I64 */ 911, /* ATOMIC_LOAD_UMAX_I64_POSTRA */ 914, /* ATOMIC_LOAD_UMAX_I8 */ 917, /* ATOMIC_LOAD_UMAX_I8_POSTRA */ 920, /* ATOMIC_LOAD_UMIN_I16 */ 926, /* ATOMIC_LOAD_UMIN_I16_POSTRA */ 929, /* ATOMIC_LOAD_UMIN_I32 */ 935, /* ATOMIC_LOAD_UMIN_I32_POSTRA */ 938, /* ATOMIC_LOAD_UMIN_I64 */ 941, /* ATOMIC_LOAD_UMIN_I64_POSTRA */ 944, /* ATOMIC_LOAD_UMIN_I8 */ 947, /* ATOMIC_LOAD_UMIN_I8_POSTRA */ 950, /* ATOMIC_LOAD_XOR_I16 */ 956, /* ATOMIC_LOAD_XOR_I16_POSTRA */ 959, /* ATOMIC_LOAD_XOR_I32 */ 965, /* ATOMIC_LOAD_XOR_I32_POSTRA */ 968, /* ATOMIC_LOAD_XOR_I64 */ 971, /* ATOMIC_LOAD_XOR_I64_POSTRA */ 974, /* ATOMIC_LOAD_XOR_I8 */ 977, /* ATOMIC_LOAD_XOR_I8_POSTRA */ 980, /* ATOMIC_SWAP_I16 */ 986, /* ATOMIC_SWAP_I16_POSTRA */ 989, /* ATOMIC_SWAP_I32 */ 995, /* ATOMIC_SWAP_I32_POSTRA */ 998, /* ATOMIC_SWAP_I64 */ 1001, /* ATOMIC_SWAP_I64_POSTRA */ 1004, /* ATOMIC_SWAP_I8 */ 1007, /* ATOMIC_SWAP_I8_POSTRA */ 1010, /* B */ 1016, /* BAL_BR */ 1017, /* BAL_BR_MM */ 1018, /* BEQLImmMacro */ 1019, /* BGE */ 1022, /* BGEImmMacro */ 1025, /* BGEL */ 1028, /* BGELImmMacro */ 1031, /* BGEU */ 1034, /* BGEUImmMacro */ 1037, /* BGEUL */ 1040, /* BGEULImmMacro */ 1043, /* BGT */ 1046, /* BGTImmMacro */ 1049, /* BGTL */ 1052, /* BGTLImmMacro */ 1055, /* BGTU */ 1058, /* BGTUImmMacro */ 1061, /* BGTUL */ 1064, /* BGTULImmMacro */ 1067, /* BLE */ 1070, /* BLEImmMacro */ 1073, /* BLEL */ 1076, /* BLELImmMacro */ 1079, /* BLEU */ 1082, /* BLEUImmMacro */ 1085, /* BLEUL */ 1088, /* BLEULImmMacro */ 1091, /* BLT */ 1094, /* BLTImmMacro */ 1097, /* BLTL */ 1100, /* BLTLImmMacro */ 1103, /* BLTU */ 1106, /* BLTUImmMacro */ 1109, /* BLTUL */ 1112, /* BLTULImmMacro */ 1115, /* BNELImmMacro */ 1118, /* BPOSGE32_PSEUDO */ 1121, /* BSEL_D_PSEUDO */ 1122, /* BSEL_FD_PSEUDO */ 1126, /* BSEL_FW_PSEUDO */ 1130, /* BSEL_H_PSEUDO */ 1134, /* BSEL_W_PSEUDO */ 1138, /* B_MM */ 1142, /* B_MMR6_Pseudo */ 1143, /* B_MM_Pseudo */ 1144, /* BeqImm */ 1145, /* BneImm */ 1148, /* BteqzT8CmpX16 */ 1151, /* BteqzT8CmpiX16 */ 1154, /* BteqzT8SltX16 */ 1157, /* BteqzT8SltiX16 */ 1160, /* BteqzT8SltiuX16 */ 1163, /* BteqzT8SltuX16 */ 1166, /* BtnezT8CmpX16 */ 1169, /* BtnezT8CmpiX16 */ 1172, /* BtnezT8SltX16 */ 1175, /* BtnezT8SltiX16 */ 1178, /* BtnezT8SltiuX16 */ 1181, /* BtnezT8SltuX16 */ 1184, /* BuildPairF64 */ 1187, /* BuildPairF64_64 */ 1190, /* CFTC1 */ 1193, /* CONSTPOOL_ENTRY */ 1195, /* COPY_FD_PSEUDO */ 1198, /* COPY_FW_PSEUDO */ 1201, /* CTTC1 */ 1204, /* Constant32 */ 1206, /* DMULImmMacro */ 1207, /* DMULMacro */ 1210, /* DMULOMacro */ 1213, /* DMULOUMacro */ 1216, /* DROL */ 1219, /* DROLImm */ 1222, /* DROR */ 1225, /* DRORImm */ 1228, /* DSDivIMacro */ 1231, /* DSDivMacro */ 1234, /* DSRemIMacro */ 1237, /* DSRemMacro */ 1240, /* DUDivIMacro */ 1243, /* DUDivMacro */ 1246, /* DURemIMacro */ 1249, /* DURemMacro */ 1252, /* ERet */ 1255, /* ExtractElementF64 */ 1255, /* ExtractElementF64_64 */ 1258, /* FABS_D */ 1261, /* FABS_W */ 1263, /* FEXP2_D_1_PSEUDO */ 1265, /* FEXP2_W_1_PSEUDO */ 1267, /* FILL_FD_PSEUDO */ 1269, /* FILL_FW_PSEUDO */ 1271, /* GotPrologue16 */ 1273, /* INSERT_B_VIDX64_PSEUDO */ 1277, /* INSERT_B_VIDX_PSEUDO */ 1281, /* INSERT_D_VIDX64_PSEUDO */ 1285, /* INSERT_D_VIDX_PSEUDO */ 1289, /* INSERT_FD_PSEUDO */ 1293, /* INSERT_FD_VIDX64_PSEUDO */ 1297, /* INSERT_FD_VIDX_PSEUDO */ 1301, /* INSERT_FW_PSEUDO */ 1305, /* INSERT_FW_VIDX64_PSEUDO */ 1309, /* INSERT_FW_VIDX_PSEUDO */ 1313, /* INSERT_H_VIDX64_PSEUDO */ 1317, /* INSERT_H_VIDX_PSEUDO */ 1321, /* INSERT_W_VIDX64_PSEUDO */ 1325, /* INSERT_W_VIDX_PSEUDO */ 1329, /* JALR64Pseudo */ 1333, /* JALRHB64Pseudo */ 1334, /* JALRHBPseudo */ 1335, /* JALRPseudo */ 1336, /* JAL_MMR6 */ 1337, /* JalOneReg */ 1338, /* JalTwoReg */ 1339, /* LDMacro */ 1341, /* LDR_D */ 1344, /* LDR_W */ 1347, /* LD_F16 */ 1350, /* LOAD_ACC128 */ 1353, /* LOAD_ACC64 */ 1356, /* LOAD_ACC64DSP */ 1359, /* LOAD_CCOND_DSP */ 1362, /* LONG_BRANCH_ADDiu */ 1365, /* LONG_BRANCH_ADDiu2Op */ 1369, /* LONG_BRANCH_DADDiu */ 1372, /* LONG_BRANCH_DADDiu2Op */ 1376, /* LONG_BRANCH_LUi */ 1379, /* LONG_BRANCH_LUi2Op */ 1382, /* LONG_BRANCH_LUi2Op_64 */ 1384, /* LWM_MM */ 1386, /* LoadAddrImm32 */ 1389, /* LoadAddrImm64 */ 1391, /* LoadAddrReg32 */ 1393, /* LoadAddrReg64 */ 1396, /* LoadImm32 */ 1399, /* LoadImm64 */ 1401, /* LoadImmDoubleFGR */ 1403, /* LoadImmDoubleFGR_32 */ 1405, /* LoadImmDoubleGPR */ 1407, /* LoadImmSingleFGR */ 1409, /* LoadImmSingleGPR */ 1411, /* LwConstant32 */ 1413, /* MFTACX */ 1416, /* MFTC0 */ 1418, /* MFTC1 */ 1421, /* MFTDSP */ 1423, /* MFTGPR */ 1424, /* MFTHC1 */ 1427, /* MFTHI */ 1429, /* MFTLO */ 1431, /* MIPSeh_return32 */ 1433, /* MIPSeh_return64 */ 1435, /* MSA_FP_EXTEND_D_PSEUDO */ 1437, /* MSA_FP_EXTEND_W_PSEUDO */ 1439, /* MSA_FP_ROUND_D_PSEUDO */ 1441, /* MSA_FP_ROUND_W_PSEUDO */ 1443, /* MTTACX */ 1445, /* MTTC0 */ 1447, /* MTTC1 */ 1450, /* MTTDSP */ 1452, /* MTTGPR */ 1453, /* MTTHC1 */ 1455, /* MTTHI */ 1457, /* MTTLO */ 1459, /* MULImmMacro */ 1461, /* MULOMacro */ 1464, /* MULOUMacro */ 1467, /* MultRxRy16 */ 1470, /* MultRxRyRz16 */ 1472, /* MultuRxRy16 */ 1475, /* MultuRxRyRz16 */ 1477, /* NOP */ 1480, /* NORImm */ 1480, /* NORImm64 */ 1483, /* NOR_V_D_PSEUDO */ 1486, /* NOR_V_H_PSEUDO */ 1489, /* NOR_V_W_PSEUDO */ 1492, /* OR_V_D_PSEUDO */ 1495, /* OR_V_H_PSEUDO */ 1498, /* OR_V_W_PSEUDO */ 1501, /* PseudoCMPU_EQ_QB */ 1504, /* PseudoCMPU_LE_QB */ 1507, /* PseudoCMPU_LT_QB */ 1510, /* PseudoCMP_EQ_PH */ 1513, /* PseudoCMP_LE_PH */ 1516, /* PseudoCMP_LT_PH */ 1519, /* PseudoCVT_D32_W */ 1522, /* PseudoCVT_D64_L */ 1524, /* PseudoCVT_D64_W */ 1526, /* PseudoCVT_S_L */ 1528, /* PseudoCVT_S_W */ 1530, /* PseudoDMULT */ 1532, /* PseudoDMULTu */ 1535, /* PseudoDSDIV */ 1538, /* PseudoDUDIV */ 1541, /* PseudoD_SELECT_I */ 1544, /* PseudoD_SELECT_I64 */ 1551, /* PseudoIndirectBranch */ 1558, /* PseudoIndirectBranch64 */ 1559, /* PseudoIndirectBranch64R6 */ 1560, /* PseudoIndirectBranchR6 */ 1561, /* PseudoIndirectBranch_MM */ 1562, /* PseudoIndirectBranch_MMR6 */ 1563, /* PseudoIndirectHazardBranch */ 1564, /* PseudoIndirectHazardBranch64 */ 1565, /* PseudoIndrectHazardBranch64R6 */ 1566, /* PseudoIndrectHazardBranchR6 */ 1567, /* PseudoMADD */ 1568, /* PseudoMADDU */ 1572, /* PseudoMADDU_MM */ 1576, /* PseudoMADD_MM */ 1580, /* PseudoMFHI */ 1584, /* PseudoMFHI64 */ 1586, /* PseudoMFHI_MM */ 1588, /* PseudoMFLO */ 1590, /* PseudoMFLO64 */ 1592, /* PseudoMFLO_MM */ 1594, /* PseudoMSUB */ 1596, /* PseudoMSUBU */ 1600, /* PseudoMSUBU_MM */ 1604, /* PseudoMSUB_MM */ 1608, /* PseudoMTLOHI */ 1612, /* PseudoMTLOHI64 */ 1615, /* PseudoMTLOHI_DSP */ 1618, /* PseudoMTLOHI_MM */ 1621, /* PseudoMULT */ 1624, /* PseudoMULT_MM */ 1627, /* PseudoMULTu */ 1630, /* PseudoMULTu_MM */ 1633, /* PseudoPICK_PH */ 1636, /* PseudoPICK_QB */ 1640, /* PseudoReturn */ 1644, /* PseudoReturn64 */ 1645, /* PseudoSDIV */ 1646, /* PseudoSELECTFP_F_D32 */ 1649, /* PseudoSELECTFP_F_D64 */ 1653, /* PseudoSELECTFP_F_I */ 1657, /* PseudoSELECTFP_F_I64 */ 1661, /* PseudoSELECTFP_F_S */ 1665, /* PseudoSELECTFP_T_D32 */ 1669, /* PseudoSELECTFP_T_D64 */ 1673, /* PseudoSELECTFP_T_I */ 1677, /* PseudoSELECTFP_T_I64 */ 1681, /* PseudoSELECTFP_T_S */ 1685, /* PseudoSELECT_D32 */ 1689, /* PseudoSELECT_D64 */ 1693, /* PseudoSELECT_I */ 1697, /* PseudoSELECT_I64 */ 1701, /* PseudoSELECT_S */ 1705, /* PseudoTRUNC_W_D */ 1709, /* PseudoTRUNC_W_D32 */ 1712, /* PseudoTRUNC_W_S */ 1715, /* PseudoUDIV */ 1718, /* ROL */ 1721, /* ROLImm */ 1724, /* ROR */ 1727, /* RORImm */ 1730, /* RetRA */ 1733, /* RetRA16 */ 1733, /* SDC1_M1 */ 1733, /* SDIV_MM_Pseudo */ 1736, /* SDMacro */ 1739, /* SDivIMacro */ 1742, /* SDivMacro */ 1745, /* SEQIMacro */ 1748, /* SEQMacro */ 1751, /* SGE */ 1754, /* SGEImm */ 1757, /* SGEImm64 */ 1760, /* SGEU */ 1763, /* SGEUImm */ 1766, /* SGEUImm64 */ 1769, /* SGTImm */ 1772, /* SGTImm64 */ 1775, /* SGTUImm */ 1778, /* SGTUImm64 */ 1781, /* SLE */ 1784, /* SLEImm */ 1787, /* SLEImm64 */ 1790, /* SLEU */ 1793, /* SLEUImm */ 1796, /* SLEUImm64 */ 1799, /* SLTImm64 */ 1802, /* SLTUImm64 */ 1805, /* SNEIMacro */ 1808, /* SNEMacro */ 1811, /* SNZ_B_PSEUDO */ 1814, /* SNZ_D_PSEUDO */ 1816, /* SNZ_H_PSEUDO */ 1818, /* SNZ_V_PSEUDO */ 1820, /* SNZ_W_PSEUDO */ 1822, /* SRemIMacro */ 1824, /* SRemMacro */ 1827, /* STORE_ACC128 */ 1830, /* STORE_ACC64 */ 1833, /* STORE_ACC64DSP */ 1836, /* STORE_CCOND_DSP */ 1839, /* STR_D */ 1842, /* STR_W */ 1845, /* ST_F16 */ 1848, /* SWM_MM */ 1851, /* SZ_B_PSEUDO */ 1854, /* SZ_D_PSEUDO */ 1856, /* SZ_H_PSEUDO */ 1858, /* SZ_V_PSEUDO */ 1860, /* SZ_W_PSEUDO */ 1862, /* SaaAddr */ 1864, /* SaadAddr */ 1867, /* SelBeqZ */ 1870, /* SelBneZ */ 1874, /* SelTBteqZCmp */ 1878, /* SelTBteqZCmpi */ 1883, /* SelTBteqZSlt */ 1888, /* SelTBteqZSlti */ 1893, /* SelTBteqZSltiu */ 1898, /* SelTBteqZSltu */ 1903, /* SelTBtneZCmp */ 1908, /* SelTBtneZCmpi */ 1913, /* SelTBtneZSlt */ 1918, /* SelTBtneZSlti */ 1923, /* SelTBtneZSltiu */ 1928, /* SelTBtneZSltu */ 1933, /* SltCCRxRy16 */ 1938, /* SltiCCRxImmX16 */ 1941, /* SltiuCCRxImmX16 */ 1944, /* SltuCCRxRy16 */ 1947, /* SltuRxRyRz16 */ 1950, /* TAILCALL */ 1953, /* TAILCALL64R6REG */ 1954, /* TAILCALLHB64R6REG */ 1955, /* TAILCALLHBR6REG */ 1956, /* TAILCALLR6REG */ 1957, /* TAILCALLREG */ 1958, /* TAILCALLREG64 */ 1959, /* TAILCALLREGHB */ 1960, /* TAILCALLREGHB64 */ 1961, /* TAILCALLREG_MM */ 1962, /* TAILCALLREG_MMR6 */ 1963, /* TAILCALL_MM */ 1964, /* TAILCALL_MMR6 */ 1965, /* TRAP */ 1966, /* TRAP_MM */ 1966, /* UDIV_MM_Pseudo */ 1966, /* UDivIMacro */ 1969, /* UDivMacro */ 1972, /* URemIMacro */ 1975, /* URemMacro */ 1978, /* Ulh */ 1981, /* Ulhu */ 1984, /* Ulw */ 1987, /* Ush */ 1990, /* Usw */ 1993, /* XOR_V_D_PSEUDO */ 1996, /* XOR_V_H_PSEUDO */ 1999, /* XOR_V_W_PSEUDO */ 2002, /* ABSQ_S_PH */ 2005, /* ABSQ_S_PH_MM */ 2007, /* ABSQ_S_QB */ 2009, /* ABSQ_S_QB_MMR2 */ 2011, /* ABSQ_S_W */ 2013, /* ABSQ_S_W_MM */ 2015, /* ADD */ 2017, /* ADDIUPC */ 2020, /* ADDIUPC_MM */ 2022, /* ADDIUPC_MMR6 */ 2024, /* ADDIUR1SP_MM */ 2026, /* ADDIUR2_MM */ 2028, /* ADDIUS5_MM */ 2031, /* ADDIUSP_MM */ 2034, /* ADDIU_MMR6 */ 2035, /* ADDQH_PH */ 2038, /* ADDQH_PH_MMR2 */ 2041, /* ADDQH_R_PH */ 2044, /* ADDQH_R_PH_MMR2 */ 2047, /* ADDQH_R_W */ 2050, /* ADDQH_R_W_MMR2 */ 2053, /* ADDQH_W */ 2056, /* ADDQH_W_MMR2 */ 2059, /* ADDQ_PH */ 2062, /* ADDQ_PH_MM */ 2065, /* ADDQ_S_PH */ 2068, /* ADDQ_S_PH_MM */ 2071, /* ADDQ_S_W */ 2074, /* ADDQ_S_W_MM */ 2077, /* ADDR_PS64 */ 2080, /* ADDSC */ 2083, /* ADDSC_MM */ 2086, /* ADDS_A_B */ 2089, /* ADDS_A_D */ 2092, /* ADDS_A_H */ 2095, /* ADDS_A_W */ 2098, /* ADDS_S_B */ 2101, /* ADDS_S_D */ 2104, /* ADDS_S_H */ 2107, /* ADDS_S_W */ 2110, /* ADDS_U_B */ 2113, /* ADDS_U_D */ 2116, /* ADDS_U_H */ 2119, /* ADDS_U_W */ 2122, /* ADDU16_MM */ 2125, /* ADDU16_MMR6 */ 2128, /* ADDUH_QB */ 2131, /* ADDUH_QB_MMR2 */ 2134, /* ADDUH_R_QB */ 2137, /* ADDUH_R_QB_MMR2 */ 2140, /* ADDU_MMR6 */ 2143, /* ADDU_PH */ 2146, /* ADDU_PH_MMR2 */ 2149, /* ADDU_QB */ 2152, /* ADDU_QB_MM */ 2155, /* ADDU_S_PH */ 2158, /* ADDU_S_PH_MMR2 */ 2161, /* ADDU_S_QB */ 2164, /* ADDU_S_QB_MM */ 2167, /* ADDVI_B */ 2170, /* ADDVI_D */ 2173, /* ADDVI_H */ 2176, /* ADDVI_W */ 2179, /* ADDV_B */ 2182, /* ADDV_D */ 2185, /* ADDV_H */ 2188, /* ADDV_W */ 2191, /* ADDWC */ 2194, /* ADDWC_MM */ 2197, /* ADD_A_B */ 2200, /* ADD_A_D */ 2203, /* ADD_A_H */ 2206, /* ADD_A_W */ 2209, /* ADD_MM */ 2212, /* ADD_MMR6 */ 2215, /* ADDi */ 2218, /* ADDi_MM */ 2221, /* ADDiu */ 2224, /* ADDiu_MM */ 2227, /* ADDu */ 2230, /* ADDu_MM */ 2233, /* ALIGN */ 2236, /* ALIGN_MMR6 */ 2240, /* ALUIPC */ 2244, /* ALUIPC_MMR6 */ 2246, /* AND */ 2248, /* AND16_MM */ 2251, /* AND16_MMR6 */ 2254, /* AND64 */ 2257, /* ANDI16_MM */ 2260, /* ANDI16_MMR6 */ 2263, /* ANDI_B */ 2266, /* ANDI_MMR6 */ 2269, /* AND_MM */ 2272, /* AND_MMR6 */ 2275, /* AND_V */ 2278, /* ANDi */ 2281, /* ANDi64 */ 2284, /* ANDi_MM */ 2287, /* APPEND */ 2290, /* APPEND_MMR2 */ 2294, /* ASUB_S_B */ 2298, /* ASUB_S_D */ 2301, /* ASUB_S_H */ 2304, /* ASUB_S_W */ 2307, /* ASUB_U_B */ 2310, /* ASUB_U_D */ 2313, /* ASUB_U_H */ 2316, /* ASUB_U_W */ 2319, /* AUI */ 2322, /* AUIPC */ 2325, /* AUIPC_MMR6 */ 2327, /* AUI_MMR6 */ 2329, /* AVER_S_B */ 2332, /* AVER_S_D */ 2335, /* AVER_S_H */ 2338, /* AVER_S_W */ 2341, /* AVER_U_B */ 2344, /* AVER_U_D */ 2347, /* AVER_U_H */ 2350, /* AVER_U_W */ 2353, /* AVE_S_B */ 2356, /* AVE_S_D */ 2359, /* AVE_S_H */ 2362, /* AVE_S_W */ 2365, /* AVE_U_B */ 2368, /* AVE_U_D */ 2371, /* AVE_U_H */ 2374, /* AVE_U_W */ 2377, /* AddiuRxImmX16 */ 2380, /* AddiuRxPcImmX16 */ 2382, /* AddiuRxRxImm16 */ 2384, /* AddiuRxRxImmX16 */ 2387, /* AddiuRxRyOffMemX16 */ 2390, /* AddiuSpImm16 */ 2393, /* AddiuSpImmX16 */ 2394, /* AdduRxRyRz16 */ 2395, /* AndRxRxRy16 */ 2398, /* B16_MM */ 2401, /* BADDu */ 2402, /* BAL */ 2405, /* BALC */ 2406, /* BALC_MMR6 */ 2407, /* BALIGN */ 2408, /* BALIGN_MMR2 */ 2412, /* BBIT0 */ 2416, /* BBIT032 */ 2419, /* BBIT1 */ 2422, /* BBIT132 */ 2425, /* BC */ 2428, /* BC16_MMR6 */ 2429, /* BC1EQZ */ 2430, /* BC1EQZC_MMR6 */ 2432, /* BC1F */ 2434, /* BC1FL */ 2436, /* BC1F_MM */ 2438, /* BC1NEZ */ 2440, /* BC1NEZC_MMR6 */ 2442, /* BC1T */ 2444, /* BC1TL */ 2446, /* BC1T_MM */ 2448, /* BC2EQZ */ 2450, /* BC2EQZC_MMR6 */ 2452, /* BC2NEZ */ 2454, /* BC2NEZC_MMR6 */ 2456, /* BCLRI_B */ 2458, /* BCLRI_D */ 2461, /* BCLRI_H */ 2464, /* BCLRI_W */ 2467, /* BCLR_B */ 2470, /* BCLR_D */ 2473, /* BCLR_H */ 2476, /* BCLR_W */ 2479, /* BC_MMR6 */ 2482, /* BEQ */ 2483, /* BEQ64 */ 2486, /* BEQC */ 2489, /* BEQC64 */ 2492, /* BEQC_MMR6 */ 2495, /* BEQL */ 2498, /* BEQZ16_MM */ 2501, /* BEQZALC */ 2503, /* BEQZALC_MMR6 */ 2505, /* BEQZC */ 2507, /* BEQZC16_MMR6 */ 2509, /* BEQZC64 */ 2511, /* BEQZC_MM */ 2513, /* BEQZC_MMR6 */ 2515, /* BEQ_MM */ 2517, /* BGEC */ 2520, /* BGEC64 */ 2523, /* BGEC_MMR6 */ 2526, /* BGEUC */ 2529, /* BGEUC64 */ 2532, /* BGEUC_MMR6 */ 2535, /* BGEZ */ 2538, /* BGEZ64 */ 2540, /* BGEZAL */ 2542, /* BGEZALC */ 2544, /* BGEZALC_MMR6 */ 2546, /* BGEZALL */ 2548, /* BGEZALS_MM */ 2550, /* BGEZAL_MM */ 2552, /* BGEZC */ 2554, /* BGEZC64 */ 2556, /* BGEZC_MMR6 */ 2558, /* BGEZL */ 2560, /* BGEZ_MM */ 2562, /* BGTZ */ 2564, /* BGTZ64 */ 2566, /* BGTZALC */ 2568, /* BGTZALC_MMR6 */ 2570, /* BGTZC */ 2572, /* BGTZC64 */ 2574, /* BGTZC_MMR6 */ 2576, /* BGTZL */ 2578, /* BGTZ_MM */ 2580, /* BINSLI_B */ 2582, /* BINSLI_D */ 2586, /* BINSLI_H */ 2590, /* BINSLI_W */ 2594, /* BINSL_B */ 2598, /* BINSL_D */ 2602, /* BINSL_H */ 2606, /* BINSL_W */ 2610, /* BINSRI_B */ 2614, /* BINSRI_D */ 2618, /* BINSRI_H */ 2622, /* BINSRI_W */ 2626, /* BINSR_B */ 2630, /* BINSR_D */ 2634, /* BINSR_H */ 2638, /* BINSR_W */ 2642, /* BITREV */ 2646, /* BITREV_MM */ 2648, /* BITSWAP */ 2650, /* BITSWAP_MMR6 */ 2652, /* BLEZ */ 2654, /* BLEZ64 */ 2656, /* BLEZALC */ 2658, /* BLEZALC_MMR6 */ 2660, /* BLEZC */ 2662, /* BLEZC64 */ 2664, /* BLEZC_MMR6 */ 2666, /* BLEZL */ 2668, /* BLEZ_MM */ 2670, /* BLTC */ 2672, /* BLTC64 */ 2675, /* BLTC_MMR6 */ 2678, /* BLTUC */ 2681, /* BLTUC64 */ 2684, /* BLTUC_MMR6 */ 2687, /* BLTZ */ 2690, /* BLTZ64 */ 2692, /* BLTZAL */ 2694, /* BLTZALC */ 2696, /* BLTZALC_MMR6 */ 2698, /* BLTZALL */ 2700, /* BLTZALS_MM */ 2702, /* BLTZAL_MM */ 2704, /* BLTZC */ 2706, /* BLTZC64 */ 2708, /* BLTZC_MMR6 */ 2710, /* BLTZL */ 2712, /* BLTZ_MM */ 2714, /* BMNZI_B */ 2716, /* BMNZ_V */ 2720, /* BMZI_B */ 2724, /* BMZ_V */ 2728, /* BNE */ 2732, /* BNE64 */ 2735, /* BNEC */ 2738, /* BNEC64 */ 2741, /* BNEC_MMR6 */ 2744, /* BNEGI_B */ 2747, /* BNEGI_D */ 2750, /* BNEGI_H */ 2753, /* BNEGI_W */ 2756, /* BNEG_B */ 2759, /* BNEG_D */ 2762, /* BNEG_H */ 2765, /* BNEG_W */ 2768, /* BNEL */ 2771, /* BNEZ16_MM */ 2774, /* BNEZALC */ 2776, /* BNEZALC_MMR6 */ 2778, /* BNEZC */ 2780, /* BNEZC16_MMR6 */ 2782, /* BNEZC64 */ 2784, /* BNEZC_MM */ 2786, /* BNEZC_MMR6 */ 2788, /* BNE_MM */ 2790, /* BNVC */ 2793, /* BNVC_MMR6 */ 2796, /* BNZ_B */ 2799, /* BNZ_D */ 2801, /* BNZ_H */ 2803, /* BNZ_V */ 2805, /* BNZ_W */ 2807, /* BOVC */ 2809, /* BOVC_MMR6 */ 2812, /* BPOSGE32 */ 2815, /* BPOSGE32C_MMR3 */ 2816, /* BPOSGE32_MM */ 2817, /* BREAK */ 2818, /* BREAK16_MM */ 2820, /* BREAK16_MMR6 */ 2821, /* BREAK_MM */ 2822, /* BREAK_MMR6 */ 2824, /* BSELI_B */ 2826, /* BSEL_V */ 2830, /* BSETI_B */ 2834, /* BSETI_D */ 2837, /* BSETI_H */ 2840, /* BSETI_W */ 2843, /* BSET_B */ 2846, /* BSET_D */ 2849, /* BSET_H */ 2852, /* BSET_W */ 2855, /* BZ_B */ 2858, /* BZ_D */ 2860, /* BZ_H */ 2862, /* BZ_V */ 2864, /* BZ_W */ 2866, /* BeqzRxImm16 */ 2868, /* BeqzRxImmX16 */ 2870, /* Bimm16 */ 2872, /* BimmX16 */ 2873, /* BnezRxImm16 */ 2874, /* BnezRxImmX16 */ 2876, /* Break16 */ 2878, /* Bteqz16 */ 2878, /* BteqzX16 */ 2879, /* Btnez16 */ 2880, /* BtnezX16 */ 2881, /* CACHE */ 2882, /* CACHEE */ 2885, /* CACHEE_MM */ 2888, /* CACHE_MM */ 2891, /* CACHE_MMR6 */ 2894, /* CACHE_R6 */ 2897, /* CEIL_L_D64 */ 2900, /* CEIL_L_D_MMR6 */ 2902, /* CEIL_L_S */ 2904, /* CEIL_L_S_MMR6 */ 2906, /* CEIL_W_D32 */ 2908, /* CEIL_W_D64 */ 2910, /* CEIL_W_D_MMR6 */ 2912, /* CEIL_W_MM */ 2914, /* CEIL_W_S */ 2916, /* CEIL_W_S_MM */ 2918, /* CEIL_W_S_MMR6 */ 2920, /* CEQI_B */ 2922, /* CEQI_D */ 2925, /* CEQI_H */ 2928, /* CEQI_W */ 2931, /* CEQ_B */ 2934, /* CEQ_D */ 2937, /* CEQ_H */ 2940, /* CEQ_W */ 2943, /* CFC1 */ 2946, /* CFC1_MM */ 2948, /* CFC2_MM */ 2950, /* CFCMSA */ 2952, /* CINS */ 2954, /* CINS32 */ 2958, /* CINS64_32 */ 2962, /* CINS_i32 */ 2966, /* CLASS_D */ 2970, /* CLASS_D_MMR6 */ 2972, /* CLASS_S */ 2974, /* CLASS_S_MMR6 */ 2976, /* CLEI_S_B */ 2978, /* CLEI_S_D */ 2981, /* CLEI_S_H */ 2984, /* CLEI_S_W */ 2987, /* CLEI_U_B */ 2990, /* CLEI_U_D */ 2993, /* CLEI_U_H */ 2996, /* CLEI_U_W */ 2999, /* CLE_S_B */ 3002, /* CLE_S_D */ 3005, /* CLE_S_H */ 3008, /* CLE_S_W */ 3011, /* CLE_U_B */ 3014, /* CLE_U_D */ 3017, /* CLE_U_H */ 3020, /* CLE_U_W */ 3023, /* CLO */ 3026, /* CLO_MM */ 3028, /* CLO_MMR6 */ 3030, /* CLO_R6 */ 3032, /* CLTI_S_B */ 3034, /* CLTI_S_D */ 3037, /* CLTI_S_H */ 3040, /* CLTI_S_W */ 3043, /* CLTI_U_B */ 3046, /* CLTI_U_D */ 3049, /* CLTI_U_H */ 3052, /* CLTI_U_W */ 3055, /* CLT_S_B */ 3058, /* CLT_S_D */ 3061, /* CLT_S_H */ 3064, /* CLT_S_W */ 3067, /* CLT_U_B */ 3070, /* CLT_U_D */ 3073, /* CLT_U_H */ 3076, /* CLT_U_W */ 3079, /* CLZ */ 3082, /* CLZ_MM */ 3084, /* CLZ_MMR6 */ 3086, /* CLZ_R6 */ 3088, /* CMPGDU_EQ_QB */ 3090, /* CMPGDU_EQ_QB_MMR2 */ 3093, /* CMPGDU_LE_QB */ 3096, /* CMPGDU_LE_QB_MMR2 */ 3099, /* CMPGDU_LT_QB */ 3102, /* CMPGDU_LT_QB_MMR2 */ 3105, /* CMPGU_EQ_QB */ 3108, /* CMPGU_EQ_QB_MM */ 3111, /* CMPGU_LE_QB */ 3114, /* CMPGU_LE_QB_MM */ 3117, /* CMPGU_LT_QB */ 3120, /* CMPGU_LT_QB_MM */ 3123, /* CMPU_EQ_QB */ 3126, /* CMPU_EQ_QB_MM */ 3128, /* CMPU_LE_QB */ 3130, /* CMPU_LE_QB_MM */ 3132, /* CMPU_LT_QB */ 3134, /* CMPU_LT_QB_MM */ 3136, /* CMP_AF_D_MMR6 */ 3138, /* CMP_AF_S_MMR6 */ 3141, /* CMP_EQ_D */ 3144, /* CMP_EQ_D_MMR6 */ 3147, /* CMP_EQ_PH */ 3150, /* CMP_EQ_PH_MM */ 3152, /* CMP_EQ_S */ 3154, /* CMP_EQ_S_MMR6 */ 3157, /* CMP_F_D */ 3160, /* CMP_F_S */ 3163, /* CMP_LE_D */ 3166, /* CMP_LE_D_MMR6 */ 3169, /* CMP_LE_PH */ 3172, /* CMP_LE_PH_MM */ 3174, /* CMP_LE_S */ 3176, /* CMP_LE_S_MMR6 */ 3179, /* CMP_LT_D */ 3182, /* CMP_LT_D_MMR6 */ 3185, /* CMP_LT_PH */ 3188, /* CMP_LT_PH_MM */ 3190, /* CMP_LT_S */ 3192, /* CMP_LT_S_MMR6 */ 3195, /* CMP_SAF_D */ 3198, /* CMP_SAF_D_MMR6 */ 3201, /* CMP_SAF_S */ 3204, /* CMP_SAF_S_MMR6 */ 3207, /* CMP_SEQ_D */ 3210, /* CMP_SEQ_D_MMR6 */ 3213, /* CMP_SEQ_S */ 3216, /* CMP_SEQ_S_MMR6 */ 3219, /* CMP_SLE_D */ 3222, /* CMP_SLE_D_MMR6 */ 3225, /* CMP_SLE_S */ 3228, /* CMP_SLE_S_MMR6 */ 3231, /* CMP_SLT_D */ 3234, /* CMP_SLT_D_MMR6 */ 3237, /* CMP_SLT_S */ 3240, /* CMP_SLT_S_MMR6 */ 3243, /* CMP_SUEQ_D */ 3246, /* CMP_SUEQ_D_MMR6 */ 3249, /* CMP_SUEQ_S */ 3252, /* CMP_SUEQ_S_MMR6 */ 3255, /* CMP_SULE_D */ 3258, /* CMP_SULE_D_MMR6 */ 3261, /* CMP_SULE_S */ 3264, /* CMP_SULE_S_MMR6 */ 3267, /* CMP_SULT_D */ 3270, /* CMP_SULT_D_MMR6 */ 3273, /* CMP_SULT_S */ 3276, /* CMP_SULT_S_MMR6 */ 3279, /* CMP_SUN_D */ 3282, /* CMP_SUN_D_MMR6 */ 3285, /* CMP_SUN_S */ 3288, /* CMP_SUN_S_MMR6 */ 3291, /* CMP_UEQ_D */ 3294, /* CMP_UEQ_D_MMR6 */ 3297, /* CMP_UEQ_S */ 3300, /* CMP_UEQ_S_MMR6 */ 3303, /* CMP_ULE_D */ 3306, /* CMP_ULE_D_MMR6 */ 3309, /* CMP_ULE_S */ 3312, /* CMP_ULE_S_MMR6 */ 3315, /* CMP_ULT_D */ 3318, /* CMP_ULT_D_MMR6 */ 3321, /* CMP_ULT_S */ 3324, /* CMP_ULT_S_MMR6 */ 3327, /* CMP_UN_D */ 3330, /* CMP_UN_D_MMR6 */ 3333, /* CMP_UN_S */ 3336, /* CMP_UN_S_MMR6 */ 3339, /* COPY_S_B */ 3342, /* COPY_S_D */ 3345, /* COPY_S_H */ 3348, /* COPY_S_W */ 3351, /* COPY_U_B */ 3354, /* COPY_U_H */ 3357, /* COPY_U_W */ 3360, /* CRC32B */ 3363, /* CRC32CB */ 3366, /* CRC32CD */ 3369, /* CRC32CH */ 3372, /* CRC32CW */ 3375, /* CRC32D */ 3378, /* CRC32H */ 3381, /* CRC32W */ 3384, /* CTC1 */ 3387, /* CTC1_MM */ 3389, /* CTC2_MM */ 3391, /* CTCMSA */ 3393, /* CVT_D32_S */ 3395, /* CVT_D32_S_MM */ 3397, /* CVT_D32_W */ 3399, /* CVT_D32_W_MM */ 3401, /* CVT_D64_L */ 3403, /* CVT_D64_S */ 3405, /* CVT_D64_S_MM */ 3407, /* CVT_D64_W */ 3409, /* CVT_D64_W_MM */ 3411, /* CVT_D_L_MMR6 */ 3413, /* CVT_L_D64 */ 3415, /* CVT_L_D64_MM */ 3417, /* CVT_L_D_MMR6 */ 3419, /* CVT_L_S */ 3421, /* CVT_L_S_MM */ 3423, /* CVT_L_S_MMR6 */ 3425, /* CVT_PS_PW64 */ 3427, /* CVT_PS_S64 */ 3429, /* CVT_PW_PS64 */ 3432, /* CVT_S_D32 */ 3434, /* CVT_S_D32_MM */ 3436, /* CVT_S_D64 */ 3438, /* CVT_S_D64_MM */ 3440, /* CVT_S_L */ 3442, /* CVT_S_L_MMR6 */ 3444, /* CVT_S_PL64 */ 3446, /* CVT_S_PU64 */ 3448, /* CVT_S_W */ 3450, /* CVT_S_W_MM */ 3452, /* CVT_S_W_MMR6 */ 3454, /* CVT_W_D32 */ 3456, /* CVT_W_D32_MM */ 3458, /* CVT_W_D64 */ 3460, /* CVT_W_D64_MM */ 3462, /* CVT_W_S */ 3464, /* CVT_W_S_MM */ 3466, /* CVT_W_S_MMR6 */ 3468, /* C_EQ_D32 */ 3470, /* C_EQ_D32_MM */ 3473, /* C_EQ_D64 */ 3476, /* C_EQ_D64_MM */ 3479, /* C_EQ_S */ 3482, /* C_EQ_S_MM */ 3485, /* C_F_D32 */ 3488, /* C_F_D32_MM */ 3491, /* C_F_D64 */ 3494, /* C_F_D64_MM */ 3497, /* C_F_S */ 3500, /* C_F_S_MM */ 3503, /* C_LE_D32 */ 3506, /* C_LE_D32_MM */ 3509, /* C_LE_D64 */ 3512, /* C_LE_D64_MM */ 3515, /* C_LE_S */ 3518, /* C_LE_S_MM */ 3521, /* C_LT_D32 */ 3524, /* C_LT_D32_MM */ 3527, /* C_LT_D64 */ 3530, /* C_LT_D64_MM */ 3533, /* C_LT_S */ 3536, /* C_LT_S_MM */ 3539, /* C_NGE_D32 */ 3542, /* C_NGE_D32_MM */ 3545, /* C_NGE_D64 */ 3548, /* C_NGE_D64_MM */ 3551, /* C_NGE_S */ 3554, /* C_NGE_S_MM */ 3557, /* C_NGLE_D32 */ 3560, /* C_NGLE_D32_MM */ 3563, /* C_NGLE_D64 */ 3566, /* C_NGLE_D64_MM */ 3569, /* C_NGLE_S */ 3572, /* C_NGLE_S_MM */ 3575, /* C_NGL_D32 */ 3578, /* C_NGL_D32_MM */ 3581, /* C_NGL_D64 */ 3584, /* C_NGL_D64_MM */ 3587, /* C_NGL_S */ 3590, /* C_NGL_S_MM */ 3593, /* C_NGT_D32 */ 3596, /* C_NGT_D32_MM */ 3599, /* C_NGT_D64 */ 3602, /* C_NGT_D64_MM */ 3605, /* C_NGT_S */ 3608, /* C_NGT_S_MM */ 3611, /* C_OLE_D32 */ 3614, /* C_OLE_D32_MM */ 3617, /* C_OLE_D64 */ 3620, /* C_OLE_D64_MM */ 3623, /* C_OLE_S */ 3626, /* C_OLE_S_MM */ 3629, /* C_OLT_D32 */ 3632, /* C_OLT_D32_MM */ 3635, /* C_OLT_D64 */ 3638, /* C_OLT_D64_MM */ 3641, /* C_OLT_S */ 3644, /* C_OLT_S_MM */ 3647, /* C_SEQ_D32 */ 3650, /* C_SEQ_D32_MM */ 3653, /* C_SEQ_D64 */ 3656, /* C_SEQ_D64_MM */ 3659, /* C_SEQ_S */ 3662, /* C_SEQ_S_MM */ 3665, /* C_SF_D32 */ 3668, /* C_SF_D32_MM */ 3671, /* C_SF_D64 */ 3674, /* C_SF_D64_MM */ 3677, /* C_SF_S */ 3680, /* C_SF_S_MM */ 3683, /* C_UEQ_D32 */ 3686, /* C_UEQ_D32_MM */ 3689, /* C_UEQ_D64 */ 3692, /* C_UEQ_D64_MM */ 3695, /* C_UEQ_S */ 3698, /* C_UEQ_S_MM */ 3701, /* C_ULE_D32 */ 3704, /* C_ULE_D32_MM */ 3707, /* C_ULE_D64 */ 3710, /* C_ULE_D64_MM */ 3713, /* C_ULE_S */ 3716, /* C_ULE_S_MM */ 3719, /* C_ULT_D32 */ 3722, /* C_ULT_D32_MM */ 3725, /* C_ULT_D64 */ 3728, /* C_ULT_D64_MM */ 3731, /* C_ULT_S */ 3734, /* C_ULT_S_MM */ 3737, /* C_UN_D32 */ 3740, /* C_UN_D32_MM */ 3743, /* C_UN_D64 */ 3746, /* C_UN_D64_MM */ 3749, /* C_UN_S */ 3752, /* C_UN_S_MM */ 3755, /* CmpRxRy16 */ 3758, /* CmpiRxImm16 */ 3760, /* CmpiRxImmX16 */ 3762, /* DADD */ 3764, /* DADDi */ 3767, /* DADDiu */ 3770, /* DADDu */ 3773, /* DAHI */ 3776, /* DALIGN */ 3779, /* DATI */ 3783, /* DAUI */ 3786, /* DBITSWAP */ 3789, /* DCLO */ 3791, /* DCLO_R6 */ 3793, /* DCLZ */ 3795, /* DCLZ_R6 */ 3797, /* DDIV */ 3799, /* DDIVU */ 3802, /* DERET */ 3805, /* DERET_MM */ 3805, /* DERET_MMR6 */ 3805, /* DEXT */ 3805, /* DEXT64_32 */ 3809, /* DEXTM */ 3813, /* DEXTU */ 3817, /* DI */ 3821, /* DINS */ 3822, /* DINSM */ 3827, /* DINSU */ 3832, /* DIV */ 3837, /* DIVU */ 3840, /* DIVU_MMR6 */ 3843, /* DIV_MMR6 */ 3846, /* DIV_S_B */ 3849, /* DIV_S_D */ 3852, /* DIV_S_H */ 3855, /* DIV_S_W */ 3858, /* DIV_U_B */ 3861, /* DIV_U_D */ 3864, /* DIV_U_H */ 3867, /* DIV_U_W */ 3870, /* DI_MM */ 3873, /* DI_MMR6 */ 3874, /* DLSA */ 3875, /* DLSA_R6 */ 3879, /* DMFC0 */ 3883, /* DMFC1 */ 3886, /* DMFC2 */ 3888, /* DMFC2_OCTEON */ 3891, /* DMFGC0 */ 3893, /* DMOD */ 3896, /* DMODU */ 3899, /* DMT */ 3902, /* DMTC0 */ 3903, /* DMTC1 */ 3906, /* DMTC2 */ 3908, /* DMTC2_OCTEON */ 3911, /* DMTGC0 */ 3913, /* DMUH */ 3916, /* DMUHU */ 3919, /* DMUL */ 3922, /* DMULT */ 3925, /* DMULTu */ 3927, /* DMULU */ 3929, /* DMUL_R6 */ 3932, /* DOTP_S_D */ 3935, /* DOTP_S_H */ 3938, /* DOTP_S_W */ 3941, /* DOTP_U_D */ 3944, /* DOTP_U_H */ 3947, /* DOTP_U_W */ 3950, /* DPADD_S_D */ 3953, /* DPADD_S_H */ 3957, /* DPADD_S_W */ 3961, /* DPADD_U_D */ 3965, /* DPADD_U_H */ 3969, /* DPADD_U_W */ 3973, /* DPAQX_SA_W_PH */ 3977, /* DPAQX_SA_W_PH_MMR2 */ 3981, /* DPAQX_S_W_PH */ 3985, /* DPAQX_S_W_PH_MMR2 */ 3989, /* DPAQ_SA_L_W */ 3993, /* DPAQ_SA_L_W_MM */ 3997, /* DPAQ_S_W_PH */ 4001, /* DPAQ_S_W_PH_MM */ 4005, /* DPAU_H_QBL */ 4009, /* DPAU_H_QBL_MM */ 4013, /* DPAU_H_QBR */ 4017, /* DPAU_H_QBR_MM */ 4021, /* DPAX_W_PH */ 4025, /* DPAX_W_PH_MMR2 */ 4029, /* DPA_W_PH */ 4033, /* DPA_W_PH_MMR2 */ 4037, /* DPOP */ 4041, /* DPSQX_SA_W_PH */ 4043, /* DPSQX_SA_W_PH_MMR2 */ 4047, /* DPSQX_S_W_PH */ 4051, /* DPSQX_S_W_PH_MMR2 */ 4055, /* DPSQ_SA_L_W */ 4059, /* DPSQ_SA_L_W_MM */ 4063, /* DPSQ_S_W_PH */ 4067, /* DPSQ_S_W_PH_MM */ 4071, /* DPSUB_S_D */ 4075, /* DPSUB_S_H */ 4079, /* DPSUB_S_W */ 4083, /* DPSUB_U_D */ 4087, /* DPSUB_U_H */ 4091, /* DPSUB_U_W */ 4095, /* DPSU_H_QBL */ 4099, /* DPSU_H_QBL_MM */ 4103, /* DPSU_H_QBR */ 4107, /* DPSU_H_QBR_MM */ 4111, /* DPSX_W_PH */ 4115, /* DPSX_W_PH_MMR2 */ 4119, /* DPS_W_PH */ 4123, /* DPS_W_PH_MMR2 */ 4127, /* DROTR */ 4131, /* DROTR32 */ 4134, /* DROTRV */ 4137, /* DSBH */ 4140, /* DSDIV */ 4142, /* DSHD */ 4144, /* DSLL */ 4146, /* DSLL32 */ 4149, /* DSLL64_32 */ 4152, /* DSLLV */ 4154, /* DSRA */ 4157, /* DSRA32 */ 4160, /* DSRAV */ 4163, /* DSRL */ 4166, /* DSRL32 */ 4169, /* DSRLV */ 4172, /* DSUB */ 4175, /* DSUBu */ 4178, /* DUDIV */ 4181, /* DVP */ 4183, /* DVPE */ 4184, /* DVP_MMR6 */ 4185, /* DivRxRy16 */ 4186, /* DivuRxRy16 */ 4188, /* EHB */ 4190, /* EHB_MM */ 4190, /* EHB_MMR6 */ 4190, /* EI */ 4190, /* EI_MM */ 4191, /* EI_MMR6 */ 4192, /* EMT */ 4193, /* ERET */ 4194, /* ERETNC */ 4194, /* ERETNC_MMR6 */ 4194, /* ERET_MM */ 4194, /* ERET_MMR6 */ 4194, /* EVP */ 4194, /* EVPE */ 4195, /* EVP_MMR6 */ 4196, /* EXT */ 4197, /* EXTP */ 4201, /* EXTPDP */ 4204, /* EXTPDPV */ 4207, /* EXTPDPV_MM */ 4210, /* EXTPDP_MM */ 4213, /* EXTPV */ 4216, /* EXTPV_MM */ 4219, /* EXTP_MM */ 4222, /* EXTRV_RS_W */ 4225, /* EXTRV_RS_W_MM */ 4228, /* EXTRV_R_W */ 4231, /* EXTRV_R_W_MM */ 4234, /* EXTRV_S_H */ 4237, /* EXTRV_S_H_MM */ 4240, /* EXTRV_W */ 4243, /* EXTRV_W_MM */ 4246, /* EXTR_RS_W */ 4249, /* EXTR_RS_W_MM */ 4252, /* EXTR_R_W */ 4255, /* EXTR_R_W_MM */ 4258, /* EXTR_S_H */ 4261, /* EXTR_S_H_MM */ 4264, /* EXTR_W */ 4267, /* EXTR_W_MM */ 4270, /* EXTS */ 4273, /* EXTS32 */ 4277, /* EXT_MM */ 4281, /* EXT_MMR6 */ 4285, /* FABS_D32 */ 4289, /* FABS_D32_MM */ 4291, /* FABS_D64 */ 4293, /* FABS_D64_MM */ 4295, /* FABS_S */ 4297, /* FABS_S_MM */ 4299, /* FADD_D */ 4301, /* FADD_D32 */ 4304, /* FADD_D32_MM */ 4307, /* FADD_D64 */ 4310, /* FADD_D64_MM */ 4313, /* FADD_PS64 */ 4316, /* FADD_S */ 4319, /* FADD_S_MM */ 4322, /* FADD_S_MMR6 */ 4325, /* FADD_W */ 4328, /* FCAF_D */ 4331, /* FCAF_W */ 4334, /* FCEQ_D */ 4337, /* FCEQ_W */ 4340, /* FCLASS_D */ 4343, /* FCLASS_W */ 4345, /* FCLE_D */ 4347, /* FCLE_W */ 4350, /* FCLT_D */ 4353, /* FCLT_W */ 4356, /* FCMP_D32 */ 4359, /* FCMP_D32_MM */ 4362, /* FCMP_D64 */ 4365, /* FCMP_S32 */ 4368, /* FCMP_S32_MM */ 4371, /* FCNE_D */ 4374, /* FCNE_W */ 4377, /* FCOR_D */ 4380, /* FCOR_W */ 4383, /* FCUEQ_D */ 4386, /* FCUEQ_W */ 4389, /* FCULE_D */ 4392, /* FCULE_W */ 4395, /* FCULT_D */ 4398, /* FCULT_W */ 4401, /* FCUNE_D */ 4404, /* FCUNE_W */ 4407, /* FCUN_D */ 4410, /* FCUN_W */ 4413, /* FDIV_D */ 4416, /* FDIV_D32 */ 4419, /* FDIV_D32_MM */ 4422, /* FDIV_D64 */ 4425, /* FDIV_D64_MM */ 4428, /* FDIV_S */ 4431, /* FDIV_S_MM */ 4434, /* FDIV_S_MMR6 */ 4437, /* FDIV_W */ 4440, /* FEXDO_H */ 4443, /* FEXDO_W */ 4446, /* FEXP2_D */ 4449, /* FEXP2_W */ 4452, /* FEXUPL_D */ 4455, /* FEXUPL_W */ 4457, /* FEXUPR_D */ 4459, /* FEXUPR_W */ 4461, /* FFINT_S_D */ 4463, /* FFINT_S_W */ 4465, /* FFINT_U_D */ 4467, /* FFINT_U_W */ 4469, /* FFQL_D */ 4471, /* FFQL_W */ 4473, /* FFQR_D */ 4475, /* FFQR_W */ 4477, /* FILL_B */ 4479, /* FILL_D */ 4481, /* FILL_H */ 4483, /* FILL_W */ 4485, /* FLOG2_D */ 4487, /* FLOG2_W */ 4489, /* FLOOR_L_D64 */ 4491, /* FLOOR_L_D_MMR6 */ 4493, /* FLOOR_L_S */ 4495, /* FLOOR_L_S_MMR6 */ 4497, /* FLOOR_W_D32 */ 4499, /* FLOOR_W_D64 */ 4501, /* FLOOR_W_D_MMR6 */ 4503, /* FLOOR_W_MM */ 4505, /* FLOOR_W_S */ 4507, /* FLOOR_W_S_MM */ 4509, /* FLOOR_W_S_MMR6 */ 4511, /* FMADD_D */ 4513, /* FMADD_W */ 4517, /* FMAX_A_D */ 4521, /* FMAX_A_W */ 4524, /* FMAX_D */ 4527, /* FMAX_W */ 4530, /* FMIN_A_D */ 4533, /* FMIN_A_W */ 4536, /* FMIN_D */ 4539, /* FMIN_W */ 4542, /* FMOV_D32 */ 4545, /* FMOV_D32_MM */ 4547, /* FMOV_D64 */ 4549, /* FMOV_D64_MM */ 4551, /* FMOV_D_MMR6 */ 4553, /* FMOV_S */ 4555, /* FMOV_S_MM */ 4557, /* FMOV_S_MMR6 */ 4559, /* FMSUB_D */ 4561, /* FMSUB_W */ 4565, /* FMUL_D */ 4569, /* FMUL_D32 */ 4572, /* FMUL_D32_MM */ 4575, /* FMUL_D64 */ 4578, /* FMUL_D64_MM */ 4581, /* FMUL_PS64 */ 4584, /* FMUL_S */ 4587, /* FMUL_S_MM */ 4590, /* FMUL_S_MMR6 */ 4593, /* FMUL_W */ 4596, /* FNEG_D32 */ 4599, /* FNEG_D32_MM */ 4601, /* FNEG_D64 */ 4603, /* FNEG_D64_MM */ 4605, /* FNEG_S */ 4607, /* FNEG_S_MM */ 4609, /* FNEG_S_MMR6 */ 4611, /* FORK */ 4613, /* FRCP_D */ 4616, /* FRCP_W */ 4618, /* FRINT_D */ 4620, /* FRINT_W */ 4622, /* FRSQRT_D */ 4624, /* FRSQRT_W */ 4626, /* FSAF_D */ 4628, /* FSAF_W */ 4631, /* FSEQ_D */ 4634, /* FSEQ_W */ 4637, /* FSLE_D */ 4640, /* FSLE_W */ 4643, /* FSLT_D */ 4646, /* FSLT_W */ 4649, /* FSNE_D */ 4652, /* FSNE_W */ 4655, /* FSOR_D */ 4658, /* FSOR_W */ 4661, /* FSQRT_D */ 4664, /* FSQRT_D32 */ 4666, /* FSQRT_D32_MM */ 4668, /* FSQRT_D64 */ 4670, /* FSQRT_D64_MM */ 4672, /* FSQRT_S */ 4674, /* FSQRT_S_MM */ 4676, /* FSQRT_W */ 4678, /* FSUB_D */ 4680, /* FSUB_D32 */ 4683, /* FSUB_D32_MM */ 4686, /* FSUB_D64 */ 4689, /* FSUB_D64_MM */ 4692, /* FSUB_PS64 */ 4695, /* FSUB_S */ 4698, /* FSUB_S_MM */ 4701, /* FSUB_S_MMR6 */ 4704, /* FSUB_W */ 4707, /* FSUEQ_D */ 4710, /* FSUEQ_W */ 4713, /* FSULE_D */ 4716, /* FSULE_W */ 4719, /* FSULT_D */ 4722, /* FSULT_W */ 4725, /* FSUNE_D */ 4728, /* FSUNE_W */ 4731, /* FSUN_D */ 4734, /* FSUN_W */ 4737, /* FTINT_S_D */ 4740, /* FTINT_S_W */ 4742, /* FTINT_U_D */ 4744, /* FTINT_U_W */ 4746, /* FTQ_H */ 4748, /* FTQ_W */ 4751, /* FTRUNC_S_D */ 4754, /* FTRUNC_S_W */ 4756, /* FTRUNC_U_D */ 4758, /* FTRUNC_U_W */ 4760, /* GINVI */ 4762, /* GINVI_MMR6 */ 4763, /* GINVT */ 4764, /* GINVT_MMR6 */ 4766, /* HADD_S_D */ 4768, /* HADD_S_H */ 4771, /* HADD_S_W */ 4774, /* HADD_U_D */ 4777, /* HADD_U_H */ 4780, /* HADD_U_W */ 4783, /* HSUB_S_D */ 4786, /* HSUB_S_H */ 4789, /* HSUB_S_W */ 4792, /* HSUB_U_D */ 4795, /* HSUB_U_H */ 4798, /* HSUB_U_W */ 4801, /* HYPCALL */ 4804, /* HYPCALL_MM */ 4805, /* ILVEV_B */ 4806, /* ILVEV_D */ 4809, /* ILVEV_H */ 4812, /* ILVEV_W */ 4815, /* ILVL_B */ 4818, /* ILVL_D */ 4821, /* ILVL_H */ 4824, /* ILVL_W */ 4827, /* ILVOD_B */ 4830, /* ILVOD_D */ 4833, /* ILVOD_H */ 4836, /* ILVOD_W */ 4839, /* ILVR_B */ 4842, /* ILVR_D */ 4845, /* ILVR_H */ 4848, /* ILVR_W */ 4851, /* INS */ 4854, /* INSERT_B */ 4859, /* INSERT_D */ 4863, /* INSERT_H */ 4867, /* INSERT_W */ 4871, /* INSV */ 4875, /* INSVE_B */ 4878, /* INSVE_D */ 4883, /* INSVE_H */ 4888, /* INSVE_W */ 4893, /* INSV_MM */ 4898, /* INS_MM */ 4901, /* INS_MMR6 */ 4906, /* J */ 4911, /* JAL */ 4912, /* JALR */ 4913, /* JALR16_MM */ 4915, /* JALR64 */ 4916, /* JALRC16_MMR6 */ 4918, /* JALRC_HB_MMR6 */ 4919, /* JALRC_MMR6 */ 4921, /* JALRS16_MM */ 4923, /* JALRS_MM */ 4924, /* JALR_HB */ 4926, /* JALR_HB64 */ 4928, /* JALR_MM */ 4930, /* JALS_MM */ 4932, /* JALX */ 4933, /* JALX_MM */ 4934, /* JAL_MM */ 4935, /* JIALC */ 4936, /* JIALC64 */ 4938, /* JIALC_MMR6 */ 4940, /* JIC */ 4942, /* JIC64 */ 4944, /* JIC_MMR6 */ 4946, /* JR */ 4948, /* JR16_MM */ 4949, /* JR64 */ 4950, /* JRADDIUSP */ 4951, /* JRC16_MM */ 4952, /* JRC16_MMR6 */ 4953, /* JRCADDIUSP_MMR6 */ 4954, /* JR_HB */ 4955, /* JR_HB64 */ 4956, /* JR_HB64_R6 */ 4957, /* JR_HB_R6 */ 4958, /* JR_MM */ 4959, /* J_MM */ 4960, /* Jal16 */ 4961, /* JalB16 */ 4962, /* JrRa16 */ 4963, /* JrcRa16 */ 4963, /* JrcRx16 */ 4963, /* JumpLinkReg16 */ 4964, /* LB */ 4965, /* LB64 */ 4968, /* LBE */ 4971, /* LBE_MM */ 4974, /* LBU16_MM */ 4977, /* LBUX */ 4980, /* LBUX_MM */ 4983, /* LBU_MMR6 */ 4986, /* LB_MM */ 4989, /* LB_MMR6 */ 4992, /* LBu */ 4995, /* LBu64 */ 4998, /* LBuE */ 5001, /* LBuE_MM */ 5004, /* LBu_MM */ 5007, /* LD */ 5010, /* LDC1 */ 5013, /* LDC164 */ 5016, /* LDC1_D64_MMR6 */ 5019, /* LDC1_MM_D32 */ 5022, /* LDC1_MM_D64 */ 5025, /* LDC2 */ 5028, /* LDC2_MMR6 */ 5031, /* LDC2_R6 */ 5034, /* LDC3 */ 5037, /* LDI_B */ 5040, /* LDI_D */ 5042, /* LDI_H */ 5044, /* LDI_W */ 5046, /* LDL */ 5048, /* LDPC */ 5052, /* LDR */ 5054, /* LDXC1 */ 5058, /* LDXC164 */ 5061, /* LD_B */ 5064, /* LD_D */ 5067, /* LD_H */ 5070, /* LD_W */ 5073, /* LEA_ADDiu */ 5076, /* LEA_ADDiu64 */ 5079, /* LEA_ADDiu_MM */ 5082, /* LH */ 5085, /* LH64 */ 5088, /* LHE */ 5091, /* LHE_MM */ 5094, /* LHU16_MM */ 5097, /* LHX */ 5100, /* LHX_MM */ 5103, /* LH_MM */ 5106, /* LHu */ 5109, /* LHu64 */ 5112, /* LHuE */ 5115, /* LHuE_MM */ 5118, /* LHu_MM */ 5121, /* LI16_MM */ 5124, /* LI16_MMR6 */ 5126, /* LL */ 5128, /* LL64 */ 5131, /* LL64_R6 */ 5134, /* LLD */ 5137, /* LLD_R6 */ 5140, /* LLE */ 5143, /* LLE_MM */ 5146, /* LL_MM */ 5149, /* LL_MMR6 */ 5152, /* LL_R6 */ 5155, /* LSA */ 5158, /* LSA_MMR6 */ 5162, /* LSA_R6 */ 5166, /* LUI_MMR6 */ 5170, /* LUXC1 */ 5172, /* LUXC164 */ 5175, /* LUXC1_MM */ 5178, /* LUi */ 5181, /* LUi64 */ 5183, /* LUi_MM */ 5185, /* LW */ 5187, /* LW16_MM */ 5190, /* LW64 */ 5193, /* LWC1 */ 5196, /* LWC1_MM */ 5199, /* LWC2 */ 5202, /* LWC2_MMR6 */ 5205, /* LWC2_R6 */ 5208, /* LWC3 */ 5211, /* LWDSP */ 5214, /* LWDSP_MM */ 5217, /* LWE */ 5220, /* LWE_MM */ 5223, /* LWGP_MM */ 5226, /* LWL */ 5229, /* LWL64 */ 5233, /* LWLE */ 5237, /* LWLE_MM */ 5241, /* LWL_MM */ 5245, /* LWM16_MM */ 5249, /* LWM16_MMR6 */ 5252, /* LWM32_MM */ 5255, /* LWPC */ 5258, /* LWPC_MMR6 */ 5260, /* LWP_MM */ 5262, /* LWR */ 5266, /* LWR64 */ 5270, /* LWRE */ 5274, /* LWRE_MM */ 5278, /* LWR_MM */ 5282, /* LWSP_MM */ 5286, /* LWUPC */ 5289, /* LWU_MM */ 5291, /* LWX */ 5294, /* LWXC1 */ 5297, /* LWXC1_MM */ 5300, /* LWXS_MM */ 5303, /* LWX_MM */ 5306, /* LW_MM */ 5309, /* LW_MMR6 */ 5312, /* LWu */ 5315, /* LbRxRyOffMemX16 */ 5318, /* LbuRxRyOffMemX16 */ 5321, /* LhRxRyOffMemX16 */ 5324, /* LhuRxRyOffMemX16 */ 5327, /* LiRxImm16 */ 5330, /* LiRxImmAlignX16 */ 5332, /* LiRxImmX16 */ 5334, /* LwRxPcTcp16 */ 5336, /* LwRxPcTcpX16 */ 5339, /* LwRxRyOffMemX16 */ 5342, /* LwRxSpImmX16 */ 5345, /* MADD */ 5348, /* MADDF_D */ 5350, /* MADDF_D_MMR6 */ 5354, /* MADDF_S */ 5358, /* MADDF_S_MMR6 */ 5362, /* MADDR_Q_H */ 5366, /* MADDR_Q_W */ 5370, /* MADDU */ 5374, /* MADDU_DSP */ 5376, /* MADDU_DSP_MM */ 5380, /* MADDU_MM */ 5384, /* MADDV_B */ 5386, /* MADDV_D */ 5390, /* MADDV_H */ 5394, /* MADDV_W */ 5398, /* MADD_D32 */ 5402, /* MADD_D32_MM */ 5406, /* MADD_D64 */ 5410, /* MADD_DSP */ 5414, /* MADD_DSP_MM */ 5418, /* MADD_MM */ 5422, /* MADD_Q_H */ 5424, /* MADD_Q_W */ 5428, /* MADD_S */ 5432, /* MADD_S_MM */ 5436, /* MAQ_SA_W_PHL */ 5440, /* MAQ_SA_W_PHL_MM */ 5444, /* MAQ_SA_W_PHR */ 5448, /* MAQ_SA_W_PHR_MM */ 5452, /* MAQ_S_W_PHL */ 5456, /* MAQ_S_W_PHL_MM */ 5460, /* MAQ_S_W_PHR */ 5464, /* MAQ_S_W_PHR_MM */ 5468, /* MAXA_D */ 5472, /* MAXA_D_MMR6 */ 5475, /* MAXA_S */ 5478, /* MAXA_S_MMR6 */ 5481, /* MAXI_S_B */ 5484, /* MAXI_S_D */ 5487, /* MAXI_S_H */ 5490, /* MAXI_S_W */ 5493, /* MAXI_U_B */ 5496, /* MAXI_U_D */ 5499, /* MAXI_U_H */ 5502, /* MAXI_U_W */ 5505, /* MAX_A_B */ 5508, /* MAX_A_D */ 5511, /* MAX_A_H */ 5514, /* MAX_A_W */ 5517, /* MAX_D */ 5520, /* MAX_D_MMR6 */ 5523, /* MAX_S */ 5526, /* MAX_S_B */ 5529, /* MAX_S_D */ 5532, /* MAX_S_H */ 5535, /* MAX_S_MMR6 */ 5538, /* MAX_S_W */ 5541, /* MAX_U_B */ 5544, /* MAX_U_D */ 5547, /* MAX_U_H */ 5550, /* MAX_U_W */ 5553, /* MFC0 */ 5556, /* MFC0_MMR6 */ 5559, /* MFC1 */ 5562, /* MFC1_D64 */ 5564, /* MFC1_MM */ 5566, /* MFC1_MMR6 */ 5568, /* MFC2 */ 5570, /* MFC2_MMR6 */ 5573, /* MFGC0 */ 5575, /* MFGC0_MM */ 5578, /* MFHC0_MMR6 */ 5581, /* MFHC1_D32 */ 5584, /* MFHC1_D32_MM */ 5586, /* MFHC1_D64 */ 5588, /* MFHC1_D64_MM */ 5590, /* MFHC2_MMR6 */ 5592, /* MFHGC0 */ 5594, /* MFHGC0_MM */ 5597, /* MFHI */ 5600, /* MFHI16_MM */ 5601, /* MFHI64 */ 5602, /* MFHI_DSP */ 5603, /* MFHI_DSP_MM */ 5605, /* MFHI_MM */ 5607, /* MFLO */ 5608, /* MFLO16_MM */ 5609, /* MFLO64 */ 5610, /* MFLO_DSP */ 5611, /* MFLO_DSP_MM */ 5613, /* MFLO_MM */ 5615, /* MFTR */ 5616, /* MINA_D */ 5621, /* MINA_D_MMR6 */ 5624, /* MINA_S */ 5627, /* MINA_S_MMR6 */ 5630, /* MINI_S_B */ 5633, /* MINI_S_D */ 5636, /* MINI_S_H */ 5639, /* MINI_S_W */ 5642, /* MINI_U_B */ 5645, /* MINI_U_D */ 5648, /* MINI_U_H */ 5651, /* MINI_U_W */ 5654, /* MIN_A_B */ 5657, /* MIN_A_D */ 5660, /* MIN_A_H */ 5663, /* MIN_A_W */ 5666, /* MIN_D */ 5669, /* MIN_D_MMR6 */ 5672, /* MIN_S */ 5675, /* MIN_S_B */ 5678, /* MIN_S_D */ 5681, /* MIN_S_H */ 5684, /* MIN_S_MMR6 */ 5687, /* MIN_S_W */ 5690, /* MIN_U_B */ 5693, /* MIN_U_D */ 5696, /* MIN_U_H */ 5699, /* MIN_U_W */ 5702, /* MOD */ 5705, /* MODSUB */ 5708, /* MODSUB_MM */ 5711, /* MODU */ 5714, /* MODU_MMR6 */ 5717, /* MOD_MMR6 */ 5720, /* MOD_S_B */ 5723, /* MOD_S_D */ 5726, /* MOD_S_H */ 5729, /* MOD_S_W */ 5732, /* MOD_U_B */ 5735, /* MOD_U_D */ 5738, /* MOD_U_H */ 5741, /* MOD_U_W */ 5744, /* MOVE16_MM */ 5747, /* MOVE16_MMR6 */ 5749, /* MOVEP_MM */ 5751, /* MOVEP_MMR6 */ 5755, /* MOVE_V */ 5759, /* MOVF_D32 */ 5761, /* MOVF_D32_MM */ 5765, /* MOVF_D64 */ 5769, /* MOVF_I */ 5773, /* MOVF_I64 */ 5777, /* MOVF_I_MM */ 5781, /* MOVF_S */ 5785, /* MOVF_S_MM */ 5789, /* MOVN_I64_D64 */ 5793, /* MOVN_I64_I */ 5797, /* MOVN_I64_I64 */ 5801, /* MOVN_I64_S */ 5805, /* MOVN_I_D32 */ 5809, /* MOVN_I_D32_MM */ 5813, /* MOVN_I_D64 */ 5817, /* MOVN_I_I */ 5821, /* MOVN_I_I64 */ 5825, /* MOVN_I_MM */ 5829, /* MOVN_I_S */ 5833, /* MOVN_I_S_MM */ 5837, /* MOVT_D32 */ 5841, /* MOVT_D32_MM */ 5845, /* MOVT_D64 */ 5849, /* MOVT_I */ 5853, /* MOVT_I64 */ 5857, /* MOVT_I_MM */ 5861, /* MOVT_S */ 5865, /* MOVT_S_MM */ 5869, /* MOVZ_I64_D64 */ 5873, /* MOVZ_I64_I */ 5877, /* MOVZ_I64_I64 */ 5881, /* MOVZ_I64_S */ 5885, /* MOVZ_I_D32 */ 5889, /* MOVZ_I_D32_MM */ 5893, /* MOVZ_I_D64 */ 5897, /* MOVZ_I_I */ 5901, /* MOVZ_I_I64 */ 5905, /* MOVZ_I_MM */ 5909, /* MOVZ_I_S */ 5913, /* MOVZ_I_S_MM */ 5917, /* MSUB */ 5921, /* MSUBF_D */ 5923, /* MSUBF_D_MMR6 */ 5927, /* MSUBF_S */ 5931, /* MSUBF_S_MMR6 */ 5935, /* MSUBR_Q_H */ 5939, /* MSUBR_Q_W */ 5943, /* MSUBU */ 5947, /* MSUBU_DSP */ 5949, /* MSUBU_DSP_MM */ 5953, /* MSUBU_MM */ 5957, /* MSUBV_B */ 5959, /* MSUBV_D */ 5963, /* MSUBV_H */ 5967, /* MSUBV_W */ 5971, /* MSUB_D32 */ 5975, /* MSUB_D32_MM */ 5979, /* MSUB_D64 */ 5983, /* MSUB_DSP */ 5987, /* MSUB_DSP_MM */ 5991, /* MSUB_MM */ 5995, /* MSUB_Q_H */ 5997, /* MSUB_Q_W */ 6001, /* MSUB_S */ 6005, /* MSUB_S_MM */ 6009, /* MTC0 */ 6013, /* MTC0_MMR6 */ 6016, /* MTC1 */ 6019, /* MTC1_D64 */ 6021, /* MTC1_D64_MM */ 6023, /* MTC1_MM */ 6025, /* MTC1_MMR6 */ 6027, /* MTC2 */ 6029, /* MTC2_MMR6 */ 6032, /* MTGC0 */ 6034, /* MTGC0_MM */ 6037, /* MTHC0_MMR6 */ 6040, /* MTHC1_D32 */ 6043, /* MTHC1_D32_MM */ 6046, /* MTHC1_D64 */ 6049, /* MTHC1_D64_MM */ 6052, /* MTHC2_MMR6 */ 6055, /* MTHGC0 */ 6057, /* MTHGC0_MM */ 6060, /* MTHI */ 6063, /* MTHI64 */ 6064, /* MTHI_DSP */ 6065, /* MTHI_DSP_MM */ 6067, /* MTHI_MM */ 6069, /* MTHLIP */ 6070, /* MTHLIP_MM */ 6073, /* MTLO */ 6076, /* MTLO64 */ 6077, /* MTLO_DSP */ 6078, /* MTLO_DSP_MM */ 6080, /* MTLO_MM */ 6082, /* MTM0 */ 6083, /* MTM1 */ 6084, /* MTM2 */ 6085, /* MTP0 */ 6086, /* MTP1 */ 6087, /* MTP2 */ 6088, /* MTTR */ 6089, /* MUH */ 6094, /* MUHU */ 6097, /* MUHU_MMR6 */ 6100, /* MUH_MMR6 */ 6103, /* MUL */ 6106, /* MULEQ_S_W_PHL */ 6109, /* MULEQ_S_W_PHL_MM */ 6112, /* MULEQ_S_W_PHR */ 6115, /* MULEQ_S_W_PHR_MM */ 6118, /* MULEU_S_PH_QBL */ 6121, /* MULEU_S_PH_QBL_MM */ 6124, /* MULEU_S_PH_QBR */ 6127, /* MULEU_S_PH_QBR_MM */ 6130, /* MULQ_RS_PH */ 6133, /* MULQ_RS_PH_MM */ 6136, /* MULQ_RS_W */ 6139, /* MULQ_RS_W_MMR2 */ 6142, /* MULQ_S_PH */ 6145, /* MULQ_S_PH_MMR2 */ 6148, /* MULQ_S_W */ 6151, /* MULQ_S_W_MMR2 */ 6154, /* MULR_PS64 */ 6157, /* MULR_Q_H */ 6160, /* MULR_Q_W */ 6163, /* MULSAQ_S_W_PH */ 6166, /* MULSAQ_S_W_PH_MM */ 6170, /* MULSA_W_PH */ 6174, /* MULSA_W_PH_MMR2 */ 6178, /* MULT */ 6182, /* MULTU_DSP */ 6184, /* MULTU_DSP_MM */ 6187, /* MULT_DSP */ 6190, /* MULT_DSP_MM */ 6193, /* MULT_MM */ 6196, /* MULTu */ 6198, /* MULTu_MM */ 6200, /* MULU */ 6202, /* MULU_MMR6 */ 6205, /* MULV_B */ 6208, /* MULV_D */ 6211, /* MULV_H */ 6214, /* MULV_W */ 6217, /* MUL_MM */ 6220, /* MUL_MMR6 */ 6223, /* MUL_PH */ 6226, /* MUL_PH_MMR2 */ 6229, /* MUL_Q_H */ 6232, /* MUL_Q_W */ 6235, /* MUL_R6 */ 6238, /* MUL_S_PH */ 6241, /* MUL_S_PH_MMR2 */ 6244, /* Mfhi16 */ 6247, /* Mflo16 */ 6248, /* Move32R16 */ 6249, /* MoveR3216 */ 6251, /* NLOC_B */ 6253, /* NLOC_D */ 6255, /* NLOC_H */ 6257, /* NLOC_W */ 6259, /* NLZC_B */ 6261, /* NLZC_D */ 6263, /* NLZC_H */ 6265, /* NLZC_W */ 6267, /* NMADD_D32 */ 6269, /* NMADD_D32_MM */ 6273, /* NMADD_D64 */ 6277, /* NMADD_S */ 6281, /* NMADD_S_MM */ 6285, /* NMSUB_D32 */ 6289, /* NMSUB_D32_MM */ 6293, /* NMSUB_D64 */ 6297, /* NMSUB_S */ 6301, /* NMSUB_S_MM */ 6305, /* NOR */ 6309, /* NOR64 */ 6312, /* NORI_B */ 6315, /* NOR_MM */ 6318, /* NOR_MMR6 */ 6321, /* NOR_V */ 6324, /* NOT16_MM */ 6327, /* NOT16_MMR6 */ 6329, /* NegRxRy16 */ 6331, /* NotRxRy16 */ 6333, /* OR */ 6335, /* OR16_MM */ 6338, /* OR16_MMR6 */ 6341, /* OR64 */ 6344, /* ORI_B */ 6347, /* ORI_MMR6 */ 6350, /* OR_MM */ 6353, /* OR_MMR6 */ 6356, /* OR_V */ 6359, /* ORi */ 6362, /* ORi64 */ 6365, /* ORi_MM */ 6368, /* OrRxRxRy16 */ 6371, /* PACKRL_PH */ 6374, /* PACKRL_PH_MM */ 6377, /* PAUSE */ 6380, /* PAUSE_MM */ 6380, /* PAUSE_MMR6 */ 6380, /* PCKEV_B */ 6380, /* PCKEV_D */ 6383, /* PCKEV_H */ 6386, /* PCKEV_W */ 6389, /* PCKOD_B */ 6392, /* PCKOD_D */ 6395, /* PCKOD_H */ 6398, /* PCKOD_W */ 6401, /* PCNT_B */ 6404, /* PCNT_D */ 6406, /* PCNT_H */ 6408, /* PCNT_W */ 6410, /* PICK_PH */ 6412, /* PICK_PH_MM */ 6415, /* PICK_QB */ 6418, /* PICK_QB_MM */ 6421, /* PLL_PS64 */ 6424, /* PLU_PS64 */ 6427, /* POP */ 6430, /* PRECEQU_PH_QBL */ 6432, /* PRECEQU_PH_QBLA */ 6434, /* PRECEQU_PH_QBLA_MM */ 6436, /* PRECEQU_PH_QBL_MM */ 6438, /* PRECEQU_PH_QBR */ 6440, /* PRECEQU_PH_QBRA */ 6442, /* PRECEQU_PH_QBRA_MM */ 6444, /* PRECEQU_PH_QBR_MM */ 6446, /* PRECEQ_W_PHL */ 6448, /* PRECEQ_W_PHL_MM */ 6450, /* PRECEQ_W_PHR */ 6452, /* PRECEQ_W_PHR_MM */ 6454, /* PRECEU_PH_QBL */ 6456, /* PRECEU_PH_QBLA */ 6458, /* PRECEU_PH_QBLA_MM */ 6460, /* PRECEU_PH_QBL_MM */ 6462, /* PRECEU_PH_QBR */ 6464, /* PRECEU_PH_QBRA */ 6466, /* PRECEU_PH_QBRA_MM */ 6468, /* PRECEU_PH_QBR_MM */ 6470, /* PRECRQU_S_QB_PH */ 6472, /* PRECRQU_S_QB_PH_MM */ 6475, /* PRECRQ_PH_W */ 6478, /* PRECRQ_PH_W_MM */ 6481, /* PRECRQ_QB_PH */ 6484, /* PRECRQ_QB_PH_MM */ 6487, /* PRECRQ_RS_PH_W */ 6490, /* PRECRQ_RS_PH_W_MM */ 6493, /* PRECR_QB_PH */ 6496, /* PRECR_QB_PH_MMR2 */ 6499, /* PRECR_SRA_PH_W */ 6502, /* PRECR_SRA_PH_W_MMR2 */ 6506, /* PRECR_SRA_R_PH_W */ 6510, /* PRECR_SRA_R_PH_W_MMR2 */ 6514, /* PREF */ 6518, /* PREFE */ 6521, /* PREFE_MM */ 6524, /* PREFX_MM */ 6527, /* PREF_MM */ 6530, /* PREF_MMR6 */ 6533, /* PREF_R6 */ 6536, /* PREPEND */ 6539, /* PREPEND_MMR2 */ 6543, /* PUL_PS64 */ 6547, /* PUU_PS64 */ 6550, /* RADDU_W_QB */ 6553, /* RADDU_W_QB_MM */ 6555, /* RDDSP */ 6557, /* RDDSP_MM */ 6559, /* RDHWR */ 6561, /* RDHWR64 */ 6564, /* RDHWR_MM */ 6567, /* RDHWR_MMR6 */ 6570, /* RDPGPR_MMR6 */ 6573, /* RECIP_D32 */ 6575, /* RECIP_D32_MM */ 6577, /* RECIP_D64 */ 6579, /* RECIP_D64_MM */ 6581, /* RECIP_S */ 6583, /* RECIP_S_MM */ 6585, /* REPLV_PH */ 6587, /* REPLV_PH_MM */ 6589, /* REPLV_QB */ 6591, /* REPLV_QB_MM */ 6593, /* REPL_PH */ 6595, /* REPL_PH_MM */ 6597, /* REPL_QB */ 6599, /* REPL_QB_MM */ 6601, /* RINT_D */ 6603, /* RINT_D_MMR6 */ 6605, /* RINT_S */ 6607, /* RINT_S_MMR6 */ 6609, /* ROTR */ 6611, /* ROTRV */ 6614, /* ROTRV_MM */ 6617, /* ROTR_MM */ 6620, /* ROUND_L_D64 */ 6623, /* ROUND_L_D_MMR6 */ 6625, /* ROUND_L_S */ 6627, /* ROUND_L_S_MMR6 */ 6629, /* ROUND_W_D32 */ 6631, /* ROUND_W_D64 */ 6633, /* ROUND_W_D_MMR6 */ 6635, /* ROUND_W_MM */ 6637, /* ROUND_W_S */ 6639, /* ROUND_W_S_MM */ 6641, /* ROUND_W_S_MMR6 */ 6643, /* RSQRT_D32 */ 6645, /* RSQRT_D32_MM */ 6647, /* RSQRT_D64 */ 6649, /* RSQRT_D64_MM */ 6651, /* RSQRT_S */ 6653, /* RSQRT_S_MM */ 6655, /* Restore16 */ 6657, /* RestoreX16 */ 6657, /* SAA */ 6657, /* SAAD */ 6659, /* SAT_S_B */ 6661, /* SAT_S_D */ 6664, /* SAT_S_H */ 6667, /* SAT_S_W */ 6670, /* SAT_U_B */ 6673, /* SAT_U_D */ 6676, /* SAT_U_H */ 6679, /* SAT_U_W */ 6682, /* SB */ 6685, /* SB16_MM */ 6688, /* SB16_MMR6 */ 6691, /* SB64 */ 6694, /* SBE */ 6697, /* SBE_MM */ 6700, /* SB_MM */ 6703, /* SB_MMR6 */ 6706, /* SC */ 6709, /* SC64 */ 6713, /* SC64_R6 */ 6717, /* SCD */ 6721, /* SCD_R6 */ 6725, /* SCE */ 6729, /* SCE_MM */ 6733, /* SC_MM */ 6737, /* SC_MMR6 */ 6741, /* SC_R6 */ 6745, /* SD */ 6749, /* SDBBP */ 6752, /* SDBBP16_MM */ 6753, /* SDBBP16_MMR6 */ 6754, /* SDBBP_MM */ 6755, /* SDBBP_MMR6 */ 6756, /* SDBBP_R6 */ 6757, /* SDC1 */ 6758, /* SDC164 */ 6761, /* SDC1_D64_MMR6 */ 6764, /* SDC1_MM_D32 */ 6767, /* SDC1_MM_D64 */ 6770, /* SDC2 */ 6773, /* SDC2_MMR6 */ 6776, /* SDC2_R6 */ 6779, /* SDC3 */ 6782, /* SDIV */ 6785, /* SDIV_MM */ 6787, /* SDL */ 6789, /* SDR */ 6792, /* SDXC1 */ 6795, /* SDXC164 */ 6798, /* SEB */ 6801, /* SEB64 */ 6803, /* SEB_MM */ 6805, /* SEH */ 6807, /* SEH64 */ 6809, /* SEH_MM */ 6811, /* SELEQZ */ 6813, /* SELEQZ64 */ 6816, /* SELEQZ_D */ 6819, /* SELEQZ_D_MMR6 */ 6822, /* SELEQZ_MMR6 */ 6825, /* SELEQZ_S */ 6828, /* SELEQZ_S_MMR6 */ 6831, /* SELNEZ */ 6834, /* SELNEZ64 */ 6837, /* SELNEZ_D */ 6840, /* SELNEZ_D_MMR6 */ 6843, /* SELNEZ_MMR6 */ 6846, /* SELNEZ_S */ 6849, /* SELNEZ_S_MMR6 */ 6852, /* SEL_D */ 6855, /* SEL_D_MMR6 */ 6859, /* SEL_S */ 6863, /* SEL_S_MMR6 */ 6867, /* SEQ */ 6871, /* SEQi */ 6874, /* SH */ 6877, /* SH16_MM */ 6880, /* SH16_MMR6 */ 6883, /* SH64 */ 6886, /* SHE */ 6889, /* SHE_MM */ 6892, /* SHF_B */ 6895, /* SHF_H */ 6898, /* SHF_W */ 6901, /* SHILO */ 6904, /* SHILOV */ 6907, /* SHILOV_MM */ 6910, /* SHILO_MM */ 6913, /* SHLLV_PH */ 6916, /* SHLLV_PH_MM */ 6919, /* SHLLV_QB */ 6922, /* SHLLV_QB_MM */ 6925, /* SHLLV_S_PH */ 6928, /* SHLLV_S_PH_MM */ 6931, /* SHLLV_S_W */ 6934, /* SHLLV_S_W_MM */ 6937, /* SHLL_PH */ 6940, /* SHLL_PH_MM */ 6943, /* SHLL_QB */ 6946, /* SHLL_QB_MM */ 6949, /* SHLL_S_PH */ 6952, /* SHLL_S_PH_MM */ 6955, /* SHLL_S_W */ 6958, /* SHLL_S_W_MM */ 6961, /* SHRAV_PH */ 6964, /* SHRAV_PH_MM */ 6967, /* SHRAV_QB */ 6970, /* SHRAV_QB_MMR2 */ 6973, /* SHRAV_R_PH */ 6976, /* SHRAV_R_PH_MM */ 6979, /* SHRAV_R_QB */ 6982, /* SHRAV_R_QB_MMR2 */ 6985, /* SHRAV_R_W */ 6988, /* SHRAV_R_W_MM */ 6991, /* SHRA_PH */ 6994, /* SHRA_PH_MM */ 6997, /* SHRA_QB */ 7000, /* SHRA_QB_MMR2 */ 7003, /* SHRA_R_PH */ 7006, /* SHRA_R_PH_MM */ 7009, /* SHRA_R_QB */ 7012, /* SHRA_R_QB_MMR2 */ 7015, /* SHRA_R_W */ 7018, /* SHRA_R_W_MM */ 7021, /* SHRLV_PH */ 7024, /* SHRLV_PH_MMR2 */ 7027, /* SHRLV_QB */ 7030, /* SHRLV_QB_MM */ 7033, /* SHRL_PH */ 7036, /* SHRL_PH_MMR2 */ 7039, /* SHRL_QB */ 7042, /* SHRL_QB_MM */ 7045, /* SH_MM */ 7048, /* SH_MMR6 */ 7051, /* SIGRIE */ 7054, /* SIGRIE_MMR6 */ 7055, /* SLDI_B */ 7056, /* SLDI_D */ 7060, /* SLDI_H */ 7064, /* SLDI_W */ 7068, /* SLD_B */ 7072, /* SLD_D */ 7076, /* SLD_H */ 7080, /* SLD_W */ 7084, /* SLL */ 7088, /* SLL16_MM */ 7091, /* SLL16_MMR6 */ 7094, /* SLL64_32 */ 7097, /* SLL64_64 */ 7099, /* SLLI_B */ 7101, /* SLLI_D */ 7104, /* SLLI_H */ 7107, /* SLLI_W */ 7110, /* SLLV */ 7113, /* SLLV_MM */ 7116, /* SLL_B */ 7119, /* SLL_D */ 7122, /* SLL_H */ 7125, /* SLL_MM */ 7128, /* SLL_MMR6 */ 7131, /* SLL_W */ 7134, /* SLT */ 7137, /* SLT64 */ 7140, /* SLT_MM */ 7143, /* SLTi */ 7146, /* SLTi64 */ 7149, /* SLTi_MM */ 7152, /* SLTiu */ 7155, /* SLTiu64 */ 7158, /* SLTiu_MM */ 7161, /* SLTu */ 7164, /* SLTu64 */ 7167, /* SLTu_MM */ 7170, /* SNE */ 7173, /* SNEi */ 7176, /* SPLATI_B */ 7179, /* SPLATI_D */ 7182, /* SPLATI_H */ 7185, /* SPLATI_W */ 7188, /* SPLAT_B */ 7191, /* SPLAT_D */ 7194, /* SPLAT_H */ 7197, /* SPLAT_W */ 7200, /* SRA */ 7203, /* SRAI_B */ 7206, /* SRAI_D */ 7209, /* SRAI_H */ 7212, /* SRAI_W */ 7215, /* SRARI_B */ 7218, /* SRARI_D */ 7221, /* SRARI_H */ 7224, /* SRARI_W */ 7227, /* SRAR_B */ 7230, /* SRAR_D */ 7233, /* SRAR_H */ 7236, /* SRAR_W */ 7239, /* SRAV */ 7242, /* SRAV_MM */ 7245, /* SRA_B */ 7248, /* SRA_D */ 7251, /* SRA_H */ 7254, /* SRA_MM */ 7257, /* SRA_W */ 7260, /* SRL */ 7263, /* SRL16_MM */ 7266, /* SRL16_MMR6 */ 7269, /* SRLI_B */ 7272, /* SRLI_D */ 7275, /* SRLI_H */ 7278, /* SRLI_W */ 7281, /* SRLRI_B */ 7284, /* SRLRI_D */ 7287, /* SRLRI_H */ 7290, /* SRLRI_W */ 7293, /* SRLR_B */ 7296, /* SRLR_D */ 7299, /* SRLR_H */ 7302, /* SRLR_W */ 7305, /* SRLV */ 7308, /* SRLV_MM */ 7311, /* SRL_B */ 7314, /* SRL_D */ 7317, /* SRL_H */ 7320, /* SRL_MM */ 7323, /* SRL_W */ 7326, /* SSNOP */ 7329, /* SSNOP_MM */ 7329, /* SSNOP_MMR6 */ 7329, /* ST_B */ 7329, /* ST_D */ 7332, /* ST_H */ 7335, /* ST_W */ 7338, /* SUB */ 7341, /* SUBQH_PH */ 7344, /* SUBQH_PH_MMR2 */ 7347, /* SUBQH_R_PH */ 7350, /* SUBQH_R_PH_MMR2 */ 7353, /* SUBQH_R_W */ 7356, /* SUBQH_R_W_MMR2 */ 7359, /* SUBQH_W */ 7362, /* SUBQH_W_MMR2 */ 7365, /* SUBQ_PH */ 7368, /* SUBQ_PH_MM */ 7371, /* SUBQ_S_PH */ 7374, /* SUBQ_S_PH_MM */ 7377, /* SUBQ_S_W */ 7380, /* SUBQ_S_W_MM */ 7383, /* SUBSUS_U_B */ 7386, /* SUBSUS_U_D */ 7389, /* SUBSUS_U_H */ 7392, /* SUBSUS_U_W */ 7395, /* SUBSUU_S_B */ 7398, /* SUBSUU_S_D */ 7401, /* SUBSUU_S_H */ 7404, /* SUBSUU_S_W */ 7407, /* SUBS_S_B */ 7410, /* SUBS_S_D */ 7413, /* SUBS_S_H */ 7416, /* SUBS_S_W */ 7419, /* SUBS_U_B */ 7422, /* SUBS_U_D */ 7425, /* SUBS_U_H */ 7428, /* SUBS_U_W */ 7431, /* SUBU16_MM */ 7434, /* SUBU16_MMR6 */ 7437, /* SUBUH_QB */ 7440, /* SUBUH_QB_MMR2 */ 7443, /* SUBUH_R_QB */ 7446, /* SUBUH_R_QB_MMR2 */ 7449, /* SUBU_MMR6 */ 7452, /* SUBU_PH */ 7455, /* SUBU_PH_MMR2 */ 7458, /* SUBU_QB */ 7461, /* SUBU_QB_MM */ 7464, /* SUBU_S_PH */ 7467, /* SUBU_S_PH_MMR2 */ 7470, /* SUBU_S_QB */ 7473, /* SUBU_S_QB_MM */ 7476, /* SUBVI_B */ 7479, /* SUBVI_D */ 7482, /* SUBVI_H */ 7485, /* SUBVI_W */ 7488, /* SUBV_B */ 7491, /* SUBV_D */ 7494, /* SUBV_H */ 7497, /* SUBV_W */ 7500, /* SUB_MM */ 7503, /* SUB_MMR6 */ 7506, /* SUBu */ 7509, /* SUBu_MM */ 7512, /* SUXC1 */ 7515, /* SUXC164 */ 7518, /* SUXC1_MM */ 7521, /* SW */ 7524, /* SW16_MM */ 7527, /* SW16_MMR6 */ 7530, /* SW64 */ 7533, /* SWC1 */ 7536, /* SWC1_MM */ 7539, /* SWC2 */ 7542, /* SWC2_MMR6 */ 7545, /* SWC2_R6 */ 7548, /* SWC3 */ 7551, /* SWDSP */ 7554, /* SWDSP_MM */ 7557, /* SWE */ 7560, /* SWE_MM */ 7563, /* SWL */ 7566, /* SWL64 */ 7569, /* SWLE */ 7572, /* SWLE_MM */ 7575, /* SWL_MM */ 7578, /* SWM16_MM */ 7581, /* SWM16_MMR6 */ 7584, /* SWM32_MM */ 7587, /* SWP_MM */ 7590, /* SWR */ 7594, /* SWR64 */ 7597, /* SWRE */ 7600, /* SWRE_MM */ 7603, /* SWR_MM */ 7606, /* SWSP_MM */ 7609, /* SWSP_MMR6 */ 7612, /* SWXC1 */ 7615, /* SWXC1_MM */ 7618, /* SW_MM */ 7621, /* SW_MMR6 */ 7624, /* SYNC */ 7627, /* SYNCI */ 7628, /* SYNCI_MM */ 7630, /* SYNCI_MMR6 */ 7632, /* SYNC_MM */ 7634, /* SYNC_MMR6 */ 7635, /* SYSCALL */ 7636, /* SYSCALL_MM */ 7637, /* Save16 */ 7638, /* SaveX16 */ 7638, /* SbRxRyOffMemX16 */ 7638, /* SebRx16 */ 7641, /* SehRx16 */ 7643, /* ShRxRyOffMemX16 */ 7645, /* SllX16 */ 7648, /* SllvRxRy16 */ 7651, /* SltRxRy16 */ 7654, /* SltiRxImm16 */ 7656, /* SltiRxImmX16 */ 7658, /* SltiuRxImm16 */ 7660, /* SltiuRxImmX16 */ 7662, /* SltuRxRy16 */ 7664, /* SraX16 */ 7666, /* SravRxRy16 */ 7669, /* SrlX16 */ 7672, /* SrlvRxRy16 */ 7675, /* SubuRxRyRz16 */ 7678, /* SwRxRyOffMemX16 */ 7681, /* SwRxSpImmX16 */ 7684, /* TEQ */ 7687, /* TEQI */ 7690, /* TEQI_MM */ 7692, /* TEQ_MM */ 7694, /* TGE */ 7697, /* TGEI */ 7700, /* TGEIU */ 7702, /* TGEIU_MM */ 7704, /* TGEI_MM */ 7706, /* TGEU */ 7708, /* TGEU_MM */ 7711, /* TGE_MM */ 7714, /* TLBGINV */ 7717, /* TLBGINVF */ 7717, /* TLBGINVF_MM */ 7717, /* TLBGINV_MM */ 7717, /* TLBGP */ 7717, /* TLBGP_MM */ 7717, /* TLBGR */ 7717, /* TLBGR_MM */ 7717, /* TLBGWI */ 7717, /* TLBGWI_MM */ 7717, /* TLBGWR */ 7717, /* TLBGWR_MM */ 7717, /* TLBINV */ 7717, /* TLBINVF */ 7717, /* TLBINVF_MMR6 */ 7717, /* TLBINV_MMR6 */ 7717, /* TLBP */ 7717, /* TLBP_MM */ 7717, /* TLBR */ 7717, /* TLBR_MM */ 7717, /* TLBWI */ 7717, /* TLBWI_MM */ 7717, /* TLBWR */ 7717, /* TLBWR_MM */ 7717, /* TLT */ 7717, /* TLTI */ 7720, /* TLTIU_MM */ 7722, /* TLTI_MM */ 7724, /* TLTU */ 7726, /* TLTU_MM */ 7729, /* TLT_MM */ 7732, /* TNE */ 7735, /* TNEI */ 7738, /* TNEI_MM */ 7740, /* TNE_MM */ 7742, /* TRUNC_L_D64 */ 7745, /* TRUNC_L_D_MMR6 */ 7747, /* TRUNC_L_S */ 7749, /* TRUNC_L_S_MMR6 */ 7751, /* TRUNC_W_D32 */ 7753, /* TRUNC_W_D64 */ 7755, /* TRUNC_W_D_MMR6 */ 7757, /* TRUNC_W_MM */ 7759, /* TRUNC_W_S */ 7761, /* TRUNC_W_S_MM */ 7763, /* TRUNC_W_S_MMR6 */ 7765, /* TTLTIU */ 7767, /* UDIV */ 7769, /* UDIV_MM */ 7771, /* V3MULU */ 7773, /* VMM0 */ 7776, /* VMULU */ 7779, /* VSHF_B */ 7782, /* VSHF_D */ 7786, /* VSHF_H */ 7790, /* VSHF_W */ 7794, /* WAIT */ 7798, /* WAIT_MM */ 7798, /* WAIT_MMR6 */ 7799, /* WRDSP */ 7800, /* WRDSP_MM */ 7802, /* WRPGPR_MMR6 */ 7804, /* WSBH */ 7806, /* WSBH_MM */ 7808, /* WSBH_MMR6 */ 7810, /* XOR */ 7812, /* XOR16_MM */ 7815, /* XOR16_MMR6 */ 7818, /* XOR64 */ 7821, /* XORI_B */ 7824, /* XORI_MMR6 */ 7827, /* XOR_MM */ 7830, /* XOR_MMR6 */ 7833, /* XOR_V */ 7836, /* XORi */ 7839, /* XORi64 */ 7842, /* XORi_MM */ 7845, /* XorRxRxRy16 */ 7848, /* YIELD */ 7851, }; using namespace OpTypes; const int16_t OpcodeOperandTypes[] = { /* PHI */ -1, /* INLINEASM */ /* INLINEASM_BR */ /* CFI_INSTRUCTION */ i32imm, /* EH_LABEL */ i32imm, /* GC_LABEL */ i32imm, /* ANNOTATION_LABEL */ i32imm, /* KILL */ /* EXTRACT_SUBREG */ -1, -1, i32imm, /* INSERT_SUBREG */ -1, -1, -1, i32imm, /* IMPLICIT_DEF */ -1, /* SUBREG_TO_REG */ -1, -1, -1, i32imm, /* COPY_TO_REGCLASS */ -1, -1, i32imm, /* DBG_VALUE */ /* DBG_VALUE_LIST */ /* DBG_INSTR_REF */ /* DBG_PHI */ /* DBG_LABEL */ -1, /* REG_SEQUENCE */ -1, -1, /* COPY */ -1, -1, /* BUNDLE */ /* LIFETIME_START */ i32imm, /* LIFETIME_END */ i32imm, /* PSEUDO_PROBE */ i64imm, i64imm, i8imm, i32imm, /* ARITH_FENCE */ -1, -1, /* STACKMAP */ i64imm, i32imm, /* FENTRY_CALL */ /* PATCHPOINT */ -1, i64imm, i32imm, -1, i32imm, i32imm, /* LOAD_STACK_GUARD */ -1, /* PREALLOCATED_SETUP */ i32imm, /* PREALLOCATED_ARG */ -1, i32imm, i32imm, /* STATEPOINT */ /* LOCAL_ESCAPE */ -1, i32imm, /* FAULTING_OP */ -1, /* PATCHABLE_OP */ /* PATCHABLE_FUNCTION_ENTER */ /* PATCHABLE_RET */ /* PATCHABLE_FUNCTION_EXIT */ /* PATCHABLE_TAIL_CALL */ /* PATCHABLE_EVENT_CALL */ -1, -1, /* PATCHABLE_TYPED_EVENT_CALL */ -1, -1, -1, /* ICALL_BRANCH_FUNNEL */ /* MEMBARRIER */ /* G_ASSERT_SEXT */ type0, type0, untyped_imm_0, /* G_ASSERT_ZEXT */ type0, type0, untyped_imm_0, /* G_ASSERT_ALIGN */ type0, type0, untyped_imm_0, /* G_ADD */ type0, type0, type0, /* G_SUB */ type0, type0, type0, /* G_MUL */ type0, type0, type0, /* G_SDIV */ type0, type0, type0, /* G_UDIV */ type0, type0, type0, /* G_SREM */ type0, type0, type0, /* G_UREM */ type0, type0, type0, /* G_SDIVREM */ type0, type0, type0, type0, /* G_UDIVREM */ type0, type0, type0, type0, /* G_AND */ type0, type0, type0, /* G_OR */ type0, type0, type0, /* G_XOR */ type0, type0, type0, /* G_IMPLICIT_DEF */ type0, /* G_PHI */ type0, /* G_FRAME_INDEX */ type0, -1, /* G_GLOBAL_VALUE */ type0, -1, /* G_EXTRACT */ type0, type1, untyped_imm_0, /* G_UNMERGE_VALUES */ type0, type1, /* G_INSERT */ type0, type0, type1, untyped_imm_0, /* G_MERGE_VALUES */ type0, type1, /* G_BUILD_VECTOR */ type0, type1, /* G_BUILD_VECTOR_TRUNC */ type0, type1, /* G_CONCAT_VECTORS */ type0, type1, /* G_PTRTOINT */ type0, type1, /* G_INTTOPTR */ type0, type1, /* G_BITCAST */ type0, type1, /* G_FREEZE */ type0, type0, /* G_INTRINSIC_FPTRUNC_ROUND */ type0, type1, i32imm, /* G_INTRINSIC_TRUNC */ type0, type0, /* G_INTRINSIC_ROUND */ type0, type0, /* G_INTRINSIC_LRINT */ type0, type1, /* G_INTRINSIC_ROUNDEVEN */ type0, type0, /* G_READCYCLECOUNTER */ type0, /* G_LOAD */ type0, ptype1, /* G_SEXTLOAD */ type0, ptype1, /* G_ZEXTLOAD */ type0, ptype1, /* G_INDEXED_LOAD */ type0, ptype1, ptype1, type2, -1, /* G_INDEXED_SEXTLOAD */ type0, ptype1, ptype1, type2, -1, /* G_INDEXED_ZEXTLOAD */ type0, ptype1, ptype1, type2, -1, /* G_STORE */ type0, ptype1, /* G_INDEXED_STORE */ ptype0, type1, ptype0, ptype2, -1, /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ type0, type1, type2, type0, type0, /* G_ATOMIC_CMPXCHG */ type0, ptype1, type0, type0, /* G_ATOMICRMW_XCHG */ type0, ptype1, type0, /* G_ATOMICRMW_ADD */ type0, ptype1, type0, /* G_ATOMICRMW_SUB */ type0, ptype1, type0, /* G_ATOMICRMW_AND */ type0, ptype1, type0, /* G_ATOMICRMW_NAND */ type0, ptype1, type0, /* G_ATOMICRMW_OR */ type0, ptype1, type0, /* G_ATOMICRMW_XOR */ type0, ptype1, type0, /* G_ATOMICRMW_MAX */ type0, ptype1, type0, /* G_ATOMICRMW_MIN */ type0, ptype1, type0, /* G_ATOMICRMW_UMAX */ type0, ptype1, type0, /* G_ATOMICRMW_UMIN */ type0, ptype1, type0, /* G_ATOMICRMW_FADD */ type0, ptype1, type0, /* G_ATOMICRMW_FSUB */ type0, ptype1, type0, /* G_ATOMICRMW_FMAX */ type0, ptype1, type0, /* G_ATOMICRMW_FMIN */ type0, ptype1, type0, /* G_ATOMICRMW_UINC_WRAP */ type0, ptype1, type0, /* G_ATOMICRMW_UDEC_WRAP */ type0, ptype1, type0, /* G_FENCE */ i32imm, i32imm, /* G_BRCOND */ type0, -1, /* G_BRINDIRECT */ type0, /* G_INVOKE_REGION_START */ /* G_INTRINSIC */ -1, /* G_INTRINSIC_W_SIDE_EFFECTS */ -1, /* G_ANYEXT */ type0, type1, /* G_TRUNC */ type0, type1, /* G_CONSTANT */ type0, -1, /* G_FCONSTANT */ type0, -1, /* G_VASTART */ type0, /* G_VAARG */ type0, type1, -1, /* G_SEXT */ type0, type1, /* G_SEXT_INREG */ type0, type0, untyped_imm_0, /* G_ZEXT */ type0, type1, /* G_SHL */ type0, type0, type1, /* G_LSHR */ type0, type0, type1, /* G_ASHR */ type0, type0, type1, /* G_FSHL */ type0, type0, type0, type1, /* G_FSHR */ type0, type0, type0, type1, /* G_ROTR */ type0, type0, type1, /* G_ROTL */ type0, type0, type1, /* G_ICMP */ type0, -1, type1, type1, /* G_FCMP */ type0, -1, type1, type1, /* G_SELECT */ type0, type1, type0, type0, /* G_UADDO */ type0, type1, type0, type0, /* G_UADDE */ type0, type1, type0, type0, type1, /* G_USUBO */ type0, type1, type0, type0, /* G_USUBE */ type0, type1, type0, type0, type1, /* G_SADDO */ type0, type1, type0, type0, /* G_SADDE */ type0, type1, type0, type0, type1, /* G_SSUBO */ type0, type1, type0, type0, /* G_SSUBE */ type0, type1, type0, type0, type1, /* G_UMULO */ type0, type1, type0, type0, /* G_SMULO */ type0, type1, type0, type0, /* G_UMULH */ type0, type0, type0, /* G_SMULH */ type0, type0, type0, /* G_UADDSAT */ type0, type0, type0, /* G_SADDSAT */ type0, type0, type0, /* G_USUBSAT */ type0, type0, type0, /* G_SSUBSAT */ type0, type0, type0, /* G_USHLSAT */ type0, type0, type1, /* G_SSHLSAT */ type0, type0, type1, /* G_SMULFIX */ type0, type0, type0, untyped_imm_0, /* G_UMULFIX */ type0, type0, type0, untyped_imm_0, /* G_SMULFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_UMULFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_SDIVFIX */ type0, type0, type0, untyped_imm_0, /* G_UDIVFIX */ type0, type0, type0, untyped_imm_0, /* G_SDIVFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_UDIVFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_FADD */ type0, type0, type0, /* G_FSUB */ type0, type0, type0, /* G_FMUL */ type0, type0, type0, /* G_FMA */ type0, type0, type0, type0, /* G_FMAD */ type0, type0, type0, type0, /* G_FDIV */ type0, type0, type0, /* G_FREM */ type0, type0, type0, /* G_FPOW */ type0, type0, type0, /* G_FPOWI */ type0, type0, type1, /* G_FEXP */ type0, type0, /* G_FEXP2 */ type0, type0, /* G_FLOG */ type0, type0, /* G_FLOG2 */ type0, type0, /* G_FLOG10 */ type0, type0, /* G_FNEG */ type0, type0, /* G_FPEXT */ type0, type1, /* G_FPTRUNC */ type0, type1, /* G_FPTOSI */ type0, type1, /* G_FPTOUI */ type0, type1, /* G_SITOFP */ type0, type1, /* G_UITOFP */ type0, type1, /* G_FABS */ type0, type0, /* G_FCOPYSIGN */ type0, type0, type1, /* G_IS_FPCLASS */ type0, type1, -1, /* G_FCANONICALIZE */ type0, type0, /* G_FMINNUM */ type0, type0, type0, /* G_FMAXNUM */ type0, type0, type0, /* G_FMINNUM_IEEE */ type0, type0, type0, /* G_FMAXNUM_IEEE */ type0, type0, type0, /* G_FMINIMUM */ type0, type0, type0, /* G_FMAXIMUM */ type0, type0, type0, /* G_PTR_ADD */ ptype0, ptype0, type1, /* G_PTRMASK */ ptype0, ptype0, type1, /* G_SMIN */ type0, type0, type0, /* G_SMAX */ type0, type0, type0, /* G_UMIN */ type0, type0, type0, /* G_UMAX */ type0, type0, type0, /* G_ABS */ type0, type0, /* G_LROUND */ type0, type1, /* G_LLROUND */ type0, type1, /* G_BR */ -1, /* G_BRJT */ ptype0, -1, type1, /* G_INSERT_VECTOR_ELT */ type0, type0, type1, type2, /* G_EXTRACT_VECTOR_ELT */ type0, type1, type2, /* G_SHUFFLE_VECTOR */ type0, type1, type1, -1, /* G_CTTZ */ type0, type1, /* G_CTTZ_ZERO_UNDEF */ type0, type1, /* G_CTLZ */ type0, type1, /* G_CTLZ_ZERO_UNDEF */ type0, type1, /* G_CTPOP */ type0, type1, /* G_BSWAP */ type0, type0, /* G_BITREVERSE */ type0, type0, /* G_FCEIL */ type0, type0, /* G_FCOS */ type0, type0, /* G_FSIN */ type0, type0, /* G_FSQRT */ type0, type0, /* G_FFLOOR */ type0, type0, /* G_FRINT */ type0, type0, /* G_FNEARBYINT */ type0, type0, /* G_ADDRSPACE_CAST */ type0, type1, /* G_BLOCK_ADDR */ type0, -1, /* G_JUMP_TABLE */ type0, -1, /* G_DYN_STACKALLOC */ ptype0, type1, i32imm, /* G_STRICT_FADD */ type0, type0, type0, /* G_STRICT_FSUB */ type0, type0, type0, /* G_STRICT_FMUL */ type0, type0, type0, /* G_STRICT_FDIV */ type0, type0, type0, /* G_STRICT_FREM */ type0, type0, type0, /* G_STRICT_FMA */ type0, type0, type0, type0, /* G_STRICT_FSQRT */ type0, type0, /* G_READ_REGISTER */ type0, -1, /* G_WRITE_REGISTER */ -1, type0, /* G_MEMCPY */ ptype0, ptype1, type2, untyped_imm_0, /* G_MEMCPY_INLINE */ ptype0, ptype1, type2, /* G_MEMMOVE */ ptype0, ptype1, type2, untyped_imm_0, /* G_MEMSET */ ptype0, type1, type2, untyped_imm_0, /* G_BZERO */ ptype0, type1, untyped_imm_0, /* G_VECREDUCE_SEQ_FADD */ type0, type1, type2, /* G_VECREDUCE_SEQ_FMUL */ type0, type1, type2, /* G_VECREDUCE_FADD */ type0, type1, /* G_VECREDUCE_FMUL */ type0, type1, /* G_VECREDUCE_FMAX */ type0, type1, /* G_VECREDUCE_FMIN */ type0, type1, /* G_VECREDUCE_ADD */ type0, type1, /* G_VECREDUCE_MUL */ type0, type1, /* G_VECREDUCE_AND */ type0, type1, /* G_VECREDUCE_OR */ type0, type1, /* G_VECREDUCE_XOR */ type0, type1, /* G_VECREDUCE_SMAX */ type0, type1, /* G_VECREDUCE_SMIN */ type0, type1, /* G_VECREDUCE_UMAX */ type0, type1, /* G_VECREDUCE_UMIN */ type0, type1, /* G_SBFX */ type0, type0, type1, type1, /* G_UBFX */ type0, type0, type1, type1, /* ABSMacro */ GPR32Opnd, GPR32Opnd, /* ADJCALLSTACKDOWN */ i32imm, i32imm, /* ADJCALLSTACKUP */ i32imm, i32imm, /* AND_V_D_PSEUDO */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* AND_V_H_PSEUDO */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* AND_V_W_PSEUDO */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* ATOMIC_CMP_SWAP_I16 */ GPR32, -1, GPR32, GPR32, /* ATOMIC_CMP_SWAP_I16_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_CMP_SWAP_I32 */ GPR32, -1, GPR32, GPR32, /* ATOMIC_CMP_SWAP_I32_POSTRA */ GPR32, -1, GPR32, GPR32, /* ATOMIC_CMP_SWAP_I64 */ GPR64, -1, GPR64, GPR64, /* ATOMIC_CMP_SWAP_I64_POSTRA */ GPR64, -1, GPR64, GPR64, /* ATOMIC_CMP_SWAP_I8 */ GPR32, -1, GPR32, GPR32, /* ATOMIC_CMP_SWAP_I8_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_ADD_I16 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_ADD_I16_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_ADD_I32 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_ADD_I32_POSTRA */ GPR32, -1, GPR32, /* ATOMIC_LOAD_ADD_I64 */ GPR64, -1, GPR64, /* ATOMIC_LOAD_ADD_I64_POSTRA */ GPR64, -1, GPR64, /* ATOMIC_LOAD_ADD_I8 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_ADD_I8_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_AND_I16 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_AND_I16_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_AND_I32 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_AND_I32_POSTRA */ GPR32, -1, GPR32, /* ATOMIC_LOAD_AND_I64 */ GPR64, -1, GPR64, /* ATOMIC_LOAD_AND_I64_POSTRA */ GPR64, -1, GPR64, /* ATOMIC_LOAD_AND_I8 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_AND_I8_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_MAX_I16 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_MAX_I16_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_MAX_I32 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_MAX_I32_POSTRA */ GPR32, -1, GPR32, /* ATOMIC_LOAD_MAX_I64 */ GPR64, -1, GPR64, /* ATOMIC_LOAD_MAX_I64_POSTRA */ GPR64, -1, GPR64, /* ATOMIC_LOAD_MAX_I8 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_MAX_I8_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_MIN_I16 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_MIN_I16_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_MIN_I32 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_MIN_I32_POSTRA */ GPR32, -1, GPR32, /* ATOMIC_LOAD_MIN_I64 */ GPR64, -1, GPR64, /* ATOMIC_LOAD_MIN_I64_POSTRA */ GPR64, -1, GPR64, /* ATOMIC_LOAD_MIN_I8 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_MIN_I8_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_NAND_I16 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_NAND_I16_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_NAND_I32 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_NAND_I32_POSTRA */ GPR32, -1, GPR32, /* ATOMIC_LOAD_NAND_I64 */ GPR64, -1, GPR64, /* ATOMIC_LOAD_NAND_I64_POSTRA */ GPR64, -1, GPR64, /* ATOMIC_LOAD_NAND_I8 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_NAND_I8_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_OR_I16 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_OR_I16_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_OR_I32 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_OR_I32_POSTRA */ GPR32, -1, GPR32, /* ATOMIC_LOAD_OR_I64 */ GPR64, -1, GPR64, /* ATOMIC_LOAD_OR_I64_POSTRA */ GPR64, -1, GPR64, /* ATOMIC_LOAD_OR_I8 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_OR_I8_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_SUB_I16 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_SUB_I16_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_SUB_I32 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_SUB_I32_POSTRA */ GPR32, -1, GPR32, /* ATOMIC_LOAD_SUB_I64 */ GPR64, -1, GPR64, /* ATOMIC_LOAD_SUB_I64_POSTRA */ GPR64, -1, GPR64, /* ATOMIC_LOAD_SUB_I8 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_SUB_I8_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_UMAX_I16 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_UMAX_I16_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_UMAX_I32 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_UMAX_I32_POSTRA */ GPR32, -1, GPR32, /* ATOMIC_LOAD_UMAX_I64 */ GPR64, -1, GPR64, /* ATOMIC_LOAD_UMAX_I64_POSTRA */ GPR64, -1, GPR64, /* ATOMIC_LOAD_UMAX_I8 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_UMAX_I8_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_UMIN_I16 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_UMIN_I16_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_UMIN_I32 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_UMIN_I32_POSTRA */ GPR32, -1, GPR32, /* ATOMIC_LOAD_UMIN_I64 */ GPR64, -1, GPR64, /* ATOMIC_LOAD_UMIN_I64_POSTRA */ GPR64, -1, GPR64, /* ATOMIC_LOAD_UMIN_I8 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_UMIN_I8_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_XOR_I16 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_XOR_I16_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_LOAD_XOR_I32 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_XOR_I32_POSTRA */ GPR32, -1, GPR32, /* ATOMIC_LOAD_XOR_I64 */ GPR64, -1, GPR64, /* ATOMIC_LOAD_XOR_I64_POSTRA */ GPR64, -1, GPR64, /* ATOMIC_LOAD_XOR_I8 */ GPR32, -1, GPR32, /* ATOMIC_LOAD_XOR_I8_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_SWAP_I16 */ GPR32, -1, GPR32, /* ATOMIC_SWAP_I16_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* ATOMIC_SWAP_I32 */ GPR32, -1, GPR32, /* ATOMIC_SWAP_I32_POSTRA */ GPR32, -1, GPR32, /* ATOMIC_SWAP_I64 */ GPR64, -1, GPR64, /* ATOMIC_SWAP_I64_POSTRA */ GPR64, -1, GPR64, /* ATOMIC_SWAP_I8 */ GPR32, -1, GPR32, /* ATOMIC_SWAP_I8_POSTRA */ GPR32, -1, GPR32, GPR32, GPR32, GPR32, /* B */ brtarget, /* BAL_BR */ brtarget, /* BAL_BR_MM */ brtarget_mm, /* BEQLImmMacro */ GPR32Opnd, imm64, brtarget, /* BGE */ GPR32Opnd, GPR32Opnd, brtarget, /* BGEImmMacro */ GPR32Opnd, imm64, brtarget, /* BGEL */ GPR32Opnd, GPR32Opnd, brtarget, /* BGELImmMacro */ GPR32Opnd, imm64, brtarget, /* BGEU */ GPR32Opnd, GPR32Opnd, brtarget, /* BGEUImmMacro */ GPR32Opnd, imm64, brtarget, /* BGEUL */ GPR32Opnd, GPR32Opnd, brtarget, /* BGEULImmMacro */ GPR32Opnd, imm64, brtarget, /* BGT */ GPR32Opnd, GPR32Opnd, brtarget, /* BGTImmMacro */ GPR32Opnd, imm64, brtarget, /* BGTL */ GPR32Opnd, GPR32Opnd, brtarget, /* BGTLImmMacro */ GPR32Opnd, imm64, brtarget, /* BGTU */ GPR32Opnd, GPR32Opnd, brtarget, /* BGTUImmMacro */ GPR32Opnd, imm64, brtarget, /* BGTUL */ GPR32Opnd, GPR32Opnd, brtarget, /* BGTULImmMacro */ GPR32Opnd, imm64, brtarget, /* BLE */ GPR32Opnd, GPR32Opnd, brtarget, /* BLEImmMacro */ GPR32Opnd, imm64, brtarget, /* BLEL */ GPR32Opnd, GPR32Opnd, brtarget, /* BLELImmMacro */ GPR32Opnd, imm64, brtarget, /* BLEU */ GPR32Opnd, GPR32Opnd, brtarget, /* BLEUImmMacro */ GPR32Opnd, imm64, brtarget, /* BLEUL */ GPR32Opnd, GPR32Opnd, brtarget, /* BLEULImmMacro */ GPR32Opnd, imm64, brtarget, /* BLT */ GPR32Opnd, GPR32Opnd, brtarget, /* BLTImmMacro */ GPR32Opnd, imm64, brtarget, /* BLTL */ GPR32Opnd, GPR32Opnd, brtarget, /* BLTLImmMacro */ GPR32Opnd, imm64, brtarget, /* BLTU */ GPR32Opnd, GPR32Opnd, brtarget, /* BLTUImmMacro */ GPR32Opnd, imm64, brtarget, /* BLTUL */ GPR32Opnd, GPR32Opnd, brtarget, /* BLTULImmMacro */ GPR32Opnd, imm64, brtarget, /* BNELImmMacro */ GPR32Opnd, imm64, brtarget, /* BPOSGE32_PSEUDO */ GPR32Opnd, /* BSEL_D_PSEUDO */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* BSEL_FD_PSEUDO */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* BSEL_FW_PSEUDO */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* BSEL_H_PSEUDO */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* BSEL_W_PSEUDO */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* B_MM */ brtarget, /* B_MMR6_Pseudo */ brtarget_mm, /* B_MM_Pseudo */ brtarget_mm, /* BeqImm */ GPR32Opnd, imm64, brtarget, /* BneImm */ GPR32Opnd, imm64, brtarget, /* BteqzT8CmpX16 */ CPU16Regs, CPU16Regs, brtarget, /* BteqzT8CmpiX16 */ CPU16Regs, simm16, brtarget, /* BteqzT8SltX16 */ CPU16Regs, CPU16Regs, brtarget, /* BteqzT8SltiX16 */ CPU16Regs, simm16, brtarget, /* BteqzT8SltiuX16 */ CPU16Regs, simm16, brtarget, /* BteqzT8SltuX16 */ CPU16Regs, CPU16Regs, brtarget, /* BtnezT8CmpX16 */ CPU16Regs, CPU16Regs, brtarget, /* BtnezT8CmpiX16 */ CPU16Regs, simm16, brtarget, /* BtnezT8SltX16 */ CPU16Regs, CPU16Regs, brtarget, /* BtnezT8SltiX16 */ CPU16Regs, simm16, brtarget, /* BtnezT8SltiuX16 */ CPU16Regs, simm16, brtarget, /* BtnezT8SltuX16 */ CPU16Regs, CPU16Regs, brtarget, /* BuildPairF64 */ AFGR64Opnd, GPR32Opnd, GPR32Opnd, /* BuildPairF64_64 */ FGR64Opnd, GPR32Opnd, GPR32Opnd, /* CFTC1 */ GPR32Opnd, FGRCCOpnd, /* CONSTPOOL_ENTRY */ cpinst_operand, cpinst_operand, i32imm, /* COPY_FD_PSEUDO */ FGR64, MSA128D, uimm1_ptr, /* COPY_FW_PSEUDO */ FGR32, MSA128W, uimm2_ptr, /* CTTC1 */ FGRCCOpnd, GPR32Opnd, /* Constant32 */ simm32, /* DMULImmMacro */ GPR64Opnd, GPR64Opnd, simm32_relaxed, /* DMULMacro */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DMULOMacro */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DMULOUMacro */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DROL */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* DROLImm */ GPR32Opnd, GPR32Opnd, simm16, /* DROR */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* DRORImm */ GPR32Opnd, GPR32Opnd, simm16, /* DSDivIMacro */ GPR64Opnd, GPR64Opnd, imm64, /* DSDivMacro */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DSRemIMacro */ GPR64Opnd, GPR64Opnd, simm32_relaxed, /* DSRemMacro */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DUDivIMacro */ GPR64Opnd, GPR64Opnd, imm64, /* DUDivMacro */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DURemIMacro */ GPR64Opnd, GPR64Opnd, simm32_relaxed, /* DURemMacro */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* ERet */ /* ExtractElementF64 */ GPR32Opnd, AFGR64Opnd, i32imm, /* ExtractElementF64_64 */ GPR32Opnd, FGR64Opnd, i32imm, /* FABS_D */ MSA128DOpnd, MSA128DOpnd, /* FABS_W */ MSA128WOpnd, MSA128WOpnd, /* FEXP2_D_1_PSEUDO */ MSA128D, MSA128D, /* FEXP2_W_1_PSEUDO */ MSA128W, MSA128W, /* FILL_FD_PSEUDO */ MSA128D, FGR64, /* FILL_FW_PSEUDO */ MSA128W, FGR32, /* GotPrologue16 */ CPU16Regs, CPU16Regs, simm16, simm16, /* INSERT_B_VIDX64_PSEUDO */ MSA128BOpnd, MSA128BOpnd, GPR64Opnd, GPR32Opnd, /* INSERT_B_VIDX_PSEUDO */ MSA128BOpnd, MSA128BOpnd, GPR32Opnd, GPR32Opnd, /* INSERT_D_VIDX64_PSEUDO */ MSA128DOpnd, MSA128DOpnd, GPR64Opnd, GPR64Opnd, /* INSERT_D_VIDX_PSEUDO */ MSA128DOpnd, MSA128DOpnd, GPR32Opnd, GPR64Opnd, /* INSERT_FD_PSEUDO */ MSA128DOpnd, MSA128DOpnd, uimm1, FGR64Opnd, /* INSERT_FD_VIDX64_PSEUDO */ MSA128DOpnd, MSA128DOpnd, GPR64Opnd, FGR64Opnd, /* INSERT_FD_VIDX_PSEUDO */ MSA128DOpnd, MSA128DOpnd, GPR32Opnd, FGR64Opnd, /* INSERT_FW_PSEUDO */ MSA128WOpnd, MSA128WOpnd, uimm2, FGR32Opnd, /* INSERT_FW_VIDX64_PSEUDO */ MSA128WOpnd, MSA128WOpnd, GPR64Opnd, FGR32Opnd, /* INSERT_FW_VIDX_PSEUDO */ MSA128WOpnd, MSA128WOpnd, GPR32Opnd, FGR32Opnd, /* INSERT_H_VIDX64_PSEUDO */ MSA128HOpnd, MSA128HOpnd, GPR64Opnd, GPR32Opnd, /* INSERT_H_VIDX_PSEUDO */ MSA128HOpnd, MSA128HOpnd, GPR32Opnd, GPR32Opnd, /* INSERT_W_VIDX64_PSEUDO */ MSA128WOpnd, MSA128WOpnd, GPR64Opnd, GPR32Opnd, /* INSERT_W_VIDX_PSEUDO */ MSA128WOpnd, MSA128WOpnd, GPR32Opnd, GPR32Opnd, /* JALR64Pseudo */ GPR64Opnd, /* JALRHB64Pseudo */ GPR64Opnd, /* JALRHBPseudo */ GPR32Opnd, /* JALRPseudo */ GPR32Opnd, /* JAL_MMR6 */ calltarget, /* JalOneReg */ GPR32Opnd, /* JalTwoReg */ GPR32Opnd, GPR32Opnd, /* LDMacro */ GPR32Opnd, -1, simm16, /* LDR_D */ MSA128DOpnd, -1, GPR32, /* LDR_W */ MSA128WOpnd, -1, GPR32, /* LD_F16 */ MSA128F16, -1, simm10, /* LOAD_ACC128 */ ACC128, -1, simm16, /* LOAD_ACC64 */ ACC64, -1, simm16, /* LOAD_ACC64DSP */ ACC64DSPOpnd, -1, simm16, /* LOAD_CCOND_DSP */ DSPCC, -1, simm16, /* LONG_BRANCH_ADDiu */ GPR32Opnd, GPR32Opnd, brtarget, brtarget, /* LONG_BRANCH_ADDiu2Op */ GPR32Opnd, GPR32Opnd, brtarget, /* LONG_BRANCH_DADDiu */ GPR64Opnd, GPR64Opnd, brtarget, brtarget, /* LONG_BRANCH_DADDiu2Op */ GPR64Opnd, GPR64Opnd, brtarget, /* LONG_BRANCH_LUi */ GPR32Opnd, brtarget, brtarget, /* LONG_BRANCH_LUi2Op */ GPR32Opnd, brtarget, /* LONG_BRANCH_LUi2Op_64 */ GPR64Opnd, brtarget, /* LWM_MM */ reglist, -1, simm12, /* LoadAddrImm32 */ GPR32Opnd, i32imm, /* LoadAddrImm64 */ GPR64Opnd, imm64, /* LoadAddrReg32 */ GPR32Opnd, -1, simm16, /* LoadAddrReg64 */ GPR64Opnd, -1, simm16, /* LoadImm32 */ GPR32Opnd, uimm32_coerced, /* LoadImm64 */ GPR64Opnd, imm64, /* LoadImmDoubleFGR */ StrictlyFGR64Opnd, imm64, /* LoadImmDoubleFGR_32 */ StrictlyAFGR64Opnd, imm64, /* LoadImmDoubleGPR */ GPR32Opnd, imm64, /* LoadImmSingleFGR */ StrictlyFGR32Opnd, imm64, /* LoadImmSingleGPR */ GPR32Opnd, imm64, /* LwConstant32 */ CPU16Regs, simm32, simm32, /* MFTACX */ GPR32Opnd, ACC64DSPOpnd, /* MFTC0 */ GPR32Opnd, COP0Opnd, uimm3, /* MFTC1 */ GPR32Opnd, FGR32Opnd, /* MFTDSP */ GPR32Opnd, /* MFTGPR */ GPR32Opnd, GPR32Opnd, uimm3, /* MFTHC1 */ GPR32Opnd, FGR32Opnd, /* MFTHI */ GPR32Opnd, ACC64DSPOpnd, /* MFTLO */ GPR32Opnd, ACC64DSPOpnd, /* MIPSeh_return32 */ GPR32, GPR32, /* MIPSeh_return64 */ GPR64, GPR64, /* MSA_FP_EXTEND_D_PSEUDO */ FGR64Opnd, MSA128F16, /* MSA_FP_EXTEND_W_PSEUDO */ FGR32Opnd, MSA128F16, /* MSA_FP_ROUND_D_PSEUDO */ MSA128F16, FGR64Opnd, /* MSA_FP_ROUND_W_PSEUDO */ MSA128F16, FGR32Opnd, /* MTTACX */ ACC64DSPOpnd, GPR32Opnd, /* MTTC0 */ COP0Opnd, GPR32Opnd, uimm3, /* MTTC1 */ FGR32Opnd, GPR32Opnd, /* MTTDSP */ GPR32Opnd, /* MTTGPR */ GPR32Opnd, GPR32Opnd, /* MTTHC1 */ FGR32Opnd, GPR32Opnd, /* MTTHI */ ACC64DSPOpnd, GPR32Opnd, /* MTTLO */ ACC64DSPOpnd, GPR32Opnd, /* MULImmMacro */ GPR32Opnd, GPR32Opnd, simm32_relaxed, /* MULOMacro */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MULOUMacro */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MultRxRy16 */ CPU16Regs, CPU16Regs, /* MultRxRyRz16 */ CPU16Regs, CPU16Regs, CPU16Regs, /* MultuRxRy16 */ CPU16Regs, CPU16Regs, /* MultuRxRyRz16 */ CPU16Regs, CPU16Regs, CPU16Regs, /* NOP */ /* NORImm */ GPR32Opnd, GPR32Opnd, simm32_relaxed, /* NORImm64 */ GPR64Opnd, GPR64Opnd, imm64, /* NOR_V_D_PSEUDO */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* NOR_V_H_PSEUDO */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* NOR_V_W_PSEUDO */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* OR_V_D_PSEUDO */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* OR_V_H_PSEUDO */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* OR_V_W_PSEUDO */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* PseudoCMPU_EQ_QB */ DSPCC, DSPROpnd, DSPROpnd, /* PseudoCMPU_LE_QB */ DSPCC, DSPROpnd, DSPROpnd, /* PseudoCMPU_LT_QB */ DSPCC, DSPROpnd, DSPROpnd, /* PseudoCMP_EQ_PH */ DSPCC, DSPROpnd, DSPROpnd, /* PseudoCMP_LE_PH */ DSPCC, DSPROpnd, DSPROpnd, /* PseudoCMP_LT_PH */ DSPCC, DSPROpnd, DSPROpnd, /* PseudoCVT_D32_W */ AFGR64Opnd, GPR32Opnd, /* PseudoCVT_D64_L */ FGR64Opnd, GPR64Opnd, /* PseudoCVT_D64_W */ FGR64Opnd, GPR32Opnd, /* PseudoCVT_S_L */ FGR64Opnd, GPR64Opnd, /* PseudoCVT_S_W */ FGR32Opnd, GPR32Opnd, /* PseudoDMULT */ ACC128, GPR64Opnd, GPR64Opnd, /* PseudoDMULTu */ ACC128, GPR64Opnd, GPR64Opnd, /* PseudoDSDIV */ ACC128, GPR64Opnd, GPR64Opnd, /* PseudoDUDIV */ ACC128, GPR64Opnd, GPR64Opnd, /* PseudoD_SELECT_I */ GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, /* PseudoD_SELECT_I64 */ GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, /* PseudoIndirectBranch */ GPR32Opnd, /* PseudoIndirectBranch64 */ GPR64Opnd, /* PseudoIndirectBranch64R6 */ GPR64Opnd, /* PseudoIndirectBranchR6 */ GPR32Opnd, /* PseudoIndirectBranch_MM */ GPR32Opnd, /* PseudoIndirectBranch_MMR6 */ GPR32Opnd, /* PseudoIndirectHazardBranch */ GPR32Opnd, /* PseudoIndirectHazardBranch64 */ GPR64Opnd, /* PseudoIndrectHazardBranch64R6 */ GPR64Opnd, /* PseudoIndrectHazardBranchR6 */ GPR32Opnd, /* PseudoMADD */ ACC64, GPR32Opnd, GPR32Opnd, ACC64, /* PseudoMADDU */ ACC64, GPR32Opnd, GPR32Opnd, ACC64, /* PseudoMADDU_MM */ ACC64, GPR32Opnd, GPR32Opnd, ACC64, /* PseudoMADD_MM */ ACC64, GPR32Opnd, GPR32Opnd, ACC64, /* PseudoMFHI */ GPR32, ACC64, /* PseudoMFHI64 */ GPR64, ACC128, /* PseudoMFHI_MM */ GPR32, ACC64, /* PseudoMFLO */ GPR32, ACC64, /* PseudoMFLO64 */ GPR64, ACC128, /* PseudoMFLO_MM */ GPR32, ACC64, /* PseudoMSUB */ ACC64, GPR32Opnd, GPR32Opnd, ACC64, /* PseudoMSUBU */ ACC64, GPR32Opnd, GPR32Opnd, ACC64, /* PseudoMSUBU_MM */ ACC64, GPR32Opnd, GPR32Opnd, ACC64, /* PseudoMSUB_MM */ ACC64, GPR32Opnd, GPR32Opnd, ACC64, /* PseudoMTLOHI */ ACC64, GPR32, GPR32, /* PseudoMTLOHI64 */ ACC128, GPR64, GPR64, /* PseudoMTLOHI_DSP */ ACC64DSP, GPR32, GPR32, /* PseudoMTLOHI_MM */ ACC64, GPR32, GPR32, /* PseudoMULT */ ACC64, GPR32Opnd, GPR32Opnd, /* PseudoMULT_MM */ ACC64, GPR32Opnd, GPR32Opnd, /* PseudoMULTu */ ACC64, GPR32Opnd, GPR32Opnd, /* PseudoMULTu_MM */ ACC64, GPR32Opnd, GPR32Opnd, /* PseudoPICK_PH */ DSPROpnd, DSPCC, DSPROpnd, DSPROpnd, /* PseudoPICK_QB */ DSPROpnd, DSPCC, DSPROpnd, DSPROpnd, /* PseudoReturn */ GPR32Opnd, /* PseudoReturn64 */ GPR64Opnd, /* PseudoSDIV */ ACC64, GPR32Opnd, GPR32Opnd, /* PseudoSELECTFP_F_D32 */ AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* PseudoSELECTFP_F_D64 */ FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* PseudoSELECTFP_F_I */ GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd, /* PseudoSELECTFP_F_I64 */ GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd, /* PseudoSELECTFP_F_S */ FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* PseudoSELECTFP_T_D32 */ AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* PseudoSELECTFP_T_D64 */ FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* PseudoSELECTFP_T_I */ GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd, /* PseudoSELECTFP_T_I64 */ GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd, /* PseudoSELECTFP_T_S */ FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* PseudoSELECT_D32 */ AFGR64Opnd, GPR32Opnd, AFGR64Opnd, AFGR64Opnd, /* PseudoSELECT_D64 */ FGR64Opnd, GPR32Opnd, FGR64Opnd, FGR64Opnd, /* PseudoSELECT_I */ GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, /* PseudoSELECT_I64 */ GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd, /* PseudoSELECT_S */ FGR32Opnd, GPR32Opnd, FGR32Opnd, FGR32Opnd, /* PseudoTRUNC_W_D */ FGR32Opnd, FGR64Opnd, GPR32Opnd, /* PseudoTRUNC_W_D32 */ FGR32Opnd, AFGR64Opnd, GPR32Opnd, /* PseudoTRUNC_W_S */ FGR32Opnd, FGR32Opnd, GPR32Opnd, /* PseudoUDIV */ ACC64, GPR32Opnd, GPR32Opnd, /* ROL */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ROLImm */ GPR32Opnd, GPR32Opnd, simm16, /* ROR */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* RORImm */ GPR32Opnd, GPR32Opnd, simm16, /* RetRA */ /* RetRA16 */ /* SDC1_M1 */ AFGR64Opnd, -1, simm16, /* SDIV_MM_Pseudo */ ACC64, GPR32Opnd, GPR32Opnd, /* SDMacro */ GPR32Opnd, -1, simm16, /* SDivIMacro */ GPR32Opnd, GPR32Opnd, simm32, /* SDivMacro */ GPR32NonZeroOpnd, GPR32Opnd, GPR32Opnd, /* SEQIMacro */ GPR32Opnd, GPR32Opnd, simm32_relaxed, /* SEQMacro */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SGE */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SGEImm */ GPR32Opnd, GPR32Opnd, simm32, /* SGEImm64 */ GPR64Opnd, GPR64Opnd, imm64, /* SGEU */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SGEUImm */ GPR32Opnd, GPR32Opnd, uimm32_coerced, /* SGEUImm64 */ GPR64Opnd, GPR64Opnd, imm64, /* SGTImm */ GPR32Opnd, GPR32Opnd, simm32, /* SGTImm64 */ GPR64Opnd, GPR64Opnd, imm64, /* SGTUImm */ GPR32Opnd, GPR32Opnd, uimm32_coerced, /* SGTUImm64 */ GPR64Opnd, GPR64Opnd, imm64, /* SLE */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SLEImm */ GPR32Opnd, GPR32Opnd, simm32, /* SLEImm64 */ GPR64Opnd, GPR64Opnd, imm64, /* SLEU */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SLEUImm */ GPR32Opnd, GPR32Opnd, uimm32_coerced, /* SLEUImm64 */ GPR64Opnd, GPR64Opnd, imm64, /* SLTImm64 */ GPR64Opnd, GPR64Opnd, imm64, /* SLTUImm64 */ GPR64Opnd, GPR64Opnd, imm64, /* SNEIMacro */ GPR32Opnd, GPR32Opnd, simm32_relaxed, /* SNEMacro */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SNZ_B_PSEUDO */ GPR32, MSA128B, /* SNZ_D_PSEUDO */ GPR32, MSA128D, /* SNZ_H_PSEUDO */ GPR32, MSA128H, /* SNZ_V_PSEUDO */ GPR32, MSA128B, /* SNZ_W_PSEUDO */ GPR32, MSA128W, /* SRemIMacro */ GPR32Opnd, GPR32Opnd, simm32_relaxed, /* SRemMacro */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* STORE_ACC128 */ ACC128, -1, simm16, /* STORE_ACC64 */ ACC64, -1, simm16, /* STORE_ACC64DSP */ ACC64DSPOpnd, -1, simm16, /* STORE_CCOND_DSP */ DSPCC, -1, simm16, /* STR_D */ MSA128DOpnd, -1, GPR32, /* STR_W */ MSA128WOpnd, -1, GPR32, /* ST_F16 */ MSA128F16, -1, simm10, /* SWM_MM */ reglist, -1, simm12, /* SZ_B_PSEUDO */ GPR32, MSA128B, /* SZ_D_PSEUDO */ GPR32, MSA128D, /* SZ_H_PSEUDO */ GPR32, MSA128H, /* SZ_V_PSEUDO */ GPR32, MSA128B, /* SZ_W_PSEUDO */ GPR32, MSA128W, /* SaaAddr */ GPR64Opnd, -1, simm16, /* SaadAddr */ GPR64Opnd, -1, simm16, /* SelBeqZ */ CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, /* SelBneZ */ CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, /* SelTBteqZCmp */ CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, /* SelTBteqZCmpi */ CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, /* SelTBteqZSlt */ CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, /* SelTBteqZSlti */ CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, /* SelTBteqZSltiu */ CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, /* SelTBteqZSltu */ CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, /* SelTBtneZCmp */ CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, /* SelTBtneZCmpi */ CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, /* SelTBtneZSlt */ CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, /* SelTBtneZSlti */ CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, /* SelTBtneZSltiu */ CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, /* SelTBtneZSltu */ CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, /* SltCCRxRy16 */ CPU16Regs, CPU16Regs, CPU16Regs, /* SltiCCRxImmX16 */ CPU16Regs, CPU16Regs, simm16, /* SltiuCCRxImmX16 */ CPU16Regs, CPU16Regs, simm16, /* SltuCCRxRy16 */ CPU16Regs, CPU16Regs, CPU16Regs, /* SltuRxRyRz16 */ CPU16Regs, CPU16Regs, CPU16Regs, /* TAILCALL */ calltarget, /* TAILCALL64R6REG */ GPR64Opnd, /* TAILCALLHB64R6REG */ GPR64Opnd, /* TAILCALLHBR6REG */ GPR32Opnd, /* TAILCALLR6REG */ GPR32Opnd, /* TAILCALLREG */ GPR32Opnd, /* TAILCALLREG64 */ GPR64Opnd, /* TAILCALLREGHB */ GPR32Opnd, /* TAILCALLREGHB64 */ GPR64Opnd, /* TAILCALLREG_MM */ GPR32Opnd, /* TAILCALLREG_MMR6 */ GPR32Opnd, /* TAILCALL_MM */ calltarget, /* TAILCALL_MMR6 */ calltarget, /* TRAP */ /* TRAP_MM */ /* UDIV_MM_Pseudo */ ACC64, GPR32Opnd, GPR32Opnd, /* UDivIMacro */ GPR32Opnd, GPR32Opnd, simm32, /* UDivMacro */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* URemIMacro */ GPR32Opnd, GPR32Opnd, simm32_relaxed, /* URemMacro */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* Ulh */ GPR32Opnd, -1, simm16, /* Ulhu */ GPR32Opnd, -1, simm16, /* Ulw */ GPR32Opnd, -1, simm16, /* Ush */ GPR32Opnd, -1, simm16, /* Usw */ GPR32Opnd, -1, simm16, /* XOR_V_D_PSEUDO */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* XOR_V_H_PSEUDO */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* XOR_V_W_PSEUDO */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* ABSQ_S_PH */ DSPROpnd, DSPROpnd, /* ABSQ_S_PH_MM */ DSPROpnd, DSPROpnd, /* ABSQ_S_QB */ DSPROpnd, DSPROpnd, /* ABSQ_S_QB_MMR2 */ DSPROpnd, DSPROpnd, /* ABSQ_S_W */ GPR32Opnd, GPR32Opnd, /* ABSQ_S_W_MM */ GPR32Opnd, GPR32Opnd, /* ADD */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ADDIUPC */ GPR32Opnd, simm19_lsl2, /* ADDIUPC_MM */ GPRMM16Opnd, simm23_lsl2, /* ADDIUPC_MMR6 */ GPR32Opnd, simm19_lsl2, /* ADDIUR1SP_MM */ GPRMM16Opnd, uimm6_lsl2, /* ADDIUR2_MM */ GPRMM16Opnd, GPRMM16Opnd, simm3_lsa2, /* ADDIUS5_MM */ GPR32Opnd, GPR32Opnd, simm4, /* ADDIUSP_MM */ simm9_addiusp, /* ADDIU_MMR6 */ GPR32Opnd, GPR32Opnd, simm16, /* ADDQH_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDQH_PH_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDQH_R_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDQH_R_PH_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDQH_R_W */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ADDQH_R_W_MMR2 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ADDQH_W */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ADDQH_W_MMR2 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ADDQ_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDQ_PH_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDQ_S_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDQ_S_PH_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDQ_S_W */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ADDQ_S_W_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ADDR_PS64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* ADDSC */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ADDSC_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ADDS_A_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* ADDS_A_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* ADDS_A_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* ADDS_A_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* ADDS_S_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* ADDS_S_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* ADDS_S_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* ADDS_S_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* ADDS_U_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* ADDS_U_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* ADDS_U_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* ADDS_U_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* ADDU16_MM */ GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, /* ADDU16_MMR6 */ GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, /* ADDUH_QB */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDUH_QB_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDUH_R_QB */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDUH_R_QB_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDU_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ADDU_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDU_PH_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDU_QB */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDU_QB_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDU_S_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDU_S_PH_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDU_S_QB */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDU_S_QB_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* ADDVI_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, /* ADDVI_D */ MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, /* ADDVI_H */ MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, /* ADDVI_W */ MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, /* ADDV_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* ADDV_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* ADDV_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* ADDV_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* ADDWC */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ADDWC_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ADD_A_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* ADD_A_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* ADD_A_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* ADD_A_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* ADD_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ADD_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ADDi */ GPR32Opnd, GPR32Opnd, simm16_relaxed, /* ADDi_MM */ GPR32Opnd, GPR32Opnd, simm16, /* ADDiu */ GPR32Opnd, GPR32Opnd, simm16_relaxed, /* ADDiu_MM */ GPR32Opnd, GPR32Opnd, simm16, /* ADDu */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ADDu_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ALIGN */ GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2, /* ALIGN_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2, /* ALUIPC */ GPR32Opnd, simm16, /* ALUIPC_MMR6 */ GPR32Opnd, simm16, /* AND */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* AND16_MM */ GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, /* AND16_MMR6 */ GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, /* AND64 */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* ANDI16_MM */ GPRMM16Opnd, GPRMM16Opnd, uimm4_andi, /* ANDI16_MMR6 */ GPRMM16Opnd, GPRMM16Opnd, uimm4_andi, /* ANDI_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, /* ANDI_MMR6 */ GPR32Opnd, GPR32Opnd, uimm16, /* AND_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* AND_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* AND_V */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* ANDi */ GPR32Opnd, GPR32Opnd, uimm16, /* ANDi64 */ GPR64Opnd, GPR64Opnd, uimm16_64, /* ANDi_MM */ GPR32Opnd, GPR32Opnd, uimm16, /* APPEND */ GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, /* APPEND_MMR2 */ GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, /* ASUB_S_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* ASUB_S_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* ASUB_S_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* ASUB_S_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* ASUB_U_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* ASUB_U_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* ASUB_U_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* ASUB_U_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* AUI */ GPR32Opnd, GPR32Opnd, uimm16, /* AUIPC */ GPR32Opnd, simm16, /* AUIPC_MMR6 */ GPR32Opnd, simm16, /* AUI_MMR6 */ GPR32Opnd, GPR32Opnd, uimm16, /* AVER_S_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* AVER_S_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* AVER_S_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* AVER_S_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* AVER_U_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* AVER_U_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* AVER_U_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* AVER_U_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* AVE_S_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* AVE_S_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* AVE_S_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* AVE_S_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* AVE_U_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* AVE_U_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* AVE_U_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* AVE_U_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* AddiuRxImmX16 */ CPU16Regs, simm16, /* AddiuRxPcImmX16 */ CPU16Regs, simm16, /* AddiuRxRxImm16 */ CPU16Regs, CPU16Regs, simm16, /* AddiuRxRxImmX16 */ CPU16Regs, CPU16Regs, simm16, /* AddiuRxRyOffMemX16 */ CPU16Regs, CPU16RegsPlusSP, simm16, /* AddiuSpImm16 */ simm16, /* AddiuSpImmX16 */ simm16, /* AdduRxRyRz16 */ CPU16Regs, CPU16Regs, CPU16Regs, /* AndRxRxRy16 */ CPU16Regs, CPU16Regs, CPU16Regs, /* B16_MM */ brtarget10_mm, /* BADDu */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* BAL */ brtarget, /* BALC */ brtarget26, /* BALC_MMR6 */ brtarget26_mm, /* BALIGN */ GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd, /* BALIGN_MMR2 */ GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd, /* BBIT0 */ GPR64Opnd, uimm5_64_report_uimm6, brtarget, /* BBIT032 */ GPR64Opnd, uimm5_64, brtarget, /* BBIT1 */ GPR64Opnd, uimm5_64_report_uimm6, brtarget, /* BBIT132 */ GPR64Opnd, uimm5_64, brtarget, /* BC */ brtarget26, /* BC16_MMR6 */ brtarget10_mm, /* BC1EQZ */ FGR64Opnd, brtarget, /* BC1EQZC_MMR6 */ FGR64Opnd, brtarget_mm, /* BC1F */ FCCRegsOpnd, brtarget, /* BC1FL */ FCCRegsOpnd, brtarget, /* BC1F_MM */ FCCRegsOpnd, brtarget_mm, /* BC1NEZ */ FGR64Opnd, brtarget, /* BC1NEZC_MMR6 */ FGR64Opnd, brtarget_mm, /* BC1T */ FCCRegsOpnd, brtarget, /* BC1TL */ FCCRegsOpnd, brtarget, /* BC1T_MM */ FCCRegsOpnd, brtarget_mm, /* BC2EQZ */ COP2Opnd, brtarget, /* BC2EQZC_MMR6 */ COP2Opnd, brtarget_mm, /* BC2NEZ */ COP2Opnd, brtarget, /* BC2NEZC_MMR6 */ COP2Opnd, brtarget_mm, /* BCLRI_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, /* BCLRI_D */ MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, /* BCLRI_H */ MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, /* BCLRI_W */ MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, /* BCLR_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* BCLR_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* BCLR_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* BCLR_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* BC_MMR6 */ brtarget26_mm, /* BEQ */ GPR32Opnd, GPR32Opnd, brtarget, /* BEQ64 */ GPR64Opnd, GPR64Opnd, brtarget, /* BEQC */ GPR32Opnd, GPR32Opnd, brtarget, /* BEQC64 */ GPR64Opnd, GPR64Opnd, brtarget, /* BEQC_MMR6 */ GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, /* BEQL */ GPR32Opnd, GPR32Opnd, brtarget, /* BEQZ16_MM */ GPRMM16Opnd, brtarget7_mm, /* BEQZALC */ GPR32Opnd, brtarget, /* BEQZALC_MMR6 */ GPR32Opnd, brtarget_mm, /* BEQZC */ GPR32Opnd, brtarget21, /* BEQZC16_MMR6 */ GPRMM16Opnd, brtarget7_mm, /* BEQZC64 */ GPR64Opnd, brtarget21, /* BEQZC_MM */ GPR32Opnd, brtarget_mm, /* BEQZC_MMR6 */ GPR32Opnd, brtarget21_mm, /* BEQ_MM */ GPR32Opnd, GPR32Opnd, brtarget_mm, /* BGEC */ GPR32Opnd, GPR32Opnd, brtarget, /* BGEC64 */ GPR64Opnd, GPR64Opnd, brtarget, /* BGEC_MMR6 */ GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, /* BGEUC */ GPR32Opnd, GPR32Opnd, brtarget, /* BGEUC64 */ GPR64Opnd, GPR64Opnd, brtarget, /* BGEUC_MMR6 */ GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, /* BGEZ */ GPR32Opnd, brtarget, /* BGEZ64 */ GPR64Opnd, brtarget, /* BGEZAL */ GPR32Opnd, brtarget, /* BGEZALC */ GPR32Opnd, brtarget, /* BGEZALC_MMR6 */ GPR32Opnd, brtarget_mm, /* BGEZALL */ GPR32Opnd, brtarget, /* BGEZALS_MM */ GPR32Opnd, brtarget_mm, /* BGEZAL_MM */ GPR32Opnd, brtarget_mm, /* BGEZC */ GPR32Opnd, brtarget, /* BGEZC64 */ GPR64Opnd, brtarget, /* BGEZC_MMR6 */ GPR32Opnd, brtarget_lsl2_mm, /* BGEZL */ GPR32Opnd, brtarget, /* BGEZ_MM */ GPR32Opnd, brtarget_mm, /* BGTZ */ GPR32Opnd, brtarget, /* BGTZ64 */ GPR64Opnd, brtarget, /* BGTZALC */ GPR32Opnd, brtarget, /* BGTZALC_MMR6 */ GPR32Opnd, brtarget_mm, /* BGTZC */ GPR32Opnd, brtarget, /* BGTZC64 */ GPR64Opnd, brtarget, /* BGTZC_MMR6 */ GPR32Opnd, brtarget_lsl2_mm, /* BGTZL */ GPR32Opnd, brtarget, /* BGTZ_MM */ GPR32Opnd, brtarget_mm, /* BINSLI_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, /* BINSLI_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, /* BINSLI_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, /* BINSLI_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, /* BINSL_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* BINSL_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* BINSL_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* BINSL_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* BINSRI_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, /* BINSRI_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, /* BINSRI_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, /* BINSRI_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, /* BINSR_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* BINSR_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* BINSR_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* BINSR_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* BITREV */ GPR32Opnd, GPR32Opnd, /* BITREV_MM */ GPR32Opnd, GPR32Opnd, /* BITSWAP */ GPR32Opnd, GPR32Opnd, /* BITSWAP_MMR6 */ GPR32Opnd, GPR32Opnd, /* BLEZ */ GPR32Opnd, brtarget, /* BLEZ64 */ GPR64Opnd, brtarget, /* BLEZALC */ GPR32Opnd, brtarget, /* BLEZALC_MMR6 */ GPR32Opnd, brtarget_mm, /* BLEZC */ GPR32Opnd, brtarget, /* BLEZC64 */ GPR64Opnd, brtarget, /* BLEZC_MMR6 */ GPR32Opnd, brtarget_lsl2_mm, /* BLEZL */ GPR32Opnd, brtarget, /* BLEZ_MM */ GPR32Opnd, brtarget_mm, /* BLTC */ GPR32Opnd, GPR32Opnd, brtarget, /* BLTC64 */ GPR64Opnd, GPR64Opnd, brtarget, /* BLTC_MMR6 */ GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, /* BLTUC */ GPR32Opnd, GPR32Opnd, brtarget, /* BLTUC64 */ GPR64Opnd, GPR64Opnd, brtarget, /* BLTUC_MMR6 */ GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, /* BLTZ */ GPR32Opnd, brtarget, /* BLTZ64 */ GPR64Opnd, brtarget, /* BLTZAL */ GPR32Opnd, brtarget, /* BLTZALC */ GPR32Opnd, brtarget, /* BLTZALC_MMR6 */ GPR32Opnd, brtarget_mm, /* BLTZALL */ GPR32Opnd, brtarget, /* BLTZALS_MM */ GPR32Opnd, brtarget_mm, /* BLTZAL_MM */ GPR32Opnd, brtarget_mm, /* BLTZC */ GPR32Opnd, brtarget, /* BLTZC64 */ GPR64Opnd, brtarget, /* BLTZC_MMR6 */ GPR32Opnd, brtarget_lsl2_mm, /* BLTZL */ GPR32Opnd, brtarget, /* BLTZ_MM */ GPR32Opnd, brtarget_mm, /* BMNZI_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, /* BMNZ_V */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* BMZI_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, /* BMZ_V */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* BNE */ GPR32Opnd, GPR32Opnd, brtarget, /* BNE64 */ GPR64Opnd, GPR64Opnd, brtarget, /* BNEC */ GPR32Opnd, GPR32Opnd, brtarget, /* BNEC64 */ GPR64Opnd, GPR64Opnd, brtarget, /* BNEC_MMR6 */ GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, /* BNEGI_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, /* BNEGI_D */ MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, /* BNEGI_H */ MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, /* BNEGI_W */ MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, /* BNEG_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* BNEG_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* BNEG_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* BNEG_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* BNEL */ GPR32Opnd, GPR32Opnd, brtarget, /* BNEZ16_MM */ GPRMM16Opnd, brtarget7_mm, /* BNEZALC */ GPR32Opnd, brtarget, /* BNEZALC_MMR6 */ GPR32Opnd, brtarget_mm, /* BNEZC */ GPR32Opnd, brtarget21, /* BNEZC16_MMR6 */ GPRMM16Opnd, brtarget7_mm, /* BNEZC64 */ GPR64Opnd, brtarget21, /* BNEZC_MM */ GPR32Opnd, brtarget_mm, /* BNEZC_MMR6 */ GPR32Opnd, brtarget21_mm, /* BNE_MM */ GPR32Opnd, GPR32Opnd, brtarget_mm, /* BNVC */ GPR32Opnd, GPR32Opnd, brtarget, /* BNVC_MMR6 */ GPR32Opnd, GPR32Opnd, brtargetr6, /* BNZ_B */ MSA128BOpnd, brtarget, /* BNZ_D */ MSA128DOpnd, brtarget, /* BNZ_H */ MSA128HOpnd, brtarget, /* BNZ_V */ MSA128BOpnd, brtarget, /* BNZ_W */ MSA128WOpnd, brtarget, /* BOVC */ GPR32Opnd, GPR32Opnd, brtarget, /* BOVC_MMR6 */ GPR32Opnd, GPR32Opnd, brtargetr6, /* BPOSGE32 */ brtarget, /* BPOSGE32C_MMR3 */ brtarget1SImm16, /* BPOSGE32_MM */ brtarget_mm, /* BREAK */ uimm10, uimm10, /* BREAK16_MM */ uimm4, /* BREAK16_MMR6 */ uimm4, /* BREAK_MM */ uimm10, uimm10, /* BREAK_MMR6 */ uimm10, uimm10, /* BSELI_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, /* BSEL_V */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* BSETI_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, /* BSETI_D */ MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, /* BSETI_H */ MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, /* BSETI_W */ MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, /* BSET_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* BSET_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* BSET_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* BSET_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* BZ_B */ MSA128BOpnd, brtarget, /* BZ_D */ MSA128DOpnd, brtarget, /* BZ_H */ MSA128HOpnd, brtarget, /* BZ_V */ MSA128BOpnd, brtarget, /* BZ_W */ MSA128WOpnd, brtarget, /* BeqzRxImm16 */ CPU16Regs, brtarget, /* BeqzRxImmX16 */ CPU16Regs, brtarget, /* Bimm16 */ brtarget, /* BimmX16 */ brtarget, /* BnezRxImm16 */ CPU16Regs, brtarget, /* BnezRxImmX16 */ CPU16Regs, brtarget, /* Break16 */ /* Bteqz16 */ simm16, /* BteqzX16 */ simm16, /* Btnez16 */ simm16, /* BtnezX16 */ simm16, /* CACHE */ -1, simm16, uimm5, /* CACHEE */ -1, simm9, uimm5, /* CACHEE_MM */ -1, simm9, uimm5, /* CACHE_MM */ -1, simm12, uimm5, /* CACHE_MMR6 */ -1, simm12, uimm5, /* CACHE_R6 */ -1, simm9, uimm5, /* CEIL_L_D64 */ FGR64Opnd, FGR64Opnd, /* CEIL_L_D_MMR6 */ FGR64Opnd, FGR64Opnd, /* CEIL_L_S */ FGR64Opnd, FGR32Opnd, /* CEIL_L_S_MMR6 */ FGR64Opnd, FGR32Opnd, /* CEIL_W_D32 */ FGR32Opnd, AFGR64Opnd, /* CEIL_W_D64 */ FGR32Opnd, FGR64Opnd, /* CEIL_W_D_MMR6 */ FGR32Opnd, AFGR64Opnd, /* CEIL_W_MM */ FGR32Opnd, AFGR64Opnd, /* CEIL_W_S */ FGR32Opnd, FGR32Opnd, /* CEIL_W_S_MM */ FGR32Opnd, FGR32Opnd, /* CEIL_W_S_MMR6 */ FGR32Opnd, FGR32Opnd, /* CEQI_B */ MSA128BOpnd, MSA128BOpnd, vsplat_simm5, /* CEQI_D */ MSA128DOpnd, MSA128DOpnd, vsplat_simm5, /* CEQI_H */ MSA128HOpnd, MSA128HOpnd, vsplat_simm5, /* CEQI_W */ MSA128WOpnd, MSA128WOpnd, vsplat_simm5, /* CEQ_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* CEQ_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* CEQ_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* CEQ_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* CFC1 */ GPR32Opnd, CCROpnd, /* CFC1_MM */ GPR32Opnd, CCROpnd, /* CFC2_MM */ GPR32Opnd, COP2Opnd, /* CFCMSA */ GPR32Opnd, MSA128CROpnd, /* CINS */ GPR64Opnd, GPR64Opnd, uimm5, uimm5, /* CINS32 */ GPR64Opnd, GPR64Opnd, uimm5, uimm5, /* CINS64_32 */ GPR64Opnd, GPR32Opnd, uimm5, uimm5, /* CINS_i32 */ GPR32Opnd, GPR32Opnd, uimm5, uimm5, /* CLASS_D */ FGR64Opnd, FGR64Opnd, /* CLASS_D_MMR6 */ FGR64Opnd, FGR64Opnd, /* CLASS_S */ FGR32Opnd, FGR32Opnd, /* CLASS_S_MMR6 */ FGR32Opnd, FGR32Opnd, /* CLEI_S_B */ MSA128BOpnd, MSA128BOpnd, vsplat_simm5, /* CLEI_S_D */ MSA128DOpnd, MSA128DOpnd, vsplat_simm5, /* CLEI_S_H */ MSA128HOpnd, MSA128HOpnd, vsplat_simm5, /* CLEI_S_W */ MSA128WOpnd, MSA128WOpnd, vsplat_simm5, /* CLEI_U_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, /* CLEI_U_D */ MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, /* CLEI_U_H */ MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, /* CLEI_U_W */ MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, /* CLE_S_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* CLE_S_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* CLE_S_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* CLE_S_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* CLE_U_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* CLE_U_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* CLE_U_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* CLE_U_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* CLO */ GPR32Opnd, GPR32Opnd, /* CLO_MM */ GPR32Opnd, GPR32Opnd, /* CLO_MMR6 */ GPR32Opnd, GPR32Opnd, /* CLO_R6 */ GPR32Opnd, GPR32Opnd, /* CLTI_S_B */ MSA128BOpnd, MSA128BOpnd, vsplat_simm5, /* CLTI_S_D */ MSA128DOpnd, MSA128DOpnd, vsplat_simm5, /* CLTI_S_H */ MSA128HOpnd, MSA128HOpnd, vsplat_simm5, /* CLTI_S_W */ MSA128WOpnd, MSA128WOpnd, vsplat_simm5, /* CLTI_U_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, /* CLTI_U_D */ MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, /* CLTI_U_H */ MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, /* CLTI_U_W */ MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, /* CLT_S_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* CLT_S_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* CLT_S_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* CLT_S_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* CLT_U_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* CLT_U_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* CLT_U_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* CLT_U_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* CLZ */ GPR32Opnd, GPR32Opnd, /* CLZ_MM */ GPR32Opnd, GPR32Opnd, /* CLZ_MMR6 */ GPR32Opnd, GPR32Opnd, /* CLZ_R6 */ GPR32Opnd, GPR32Opnd, /* CMPGDU_EQ_QB */ GPR32Opnd, DSPROpnd, DSPROpnd, /* CMPGDU_EQ_QB_MMR2 */ GPR32Opnd, DSPROpnd, DSPROpnd, /* CMPGDU_LE_QB */ GPR32Opnd, DSPROpnd, DSPROpnd, /* CMPGDU_LE_QB_MMR2 */ GPR32Opnd, DSPROpnd, DSPROpnd, /* CMPGDU_LT_QB */ GPR32Opnd, DSPROpnd, DSPROpnd, /* CMPGDU_LT_QB_MMR2 */ GPR32Opnd, DSPROpnd, DSPROpnd, /* CMPGU_EQ_QB */ GPR32Opnd, DSPROpnd, DSPROpnd, /* CMPGU_EQ_QB_MM */ GPR32Opnd, DSPROpnd, DSPROpnd, /* CMPGU_LE_QB */ GPR32Opnd, DSPROpnd, DSPROpnd, /* CMPGU_LE_QB_MM */ GPR32Opnd, DSPROpnd, DSPROpnd, /* CMPGU_LT_QB */ GPR32Opnd, DSPROpnd, DSPROpnd, /* CMPGU_LT_QB_MM */ GPR32Opnd, DSPROpnd, DSPROpnd, /* CMPU_EQ_QB */ DSPROpnd, DSPROpnd, /* CMPU_EQ_QB_MM */ DSPROpnd, DSPROpnd, /* CMPU_LE_QB */ DSPROpnd, DSPROpnd, /* CMPU_LE_QB_MM */ DSPROpnd, DSPROpnd, /* CMPU_LT_QB */ DSPROpnd, DSPROpnd, /* CMPU_LT_QB_MM */ DSPROpnd, DSPROpnd, /* CMP_AF_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_AF_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_EQ_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_EQ_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_EQ_PH */ DSPROpnd, DSPROpnd, /* CMP_EQ_PH_MM */ DSPROpnd, DSPROpnd, /* CMP_EQ_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_EQ_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_F_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_F_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_LE_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_LE_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_LE_PH */ DSPROpnd, DSPROpnd, /* CMP_LE_PH_MM */ DSPROpnd, DSPROpnd, /* CMP_LE_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_LE_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_LT_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_LT_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_LT_PH */ DSPROpnd, DSPROpnd, /* CMP_LT_PH_MM */ DSPROpnd, DSPROpnd, /* CMP_LT_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_LT_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SAF_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SAF_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SAF_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SAF_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SEQ_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SEQ_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SEQ_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SEQ_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SLE_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SLE_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SLE_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SLE_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SLT_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SLT_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SLT_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SLT_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SUEQ_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SUEQ_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SUEQ_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SUEQ_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SULE_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SULE_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SULE_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SULE_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SULT_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SULT_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SULT_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SULT_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SUN_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SUN_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_SUN_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_SUN_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_UEQ_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_UEQ_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_UEQ_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_UEQ_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_ULE_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_ULE_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_ULE_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_ULE_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_ULT_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_ULT_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_ULT_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_ULT_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_UN_D */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_UN_D_MMR6 */ FGRCCOpnd, FGR64Opnd, FGR64Opnd, /* CMP_UN_S */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* CMP_UN_S_MMR6 */ FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* COPY_S_B */ GPR32Opnd, MSA128BOpnd, uimm4_ptr, /* COPY_S_D */ GPR64Opnd, MSA128DOpnd, uimm1_ptr, /* COPY_S_H */ GPR32Opnd, MSA128HOpnd, uimm3_ptr, /* COPY_S_W */ GPR32Opnd, MSA128WOpnd, uimm2_ptr, /* COPY_U_B */ GPR32Opnd, MSA128BOpnd, uimm4_ptr, /* COPY_U_H */ GPR32Opnd, MSA128HOpnd, uimm3_ptr, /* COPY_U_W */ GPR32Opnd, MSA128WOpnd, uimm2_ptr, /* CRC32B */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* CRC32CB */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* CRC32CD */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* CRC32CH */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* CRC32CW */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* CRC32D */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* CRC32H */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* CRC32W */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* CTC1 */ CCROpnd, GPR32Opnd, /* CTC1_MM */ CCROpnd, GPR32Opnd, /* CTC2_MM */ COP2Opnd, GPR32Opnd, /* CTCMSA */ MSA128CROpnd, GPR32Opnd, /* CVT_D32_S */ AFGR64Opnd, FGR32Opnd, /* CVT_D32_S_MM */ AFGR64Opnd, FGR32Opnd, /* CVT_D32_W */ AFGR64Opnd, FGR32Opnd, /* CVT_D32_W_MM */ AFGR64Opnd, FGR32Opnd, /* CVT_D64_L */ FGR64Opnd, FGR64Opnd, /* CVT_D64_S */ FGR64Opnd, FGR32Opnd, /* CVT_D64_S_MM */ FGR64Opnd, FGR32Opnd, /* CVT_D64_W */ FGR64Opnd, FGR32Opnd, /* CVT_D64_W_MM */ FGR64Opnd, FGR32Opnd, /* CVT_D_L_MMR6 */ FGR64Opnd, FGR64Opnd, /* CVT_L_D64 */ FGR64Opnd, FGR64Opnd, /* CVT_L_D64_MM */ FGR64Opnd, FGR64Opnd, /* CVT_L_D_MMR6 */ FGR64Opnd, FGR64Opnd, /* CVT_L_S */ FGR64Opnd, FGR32Opnd, /* CVT_L_S_MM */ FGR64Opnd, FGR32Opnd, /* CVT_L_S_MMR6 */ FGR64Opnd, FGR32Opnd, /* CVT_PS_PW64 */ FGR64Opnd, FGR64Opnd, /* CVT_PS_S64 */ FGR64Opnd, FGR32Opnd, FGR32Opnd, /* CVT_PW_PS64 */ FGR64Opnd, FGR64Opnd, /* CVT_S_D32 */ FGR32Opnd, AFGR64Opnd, /* CVT_S_D32_MM */ FGR32Opnd, AFGR64Opnd, /* CVT_S_D64 */ FGR32Opnd, FGR64Opnd, /* CVT_S_D64_MM */ FGR32Opnd, FGR64Opnd, /* CVT_S_L */ FGR32Opnd, FGR64Opnd, /* CVT_S_L_MMR6 */ FGR64Opnd, FGR32Opnd, /* CVT_S_PL64 */ FGR32Opnd, FGR64Opnd, /* CVT_S_PU64 */ FGR32Opnd, FGR64Opnd, /* CVT_S_W */ FGR32Opnd, FGR32Opnd, /* CVT_S_W_MM */ FGR32Opnd, FGR32Opnd, /* CVT_S_W_MMR6 */ FGR32Opnd, FGR32Opnd, /* CVT_W_D32 */ FGR32Opnd, AFGR64Opnd, /* CVT_W_D32_MM */ FGR32Opnd, AFGR64Opnd, /* CVT_W_D64 */ FGR32Opnd, FGR64Opnd, /* CVT_W_D64_MM */ FGR32Opnd, FGR64Opnd, /* CVT_W_S */ FGR32Opnd, FGR32Opnd, /* CVT_W_S_MM */ FGR32Opnd, FGR32Opnd, /* CVT_W_S_MMR6 */ FGR32Opnd, FGR32Opnd, /* C_EQ_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_EQ_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_EQ_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_EQ_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_EQ_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_EQ_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_F_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_F_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_F_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_F_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_F_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_F_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_LE_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_LE_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_LE_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_LE_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_LE_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_LE_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_LT_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_LT_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_LT_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_LT_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_LT_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_LT_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_NGE_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_NGE_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_NGE_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_NGE_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_NGE_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_NGE_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_NGLE_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_NGLE_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_NGLE_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_NGLE_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_NGLE_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_NGLE_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_NGL_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_NGL_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_NGL_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_NGL_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_NGL_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_NGL_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_NGT_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_NGT_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_NGT_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_NGT_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_NGT_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_NGT_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_OLE_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_OLE_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_OLE_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_OLE_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_OLE_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_OLE_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_OLT_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_OLT_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_OLT_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_OLT_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_OLT_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_OLT_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_SEQ_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_SEQ_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_SEQ_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_SEQ_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_SEQ_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_SEQ_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_SF_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_SF_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_SF_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_SF_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_SF_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_SF_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_UEQ_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_UEQ_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_UEQ_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_UEQ_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_UEQ_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_UEQ_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_ULE_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_ULE_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_ULE_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_ULE_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_ULE_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_ULE_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_ULT_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_ULT_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_ULT_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_ULT_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_ULT_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_ULT_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_UN_D32 */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_UN_D32_MM */ FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, /* C_UN_D64 */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_UN_D64_MM */ FCCRegsOpnd, FGR64Opnd, FGR64Opnd, /* C_UN_S */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* C_UN_S_MM */ FCCRegsOpnd, FGR32Opnd, FGR32Opnd, /* CmpRxRy16 */ CPU16Regs, CPU16Regs, /* CmpiRxImm16 */ CPU16Regs, simm16, /* CmpiRxImmX16 */ CPU16Regs, simm16, /* DADD */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DADDi */ GPR64Opnd, GPR64Opnd, simm16_64, /* DADDiu */ GPR64Opnd, GPR64Opnd, simm16_64, /* DADDu */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DAHI */ GPR64Opnd, GPR64Opnd, uimm16_altrelaxed, /* DALIGN */ GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm3, /* DATI */ GPR64Opnd, GPR64Opnd, uimm16_altrelaxed, /* DAUI */ GPR64Opnd, GPR64Opnd, uimm16, /* DBITSWAP */ GPR64Opnd, GPR64Opnd, /* DCLO */ GPR64Opnd, GPR64Opnd, /* DCLO_R6 */ GPR64Opnd, GPR64Opnd, /* DCLZ */ GPR64Opnd, GPR64Opnd, /* DCLZ_R6 */ GPR64Opnd, GPR64Opnd, /* DDIV */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DDIVU */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DERET */ /* DERET_MM */ /* DERET_MMR6 */ /* DEXT */ GPR64Opnd, GPR64Opnd, uimm5_report_uimm6, uimm5_plus1_report_uimm6, /* DEXT64_32 */ GPR64Opnd, GPR32Opnd, uimm5_report_uimm6, uimm5_plus1, /* DEXTM */ GPR64Opnd, GPR64Opnd, uimm5, uimm5_plus33, /* DEXTU */ GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_plus1, /* DI */ GPR32Opnd, /* DINS */ GPR64Opnd, GPR64Opnd, uimm6, uimm5_inssize_plus1, GPR64Opnd, /* DINSM */ GPR64Opnd, GPR64Opnd, uimm5, uimm_range_2_64, GPR64Opnd, /* DINSU */ GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1, GPR64Opnd, /* DIV */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* DIVU */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* DIVU_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* DIV_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* DIV_S_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* DIV_S_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* DIV_S_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* DIV_S_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* DIV_U_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* DIV_U_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* DIV_U_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* DIV_U_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* DI_MM */ GPR32Opnd, /* DI_MMR6 */ GPR32Opnd, /* DLSA */ GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1, /* DLSA_R6 */ GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1, /* DMFC0 */ GPR64Opnd, COP0Opnd, uimm3, /* DMFC1 */ GPR64Opnd, FGR64Opnd, /* DMFC2 */ GPR64Opnd, COP2Opnd, uimm3, /* DMFC2_OCTEON */ GPR64Opnd, uimm16, /* DMFGC0 */ GPR64Opnd, COP0Opnd, uimm3, /* DMOD */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DMODU */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DMT */ GPR32Opnd, /* DMTC0 */ COP0Opnd, GPR64Opnd, uimm3, /* DMTC1 */ FGR64Opnd, GPR64Opnd, /* DMTC2 */ COP2Opnd, GPR64Opnd, uimm3, /* DMTC2_OCTEON */ GPR64Opnd, uimm16, /* DMTGC0 */ COP0Opnd, GPR64Opnd, uimm3, /* DMUH */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DMUHU */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DMUL */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DMULT */ GPR64Opnd, GPR64Opnd, /* DMULTu */ GPR64Opnd, GPR64Opnd, /* DMULU */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DMUL_R6 */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DOTP_S_D */ MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, /* DOTP_S_H */ MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, /* DOTP_S_W */ MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, /* DOTP_U_D */ MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, /* DOTP_U_H */ MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, /* DOTP_U_W */ MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, /* DPADD_S_D */ MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, /* DPADD_S_H */ MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, /* DPADD_S_W */ MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, /* DPADD_U_D */ MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, /* DPADD_U_H */ MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, /* DPADD_U_W */ MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, /* DPAQX_SA_W_PH */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPAQX_SA_W_PH_MMR2 */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPAQX_S_W_PH */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPAQX_S_W_PH_MMR2 */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPAQ_SA_L_W */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPAQ_SA_L_W_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPAQ_S_W_PH */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPAQ_S_W_PH_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPAU_H_QBL */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPAU_H_QBL_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPAU_H_QBR */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPAU_H_QBR_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPAX_W_PH */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPAX_W_PH_MMR2 */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPA_W_PH */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPA_W_PH_MMR2 */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPOP */ GPR64Opnd, GPR64Opnd, /* DPSQX_SA_W_PH */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPSQX_SA_W_PH_MMR2 */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPSQX_S_W_PH */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPSQX_S_W_PH_MMR2 */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPSQ_SA_L_W */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPSQ_SA_L_W_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPSQ_S_W_PH */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPSQ_S_W_PH_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPSUB_S_D */ MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, /* DPSUB_S_H */ MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, /* DPSUB_S_W */ MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, /* DPSUB_U_D */ MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, /* DPSUB_U_H */ MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, /* DPSUB_U_W */ MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, /* DPSU_H_QBL */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPSU_H_QBL_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPSU_H_QBR */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPSU_H_QBR_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPSX_W_PH */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPSX_W_PH_MMR2 */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPS_W_PH */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DPS_W_PH_MMR2 */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* DROTR */ GPR64Opnd, GPR64Opnd, uimm6, /* DROTR32 */ GPR64Opnd, GPR64Opnd, uimm5, /* DROTRV */ GPR64Opnd, GPR64Opnd, GPR32Opnd, /* DSBH */ GPR64Opnd, GPR64Opnd, /* DSDIV */ GPR64Opnd, GPR64Opnd, /* DSHD */ GPR64Opnd, GPR64Opnd, /* DSLL */ GPR64Opnd, GPR64Opnd, uimm6, /* DSLL32 */ GPR64Opnd, GPR64Opnd, uimm5, /* DSLL64_32 */ GPR64, GPR32, /* DSLLV */ GPR64Opnd, GPR64Opnd, GPR32Opnd, /* DSRA */ GPR64Opnd, GPR64Opnd, uimm6, /* DSRA32 */ GPR64Opnd, GPR64Opnd, uimm5, /* DSRAV */ GPR64Opnd, GPR64Opnd, GPR32Opnd, /* DSRL */ GPR64Opnd, GPR64Opnd, uimm6, /* DSRL32 */ GPR64Opnd, GPR64Opnd, uimm5, /* DSRLV */ GPR64Opnd, GPR64Opnd, GPR32Opnd, /* DSUB */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DSUBu */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* DUDIV */ GPR64Opnd, GPR64Opnd, /* DVP */ GPR32Opnd, /* DVPE */ GPR32Opnd, /* DVP_MMR6 */ GPR32Opnd, /* DivRxRy16 */ CPU16Regs, CPU16Regs, /* DivuRxRy16 */ CPU16Regs, CPU16Regs, /* EHB */ /* EHB_MM */ /* EHB_MMR6 */ /* EI */ GPR32Opnd, /* EI_MM */ GPR32Opnd, /* EI_MMR6 */ GPR32Opnd, /* EMT */ GPR32Opnd, /* ERET */ /* ERETNC */ /* ERETNC_MMR6 */ /* ERET_MM */ /* ERET_MMR6 */ /* EVP */ GPR32Opnd, /* EVPE */ GPR32Opnd, /* EVP_MMR6 */ GPR32Opnd, /* EXT */ GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1, /* EXTP */ GPR32Opnd, ACC64DSPOpnd, uimm5, /* EXTPDP */ GPR32Opnd, ACC64DSPOpnd, uimm5, /* EXTPDPV */ GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, /* EXTPDPV_MM */ GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, /* EXTPDP_MM */ GPR32Opnd, ACC64DSPOpnd, uimm5, /* EXTPV */ GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, /* EXTPV_MM */ GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, /* EXTP_MM */ GPR32Opnd, ACC64DSPOpnd, uimm5, /* EXTRV_RS_W */ GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, /* EXTRV_RS_W_MM */ GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, /* EXTRV_R_W */ GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, /* EXTRV_R_W_MM */ GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, /* EXTRV_S_H */ GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, /* EXTRV_S_H_MM */ GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, /* EXTRV_W */ GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, /* EXTRV_W_MM */ GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, /* EXTR_RS_W */ GPR32Opnd, ACC64DSPOpnd, uimm5, /* EXTR_RS_W_MM */ GPR32Opnd, ACC64DSPOpnd, uimm5, /* EXTR_R_W */ GPR32Opnd, ACC64DSPOpnd, uimm5, /* EXTR_R_W_MM */ GPR32Opnd, ACC64DSPOpnd, uimm5, /* EXTR_S_H */ GPR32Opnd, ACC64DSPOpnd, uimm5, /* EXTR_S_H_MM */ GPR32Opnd, ACC64DSPOpnd, uimm5, /* EXTR_W */ GPR32Opnd, ACC64DSPOpnd, uimm5, /* EXTR_W_MM */ GPR32Opnd, ACC64DSPOpnd, uimm5, /* EXTS */ GPR64Opnd, GPR64Opnd, uimm5, uimm5, /* EXTS32 */ GPR64Opnd, GPR64Opnd, uimm5, uimm5, /* EXT_MM */ GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1, /* EXT_MMR6 */ GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1, /* FABS_D32 */ AFGR64Opnd, AFGR64Opnd, /* FABS_D32_MM */ AFGR64Opnd, AFGR64Opnd, /* FABS_D64 */ FGR64Opnd, FGR64Opnd, /* FABS_D64_MM */ FGR64Opnd, FGR64Opnd, /* FABS_S */ FGR32Opnd, FGR32Opnd, /* FABS_S_MM */ FGR32Opnd, FGR32Opnd, /* FADD_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FADD_D32 */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* FADD_D32_MM */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* FADD_D64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* FADD_D64_MM */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* FADD_PS64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* FADD_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* FADD_S_MM */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* FADD_S_MMR6 */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* FADD_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FCAF_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FCAF_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FCEQ_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FCEQ_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FCLASS_D */ MSA128DOpnd, MSA128DOpnd, /* FCLASS_W */ MSA128WOpnd, MSA128WOpnd, /* FCLE_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FCLE_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FCLT_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FCLT_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FCMP_D32 */ AFGR64, AFGR64, condcode, /* FCMP_D32_MM */ AFGR64, AFGR64, condcode, /* FCMP_D64 */ FGR64, FGR64, condcode, /* FCMP_S32 */ FGR32, FGR32, condcode, /* FCMP_S32_MM */ FGR32, FGR32, condcode, /* FCNE_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FCNE_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FCOR_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FCOR_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FCUEQ_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FCUEQ_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FCULE_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FCULE_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FCULT_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FCULT_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FCUNE_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FCUNE_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FCUN_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FCUN_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FDIV_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FDIV_D32 */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* FDIV_D32_MM */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* FDIV_D64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* FDIV_D64_MM */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* FDIV_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* FDIV_S_MM */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* FDIV_S_MMR6 */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* FDIV_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FEXDO_H */ MSA128HOpnd, MSA128WOpnd, MSA128WOpnd, /* FEXDO_W */ MSA128WOpnd, MSA128DOpnd, MSA128DOpnd, /* FEXP2_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FEXP2_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FEXUPL_D */ MSA128DOpnd, MSA128WOpnd, /* FEXUPL_W */ MSA128WOpnd, MSA128HOpnd, /* FEXUPR_D */ MSA128DOpnd, MSA128WOpnd, /* FEXUPR_W */ MSA128WOpnd, MSA128HOpnd, /* FFINT_S_D */ MSA128DOpnd, MSA128DOpnd, /* FFINT_S_W */ MSA128WOpnd, MSA128WOpnd, /* FFINT_U_D */ MSA128DOpnd, MSA128DOpnd, /* FFINT_U_W */ MSA128WOpnd, MSA128WOpnd, /* FFQL_D */ MSA128DOpnd, MSA128WOpnd, /* FFQL_W */ MSA128WOpnd, MSA128HOpnd, /* FFQR_D */ MSA128DOpnd, MSA128WOpnd, /* FFQR_W */ MSA128WOpnd, MSA128HOpnd, /* FILL_B */ MSA128BOpnd, GPR32Opnd, /* FILL_D */ MSA128DOpnd, GPR64Opnd, /* FILL_H */ MSA128HOpnd, GPR32Opnd, /* FILL_W */ MSA128WOpnd, GPR32Opnd, /* FLOG2_D */ MSA128DOpnd, MSA128DOpnd, /* FLOG2_W */ MSA128WOpnd, MSA128WOpnd, /* FLOOR_L_D64 */ FGR64Opnd, FGR64Opnd, /* FLOOR_L_D_MMR6 */ FGR64Opnd, FGR64Opnd, /* FLOOR_L_S */ FGR64Opnd, FGR32Opnd, /* FLOOR_L_S_MMR6 */ FGR64Opnd, FGR32Opnd, /* FLOOR_W_D32 */ FGR32Opnd, AFGR64Opnd, /* FLOOR_W_D64 */ FGR32Opnd, FGR64Opnd, /* FLOOR_W_D_MMR6 */ FGR32Opnd, AFGR64Opnd, /* FLOOR_W_MM */ FGR32Opnd, AFGR64Opnd, /* FLOOR_W_S */ FGR32Opnd, FGR32Opnd, /* FLOOR_W_S_MM */ FGR32Opnd, FGR32Opnd, /* FLOOR_W_S_MMR6 */ FGR32Opnd, FGR32Opnd, /* FMADD_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FMADD_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FMAX_A_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FMAX_A_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FMAX_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FMAX_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FMIN_A_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FMIN_A_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FMIN_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FMIN_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FMOV_D32 */ AFGR64Opnd, AFGR64Opnd, /* FMOV_D32_MM */ AFGR64Opnd, AFGR64Opnd, /* FMOV_D64 */ FGR64Opnd, FGR64Opnd, /* FMOV_D64_MM */ FGR64Opnd, FGR64Opnd, /* FMOV_D_MMR6 */ FGR64Opnd, FGR64Opnd, /* FMOV_S */ FGR32Opnd, FGR32Opnd, /* FMOV_S_MM */ FGR32Opnd, FGR32Opnd, /* FMOV_S_MMR6 */ FGR32Opnd, FGR32Opnd, /* FMSUB_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FMSUB_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FMUL_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FMUL_D32 */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* FMUL_D32_MM */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* FMUL_D64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* FMUL_D64_MM */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* FMUL_PS64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* FMUL_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* FMUL_S_MM */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* FMUL_S_MMR6 */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* FMUL_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FNEG_D32 */ AFGR64Opnd, AFGR64Opnd, /* FNEG_D32_MM */ AFGR64Opnd, AFGR64Opnd, /* FNEG_D64 */ FGR64Opnd, FGR64Opnd, /* FNEG_D64_MM */ FGR64Opnd, FGR64Opnd, /* FNEG_S */ FGR32Opnd, FGR32Opnd, /* FNEG_S_MM */ FGR32Opnd, FGR32Opnd, /* FNEG_S_MMR6 */ FGR32Opnd, FGR32Opnd, /* FORK */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* FRCP_D */ MSA128DOpnd, MSA128DOpnd, /* FRCP_W */ MSA128WOpnd, MSA128WOpnd, /* FRINT_D */ MSA128DOpnd, MSA128DOpnd, /* FRINT_W */ MSA128WOpnd, MSA128WOpnd, /* FRSQRT_D */ MSA128DOpnd, MSA128DOpnd, /* FRSQRT_W */ MSA128WOpnd, MSA128WOpnd, /* FSAF_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FSAF_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FSEQ_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FSEQ_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FSLE_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FSLE_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FSLT_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FSLT_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FSNE_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FSNE_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FSOR_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FSOR_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FSQRT_D */ MSA128DOpnd, MSA128DOpnd, /* FSQRT_D32 */ AFGR64Opnd, AFGR64Opnd, /* FSQRT_D32_MM */ AFGR64Opnd, AFGR64Opnd, /* FSQRT_D64 */ FGR64Opnd, FGR64Opnd, /* FSQRT_D64_MM */ FGR64Opnd, FGR64Opnd, /* FSQRT_S */ FGR32Opnd, FGR32Opnd, /* FSQRT_S_MM */ FGR32Opnd, FGR32Opnd, /* FSQRT_W */ MSA128WOpnd, MSA128WOpnd, /* FSUB_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FSUB_D32 */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* FSUB_D32_MM */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* FSUB_D64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* FSUB_D64_MM */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* FSUB_PS64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* FSUB_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* FSUB_S_MM */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* FSUB_S_MMR6 */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* FSUB_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FSUEQ_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FSUEQ_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FSULE_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FSULE_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FSULT_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FSULT_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FSUNE_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FSUNE_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FSUN_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* FSUN_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* FTINT_S_D */ MSA128DOpnd, MSA128DOpnd, /* FTINT_S_W */ MSA128WOpnd, MSA128WOpnd, /* FTINT_U_D */ MSA128DOpnd, MSA128DOpnd, /* FTINT_U_W */ MSA128WOpnd, MSA128WOpnd, /* FTQ_H */ MSA128HOpnd, MSA128WOpnd, MSA128WOpnd, /* FTQ_W */ MSA128WOpnd, MSA128DOpnd, MSA128DOpnd, /* FTRUNC_S_D */ MSA128DOpnd, MSA128DOpnd, /* FTRUNC_S_W */ MSA128WOpnd, MSA128WOpnd, /* FTRUNC_U_D */ MSA128DOpnd, MSA128DOpnd, /* FTRUNC_U_W */ MSA128WOpnd, MSA128WOpnd, /* GINVI */ GPR32Opnd, /* GINVI_MMR6 */ GPR32Opnd, /* GINVT */ GPR32Opnd, uimm2, /* GINVT_MMR6 */ GPR32Opnd, uimm2, /* HADD_S_D */ MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, /* HADD_S_H */ MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, /* HADD_S_W */ MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, /* HADD_U_D */ MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, /* HADD_U_H */ MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, /* HADD_U_W */ MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, /* HSUB_S_D */ MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, /* HSUB_S_H */ MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, /* HSUB_S_W */ MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, /* HSUB_U_D */ MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, /* HSUB_U_H */ MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, /* HSUB_U_W */ MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, /* HYPCALL */ uimm10, /* HYPCALL_MM */ uimm10, /* ILVEV_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* ILVEV_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* ILVEV_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* ILVEV_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* ILVL_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* ILVL_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* ILVL_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* ILVL_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* ILVOD_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* ILVOD_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* ILVOD_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* ILVOD_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* ILVR_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* ILVR_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* ILVR_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* ILVR_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* INS */ GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd, /* INSERT_B */ MSA128BOpnd, MSA128BOpnd, GPR32Opnd, uimm4, /* INSERT_D */ MSA128DOpnd, MSA128DOpnd, GPR64Opnd, uimm1, /* INSERT_H */ MSA128HOpnd, MSA128HOpnd, GPR32Opnd, uimm3, /* INSERT_W */ MSA128WOpnd, MSA128WOpnd, GPR32Opnd, uimm2, /* INSV */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* INSVE_B */ MSA128BOpnd, MSA128BOpnd, uimm4, MSA128BOpnd, uimmz, /* INSVE_D */ MSA128DOpnd, MSA128DOpnd, uimm1, MSA128DOpnd, uimmz, /* INSVE_H */ MSA128HOpnd, MSA128HOpnd, uimm3, MSA128HOpnd, uimmz, /* INSVE_W */ MSA128WOpnd, MSA128WOpnd, uimm2, MSA128WOpnd, uimmz, /* INSV_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* INS_MM */ GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd, /* INS_MMR6 */ GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd, /* J */ jmptarget, /* JAL */ calltarget, /* JALR */ GPR32Opnd, GPR32Opnd, /* JALR16_MM */ GPR32Opnd, /* JALR64 */ GPR64Opnd, GPR64Opnd, /* JALRC16_MMR6 */ GPR32Opnd, /* JALRC_HB_MMR6 */ GPR32Opnd, GPR32Opnd, /* JALRC_MMR6 */ GPR32Opnd, GPR32Opnd, /* JALRS16_MM */ GPR32Opnd, /* JALRS_MM */ GPR32Opnd, GPR32Opnd, /* JALR_HB */ GPR32Opnd, GPR32Opnd, /* JALR_HB64 */ GPR64Opnd, GPR64Opnd, /* JALR_MM */ GPR32Opnd, GPR32Opnd, /* JALS_MM */ calltarget_mm, /* JALX */ calltarget, /* JALX_MM */ calltarget, /* JAL_MM */ calltarget_mm, /* JIALC */ GPR32Opnd, calloffset16, /* JIALC64 */ GPR64Opnd, calloffset16, /* JIALC_MMR6 */ GPR32Opnd, calloffset16, /* JIC */ GPR32Opnd, jmpoffset16, /* JIC64 */ GPR64Opnd, jmpoffset16, /* JIC_MMR6 */ GPR32Opnd, jmpoffset16, /* JR */ GPR32Opnd, /* JR16_MM */ GPR32Opnd, /* JR64 */ GPR64Opnd, /* JRADDIUSP */ uimm5_lsl2, /* JRC16_MM */ GPR32Opnd, /* JRC16_MMR6 */ GPR32Opnd, /* JRCADDIUSP_MMR6 */ uimm5_lsl2, /* JR_HB */ GPR32Opnd, /* JR_HB64 */ GPR64Opnd, /* JR_HB64_R6 */ GPR64Opnd, /* JR_HB_R6 */ GPR32Opnd, /* JR_MM */ GPR32Opnd, /* J_MM */ jmptarget_mm, /* Jal16 */ uimm26, /* JalB16 */ uimm26, /* JrRa16 */ /* JrcRa16 */ /* JrcRx16 */ CPU16Regs, /* JumpLinkReg16 */ CPU16Regs, /* LB */ GPR32Opnd, -1, simm16, /* LB64 */ GPR64Opnd, -1, simm16, /* LBE */ GPR32Opnd, -1, simm9, /* LBE_MM */ GPR32Opnd, -1, simm16, /* LBU16_MM */ GPRMM16Opnd, -1, simm4, /* LBUX */ GPR32Opnd, -1, -1, /* LBUX_MM */ GPR32Opnd, -1, -1, /* LBU_MMR6 */ GPR32Opnd, -1, simm16, /* LB_MM */ GPR32Opnd, -1, simm16, /* LB_MMR6 */ GPR32Opnd, -1, simm16, /* LBu */ GPR32Opnd, -1, simm16, /* LBu64 */ GPR64Opnd, -1, simm16, /* LBuE */ GPR32Opnd, -1, simm9, /* LBuE_MM */ GPR32Opnd, -1, simm16, /* LBu_MM */ GPR32Opnd, -1, simm16, /* LD */ GPR64Opnd, -1, simm16, /* LDC1 */ AFGR64Opnd, -1, simm16, /* LDC164 */ FGR64Opnd, -1, simm16, /* LDC1_D64_MMR6 */ FGR64Opnd, -1, simm16, /* LDC1_MM_D32 */ AFGR64Opnd, -1, simm16, /* LDC1_MM_D64 */ FGR64Opnd, -1, simm16, /* LDC2 */ COP2Opnd, -1, simm16, /* LDC2_MMR6 */ COP2Opnd, GPR32, simm11, /* LDC2_R6 */ COP2Opnd, -1, simm11, /* LDC3 */ COP3Opnd, -1, simm16, /* LDI_B */ MSA128BOpnd, vsplat_simm10, /* LDI_D */ MSA128DOpnd, vsplat_simm10, /* LDI_H */ MSA128HOpnd, vsplat_simm10, /* LDI_W */ MSA128WOpnd, vsplat_simm10, /* LDL */ GPR64Opnd, -1, simm16, GPR64Opnd, /* LDPC */ GPR64Opnd, simm18_lsl3, /* LDR */ GPR64Opnd, -1, simm16, GPR64Opnd, /* LDXC1 */ AFGR64Opnd, -1, -1, /* LDXC164 */ FGR64Opnd, -1, -1, /* LD_B */ MSA128BOpnd, -1, simm10, /* LD_D */ MSA128DOpnd, -1, simm10_lsl3, /* LD_H */ MSA128HOpnd, -1, simm10_lsl1, /* LD_W */ MSA128WOpnd, -1, simm10_lsl2, /* LEA_ADDiu */ GPR32Opnd, -1, simm16, /* LEA_ADDiu64 */ GPR64Opnd, -1, simm16, /* LEA_ADDiu_MM */ GPR32Opnd, -1, simm16, /* LH */ GPR32Opnd, -1, simm16, /* LH64 */ GPR64Opnd, -1, simm16, /* LHE */ GPR32Opnd, -1, simm9, /* LHE_MM */ GPR32Opnd, -1, simm9, /* LHU16_MM */ GPRMM16Opnd, -1, simm4, /* LHX */ GPR32Opnd, -1, -1, /* LHX_MM */ GPR32Opnd, -1, -1, /* LH_MM */ GPR32Opnd, -1, simm16, /* LHu */ GPR32Opnd, -1, simm16, /* LHu64 */ GPR64Opnd, -1, simm16, /* LHuE */ GPR32Opnd, -1, simm9, /* LHuE_MM */ GPR32Opnd, -1, simm9, /* LHu_MM */ GPR32Opnd, -1, simm16, /* LI16_MM */ GPRMM16Opnd, li16_imm, /* LI16_MMR6 */ GPRMM16Opnd, li16_imm, /* LL */ GPR32Opnd, -1, simm16, /* LL64 */ GPR32Opnd, -1, simm16, /* LL64_R6 */ GPR32Opnd, -1, simm9, /* LLD */ GPR64Opnd, -1, simm16, /* LLD_R6 */ GPR64Opnd, -1, simm9, /* LLE */ GPR32Opnd, -1, simm9, /* LLE_MM */ GPR32Opnd, -1, simm9, /* LL_MM */ GPR32Opnd, -1, simm12, /* LL_MMR6 */ GPR32Opnd, -1, simm9, /* LL_R6 */ GPR32Opnd, -1, simm9, /* LSA */ GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1, /* LSA_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1, /* LSA_R6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1, /* LUI_MMR6 */ GPR32Opnd, uimm16, /* LUXC1 */ AFGR64Opnd, -1, -1, /* LUXC164 */ FGR64Opnd, -1, -1, /* LUXC1_MM */ FGR64Opnd, -1, -1, /* LUi */ GPR32Opnd, uimm16_relaxed, /* LUi64 */ GPR64Opnd, uimm16_64_relaxed, /* LUi_MM */ GPR32Opnd, uimm16_relaxed, /* LW */ GPR32Opnd, -1, simm16, /* LW16_MM */ GPRMM16Opnd, -1, simm4, /* LW64 */ GPR64Opnd, -1, simm16, /* LWC1 */ FGR32Opnd, -1, simm16, /* LWC1_MM */ FGR32Opnd, -1, simm16, /* LWC2 */ COP2Opnd, -1, simm16, /* LWC2_MMR6 */ COP2Opnd, GPR32, simm11, /* LWC2_R6 */ COP2Opnd, -1, simm11, /* LWC3 */ COP3Opnd, -1, simm16, /* LWDSP */ DSPROpnd, -1, simm16, /* LWDSP_MM */ DSPROpnd, -1, simm16, /* LWE */ GPR32Opnd, -1, simm9, /* LWE_MM */ GPR32Opnd, -1, simm9, /* LWGP_MM */ GPRMM16Opnd, -1, simm7_lsl2, /* LWL */ GPR32Opnd, -1, simm16, GPR32Opnd, /* LWL64 */ GPR64Opnd, -1, simm16, GPR64Opnd, /* LWLE */ GPR32Opnd, -1, simm9, GPR32Opnd, /* LWLE_MM */ GPR32Opnd, -1, simm9, GPR32Opnd, /* LWL_MM */ GPR32Opnd, -1, simm12, GPR32Opnd, /* LWM16_MM */ reglist16, -1, uimm8, /* LWM16_MMR6 */ reglist16, -1, uimm8, /* LWM32_MM */ reglist, -1, simm12, /* LWPC */ GPR32Opnd, simm19_lsl2, /* LWPC_MMR6 */ GPR32Opnd, simm19_lsl2, /* LWP_MM */ GPR32Opnd, GPR32Opnd, -1, simm12, /* LWR */ GPR32Opnd, -1, simm16, GPR32Opnd, /* LWR64 */ GPR64Opnd, -1, simm16, GPR64Opnd, /* LWRE */ GPR32Opnd, -1, simm9, GPR32Opnd, /* LWRE_MM */ GPR32Opnd, -1, simm9, GPR32Opnd, /* LWR_MM */ GPR32Opnd, -1, simm12, GPR32Opnd, /* LWSP_MM */ GPR32Opnd, -1, simm5, /* LWUPC */ GPR32Opnd, simm19_lsl2, /* LWU_MM */ GPR32Opnd, -1, simm12, /* LWX */ GPR32Opnd, -1, -1, /* LWXC1 */ FGR32Opnd, -1, -1, /* LWXC1_MM */ FGR32Opnd, -1, -1, /* LWXS_MM */ GPR32Opnd, -1, -1, /* LWX_MM */ GPR32Opnd, -1, -1, /* LW_MM */ GPR32Opnd, -1, simm16, /* LW_MMR6 */ GPR32Opnd, -1, simm16, /* LWu */ GPR64Opnd, -1, simm16, /* LbRxRyOffMemX16 */ CPU16Regs, CPU16Regs, simm16, /* LbuRxRyOffMemX16 */ CPU16Regs, CPU16Regs, simm16, /* LhRxRyOffMemX16 */ CPU16Regs, CPU16Regs, simm16, /* LhuRxRyOffMemX16 */ CPU16Regs, CPU16Regs, simm16, /* LiRxImm16 */ CPU16Regs, simm16, /* LiRxImmAlignX16 */ CPU16Regs, simm16, /* LiRxImmX16 */ CPU16Regs, simm16, /* LwRxPcTcp16 */ CPU16Regs, pcrel16, i32imm, /* LwRxPcTcpX16 */ CPU16Regs, pcrel16, i32imm, /* LwRxRyOffMemX16 */ CPU16Regs, CPU16Regs, simm16, /* LwRxSpImmX16 */ CPU16Regs, CPU16RegsPlusSP, simm16, /* MADD */ GPR32Opnd, GPR32Opnd, /* MADDF_D */ FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, /* MADDF_D_MMR6 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, /* MADDF_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MADDF_S_MMR6 */ FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MADDR_Q_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MADDR_Q_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MADDU */ GPR32Opnd, GPR32Opnd, /* MADDU_DSP */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MADDU_DSP_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MADDU_MM */ GPR32Opnd, GPR32Opnd, /* MADDV_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* MADDV_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* MADDV_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MADDV_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MADD_D32 */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* MADD_D32_MM */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* MADD_D64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, /* MADD_DSP */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MADD_DSP_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MADD_MM */ GPR32Opnd, GPR32Opnd, /* MADD_Q_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MADD_Q_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MADD_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MADD_S_MM */ FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MAQ_SA_W_PHL */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MAQ_SA_W_PHL_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MAQ_SA_W_PHR */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MAQ_SA_W_PHR_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MAQ_S_W_PHL */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MAQ_S_W_PHL_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MAQ_S_W_PHR */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MAQ_S_W_PHR_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MAXA_D */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* MAXA_D_MMR6 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* MAXA_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MAXA_S_MMR6 */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MAXI_S_B */ MSA128BOpnd, MSA128BOpnd, vsplat_simm5, /* MAXI_S_D */ MSA128DOpnd, MSA128DOpnd, vsplat_simm5, /* MAXI_S_H */ MSA128HOpnd, MSA128HOpnd, vsplat_simm5, /* MAXI_S_W */ MSA128WOpnd, MSA128WOpnd, vsplat_simm5, /* MAXI_U_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, /* MAXI_U_D */ MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, /* MAXI_U_H */ MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, /* MAXI_U_W */ MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, /* MAX_A_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* MAX_A_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* MAX_A_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MAX_A_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MAX_D */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* MAX_D_MMR6 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* MAX_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MAX_S_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* MAX_S_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* MAX_S_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MAX_S_MMR6 */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MAX_S_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MAX_U_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* MAX_U_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* MAX_U_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MAX_U_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MFC0 */ GPR32Opnd, COP0Opnd, uimm3, /* MFC0_MMR6 */ GPR32Opnd, COP0Opnd, uimm3, /* MFC1 */ GPR32Opnd, FGR32Opnd, /* MFC1_D64 */ GPR32Opnd, FGR64Opnd, /* MFC1_MM */ GPR32Opnd, FGR32Opnd, /* MFC1_MMR6 */ GPR32Opnd, FGR32Opnd, /* MFC2 */ GPR32Opnd, COP2Opnd, uimm3, /* MFC2_MMR6 */ GPR32Opnd, COP2Opnd, /* MFGC0 */ GPR32Opnd, COP0Opnd, uimm3, /* MFGC0_MM */ GPR32Opnd, COP0Opnd, uimm3, /* MFHC0_MMR6 */ GPR32Opnd, COP0Opnd, uimm3, /* MFHC1_D32 */ GPR32Opnd, AFGR64Opnd, /* MFHC1_D32_MM */ GPR32Opnd, AFGR64Opnd, /* MFHC1_D64 */ GPR32Opnd, FGR64Opnd, /* MFHC1_D64_MM */ GPR32Opnd, FGR64Opnd, /* MFHC2_MMR6 */ GPR32Opnd, COP2Opnd, /* MFHGC0 */ GPR32Opnd, COP0Opnd, uimm3, /* MFHGC0_MM */ GPR32Opnd, COP0Opnd, uimm3, /* MFHI */ GPR32Opnd, /* MFHI16_MM */ GPR32Opnd, /* MFHI64 */ GPR64Opnd, /* MFHI_DSP */ GPR32Opnd, ACC64DSPOpnd, /* MFHI_DSP_MM */ GPR32Opnd, ACC64DSPOpnd, /* MFHI_MM */ GPR32Opnd, /* MFLO */ GPR32Opnd, /* MFLO16_MM */ GPR32Opnd, /* MFLO64 */ GPR64Opnd, /* MFLO_DSP */ GPR32Opnd, ACC64DSPOpnd, /* MFLO_DSP_MM */ GPR32Opnd, ACC64DSPOpnd, /* MFLO_MM */ GPR32Opnd, /* MFTR */ GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1, /* MINA_D */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* MINA_D_MMR6 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* MINA_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MINA_S_MMR6 */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MINI_S_B */ MSA128BOpnd, MSA128BOpnd, vsplat_simm5, /* MINI_S_D */ MSA128DOpnd, MSA128DOpnd, vsplat_simm5, /* MINI_S_H */ MSA128HOpnd, MSA128HOpnd, vsplat_simm5, /* MINI_S_W */ MSA128WOpnd, MSA128WOpnd, vsplat_simm5, /* MINI_U_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, /* MINI_U_D */ MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, /* MINI_U_H */ MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, /* MINI_U_W */ MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, /* MIN_A_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* MIN_A_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* MIN_A_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MIN_A_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MIN_D */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* MIN_D_MMR6 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* MIN_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MIN_S_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* MIN_S_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* MIN_S_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MIN_S_MMR6 */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MIN_S_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MIN_U_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* MIN_U_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* MIN_U_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MIN_U_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MOD */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MODSUB */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MODSUB_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MODU */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MODU_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MOD_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MOD_S_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* MOD_S_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* MOD_S_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MOD_S_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MOD_U_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* MOD_U_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* MOD_U_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MOD_U_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MOVE16_MM */ GPR32Opnd, GPR32Opnd, /* MOVE16_MMR6 */ GPR32Opnd, GPR32Opnd, /* MOVEP_MM */ GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP, /* MOVEP_MMR6 */ GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP, /* MOVE_V */ MSA128BOpnd, MSA128BOpnd, /* MOVF_D32 */ AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, /* MOVF_D32_MM */ AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, /* MOVF_D64 */ FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd, /* MOVF_I */ GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, /* MOVF_I64 */ GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd, /* MOVF_I_MM */ GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, /* MOVF_S */ FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, /* MOVF_S_MM */ FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, /* MOVN_I64_D64 */ FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd, /* MOVN_I64_I */ GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd, /* MOVN_I64_I64 */ GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, /* MOVN_I64_S */ FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd, /* MOVN_I_D32 */ AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, /* MOVN_I_D32_MM */ AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, /* MOVN_I_D64 */ FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd, /* MOVN_I_I */ GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MOVN_I_I64 */ GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, /* MOVN_I_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MOVN_I_S */ FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, /* MOVN_I_S_MM */ FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, /* MOVT_D32 */ AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, /* MOVT_D32_MM */ AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, /* MOVT_D64 */ FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd, /* MOVT_I */ GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, /* MOVT_I64 */ GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd, /* MOVT_I_MM */ GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, /* MOVT_S */ FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, /* MOVT_S_MM */ FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, /* MOVZ_I64_D64 */ FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd, /* MOVZ_I64_I */ GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd, /* MOVZ_I64_I64 */ GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, /* MOVZ_I64_S */ FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd, /* MOVZ_I_D32 */ AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, /* MOVZ_I_D32_MM */ AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, /* MOVZ_I_D64 */ FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd, /* MOVZ_I_I */ GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MOVZ_I_I64 */ GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, /* MOVZ_I_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MOVZ_I_S */ FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, /* MOVZ_I_S_MM */ FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, /* MSUB */ GPR32Opnd, GPR32Opnd, /* MSUBF_D */ FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, /* MSUBF_D_MMR6 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, /* MSUBF_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MSUBF_S_MMR6 */ FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MSUBR_Q_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MSUBR_Q_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MSUBU */ GPR32Opnd, GPR32Opnd, /* MSUBU_DSP */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MSUBU_DSP_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MSUBU_MM */ GPR32Opnd, GPR32Opnd, /* MSUBV_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* MSUBV_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* MSUBV_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MSUBV_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MSUB_D32 */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* MSUB_D32_MM */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* MSUB_D64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, /* MSUB_DSP */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MSUB_DSP_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MSUB_MM */ GPR32Opnd, GPR32Opnd, /* MSUB_Q_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MSUB_Q_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MSUB_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MSUB_S_MM */ FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, /* MTC0 */ COP0Opnd, GPR32Opnd, uimm3, /* MTC0_MMR6 */ COP0Opnd, GPR32Opnd, uimm3, /* MTC1 */ FGR32Opnd, GPR32Opnd, /* MTC1_D64 */ FGR64Opnd, GPR32Opnd, /* MTC1_D64_MM */ FGR64Opnd, GPR32Opnd, /* MTC1_MM */ FGR32Opnd, GPR32Opnd, /* MTC1_MMR6 */ FGR32Opnd, GPR32Opnd, /* MTC2 */ COP2Opnd, GPR32Opnd, uimm3, /* MTC2_MMR6 */ COP2Opnd, GPR32Opnd, /* MTGC0 */ COP0Opnd, GPR32Opnd, uimm3, /* MTGC0_MM */ COP0Opnd, GPR32Opnd, uimm3, /* MTHC0_MMR6 */ COP0Opnd, GPR32Opnd, uimm3, /* MTHC1_D32 */ AFGR64Opnd, AFGR64Opnd, GPR32Opnd, /* MTHC1_D32_MM */ AFGR64Opnd, AFGR64Opnd, GPR32Opnd, /* MTHC1_D64 */ FGR64Opnd, FGR64Opnd, GPR32Opnd, /* MTHC1_D64_MM */ FGR64Opnd, FGR64Opnd, GPR32Opnd, /* MTHC2_MMR6 */ COP2Opnd, GPR32Opnd, /* MTHGC0 */ COP0Opnd, GPR32Opnd, uimm3, /* MTHGC0_MM */ COP0Opnd, GPR32Opnd, uimm3, /* MTHI */ GPR32Opnd, /* MTHI64 */ GPR64Opnd, /* MTHI_DSP */ HI32DSPOpnd, GPR32Opnd, /* MTHI_DSP_MM */ HI32DSPOpnd, GPR32Opnd, /* MTHI_MM */ GPR32Opnd, /* MTHLIP */ ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, /* MTHLIP_MM */ ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, /* MTLO */ GPR32Opnd, /* MTLO64 */ GPR64Opnd, /* MTLO_DSP */ LO32DSPOpnd, GPR32Opnd, /* MTLO_DSP_MM */ LO32DSPOpnd, GPR32Opnd, /* MTLO_MM */ GPR32Opnd, /* MTM0 */ GPR64Opnd, /* MTM1 */ GPR64Opnd, /* MTM2 */ GPR64Opnd, /* MTP0 */ GPR64Opnd, /* MTP1 */ GPR64Opnd, /* MTP2 */ GPR64Opnd, /* MTTR */ GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1, /* MUH */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MUHU */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MUHU_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MUH_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MUL */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MULEQ_S_W_PHL */ GPR32Opnd, DSPROpnd, DSPROpnd, /* MULEQ_S_W_PHL_MM */ GPR32Opnd, DSPROpnd, DSPROpnd, /* MULEQ_S_W_PHR */ GPR32Opnd, DSPROpnd, DSPROpnd, /* MULEQ_S_W_PHR_MM */ GPR32Opnd, DSPROpnd, DSPROpnd, /* MULEU_S_PH_QBL */ DSPROpnd, DSPROpnd, DSPROpnd, /* MULEU_S_PH_QBL_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* MULEU_S_PH_QBR */ DSPROpnd, DSPROpnd, DSPROpnd, /* MULEU_S_PH_QBR_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* MULQ_RS_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* MULQ_RS_PH_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* MULQ_RS_W */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MULQ_RS_W_MMR2 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MULQ_S_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* MULQ_S_PH_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* MULQ_S_W */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MULQ_S_W_MMR2 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MULR_PS64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* MULR_Q_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MULR_Q_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MULSAQ_S_W_PH */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MULSAQ_S_W_PH_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MULSA_W_PH */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MULSA_W_PH_MMR2 */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, /* MULT */ GPR32Opnd, GPR32Opnd, /* MULTU_DSP */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, /* MULTU_DSP_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, /* MULT_DSP */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, /* MULT_DSP_MM */ ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, /* MULT_MM */ GPR32Opnd, GPR32Opnd, /* MULTu */ GPR32Opnd, GPR32Opnd, /* MULTu_MM */ GPR32Opnd, GPR32Opnd, /* MULU */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MULU_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MULV_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* MULV_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* MULV_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MULV_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MUL_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MUL_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MUL_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* MUL_PH_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* MUL_Q_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* MUL_Q_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* MUL_R6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* MUL_S_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* MUL_S_PH_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* Mfhi16 */ CPU16Regs, /* Mflo16 */ CPU16Regs, /* Move32R16 */ GPR32, CPU16Regs, /* MoveR3216 */ CPU16Regs, GPR32, /* NLOC_B */ MSA128BOpnd, MSA128BOpnd, /* NLOC_D */ MSA128DOpnd, MSA128DOpnd, /* NLOC_H */ MSA128HOpnd, MSA128HOpnd, /* NLOC_W */ MSA128WOpnd, MSA128WOpnd, /* NLZC_B */ MSA128BOpnd, MSA128BOpnd, /* NLZC_D */ MSA128DOpnd, MSA128DOpnd, /* NLZC_H */ MSA128HOpnd, MSA128HOpnd, /* NLZC_W */ MSA128WOpnd, MSA128WOpnd, /* NMADD_D32 */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* NMADD_D32_MM */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* NMADD_D64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, /* NMADD_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, /* NMADD_S_MM */ FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, /* NMSUB_D32 */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* NMSUB_D32_MM */ AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, /* NMSUB_D64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, /* NMSUB_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, /* NMSUB_S_MM */ FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, /* NOR */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* NOR64 */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* NORI_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, /* NOR_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* NOR_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* NOR_V */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* NOT16_MM */ GPRMM16Opnd, GPRMM16Opnd, /* NOT16_MMR6 */ GPRMM16Opnd, GPRMM16Opnd, /* NegRxRy16 */ CPU16Regs, CPU16Regs, /* NotRxRy16 */ CPU16Regs, CPU16Regs, /* OR */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* OR16_MM */ GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, /* OR16_MMR6 */ GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, /* OR64 */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* ORI_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, /* ORI_MMR6 */ GPR32Opnd, GPR32Opnd, uimm16, /* OR_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* OR_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* OR_V */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* ORi */ GPR32Opnd, GPR32Opnd, uimm16, /* ORi64 */ GPR64Opnd, GPR64Opnd, uimm16_64, /* ORi_MM */ GPR32Opnd, GPR32Opnd, uimm16, /* OrRxRxRy16 */ CPU16Regs, CPU16Regs, CPU16Regs, /* PACKRL_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* PACKRL_PH_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* PAUSE */ /* PAUSE_MM */ /* PAUSE_MMR6 */ /* PCKEV_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* PCKEV_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* PCKEV_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* PCKEV_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* PCKOD_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* PCKOD_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* PCKOD_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* PCKOD_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* PCNT_B */ MSA128BOpnd, MSA128BOpnd, /* PCNT_D */ MSA128DOpnd, MSA128DOpnd, /* PCNT_H */ MSA128HOpnd, MSA128HOpnd, /* PCNT_W */ MSA128WOpnd, MSA128WOpnd, /* PICK_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* PICK_PH_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* PICK_QB */ DSPROpnd, DSPROpnd, DSPROpnd, /* PICK_QB_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* PLL_PS64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* PLU_PS64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* POP */ GPR32Opnd, GPR32Opnd, /* PRECEQU_PH_QBL */ DSPROpnd, DSPROpnd, /* PRECEQU_PH_QBLA */ DSPROpnd, DSPROpnd, /* PRECEQU_PH_QBLA_MM */ DSPROpnd, DSPROpnd, /* PRECEQU_PH_QBL_MM */ DSPROpnd, DSPROpnd, /* PRECEQU_PH_QBR */ DSPROpnd, DSPROpnd, /* PRECEQU_PH_QBRA */ DSPROpnd, DSPROpnd, /* PRECEQU_PH_QBRA_MM */ DSPROpnd, DSPROpnd, /* PRECEQU_PH_QBR_MM */ DSPROpnd, DSPROpnd, /* PRECEQ_W_PHL */ GPR32Opnd, DSPROpnd, /* PRECEQ_W_PHL_MM */ GPR32Opnd, DSPROpnd, /* PRECEQ_W_PHR */ GPR32Opnd, DSPROpnd, /* PRECEQ_W_PHR_MM */ GPR32Opnd, DSPROpnd, /* PRECEU_PH_QBL */ DSPROpnd, DSPROpnd, /* PRECEU_PH_QBLA */ DSPROpnd, DSPROpnd, /* PRECEU_PH_QBLA_MM */ DSPROpnd, DSPROpnd, /* PRECEU_PH_QBL_MM */ DSPROpnd, DSPROpnd, /* PRECEU_PH_QBR */ DSPROpnd, DSPROpnd, /* PRECEU_PH_QBRA */ DSPROpnd, DSPROpnd, /* PRECEU_PH_QBRA_MM */ DSPROpnd, DSPROpnd, /* PRECEU_PH_QBR_MM */ DSPROpnd, DSPROpnd, /* PRECRQU_S_QB_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* PRECRQU_S_QB_PH_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* PRECRQ_PH_W */ DSPROpnd, GPR32Opnd, GPR32Opnd, /* PRECRQ_PH_W_MM */ DSPROpnd, GPR32Opnd, GPR32Opnd, /* PRECRQ_QB_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* PRECRQ_QB_PH_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* PRECRQ_RS_PH_W */ DSPROpnd, GPR32Opnd, GPR32Opnd, /* PRECRQ_RS_PH_W_MM */ DSPROpnd, GPR32Opnd, GPR32Opnd, /* PRECR_QB_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* PRECR_QB_PH_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* PRECR_SRA_PH_W */ DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, /* PRECR_SRA_PH_W_MMR2 */ DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, /* PRECR_SRA_R_PH_W */ DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, /* PRECR_SRA_R_PH_W_MMR2 */ DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, /* PREF */ -1, simm16, uimm5, /* PREFE */ -1, simm9, uimm5, /* PREFE_MM */ -1, simm9, uimm5, /* PREFX_MM */ -1, -1, uimm5, /* PREF_MM */ -1, simm12, uimm5, /* PREF_MMR6 */ -1, simm12, uimm5, /* PREF_R6 */ -1, simm9, uimm5, /* PREPEND */ GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, /* PREPEND_MMR2 */ GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, /* PUL_PS64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* PUU_PS64 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* RADDU_W_QB */ GPR32Opnd, DSPROpnd, /* RADDU_W_QB_MM */ GPR32Opnd, DSPROpnd, /* RDDSP */ GPR32Opnd, uimm10, /* RDDSP_MM */ GPR32Opnd, uimm7, /* RDHWR */ GPR32Opnd, HWRegsOpnd, uimm8, /* RDHWR64 */ GPR64Opnd, HWRegsOpnd, uimm8, /* RDHWR_MM */ GPR32Opnd, HWRegsOpnd, uimm8, /* RDHWR_MMR6 */ GPR32Opnd, HWRegsOpnd, uimm3, /* RDPGPR_MMR6 */ GPR32Opnd, GPR32Opnd, /* RECIP_D32 */ AFGR64Opnd, AFGR64Opnd, /* RECIP_D32_MM */ AFGR64Opnd, AFGR64Opnd, /* RECIP_D64 */ FGR64Opnd, FGR64Opnd, /* RECIP_D64_MM */ FGR64Opnd, FGR64Opnd, /* RECIP_S */ FGR32Opnd, FGR32Opnd, /* RECIP_S_MM */ FGR32Opnd, FGR32Opnd, /* REPLV_PH */ DSPROpnd, GPR32Opnd, /* REPLV_PH_MM */ DSPROpnd, GPR32Opnd, /* REPLV_QB */ DSPROpnd, GPR32Opnd, /* REPLV_QB_MM */ DSPROpnd, GPR32Opnd, /* REPL_PH */ DSPROpnd, simm10, /* REPL_PH_MM */ DSPROpnd, simm10, /* REPL_QB */ DSPROpnd, uimm8, /* REPL_QB_MM */ DSPROpnd, uimm8, /* RINT_D */ FGR64Opnd, FGR64Opnd, /* RINT_D_MMR6 */ FGR64Opnd, FGR64Opnd, /* RINT_S */ FGR32Opnd, FGR32Opnd, /* RINT_S_MMR6 */ FGR32Opnd, FGR32Opnd, /* ROTR */ GPR32Opnd, GPR32Opnd, uimm5, /* ROTRV */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ROTRV_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* ROTR_MM */ GPR32Opnd, GPR32Opnd, uimm5, /* ROUND_L_D64 */ FGR64Opnd, FGR64Opnd, /* ROUND_L_D_MMR6 */ FGR64Opnd, FGR64Opnd, /* ROUND_L_S */ FGR64Opnd, FGR32Opnd, /* ROUND_L_S_MMR6 */ FGR64Opnd, FGR32Opnd, /* ROUND_W_D32 */ FGR32Opnd, AFGR64Opnd, /* ROUND_W_D64 */ FGR32Opnd, FGR64Opnd, /* ROUND_W_D_MMR6 */ FGR64Opnd, FGR64Opnd, /* ROUND_W_MM */ FGR32Opnd, AFGR64Opnd, /* ROUND_W_S */ FGR32Opnd, FGR32Opnd, /* ROUND_W_S_MM */ FGR32Opnd, FGR32Opnd, /* ROUND_W_S_MMR6 */ FGR32Opnd, FGR32Opnd, /* RSQRT_D32 */ AFGR64Opnd, AFGR64Opnd, /* RSQRT_D32_MM */ AFGR64Opnd, AFGR64Opnd, /* RSQRT_D64 */ FGR64Opnd, FGR64Opnd, /* RSQRT_D64_MM */ FGR64Opnd, FGR64Opnd, /* RSQRT_S */ FGR32Opnd, FGR32Opnd, /* RSQRT_S_MM */ FGR32Opnd, FGR32Opnd, /* Restore16 */ /* RestoreX16 */ /* SAA */ GPR64Opnd, GPR64Opnd, /* SAAD */ GPR64Opnd, GPR64Opnd, /* SAT_S_B */ MSA128BOpnd, MSA128BOpnd, uimm3, /* SAT_S_D */ MSA128DOpnd, MSA128DOpnd, uimm6, /* SAT_S_H */ MSA128HOpnd, MSA128HOpnd, uimm4, /* SAT_S_W */ MSA128WOpnd, MSA128WOpnd, uimm5, /* SAT_U_B */ MSA128BOpnd, MSA128BOpnd, uimm3, /* SAT_U_D */ MSA128DOpnd, MSA128DOpnd, uimm6, /* SAT_U_H */ MSA128HOpnd, MSA128HOpnd, uimm4, /* SAT_U_W */ MSA128WOpnd, MSA128WOpnd, uimm5, /* SB */ GPR32Opnd, -1, simm16, /* SB16_MM */ GPRMM16OpndZero, -1, simm4, /* SB16_MMR6 */ GPRMM16OpndZero, -1, simm4, /* SB64 */ GPR64Opnd, -1, simm16, /* SBE */ GPR32Opnd, -1, simm9, /* SBE_MM */ GPR32Opnd, -1, simm9, /* SB_MM */ GPR32Opnd, -1, simm16, /* SB_MMR6 */ GPR32Opnd, -1, simm16, /* SC */ GPR32Opnd, GPR32Opnd, -1, simm16, /* SC64 */ GPR32Opnd, GPR32Opnd, -1, simm16, /* SC64_R6 */ GPR32Opnd, GPR32Opnd, -1, simm9, /* SCD */ GPR64Opnd, GPR64Opnd, -1, simm16, /* SCD_R6 */ GPR64Opnd, GPR64Opnd, -1, simm9, /* SCE */ GPR32Opnd, GPR32Opnd, -1, simm9, /* SCE_MM */ GPR32Opnd, GPR32Opnd, -1, simm9, /* SC_MM */ GPR32Opnd, GPR32Opnd, -1, simm12, /* SC_MMR6 */ GPR32Opnd, GPR32Opnd, -1, simm9, /* SC_R6 */ GPR32Opnd, GPR32Opnd, -1, simm9, /* SD */ GPR64Opnd, -1, simm16, /* SDBBP */ uimm20, /* SDBBP16_MM */ uimm4, /* SDBBP16_MMR6 */ uimm4, /* SDBBP_MM */ uimm10, /* SDBBP_MMR6 */ uimm20, /* SDBBP_R6 */ uimm20, /* SDC1 */ AFGR64Opnd, -1, simm16, /* SDC164 */ FGR64Opnd, -1, simm16, /* SDC1_D64_MMR6 */ FGR64Opnd, -1, simm16, /* SDC1_MM_D32 */ AFGR64Opnd, -1, simm16, /* SDC1_MM_D64 */ FGR64Opnd, -1, simm16, /* SDC2 */ COP2Opnd, -1, simm16, /* SDC2_MMR6 */ COP2Opnd, GPR32, simm11, /* SDC2_R6 */ COP2Opnd, -1, simm11, /* SDC3 */ COP3Opnd, -1, simm16, /* SDIV */ GPR32Opnd, GPR32Opnd, /* SDIV_MM */ GPR32Opnd, GPR32Opnd, /* SDL */ GPR64Opnd, -1, simm16, /* SDR */ GPR64Opnd, -1, simm16, /* SDXC1 */ AFGR64Opnd, -1, -1, /* SDXC164 */ FGR64Opnd, -1, -1, /* SEB */ GPR32Opnd, GPR32Opnd, /* SEB64 */ GPR64Opnd, GPR64Opnd, /* SEB_MM */ GPR32Opnd, GPR32Opnd, /* SEH */ GPR32Opnd, GPR32Opnd, /* SEH64 */ GPR64Opnd, GPR64Opnd, /* SEH_MM */ GPR32Opnd, GPR32Opnd, /* SELEQZ */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SELEQZ64 */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* SELEQZ_D */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* SELEQZ_D_MMR6 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* SELEQZ_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SELEQZ_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* SELEQZ_S_MMR6 */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* SELNEZ */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SELNEZ64 */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* SELNEZ_D */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* SELNEZ_D_MMR6 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, /* SELNEZ_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SELNEZ_S */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* SELNEZ_S_MMR6 */ FGR32Opnd, FGR32Opnd, FGR32Opnd, /* SEL_D */ FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, /* SEL_D_MMR6 */ FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, /* SEL_S */ FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* SEL_S_MMR6 */ FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd, /* SEQ */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* SEQi */ GPR64Opnd, GPR64Opnd, simm10_64, /* SH */ GPR32Opnd, -1, simm16, /* SH16_MM */ GPRMM16OpndZero, -1, simm4, /* SH16_MMR6 */ GPRMM16OpndZero, -1, simm4, /* SH64 */ GPR64Opnd, -1, simm16, /* SHE */ GPR32Opnd, -1, simm9, /* SHE_MM */ GPR32Opnd, -1, simm9, /* SHF_B */ MSA128BOpnd, MSA128BOpnd, uimm8, /* SHF_H */ MSA128HOpnd, MSA128HOpnd, uimm8, /* SHF_W */ MSA128WOpnd, MSA128WOpnd, uimm8, /* SHILO */ ACC64DSPOpnd, simm6, ACC64DSPOpnd, /* SHILOV */ ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, /* SHILOV_MM */ ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, /* SHILO_MM */ ACC64DSPOpnd, simm6, ACC64DSPOpnd, /* SHLLV_PH */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHLLV_PH_MM */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHLLV_QB */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHLLV_QB_MM */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHLLV_S_PH */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHLLV_S_PH_MM */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHLLV_S_W */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SHLLV_S_W_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SHLL_PH */ DSPROpnd, DSPROpnd, uimm4, /* SHLL_PH_MM */ DSPROpnd, DSPROpnd, uimm4, /* SHLL_QB */ DSPROpnd, DSPROpnd, uimm3, /* SHLL_QB_MM */ DSPROpnd, DSPROpnd, uimm3, /* SHLL_S_PH */ DSPROpnd, DSPROpnd, uimm4, /* SHLL_S_PH_MM */ DSPROpnd, DSPROpnd, uimm4, /* SHLL_S_W */ GPR32Opnd, GPR32Opnd, uimm5, /* SHLL_S_W_MM */ GPR32Opnd, GPR32Opnd, uimm5, /* SHRAV_PH */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHRAV_PH_MM */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHRAV_QB */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHRAV_QB_MMR2 */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHRAV_R_PH */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHRAV_R_PH_MM */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHRAV_R_QB */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHRAV_R_QB_MMR2 */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHRAV_R_W */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SHRAV_R_W_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SHRA_PH */ DSPROpnd, DSPROpnd, uimm4, /* SHRA_PH_MM */ DSPROpnd, DSPROpnd, uimm4, /* SHRA_QB */ DSPROpnd, DSPROpnd, uimm3, /* SHRA_QB_MMR2 */ DSPROpnd, DSPROpnd, uimm3, /* SHRA_R_PH */ DSPROpnd, DSPROpnd, uimm4, /* SHRA_R_PH_MM */ DSPROpnd, DSPROpnd, uimm4, /* SHRA_R_QB */ DSPROpnd, DSPROpnd, uimm3, /* SHRA_R_QB_MMR2 */ DSPROpnd, DSPROpnd, uimm3, /* SHRA_R_W */ GPR32Opnd, GPR32Opnd, uimm5, /* SHRA_R_W_MM */ GPR32Opnd, GPR32Opnd, uimm5, /* SHRLV_PH */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHRLV_PH_MMR2 */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHRLV_QB */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHRLV_QB_MM */ DSPROpnd, DSPROpnd, GPR32Opnd, /* SHRL_PH */ DSPROpnd, DSPROpnd, uimm4, /* SHRL_PH_MMR2 */ DSPROpnd, DSPROpnd, uimm4, /* SHRL_QB */ DSPROpnd, DSPROpnd, uimm3, /* SHRL_QB_MM */ DSPROpnd, DSPROpnd, uimm3, /* SH_MM */ GPR32Opnd, -1, simm16, /* SH_MMR6 */ GPR32Opnd, -1, simm16, /* SIGRIE */ uimm16, /* SIGRIE_MMR6 */ uimm16, /* SLDI_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, uimm4, /* SLDI_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, uimm1, /* SLDI_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, uimm3, /* SLDI_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, uimm2, /* SLD_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, GPR32Opnd, /* SLD_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, GPR32Opnd, /* SLD_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, GPR32Opnd, /* SLD_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, GPR32Opnd, /* SLL */ GPR32Opnd, GPR32Opnd, uimm5, /* SLL16_MM */ GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, /* SLL16_MMR6 */ GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, /* SLL64_32 */ GPR64, GPR32, /* SLL64_64 */ GPR64, GPR64, /* SLLI_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, /* SLLI_D */ MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, /* SLLI_H */ MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, /* SLLI_W */ MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, /* SLLV */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SLLV_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SLL_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* SLL_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* SLL_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* SLL_MM */ GPR32Opnd, GPR32Opnd, uimm5, /* SLL_MMR6 */ GPR32Opnd, GPR32Opnd, uimm5, /* SLL_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* SLT */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SLT64 */ GPR32Opnd, GPR64Opnd, GPR64Opnd, /* SLT_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SLTi */ GPR32Opnd, GPR32Opnd, simm16, /* SLTi64 */ GPR32Opnd, GPR64Opnd, simm16_64, /* SLTi_MM */ GPR32Opnd, GPR32Opnd, simm16, /* SLTiu */ GPR32Opnd, GPR32Opnd, simm16, /* SLTiu64 */ GPR32Opnd, GPR64Opnd, simm16_64, /* SLTiu_MM */ GPR32Opnd, GPR32Opnd, simm16, /* SLTu */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SLTu64 */ GPR32Opnd, GPR64Opnd, GPR64Opnd, /* SLTu_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SNE */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* SNEi */ GPR64Opnd, GPR64Opnd, simm10_64, /* SPLATI_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm4, /* SPLATI_D */ MSA128DOpnd, MSA128DOpnd, vsplat_uimm1, /* SPLATI_H */ MSA128HOpnd, MSA128HOpnd, vsplat_uimm3, /* SPLATI_W */ MSA128WOpnd, MSA128WOpnd, vsplat_uimm2, /* SPLAT_B */ MSA128BOpnd, MSA128BOpnd, GPR32Opnd, /* SPLAT_D */ MSA128DOpnd, MSA128DOpnd, GPR32Opnd, /* SPLAT_H */ MSA128HOpnd, MSA128HOpnd, GPR32Opnd, /* SPLAT_W */ MSA128WOpnd, MSA128WOpnd, GPR32Opnd, /* SRA */ GPR32Opnd, GPR32Opnd, uimm5, /* SRAI_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, /* SRAI_D */ MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, /* SRAI_H */ MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, /* SRAI_W */ MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, /* SRARI_B */ MSA128BOpnd, MSA128BOpnd, uimm3, /* SRARI_D */ MSA128DOpnd, MSA128DOpnd, uimm6, /* SRARI_H */ MSA128HOpnd, MSA128HOpnd, uimm4, /* SRARI_W */ MSA128WOpnd, MSA128WOpnd, uimm5, /* SRAR_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* SRAR_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* SRAR_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* SRAR_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* SRAV */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SRAV_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SRA_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* SRA_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* SRA_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* SRA_MM */ GPR32Opnd, GPR32Opnd, uimm5, /* SRA_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* SRL */ GPR32Opnd, GPR32Opnd, uimm5, /* SRL16_MM */ GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, /* SRL16_MMR6 */ GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, /* SRLI_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, /* SRLI_D */ MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, /* SRLI_H */ MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, /* SRLI_W */ MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, /* SRLRI_B */ MSA128BOpnd, MSA128BOpnd, uimm3, /* SRLRI_D */ MSA128DOpnd, MSA128DOpnd, uimm6, /* SRLRI_H */ MSA128HOpnd, MSA128HOpnd, uimm4, /* SRLRI_W */ MSA128WOpnd, MSA128WOpnd, uimm5, /* SRLR_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* SRLR_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* SRLR_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* SRLR_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* SRLV */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SRLV_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SRL_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* SRL_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* SRL_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* SRL_MM */ GPR32Opnd, GPR32Opnd, uimm5, /* SRL_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* SSNOP */ /* SSNOP_MM */ /* SSNOP_MMR6 */ /* ST_B */ MSA128BOpnd, -1, simm10, /* ST_D */ MSA128DOpnd, -1, simm10_lsl3, /* ST_H */ MSA128HOpnd, -1, simm10_lsl1, /* ST_W */ MSA128WOpnd, -1, simm10_lsl2, /* SUB */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SUBQH_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBQH_PH_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBQH_R_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBQH_R_PH_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBQH_R_W */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SUBQH_R_W_MMR2 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SUBQH_W */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SUBQH_W_MMR2 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SUBQ_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBQ_PH_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBQ_S_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBQ_S_PH_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBQ_S_W */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SUBQ_S_W_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SUBSUS_U_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* SUBSUS_U_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* SUBSUS_U_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* SUBSUS_U_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* SUBSUU_S_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* SUBSUU_S_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* SUBSUU_S_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* SUBSUU_S_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* SUBS_S_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* SUBS_S_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* SUBS_S_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* SUBS_S_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* SUBS_U_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* SUBS_U_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* SUBS_U_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* SUBS_U_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* SUBU16_MM */ GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, /* SUBU16_MMR6 */ GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, /* SUBUH_QB */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBUH_QB_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBUH_R_QB */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBUH_R_QB_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBU_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SUBU_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBU_PH_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBU_QB */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBU_QB_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBU_S_PH */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBU_S_PH_MMR2 */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBU_S_QB */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBU_S_QB_MM */ DSPROpnd, DSPROpnd, DSPROpnd, /* SUBVI_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, /* SUBVI_D */ MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, /* SUBVI_H */ MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, /* SUBVI_W */ MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, /* SUBV_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* SUBV_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* SUBV_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* SUBV_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* SUB_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SUB_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SUBu */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SUBu_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* SUXC1 */ AFGR64Opnd, -1, -1, /* SUXC164 */ FGR64Opnd, -1, -1, /* SUXC1_MM */ FGR64Opnd, -1, -1, /* SW */ GPR32Opnd, -1, simm16, /* SW16_MM */ GPRMM16OpndZero, -1, simm4, /* SW16_MMR6 */ GPRMM16OpndZero, -1, simm4, /* SW64 */ GPR64Opnd, -1, simm16, /* SWC1 */ FGR32Opnd, -1, simm16, /* SWC1_MM */ FGR32Opnd, -1, simm16, /* SWC2 */ COP2Opnd, -1, simm16, /* SWC2_MMR6 */ COP2Opnd, GPR32, simm11, /* SWC2_R6 */ COP2Opnd, -1, simm11, /* SWC3 */ COP3Opnd, -1, simm16, /* SWDSP */ DSPROpnd, -1, simm16, /* SWDSP_MM */ DSPROpnd, -1, simm16, /* SWE */ GPR32Opnd, -1, simm9, /* SWE_MM */ GPR32Opnd, -1, simm9, /* SWL */ GPR32Opnd, -1, simm16, /* SWL64 */ GPR64Opnd, -1, simm16, /* SWLE */ GPR32Opnd, -1, simm9, /* SWLE_MM */ GPR32Opnd, -1, simm9, /* SWL_MM */ GPR32Opnd, -1, simm12, /* SWM16_MM */ reglist16, -1, uimm8, /* SWM16_MMR6 */ reglist16, -1, uimm8, /* SWM32_MM */ reglist, -1, simm12, /* SWP_MM */ GPR32Opnd, GPR32Opnd, -1, simm12, /* SWR */ GPR32Opnd, -1, simm16, /* SWR64 */ GPR64Opnd, -1, simm16, /* SWRE */ GPR32Opnd, -1, simm9, /* SWRE_MM */ GPR32Opnd, -1, simm9, /* SWR_MM */ GPR32Opnd, -1, simm12, /* SWSP_MM */ GPR32Opnd, -1, simm5, /* SWSP_MMR6 */ GPR32Opnd, -1, simm5, /* SWXC1 */ FGR32Opnd, -1, -1, /* SWXC1_MM */ FGR32Opnd, -1, -1, /* SW_MM */ GPR32Opnd, -1, simm16, /* SW_MMR6 */ GPR32Opnd, -1, simm16, /* SYNC */ uimm5, /* SYNCI */ -1, simm16, /* SYNCI_MM */ -1, simm16, /* SYNCI_MMR6 */ -1, simm16, /* SYNC_MM */ uimm5, /* SYNC_MMR6 */ uimm5, /* SYSCALL */ uimm20, /* SYSCALL_MM */ uimm10, /* Save16 */ /* SaveX16 */ /* SbRxRyOffMemX16 */ CPU16Regs, CPU16Regs, simm16, /* SebRx16 */ CPU16Regs, CPU16Regs, /* SehRx16 */ CPU16Regs, CPU16Regs, /* ShRxRyOffMemX16 */ CPU16Regs, CPU16Regs, simm16, /* SllX16 */ CPU16Regs, CPU16Regs, uimm5, /* SllvRxRy16 */ CPU16Regs, CPU16Regs, CPU16Regs, /* SltRxRy16 */ CPU16Regs, CPU16Regs, /* SltiRxImm16 */ CPU16Regs, simm16, /* SltiRxImmX16 */ CPU16Regs, simm16, /* SltiuRxImm16 */ CPU16Regs, simm16, /* SltiuRxImmX16 */ CPU16Regs, simm16, /* SltuRxRy16 */ CPU16Regs, CPU16Regs, /* SraX16 */ CPU16Regs, CPU16Regs, uimm5, /* SravRxRy16 */ CPU16Regs, CPU16Regs, CPU16Regs, /* SrlX16 */ CPU16Regs, CPU16Regs, uimm5, /* SrlvRxRy16 */ CPU16Regs, CPU16Regs, CPU16Regs, /* SubuRxRyRz16 */ CPU16Regs, CPU16Regs, CPU16Regs, /* SwRxRyOffMemX16 */ CPU16Regs, CPU16Regs, simm16, /* SwRxSpImmX16 */ CPU16Regs, CPU16RegsPlusSP, simm16, /* TEQ */ GPR32Opnd, GPR32Opnd, uimm10, /* TEQI */ GPR32Opnd, simm16, /* TEQI_MM */ GPR32Opnd, simm16, /* TEQ_MM */ GPR32Opnd, GPR32Opnd, uimm4, /* TGE */ GPR32Opnd, GPR32Opnd, uimm10, /* TGEI */ GPR32Opnd, simm16, /* TGEIU */ GPR32Opnd, simm16, /* TGEIU_MM */ GPR32Opnd, simm16, /* TGEI_MM */ GPR32Opnd, simm16, /* TGEU */ GPR32Opnd, GPR32Opnd, uimm10, /* TGEU_MM */ GPR32Opnd, GPR32Opnd, uimm4, /* TGE_MM */ GPR32Opnd, GPR32Opnd, uimm4, /* TLBGINV */ /* TLBGINVF */ /* TLBGINVF_MM */ /* TLBGINV_MM */ /* TLBGP */ /* TLBGP_MM */ /* TLBGR */ /* TLBGR_MM */ /* TLBGWI */ /* TLBGWI_MM */ /* TLBGWR */ /* TLBGWR_MM */ /* TLBINV */ /* TLBINVF */ /* TLBINVF_MMR6 */ /* TLBINV_MMR6 */ /* TLBP */ /* TLBP_MM */ /* TLBR */ /* TLBR_MM */ /* TLBWI */ /* TLBWI_MM */ /* TLBWR */ /* TLBWR_MM */ /* TLT */ GPR32Opnd, GPR32Opnd, uimm10, /* TLTI */ GPR32Opnd, simm16, /* TLTIU_MM */ GPR32Opnd, simm16, /* TLTI_MM */ GPR32Opnd, simm16, /* TLTU */ GPR32Opnd, GPR32Opnd, uimm10, /* TLTU_MM */ GPR32Opnd, GPR32Opnd, uimm4, /* TLT_MM */ GPR32Opnd, GPR32Opnd, uimm4, /* TNE */ GPR32Opnd, GPR32Opnd, uimm10, /* TNEI */ GPR32Opnd, simm16, /* TNEI_MM */ GPR32Opnd, simm16, /* TNE_MM */ GPR32Opnd, GPR32Opnd, uimm4, /* TRUNC_L_D64 */ FGR64Opnd, FGR64Opnd, /* TRUNC_L_D_MMR6 */ FGR64Opnd, FGR64Opnd, /* TRUNC_L_S */ FGR64Opnd, FGR32Opnd, /* TRUNC_L_S_MMR6 */ FGR64Opnd, FGR32Opnd, /* TRUNC_W_D32 */ FGR32Opnd, AFGR64Opnd, /* TRUNC_W_D64 */ FGR32Opnd, FGR64Opnd, /* TRUNC_W_D_MMR6 */ FGR32Opnd, FGR64Opnd, /* TRUNC_W_MM */ FGR32Opnd, AFGR64Opnd, /* TRUNC_W_S */ FGR32Opnd, FGR32Opnd, /* TRUNC_W_S_MM */ FGR32Opnd, FGR32Opnd, /* TRUNC_W_S_MMR6 */ FGR32Opnd, FGR32Opnd, /* TTLTIU */ GPR32Opnd, simm16, /* UDIV */ GPR32Opnd, GPR32Opnd, /* UDIV_MM */ GPR32Opnd, GPR32Opnd, /* V3MULU */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* VMM0 */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* VMULU */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* VSHF_B */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* VSHF_D */ MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, /* VSHF_H */ MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, /* VSHF_W */ MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, /* WAIT */ /* WAIT_MM */ uimm10, /* WAIT_MMR6 */ uimm10, /* WRDSP */ GPR32Opnd, uimm10, /* WRDSP_MM */ GPR32Opnd, uimm7, /* WRPGPR_MMR6 */ GPR32Opnd, GPR32Opnd, /* WSBH */ GPR32Opnd, GPR32Opnd, /* WSBH_MM */ GPR32Opnd, GPR32Opnd, /* WSBH_MMR6 */ GPR32Opnd, GPR32Opnd, /* XOR */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* XOR16_MM */ GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, /* XOR16_MMR6 */ GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, /* XOR64 */ GPR64Opnd, GPR64Opnd, GPR64Opnd, /* XORI_B */ MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, /* XORI_MMR6 */ GPR32Opnd, GPR32Opnd, uimm16, /* XOR_MM */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* XOR_MMR6 */ GPR32Opnd, GPR32Opnd, GPR32Opnd, /* XOR_V */ MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, /* XORi */ GPR32Opnd, GPR32Opnd, uimm16, /* XORi64 */ GPR64Opnd, GPR64Opnd, uimm16_64, /* XORi_MM */ GPR32Opnd, GPR32Opnd, uimm16, /* XorRxRxRy16 */ CPU16Regs, CPU16Regs, CPU16Regs, /* YIELD */ GPR32Opnd, GPR32Opnd, }; return OpcodeOperandTypes[Offsets[Opcode] + OpIdx]; } } // end namespace Mips } // end namespace llvm #endif // GET_INSTRINFO_OPERAND_TYPE #ifdef GET_INSTRINFO_MEM_OPERAND_SIZE #undef GET_INSTRINFO_MEM_OPERAND_SIZE namespace llvm { namespace Mips { LLVM_READONLY static int getMemOperandSize(int OpType) { switch (OpType) { default: return 0; } } } // end namespace Mips } // end namespace llvm #endif // GET_INSTRINFO_MEM_OPERAND_SIZE #ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP #undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP namespace llvm { namespace Mips { LLVM_READONLY static unsigned getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) { return LogicalOpIdx; } LLVM_READONLY static inline unsigned getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) { auto S = 0U; for (auto i = 0U; i < LogicalOpIdx; ++i) S += getLogicalOperandSize(Opcode, i); return S; } } // end namespace Mips } // end namespace llvm #endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP #ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP #undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP namespace llvm { namespace Mips { LLVM_READONLY static int getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) { return -1; } } // end namespace Mips } // end namespace llvm #endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP #ifdef GET_INSTRINFO_MC_HELPER_DECLS #undef GET_INSTRINFO_MC_HELPER_DECLS namespace llvm { class MCInst; class FeatureBitset; namespace Mips_MC { void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); } // end namespace Mips_MC } // end namespace llvm #endif // GET_INSTRINFO_MC_HELPER_DECLS #ifdef GET_INSTRINFO_MC_HELPERS #undef GET_INSTRINFO_MC_HELPERS namespace llvm { namespace Mips_MC { } // end namespace Mips_MC } // end namespace llvm #endif // GET_GENISTRINFO_MC_HELPERS #ifdef ENABLE_INSTR_PREDICATE_VERIFIER #undef ENABLE_INSTR_PREDICATE_VERIFIER #include namespace llvm { namespace Mips_MC { // Bits for subtarget features that participate in instruction matching. enum SubtargetFeatureBits : uint8_t { Feature_HasMips2Bit = 11, Feature_HasMips3_32Bit = 18, Feature_HasMips3_32r2Bit = 19, Feature_HasMips3Bit = 12, Feature_NotMips3Bit = 47, Feature_HasMips4_32Bit = 20, Feature_NotMips4_32Bit = 49, Feature_HasMips4_32r2Bit = 21, Feature_HasMips5_32r2Bit = 22, Feature_HasMips32Bit = 13, Feature_HasMips32r2Bit = 14, Feature_HasMips32r5Bit = 15, Feature_HasMips32r6Bit = 16, Feature_NotMips32r6Bit = 48, Feature_IsGP64bitBit = 33, Feature_IsGP32bitBit = 32, Feature_IsPTR64bitBit = 37, Feature_IsPTR32bitBit = 36, Feature_HasMips64Bit = 23, Feature_NotMips64Bit = 50, Feature_HasMips64r2Bit = 24, Feature_HasMips64r5Bit = 25, Feature_HasMips64r6Bit = 26, Feature_NotMips64r6Bit = 51, Feature_InMips16ModeBit = 30, Feature_NotInMips16ModeBit = 46, Feature_HasCnMipsBit = 1, Feature_NotCnMipsBit = 42, Feature_HasCnMipsPBit = 2, Feature_NotCnMipsPBit = 43, Feature_IsSym32Bit = 39, Feature_IsSym64Bit = 40, Feature_HasStdEncBit = 27, Feature_InMicroMipsBit = 29, Feature_NotInMicroMipsBit = 45, Feature_HasEVABit = 6, Feature_HasMSABit = 8, Feature_HasMadd4Bit = 10, Feature_HasMTBit = 9, Feature_UseIndirectJumpsHazardBit = 52, Feature_NoIndirectJumpGuardsBit = 41, Feature_HasCRCBit = 0, Feature_HasVirtBit = 28, Feature_HasGINVBit = 7, Feature_IsFP64bitBit = 31, Feature_NotFP64bitBit = 44, Feature_IsSingleFloatBit = 38, Feature_IsNotSingleFloatBit = 34, Feature_IsNotSoftFloatBit = 35, Feature_HasMips3DBit = 17, Feature_HasDSPBit = 3, Feature_HasDSPR2Bit = 4, Feature_HasDSPR3Bit = 5, }; #ifndef NDEBUG static const char *SubtargetFeatureNames[] = { "Feature_HasCRC", "Feature_HasCnMips", "Feature_HasCnMipsP", "Feature_HasDSP", "Feature_HasDSPR2", "Feature_HasDSPR3", "Feature_HasEVA", "Feature_HasGINV", "Feature_HasMSA", "Feature_HasMT", "Feature_HasMadd4", "Feature_HasMips2", "Feature_HasMips3", "Feature_HasMips32", "Feature_HasMips32r2", "Feature_HasMips32r5", "Feature_HasMips32r6", "Feature_HasMips3D", "Feature_HasMips3_32", "Feature_HasMips3_32r2", "Feature_HasMips4_32", "Feature_HasMips4_32r2", "Feature_HasMips5_32r2", "Feature_HasMips64", "Feature_HasMips64r2", "Feature_HasMips64r5", "Feature_HasMips64r6", "Feature_HasStdEnc", "Feature_HasVirt", "Feature_InMicroMips", "Feature_InMips16Mode", "Feature_IsFP64bit", "Feature_IsGP32bit", "Feature_IsGP64bit", "Feature_IsNotSingleFloat", "Feature_IsNotSoftFloat", "Feature_IsPTR32bit", "Feature_IsPTR64bit", "Feature_IsSingleFloat", "Feature_IsSym32", "Feature_IsSym64", "Feature_NoIndirectJumpGuards", "Feature_NotCnMips", "Feature_NotCnMipsP", "Feature_NotFP64bit", "Feature_NotInMicroMips", "Feature_NotInMips16Mode", "Feature_NotMips3", "Feature_NotMips32r6", "Feature_NotMips4_32", "Feature_NotMips64", "Feature_NotMips64r6", "Feature_UseIndirectJumpsHazard", nullptr }; #endif // NDEBUG FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { FeatureBitset Features; if (FB[Mips::FeatureMips2]) Features.set(Feature_HasMips2Bit); if (FB[Mips::FeatureMips3_32]) Features.set(Feature_HasMips3_32Bit); if (FB[Mips::FeatureMips3_32r2]) Features.set(Feature_HasMips3_32r2Bit); if (FB[Mips::FeatureMips3]) Features.set(Feature_HasMips3Bit); if (!FB[Mips::FeatureMips3]) Features.set(Feature_NotMips3Bit); if (FB[Mips::FeatureMips4_32]) Features.set(Feature_HasMips4_32Bit); if (!FB[Mips::FeatureMips4_32]) Features.set(Feature_NotMips4_32Bit); if (FB[Mips::FeatureMips4_32r2]) Features.set(Feature_HasMips4_32r2Bit); if (FB[Mips::FeatureMips5_32r2]) Features.set(Feature_HasMips5_32r2Bit); if (FB[Mips::FeatureMips32]) Features.set(Feature_HasMips32Bit); if (FB[Mips::FeatureMips32r2]) Features.set(Feature_HasMips32r2Bit); if (FB[Mips::FeatureMips32r5]) Features.set(Feature_HasMips32r5Bit); if (FB[Mips::FeatureMips32r6]) Features.set(Feature_HasMips32r6Bit); if (!FB[Mips::FeatureMips32r6]) Features.set(Feature_NotMips32r6Bit); if (FB[Mips::FeatureGP64Bit]) Features.set(Feature_IsGP64bitBit); if (!FB[Mips::FeatureGP64Bit]) Features.set(Feature_IsGP32bitBit); if (FB[Mips::FeaturePTR64Bit]) Features.set(Feature_IsPTR64bitBit); if (!FB[Mips::FeaturePTR64Bit]) Features.set(Feature_IsPTR32bitBit); if (FB[Mips::FeatureMips64]) Features.set(Feature_HasMips64Bit); if (!FB[Mips::FeatureMips64]) Features.set(Feature_NotMips64Bit); if (FB[Mips::FeatureMips64r2]) Features.set(Feature_HasMips64r2Bit); if (FB[Mips::FeatureMips64r5]) Features.set(Feature_HasMips64r5Bit); if (FB[Mips::FeatureMips64r6]) Features.set(Feature_HasMips64r6Bit); if (!FB[Mips::FeatureMips64r6]) Features.set(Feature_NotMips64r6Bit); if (FB[Mips::FeatureMips16]) Features.set(Feature_InMips16ModeBit); if (!FB[Mips::FeatureMips16]) Features.set(Feature_NotInMips16ModeBit); if (FB[Mips::FeatureCnMips]) Features.set(Feature_HasCnMipsBit); if (!FB[Mips::FeatureCnMips]) Features.set(Feature_NotCnMipsBit); if (FB[Mips::FeatureCnMipsP]) Features.set(Feature_HasCnMipsPBit); if (!FB[Mips::FeatureCnMipsP]) Features.set(Feature_NotCnMipsPBit); if (FB[Mips::FeatureSym32]) Features.set(Feature_IsSym32Bit); if (!FB[Mips::FeatureSym32]) Features.set(Feature_IsSym64Bit); if (!FB[Mips::FeatureMips16]) Features.set(Feature_HasStdEncBit); if (FB[Mips::FeatureMicroMips]) Features.set(Feature_InMicroMipsBit); if (!FB[Mips::FeatureMicroMips]) Features.set(Feature_NotInMicroMipsBit); if (FB[Mips::FeatureEVA]) Features.set(Feature_HasEVABit); if (FB[Mips::FeatureMSA]) Features.set(Feature_HasMSABit); if (!FB[Mips::FeatureNoMadd4]) Features.set(Feature_HasMadd4Bit); if (FB[Mips::FeatureMT]) Features.set(Feature_HasMTBit); if (FB[Mips::FeatureUseIndirectJumpsHazard]) Features.set(Feature_UseIndirectJumpsHazardBit); if (!FB[Mips::FeatureUseIndirectJumpsHazard]) Features.set(Feature_NoIndirectJumpGuardsBit); if (FB[Mips::FeatureCRC]) Features.set(Feature_HasCRCBit); if (FB[Mips::FeatureVirt]) Features.set(Feature_HasVirtBit); if (FB[Mips::FeatureGINV]) Features.set(Feature_HasGINVBit); if (FB[Mips::FeatureFP64Bit]) Features.set(Feature_IsFP64bitBit); if (!FB[Mips::FeatureFP64Bit]) Features.set(Feature_NotFP64bitBit); if (FB[Mips::FeatureSingleFloat]) Features.set(Feature_IsSingleFloatBit); if (!FB[Mips::FeatureSingleFloat]) Features.set(Feature_IsNotSingleFloatBit); if (!FB[Mips::FeatureSoftFloat]) Features.set(Feature_IsNotSoftFloatBit); if (FB[Mips::FeatureMips3D]) Features.set(Feature_HasMips3DBit); if (FB[Mips::FeatureDSP]) Features.set(Feature_HasDSPBit); if (FB[Mips::FeatureDSPR2]) Features.set(Feature_HasDSPR2Bit); if (FB[Mips::FeatureDSPR3]) Features.set(Feature_HasDSPR3Bit); return Features; } #ifndef NDEBUG // Feature bitsets. enum : uint8_t { CEFBS_None, CEFBS_HasCnMips, CEFBS_HasCnMipsP, CEFBS_HasDSP, CEFBS_HasDSPR2, CEFBS_HasMSA, CEFBS_HasMT, CEFBS_InMicroMips, CEFBS_InMips16Mode, CEFBS_IsGP32bit, CEFBS_IsGP64bit, CEFBS_IsNotSoftFloat, CEFBS_NotCnMips, CEFBS_NotInMips16Mode, CEFBS_HasDSP_NotInMicroMips, CEFBS_HasStdEnc_HasMSA, CEFBS_HasStdEnc_HasMips32, CEFBS_HasStdEnc_HasMips32r6, CEFBS_HasStdEnc_HasMips64, CEFBS_HasStdEnc_HasMips64r6, CEFBS_HasStdEnc_IsNotSoftFloat, CEFBS_HasStdEnc_NotInMicroMips, CEFBS_HasStdEnc_NotMips3, CEFBS_HasStdEnc_NotMips4_32, CEFBS_InMicroMips_HasDSP, CEFBS_InMicroMips_HasDSPR2, CEFBS_InMicroMips_HasDSPR3, CEFBS_InMicroMips_HasEVA, CEFBS_InMicroMips_HasMips32r6, CEFBS_InMicroMips_IsNotSoftFloat, CEFBS_InMicroMips_NotMips32r6, CEFBS_IsFP64bit_IsNotSoftFloat, CEFBS_IsGP32bit_NotInMicroMips, CEFBS_NotFP64bit_IsNotSoftFloat, CEFBS_NotInMips16Mode_HasDSP, CEFBS_NotInMips16Mode_IsGP64bit, CEFBS_NotInMips16Mode_IsNotSoftFloat, CEFBS_NotInMips16Mode_IsPTR64bit, CEFBS_HasMips3_NotMips64r6_NotCnMips, CEFBS_HasMips64_HasCnMips_NotInMicroMips, CEFBS_HasStdEnc_HasMSA_HasMips64, CEFBS_HasStdEnc_HasMT_NotInMicroMips, CEFBS_HasStdEnc_HasMips2_NotInMicroMips, CEFBS_HasStdEnc_HasMips3_NotInMicroMips, CEFBS_HasStdEnc_HasMips32_NotInMicroMips, CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, CEFBS_HasStdEnc_HasMips64r5_HasVirt, CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, CEFBS_HasStdEnc_IsGP64bit_HasMips3, CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, CEFBS_InMicroMips_HasMips32r5_HasVirt, CEFBS_InMicroMips_HasMips32r6_HasGINV, CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, CEFBS_InMicroMips_NotMips32r6_HasDSP, CEFBS_InMicroMips_NotMips32r6_HasEVA, CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, CEFBS_InMicroMips_NotMips32r6_NotMips64r6, CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, }; static constexpr FeatureBitset FeatureBitsets[] = { {}, // CEFBS_None {Feature_HasCnMipsBit, }, {Feature_HasCnMipsPBit, }, {Feature_HasDSPBit, }, {Feature_HasDSPR2Bit, }, {Feature_HasMSABit, }, {Feature_HasMTBit, }, {Feature_InMicroMipsBit, }, {Feature_InMips16ModeBit, }, {Feature_IsGP32bitBit, }, {Feature_IsGP64bitBit, }, {Feature_IsNotSoftFloatBit, }, {Feature_NotCnMipsBit, }, {Feature_NotInMips16ModeBit, }, {Feature_HasDSPBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMSABit, }, {Feature_HasStdEncBit, Feature_HasMips32Bit, }, {Feature_HasStdEncBit, Feature_HasMips32r6Bit, }, {Feature_HasStdEncBit, Feature_HasMips64Bit, }, {Feature_HasStdEncBit, Feature_HasMips64r6Bit, }, {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, }, {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotMips3Bit, }, {Feature_HasStdEncBit, Feature_NotMips4_32Bit, }, {Feature_InMicroMipsBit, Feature_HasDSPBit, }, {Feature_InMicroMipsBit, Feature_HasDSPR2Bit, }, {Feature_InMicroMipsBit, Feature_HasDSPR3Bit, }, {Feature_InMicroMipsBit, Feature_HasEVABit, }, {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, }, {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, }, {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, {Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, {Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, {Feature_NotInMips16ModeBit, Feature_HasDSPBit, }, {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, }, {Feature_NotInMips16ModeBit, Feature_IsNotSoftFloatBit, }, {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, }, {Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, }, {Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, }, {Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, }, {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, }, {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, }, {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r2Bit, }, {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, }, {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, }, {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, }, {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, {Feature_HasStdEncBit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, {Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, }, {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, }, {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, }, {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, }, {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, {Feature_NotInMips16ModeBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NoIndirectJumpGuardsBit, }, {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, }, {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_UseIndirectJumpsHazardBit, }, {Feature_NotInMips16ModeBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, {Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, }; #endif // NDEBUG void verifyInstructionPredicates( unsigned Opcode, const FeatureBitset &Features) { #ifndef NDEBUG static uint8_t RequiredFeaturesRefs[] = { CEFBS_None, // PHI = 0 CEFBS_None, // INLINEASM = 1 CEFBS_None, // INLINEASM_BR = 2 CEFBS_None, // CFI_INSTRUCTION = 3 CEFBS_None, // EH_LABEL = 4 CEFBS_None, // GC_LABEL = 5 CEFBS_None, // ANNOTATION_LABEL = 6 CEFBS_None, // KILL = 7 CEFBS_None, // EXTRACT_SUBREG = 8 CEFBS_None, // INSERT_SUBREG = 9 CEFBS_None, // IMPLICIT_DEF = 10 CEFBS_None, // SUBREG_TO_REG = 11 CEFBS_None, // COPY_TO_REGCLASS = 12 CEFBS_None, // DBG_VALUE = 13 CEFBS_None, // DBG_VALUE_LIST = 14 CEFBS_None, // DBG_INSTR_REF = 15 CEFBS_None, // DBG_PHI = 16 CEFBS_None, // DBG_LABEL = 17 CEFBS_None, // REG_SEQUENCE = 18 CEFBS_None, // COPY = 19 CEFBS_None, // BUNDLE = 20 CEFBS_None, // LIFETIME_START = 21 CEFBS_None, // LIFETIME_END = 22 CEFBS_None, // PSEUDO_PROBE = 23 CEFBS_None, // ARITH_FENCE = 24 CEFBS_None, // STACKMAP = 25 CEFBS_None, // FENTRY_CALL = 26 CEFBS_None, // PATCHPOINT = 27 CEFBS_None, // LOAD_STACK_GUARD = 28 CEFBS_None, // PREALLOCATED_SETUP = 29 CEFBS_None, // PREALLOCATED_ARG = 30 CEFBS_None, // STATEPOINT = 31 CEFBS_None, // LOCAL_ESCAPE = 32 CEFBS_None, // FAULTING_OP = 33 CEFBS_None, // PATCHABLE_OP = 34 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35 CEFBS_None, // PATCHABLE_RET = 36 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37 CEFBS_None, // PATCHABLE_TAIL_CALL = 38 CEFBS_None, // PATCHABLE_EVENT_CALL = 39 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41 CEFBS_None, // MEMBARRIER = 42 CEFBS_None, // G_ASSERT_SEXT = 43 CEFBS_None, // G_ASSERT_ZEXT = 44 CEFBS_None, // G_ASSERT_ALIGN = 45 CEFBS_None, // G_ADD = 46 CEFBS_None, // G_SUB = 47 CEFBS_None, // G_MUL = 48 CEFBS_None, // G_SDIV = 49 CEFBS_None, // G_UDIV = 50 CEFBS_None, // G_SREM = 51 CEFBS_None, // G_UREM = 52 CEFBS_None, // G_SDIVREM = 53 CEFBS_None, // G_UDIVREM = 54 CEFBS_None, // G_AND = 55 CEFBS_None, // G_OR = 56 CEFBS_None, // G_XOR = 57 CEFBS_None, // G_IMPLICIT_DEF = 58 CEFBS_None, // G_PHI = 59 CEFBS_None, // G_FRAME_INDEX = 60 CEFBS_None, // G_GLOBAL_VALUE = 61 CEFBS_None, // G_EXTRACT = 62 CEFBS_None, // G_UNMERGE_VALUES = 63 CEFBS_None, // G_INSERT = 64 CEFBS_None, // G_MERGE_VALUES = 65 CEFBS_None, // G_BUILD_VECTOR = 66 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 67 CEFBS_None, // G_CONCAT_VECTORS = 68 CEFBS_None, // G_PTRTOINT = 69 CEFBS_None, // G_INTTOPTR = 70 CEFBS_None, // G_BITCAST = 71 CEFBS_None, // G_FREEZE = 72 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 73 CEFBS_None, // G_INTRINSIC_TRUNC = 74 CEFBS_None, // G_INTRINSIC_ROUND = 75 CEFBS_None, // G_INTRINSIC_LRINT = 76 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 77 CEFBS_None, // G_READCYCLECOUNTER = 78 CEFBS_None, // G_LOAD = 79 CEFBS_None, // G_SEXTLOAD = 80 CEFBS_None, // G_ZEXTLOAD = 81 CEFBS_None, // G_INDEXED_LOAD = 82 CEFBS_None, // G_INDEXED_SEXTLOAD = 83 CEFBS_None, // G_INDEXED_ZEXTLOAD = 84 CEFBS_None, // G_STORE = 85 CEFBS_None, // G_INDEXED_STORE = 86 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87 CEFBS_None, // G_ATOMIC_CMPXCHG = 88 CEFBS_None, // G_ATOMICRMW_XCHG = 89 CEFBS_None, // G_ATOMICRMW_ADD = 90 CEFBS_None, // G_ATOMICRMW_SUB = 91 CEFBS_None, // G_ATOMICRMW_AND = 92 CEFBS_None, // G_ATOMICRMW_NAND = 93 CEFBS_None, // G_ATOMICRMW_OR = 94 CEFBS_None, // G_ATOMICRMW_XOR = 95 CEFBS_None, // G_ATOMICRMW_MAX = 96 CEFBS_None, // G_ATOMICRMW_MIN = 97 CEFBS_None, // G_ATOMICRMW_UMAX = 98 CEFBS_None, // G_ATOMICRMW_UMIN = 99 CEFBS_None, // G_ATOMICRMW_FADD = 100 CEFBS_None, // G_ATOMICRMW_FSUB = 101 CEFBS_None, // G_ATOMICRMW_FMAX = 102 CEFBS_None, // G_ATOMICRMW_FMIN = 103 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 104 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 105 CEFBS_None, // G_FENCE = 106 CEFBS_None, // G_BRCOND = 107 CEFBS_None, // G_BRINDIRECT = 108 CEFBS_None, // G_INVOKE_REGION_START = 109 CEFBS_None, // G_INTRINSIC = 110 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 111 CEFBS_None, // G_ANYEXT = 112 CEFBS_None, // G_TRUNC = 113 CEFBS_None, // G_CONSTANT = 114 CEFBS_None, // G_FCONSTANT = 115 CEFBS_None, // G_VASTART = 116 CEFBS_None, // G_VAARG = 117 CEFBS_None, // G_SEXT = 118 CEFBS_None, // G_SEXT_INREG = 119 CEFBS_None, // G_ZEXT = 120 CEFBS_None, // G_SHL = 121 CEFBS_None, // G_LSHR = 122 CEFBS_None, // G_ASHR = 123 CEFBS_None, // G_FSHL = 124 CEFBS_None, // G_FSHR = 125 CEFBS_None, // G_ROTR = 126 CEFBS_None, // G_ROTL = 127 CEFBS_None, // G_ICMP = 128 CEFBS_None, // G_FCMP = 129 CEFBS_None, // G_SELECT = 130 CEFBS_None, // G_UADDO = 131 CEFBS_None, // G_UADDE = 132 CEFBS_None, // G_USUBO = 133 CEFBS_None, // G_USUBE = 134 CEFBS_None, // G_SADDO = 135 CEFBS_None, // G_SADDE = 136 CEFBS_None, // G_SSUBO = 137 CEFBS_None, // G_SSUBE = 138 CEFBS_None, // G_UMULO = 139 CEFBS_None, // G_SMULO = 140 CEFBS_None, // G_UMULH = 141 CEFBS_None, // G_SMULH = 142 CEFBS_None, // G_UADDSAT = 143 CEFBS_None, // G_SADDSAT = 144 CEFBS_None, // G_USUBSAT = 145 CEFBS_None, // G_SSUBSAT = 146 CEFBS_None, // G_USHLSAT = 147 CEFBS_None, // G_SSHLSAT = 148 CEFBS_None, // G_SMULFIX = 149 CEFBS_None, // G_UMULFIX = 150 CEFBS_None, // G_SMULFIXSAT = 151 CEFBS_None, // G_UMULFIXSAT = 152 CEFBS_None, // G_SDIVFIX = 153 CEFBS_None, // G_UDIVFIX = 154 CEFBS_None, // G_SDIVFIXSAT = 155 CEFBS_None, // G_UDIVFIXSAT = 156 CEFBS_None, // G_FADD = 157 CEFBS_None, // G_FSUB = 158 CEFBS_None, // G_FMUL = 159 CEFBS_None, // G_FMA = 160 CEFBS_None, // G_FMAD = 161 CEFBS_None, // G_FDIV = 162 CEFBS_None, // G_FREM = 163 CEFBS_None, // G_FPOW = 164 CEFBS_None, // G_FPOWI = 165 CEFBS_None, // G_FEXP = 166 CEFBS_None, // G_FEXP2 = 167 CEFBS_None, // G_FLOG = 168 CEFBS_None, // G_FLOG2 = 169 CEFBS_None, // G_FLOG10 = 170 CEFBS_None, // G_FNEG = 171 CEFBS_None, // G_FPEXT = 172 CEFBS_None, // G_FPTRUNC = 173 CEFBS_None, // G_FPTOSI = 174 CEFBS_None, // G_FPTOUI = 175 CEFBS_None, // G_SITOFP = 176 CEFBS_None, // G_UITOFP = 177 CEFBS_None, // G_FABS = 178 CEFBS_None, // G_FCOPYSIGN = 179 CEFBS_None, // G_IS_FPCLASS = 180 CEFBS_None, // G_FCANONICALIZE = 181 CEFBS_None, // G_FMINNUM = 182 CEFBS_None, // G_FMAXNUM = 183 CEFBS_None, // G_FMINNUM_IEEE = 184 CEFBS_None, // G_FMAXNUM_IEEE = 185 CEFBS_None, // G_FMINIMUM = 186 CEFBS_None, // G_FMAXIMUM = 187 CEFBS_None, // G_PTR_ADD = 188 CEFBS_None, // G_PTRMASK = 189 CEFBS_None, // G_SMIN = 190 CEFBS_None, // G_SMAX = 191 CEFBS_None, // G_UMIN = 192 CEFBS_None, // G_UMAX = 193 CEFBS_None, // G_ABS = 194 CEFBS_None, // G_LROUND = 195 CEFBS_None, // G_LLROUND = 196 CEFBS_None, // G_BR = 197 CEFBS_None, // G_BRJT = 198 CEFBS_None, // G_INSERT_VECTOR_ELT = 199 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 200 CEFBS_None, // G_SHUFFLE_VECTOR = 201 CEFBS_None, // G_CTTZ = 202 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 203 CEFBS_None, // G_CTLZ = 204 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 205 CEFBS_None, // G_CTPOP = 206 CEFBS_None, // G_BSWAP = 207 CEFBS_None, // G_BITREVERSE = 208 CEFBS_None, // G_FCEIL = 209 CEFBS_None, // G_FCOS = 210 CEFBS_None, // G_FSIN = 211 CEFBS_None, // G_FSQRT = 212 CEFBS_None, // G_FFLOOR = 213 CEFBS_None, // G_FRINT = 214 CEFBS_None, // G_FNEARBYINT = 215 CEFBS_None, // G_ADDRSPACE_CAST = 216 CEFBS_None, // G_BLOCK_ADDR = 217 CEFBS_None, // G_JUMP_TABLE = 218 CEFBS_None, // G_DYN_STACKALLOC = 219 CEFBS_None, // G_STRICT_FADD = 220 CEFBS_None, // G_STRICT_FSUB = 221 CEFBS_None, // G_STRICT_FMUL = 222 CEFBS_None, // G_STRICT_FDIV = 223 CEFBS_None, // G_STRICT_FREM = 224 CEFBS_None, // G_STRICT_FMA = 225 CEFBS_None, // G_STRICT_FSQRT = 226 CEFBS_None, // G_READ_REGISTER = 227 CEFBS_None, // G_WRITE_REGISTER = 228 CEFBS_None, // G_MEMCPY = 229 CEFBS_None, // G_MEMCPY_INLINE = 230 CEFBS_None, // G_MEMMOVE = 231 CEFBS_None, // G_MEMSET = 232 CEFBS_None, // G_BZERO = 233 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 234 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 235 CEFBS_None, // G_VECREDUCE_FADD = 236 CEFBS_None, // G_VECREDUCE_FMUL = 237 CEFBS_None, // G_VECREDUCE_FMAX = 238 CEFBS_None, // G_VECREDUCE_FMIN = 239 CEFBS_None, // G_VECREDUCE_ADD = 240 CEFBS_None, // G_VECREDUCE_MUL = 241 CEFBS_None, // G_VECREDUCE_AND = 242 CEFBS_None, // G_VECREDUCE_OR = 243 CEFBS_None, // G_VECREDUCE_XOR = 244 CEFBS_None, // G_VECREDUCE_SMAX = 245 CEFBS_None, // G_VECREDUCE_SMIN = 246 CEFBS_None, // G_VECREDUCE_UMAX = 247 CEFBS_None, // G_VECREDUCE_UMIN = 248 CEFBS_None, // G_SBFX = 249 CEFBS_None, // G_UBFX = 250 CEFBS_None, // ABSMacro = 251 CEFBS_None, // ADJCALLSTACKDOWN = 252 CEFBS_None, // ADJCALLSTACKUP = 253 CEFBS_HasStdEnc_HasMSA, // AND_V_D_PSEUDO = 254 CEFBS_HasStdEnc_HasMSA, // AND_V_H_PSEUDO = 255 CEFBS_HasStdEnc_HasMSA, // AND_V_W_PSEUDO = 256 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16 = 257 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16_POSTRA = 258 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32 = 259 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32_POSTRA = 260 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64 = 261 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64_POSTRA = 262 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8 = 263 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8_POSTRA = 264 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16 = 265 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16_POSTRA = 266 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32 = 267 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32_POSTRA = 268 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64 = 269 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64_POSTRA = 270 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8 = 271 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8_POSTRA = 272 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16 = 273 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16_POSTRA = 274 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32 = 275 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32_POSTRA = 276 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64 = 277 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64_POSTRA = 278 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8 = 279 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8_POSTRA = 280 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16 = 281 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16_POSTRA = 282 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32 = 283 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32_POSTRA = 284 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64 = 285 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64_POSTRA = 286 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8 = 287 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8_POSTRA = 288 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16 = 289 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16_POSTRA = 290 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32 = 291 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32_POSTRA = 292 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64 = 293 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64_POSTRA = 294 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8 = 295 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8_POSTRA = 296 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16 = 297 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16_POSTRA = 298 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32 = 299 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32_POSTRA = 300 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64 = 301 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64_POSTRA = 302 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8 = 303 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8_POSTRA = 304 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16 = 305 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16_POSTRA = 306 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32 = 307 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32_POSTRA = 308 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64 = 309 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64_POSTRA = 310 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8 = 311 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8_POSTRA = 312 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16 = 313 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16_POSTRA = 314 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32 = 315 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32_POSTRA = 316 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64 = 317 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64_POSTRA = 318 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8 = 319 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8_POSTRA = 320 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16 = 321 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16_POSTRA = 322 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32 = 323 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32_POSTRA = 324 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64 = 325 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64_POSTRA = 326 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8 = 327 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8_POSTRA = 328 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16 = 329 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16_POSTRA = 330 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32 = 331 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32_POSTRA = 332 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64 = 333 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64_POSTRA = 334 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8 = 335 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8_POSTRA = 336 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16 = 337 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16_POSTRA = 338 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32 = 339 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32_POSTRA = 340 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64 = 341 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64_POSTRA = 342 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8 = 343 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8_POSTRA = 344 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16 = 345 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16_POSTRA = 346 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32 = 347 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32_POSTRA = 348 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64 = 349 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64_POSTRA = 350 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8 = 351 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8_POSTRA = 352 CEFBS_HasStdEnc_NotInMicroMips, // B = 353 CEFBS_HasStdEnc_NotInMicroMips, // BAL_BR = 354 CEFBS_InMicroMips_NotMips32r6, // BAL_BR_MM = 355 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BEQLImmMacro = 356 CEFBS_None, // BGE = 357 CEFBS_None, // BGEImmMacro = 358 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEL = 359 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGELImmMacro = 360 CEFBS_None, // BGEU = 361 CEFBS_None, // BGEUImmMacro = 362 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEUL = 363 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEULImmMacro = 364 CEFBS_None, // BGT = 365 CEFBS_None, // BGTImmMacro = 366 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTL = 367 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTLImmMacro = 368 CEFBS_None, // BGTU = 369 CEFBS_None, // BGTUImmMacro = 370 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTUL = 371 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTULImmMacro = 372 CEFBS_None, // BLE = 373 CEFBS_None, // BLEImmMacro = 374 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEL = 375 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLELImmMacro = 376 CEFBS_None, // BLEU = 377 CEFBS_None, // BLEUImmMacro = 378 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEUL = 379 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEULImmMacro = 380 CEFBS_None, // BLT = 381 CEFBS_None, // BLTImmMacro = 382 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTL = 383 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTLImmMacro = 384 CEFBS_None, // BLTU = 385 CEFBS_None, // BLTUImmMacro = 386 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTUL = 387 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTULImmMacro = 388 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BNELImmMacro = 389 CEFBS_None, // BPOSGE32_PSEUDO = 390 CEFBS_HasStdEnc_HasMSA, // BSEL_D_PSEUDO = 391 CEFBS_HasStdEnc_HasMSA, // BSEL_FD_PSEUDO = 392 CEFBS_HasStdEnc_HasMSA, // BSEL_FW_PSEUDO = 393 CEFBS_HasStdEnc_HasMSA, // BSEL_H_PSEUDO = 394 CEFBS_HasStdEnc_HasMSA, // BSEL_W_PSEUDO = 395 CEFBS_InMicroMips_NotMips32r6, // B_MM = 396 CEFBS_None, // B_MMR6_Pseudo = 397 CEFBS_InMicroMips, // B_MM_Pseudo = 398 CEFBS_None, // BeqImm = 399 CEFBS_None, // BneImm = 400 CEFBS_InMips16Mode, // BteqzT8CmpX16 = 401 CEFBS_InMips16Mode, // BteqzT8CmpiX16 = 402 CEFBS_InMips16Mode, // BteqzT8SltX16 = 403 CEFBS_InMips16Mode, // BteqzT8SltiX16 = 404 CEFBS_InMips16Mode, // BteqzT8SltiuX16 = 405 CEFBS_InMips16Mode, // BteqzT8SltuX16 = 406 CEFBS_InMips16Mode, // BtnezT8CmpX16 = 407 CEFBS_InMips16Mode, // BtnezT8CmpiX16 = 408 CEFBS_InMips16Mode, // BtnezT8SltX16 = 409 CEFBS_InMips16Mode, // BtnezT8SltiX16 = 410 CEFBS_InMips16Mode, // BtnezT8SltiuX16 = 411 CEFBS_InMips16Mode, // BtnezT8SltuX16 = 412 CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // BuildPairF64 = 413 CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // BuildPairF64_64 = 414 CEFBS_HasMT, // CFTC1 = 415 CEFBS_InMips16Mode, // CONSTPOOL_ENTRY = 416 CEFBS_HasStdEnc_HasMSA, // COPY_FD_PSEUDO = 417 CEFBS_HasStdEnc_HasMSA, // COPY_FW_PSEUDO = 418 CEFBS_HasMT, // CTTC1 = 419 CEFBS_InMips16Mode, // Constant32 = 420 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULImmMacro = 421 CEFBS_HasMips3_NotMips64r6_NotCnMips, // DMULMacro = 422 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOMacro = 423 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOUMacro = 424 CEFBS_HasStdEnc_HasMips64, // DROL = 425 CEFBS_HasStdEnc_HasMips64, // DROLImm = 426 CEFBS_HasStdEnc_HasMips64, // DROR = 427 CEFBS_HasStdEnc_HasMips64, // DRORImm = 428 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivIMacro = 429 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivMacro = 430 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemIMacro = 431 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemMacro = 432 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivIMacro = 433 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivMacro = 434 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemIMacro = 435 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemMacro = 436 CEFBS_NotInMips16Mode, // ERet = 437 CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // ExtractElementF64 = 438 CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // ExtractElementF64_64 = 439 CEFBS_HasStdEnc_HasMSA, // FABS_D = 440 CEFBS_HasStdEnc_HasMSA, // FABS_W = 441 CEFBS_HasStdEnc_HasMSA, // FEXP2_D_1_PSEUDO = 442 CEFBS_HasStdEnc_HasMSA, // FEXP2_W_1_PSEUDO = 443 CEFBS_HasStdEnc_HasMSA, // FILL_FD_PSEUDO = 444 CEFBS_HasStdEnc_HasMSA, // FILL_FW_PSEUDO = 445 CEFBS_InMips16Mode, // GotPrologue16 = 446 CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX64_PSEUDO = 447 CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX_PSEUDO = 448 CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX64_PSEUDO = 449 CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX_PSEUDO = 450 CEFBS_HasStdEnc_HasMSA, // INSERT_FD_PSEUDO = 451 CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX64_PSEUDO = 452 CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX_PSEUDO = 453 CEFBS_HasStdEnc_HasMSA, // INSERT_FW_PSEUDO = 454 CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX64_PSEUDO = 455 CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX_PSEUDO = 456 CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX64_PSEUDO = 457 CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX_PSEUDO = 458 CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX64_PSEUDO = 459 CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX_PSEUDO = 460 CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, // JALR64Pseudo = 461 CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, // JALRHB64Pseudo = 462 CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // JALRHBPseudo = 463 CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALRPseudo = 464 CEFBS_InMicroMips_HasMips32r6, // JAL_MMR6 = 465 CEFBS_None, // JalOneReg = 466 CEFBS_None, // JalTwoReg = 467 CEFBS_HasStdEnc_NotMips3, // LDMacro = 468 CEFBS_NotInMips16Mode, // LDR_D = 469 CEFBS_NotInMips16Mode, // LDR_W = 470 CEFBS_HasMSA, // LD_F16 = 471 CEFBS_NotInMips16Mode, // LOAD_ACC128 = 472 CEFBS_NotInMips16Mode, // LOAD_ACC64 = 473 CEFBS_NotInMips16Mode, // LOAD_ACC64DSP = 474 CEFBS_NotInMips16Mode, // LOAD_CCOND_DSP = 475 CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu = 476 CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu2Op = 477 CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu = 478 CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu2Op = 479 CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi = 480 CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi2Op = 481 CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_LUi2Op_64 = 482 CEFBS_InMicroMips, // LWM_MM = 483 CEFBS_None, // LoadAddrImm32 = 484 CEFBS_None, // LoadAddrImm64 = 485 CEFBS_None, // LoadAddrReg32 = 486 CEFBS_None, // LoadAddrReg64 = 487 CEFBS_None, // LoadImm32 = 488 CEFBS_None, // LoadImm64 = 489 CEFBS_IsFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR = 490 CEFBS_NotFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR_32 = 491 CEFBS_None, // LoadImmDoubleGPR = 492 CEFBS_IsNotSoftFloat, // LoadImmSingleFGR = 493 CEFBS_None, // LoadImmSingleGPR = 494 CEFBS_InMips16Mode, // LwConstant32 = 495 CEFBS_HasMT, // MFTACX = 496 CEFBS_HasMT, // MFTC0 = 497 CEFBS_HasMT, // MFTC1 = 498 CEFBS_HasMT, // MFTDSP = 499 CEFBS_HasMT, // MFTGPR = 500 CEFBS_HasMT, // MFTHC1 = 501 CEFBS_HasMT, // MFTHI = 502 CEFBS_HasMT, // MFTLO = 503 CEFBS_None, // MIPSeh_return32 = 504 CEFBS_None, // MIPSeh_return64 = 505 CEFBS_HasMSA, // MSA_FP_EXTEND_D_PSEUDO = 506 CEFBS_HasMSA, // MSA_FP_EXTEND_W_PSEUDO = 507 CEFBS_HasMSA, // MSA_FP_ROUND_D_PSEUDO = 508 CEFBS_HasMSA, // MSA_FP_ROUND_W_PSEUDO = 509 CEFBS_HasMT, // MTTACX = 510 CEFBS_HasMT, // MTTC0 = 511 CEFBS_HasMT, // MTTC1 = 512 CEFBS_HasMT, // MTTDSP = 513 CEFBS_HasMT, // MTTGPR = 514 CEFBS_HasMT, // MTTHC1 = 515 CEFBS_HasMT, // MTTHI = 516 CEFBS_HasMT, // MTTLO = 517 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULImmMacro = 518 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOMacro = 519 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOUMacro = 520 CEFBS_InMips16Mode, // MultRxRy16 = 521 CEFBS_InMips16Mode, // MultRxRyRz16 = 522 CEFBS_InMips16Mode, // MultuRxRy16 = 523 CEFBS_InMips16Mode, // MultuRxRyRz16 = 524 CEFBS_HasStdEnc_NotInMicroMips, // NOP = 525 CEFBS_IsGP32bit, // NORImm = 526 CEFBS_IsGP64bit, // NORImm64 = 527 CEFBS_HasStdEnc_HasMSA, // NOR_V_D_PSEUDO = 528 CEFBS_HasStdEnc_HasMSA, // NOR_V_H_PSEUDO = 529 CEFBS_HasStdEnc_HasMSA, // NOR_V_W_PSEUDO = 530 CEFBS_HasStdEnc_HasMSA, // OR_V_D_PSEUDO = 531 CEFBS_HasStdEnc_HasMSA, // OR_V_H_PSEUDO = 532 CEFBS_HasStdEnc_HasMSA, // OR_V_W_PSEUDO = 533 CEFBS_HasDSP, // PseudoCMPU_EQ_QB = 534 CEFBS_HasDSP, // PseudoCMPU_LE_QB = 535 CEFBS_HasDSP, // PseudoCMPU_LT_QB = 536 CEFBS_HasDSP, // PseudoCMP_EQ_PH = 537 CEFBS_HasDSP, // PseudoCMP_LE_PH = 538 CEFBS_HasDSP, // PseudoCMP_LT_PH = 539 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D32_W = 540 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_L = 541 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_W = 542 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_L = 543 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_W = 544 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULT = 545 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULTu = 546 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDSDIV = 547 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDUDIV = 548 CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I = 549 CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I64 = 550 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch = 551 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64 = 552 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64R6 = 553 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranchR6 = 554 CEFBS_InMicroMips_NotMips32r6, // PseudoIndirectBranch_MM = 555 CEFBS_InMicroMips_HasMips32r6, // PseudoIndirectBranch_MMR6 = 556 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch = 557 CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch64 = 558 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranch64R6 = 559 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranchR6 = 560 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADD = 561 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADDU = 562 CEFBS_InMicroMips_NotMips32r6, // PseudoMADDU_MM = 563 CEFBS_InMicroMips_NotMips32r6, // PseudoMADD_MM = 564 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFHI = 565 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFHI64 = 566 CEFBS_InMicroMips_NotMips32r6, // PseudoMFHI_MM = 567 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFLO = 568 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFLO64 = 569 CEFBS_InMicroMips_NotMips32r6, // PseudoMFLO_MM = 570 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUB = 571 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUBU = 572 CEFBS_InMicroMips_NotMips32r6, // PseudoMSUBU_MM = 573 CEFBS_InMicroMips_NotMips32r6, // PseudoMSUB_MM = 574 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMTLOHI = 575 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMTLOHI64 = 576 CEFBS_NotInMips16Mode_HasDSP, // PseudoMTLOHI_DSP = 577 CEFBS_InMicroMips_NotMips32r6, // PseudoMTLOHI_MM = 578 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULT = 579 CEFBS_InMicroMips_NotMips32r6, // PseudoMULT_MM = 580 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULTu = 581 CEFBS_InMicroMips_NotMips32r6, // PseudoMULTu_MM = 582 CEFBS_HasDSP, // PseudoPICK_PH = 583 CEFBS_HasDSP, // PseudoPICK_QB = 584 CEFBS_None, // PseudoReturn = 585 CEFBS_IsGP64bit, // PseudoReturn64 = 586 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoSDIV = 587 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_F_D32 = 588 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_F_D64 = 589 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I = 590 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I64 = 591 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_S = 592 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_T_D32 = 593 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_T_D64 = 594 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I = 595 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I64 = 596 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_S = 597 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECT_D32 = 598 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECT_D64 = 599 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I = 600 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I64 = 601 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_S = 602 CEFBS_IsFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D = 603 CEFBS_NotFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D32 = 604 CEFBS_None, // PseudoTRUNC_W_S = 605 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoUDIV = 606 CEFBS_None, // ROL = 607 CEFBS_None, // ROLImm = 608 CEFBS_None, // ROR = 609 CEFBS_None, // RORImm = 610 CEFBS_NotInMips16Mode, // RetRA = 611 CEFBS_InMips16Mode, // RetRA16 = 612 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, // SDC1_M1 = 613 CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // SDIV_MM_Pseudo = 614 CEFBS_HasStdEnc_NotMips3, // SDMacro = 615 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivIMacro = 616 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivMacro = 617 CEFBS_NotCnMips, // SEQIMacro = 618 CEFBS_NotCnMips, // SEQMacro = 619 CEFBS_HasStdEnc_NotInMicroMips, // SGE = 620 CEFBS_IsGP32bit_NotInMicroMips, // SGEImm = 621 CEFBS_IsGP64bit, // SGEImm64 = 622 CEFBS_HasStdEnc_NotInMicroMips, // SGEU = 623 CEFBS_IsGP32bit_NotInMicroMips, // SGEUImm = 624 CEFBS_IsGP64bit, // SGEUImm64 = 625 CEFBS_IsGP32bit_NotInMicroMips, // SGTImm = 626 CEFBS_IsGP64bit, // SGTImm64 = 627 CEFBS_IsGP32bit_NotInMicroMips, // SGTUImm = 628 CEFBS_IsGP64bit, // SGTUImm64 = 629 CEFBS_HasStdEnc_NotInMicroMips, // SLE = 630 CEFBS_IsGP32bit_NotInMicroMips, // SLEImm = 631 CEFBS_IsGP64bit, // SLEImm64 = 632 CEFBS_HasStdEnc_NotInMicroMips, // SLEU = 633 CEFBS_IsGP32bit_NotInMicroMips, // SLEUImm = 634 CEFBS_IsGP64bit, // SLEUImm64 = 635 CEFBS_IsGP64bit, // SLTImm64 = 636 CEFBS_IsGP64bit, // SLTUImm64 = 637 CEFBS_NotCnMips, // SNEIMacro = 638 CEFBS_NotCnMips, // SNEMacro = 639 CEFBS_None, // SNZ_B_PSEUDO = 640 CEFBS_None, // SNZ_D_PSEUDO = 641 CEFBS_None, // SNZ_H_PSEUDO = 642 CEFBS_None, // SNZ_V_PSEUDO = 643 CEFBS_None, // SNZ_W_PSEUDO = 644 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemIMacro = 645 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemMacro = 646 CEFBS_NotInMips16Mode, // STORE_ACC128 = 647 CEFBS_NotInMips16Mode, // STORE_ACC64 = 648 CEFBS_NotInMips16Mode, // STORE_ACC64DSP = 649 CEFBS_NotInMips16Mode, // STORE_CCOND_DSP = 650 CEFBS_NotInMips16Mode, // STR_D = 651 CEFBS_NotInMips16Mode, // STR_W = 652 CEFBS_HasMSA, // ST_F16 = 653 CEFBS_InMicroMips, // SWM_MM = 654 CEFBS_None, // SZ_B_PSEUDO = 655 CEFBS_None, // SZ_D_PSEUDO = 656 CEFBS_None, // SZ_H_PSEUDO = 657 CEFBS_None, // SZ_V_PSEUDO = 658 CEFBS_None, // SZ_W_PSEUDO = 659 CEFBS_HasCnMipsP, // SaaAddr = 660 CEFBS_HasCnMipsP, // SaadAddr = 661 CEFBS_InMips16Mode, // SelBeqZ = 662 CEFBS_InMips16Mode, // SelBneZ = 663 CEFBS_InMips16Mode, // SelTBteqZCmp = 664 CEFBS_InMips16Mode, // SelTBteqZCmpi = 665 CEFBS_InMips16Mode, // SelTBteqZSlt = 666 CEFBS_InMips16Mode, // SelTBteqZSlti = 667 CEFBS_InMips16Mode, // SelTBteqZSltiu = 668 CEFBS_InMips16Mode, // SelTBteqZSltu = 669 CEFBS_InMips16Mode, // SelTBtneZCmp = 670 CEFBS_InMips16Mode, // SelTBtneZCmpi = 671 CEFBS_InMips16Mode, // SelTBtneZSlt = 672 CEFBS_InMips16Mode, // SelTBtneZSlti = 673 CEFBS_InMips16Mode, // SelTBtneZSltiu = 674 CEFBS_InMips16Mode, // SelTBtneZSltu = 675 CEFBS_InMips16Mode, // SltCCRxRy16 = 676 CEFBS_InMips16Mode, // SltiCCRxImmX16 = 677 CEFBS_InMips16Mode, // SltiuCCRxImmX16 = 678 CEFBS_InMips16Mode, // SltuCCRxRy16 = 679 CEFBS_InMips16Mode, // SltuRxRyRz16 = 680 CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, // TAILCALL = 681 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALL64R6REG = 682 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHB64R6REG = 683 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHBR6REG = 684 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLR6REG = 685 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG = 686 CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG64 = 687 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB = 688 CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB64 = 689 CEFBS_InMicroMips_NotMips32r6, // TAILCALLREG_MM = 690 CEFBS_InMicroMips_HasMips32r6, // TAILCALLREG_MMR6 = 691 CEFBS_InMicroMips_NotMips32r6, // TAILCALL_MM = 692 CEFBS_InMicroMips_HasMips32r6, // TAILCALL_MMR6 = 693 CEFBS_HasStdEnc_NotInMicroMips, // TRAP = 694 CEFBS_InMicroMips, // TRAP_MM = 695 CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // UDIV_MM_Pseudo = 696 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivIMacro = 697 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivMacro = 698 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemIMacro = 699 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemMacro = 700 CEFBS_None, // Ulh = 701 CEFBS_None, // Ulhu = 702 CEFBS_None, // Ulw = 703 CEFBS_None, // Ush = 704 CEFBS_None, // Usw = 705 CEFBS_HasStdEnc_HasMSA, // XOR_V_D_PSEUDO = 706 CEFBS_HasStdEnc_HasMSA, // XOR_V_H_PSEUDO = 707 CEFBS_HasStdEnc_HasMSA, // XOR_V_W_PSEUDO = 708 CEFBS_HasDSP, // ABSQ_S_PH = 709 CEFBS_InMicroMips_HasDSP, // ABSQ_S_PH_MM = 710 CEFBS_HasDSPR2, // ABSQ_S_QB = 711 CEFBS_InMicroMips_HasDSPR2, // ABSQ_S_QB_MMR2 = 712 CEFBS_HasDSP, // ABSQ_S_W = 713 CEFBS_InMicroMips_HasDSP, // ABSQ_S_W_MM = 714 CEFBS_HasStdEnc_NotInMicroMips, // ADD = 715 CEFBS_HasStdEnc_HasMips32r6, // ADDIUPC = 716 CEFBS_InMicroMips_NotMips32r6, // ADDIUPC_MM = 717 CEFBS_InMicroMips_HasMips32r6, // ADDIUPC_MMR6 = 718 CEFBS_InMicroMips, // ADDIUR1SP_MM = 719 CEFBS_InMicroMips, // ADDIUR2_MM = 720 CEFBS_InMicroMips, // ADDIUS5_MM = 721 CEFBS_InMicroMips, // ADDIUSP_MM = 722 CEFBS_InMicroMips_HasMips32r6, // ADDIU_MMR6 = 723 CEFBS_HasDSPR2, // ADDQH_PH = 724 CEFBS_InMicroMips_HasDSPR2, // ADDQH_PH_MMR2 = 725 CEFBS_HasDSPR2, // ADDQH_R_PH = 726 CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_PH_MMR2 = 727 CEFBS_HasDSPR2, // ADDQH_R_W = 728 CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_W_MMR2 = 729 CEFBS_HasDSPR2, // ADDQH_W = 730 CEFBS_InMicroMips_HasDSPR2, // ADDQH_W_MMR2 = 731 CEFBS_HasDSP, // ADDQ_PH = 732 CEFBS_InMicroMips_HasDSP, // ADDQ_PH_MM = 733 CEFBS_HasDSP, // ADDQ_S_PH = 734 CEFBS_InMicroMips_HasDSP, // ADDQ_S_PH_MM = 735 CEFBS_HasDSP, // ADDQ_S_W = 736 CEFBS_InMicroMips_HasDSP, // ADDQ_S_W_MM = 737 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // ADDR_PS64 = 738 CEFBS_HasDSP, // ADDSC = 739 CEFBS_InMicroMips_HasDSP, // ADDSC_MM = 740 CEFBS_HasStdEnc_HasMSA, // ADDS_A_B = 741 CEFBS_HasStdEnc_HasMSA, // ADDS_A_D = 742 CEFBS_HasStdEnc_HasMSA, // ADDS_A_H = 743 CEFBS_HasStdEnc_HasMSA, // ADDS_A_W = 744 CEFBS_HasStdEnc_HasMSA, // ADDS_S_B = 745 CEFBS_HasStdEnc_HasMSA, // ADDS_S_D = 746 CEFBS_HasStdEnc_HasMSA, // ADDS_S_H = 747 CEFBS_HasStdEnc_HasMSA, // ADDS_S_W = 748 CEFBS_HasStdEnc_HasMSA, // ADDS_U_B = 749 CEFBS_HasStdEnc_HasMSA, // ADDS_U_D = 750 CEFBS_HasStdEnc_HasMSA, // ADDS_U_H = 751 CEFBS_HasStdEnc_HasMSA, // ADDS_U_W = 752 CEFBS_InMicroMips_NotMips32r6, // ADDU16_MM = 753 CEFBS_InMicroMips_HasMips32r6, // ADDU16_MMR6 = 754 CEFBS_HasDSPR2, // ADDUH_QB = 755 CEFBS_InMicroMips_HasDSPR2, // ADDUH_QB_MMR2 = 756 CEFBS_HasDSPR2, // ADDUH_R_QB = 757 CEFBS_InMicroMips_HasDSPR2, // ADDUH_R_QB_MMR2 = 758 CEFBS_InMicroMips_HasMips32r6, // ADDU_MMR6 = 759 CEFBS_HasDSPR2, // ADDU_PH = 760 CEFBS_InMicroMips_HasDSPR2, // ADDU_PH_MMR2 = 761 CEFBS_HasDSP, // ADDU_QB = 762 CEFBS_InMicroMips_HasDSP, // ADDU_QB_MM = 763 CEFBS_HasDSPR2, // ADDU_S_PH = 764 CEFBS_InMicroMips_HasDSPR2, // ADDU_S_PH_MMR2 = 765 CEFBS_HasDSP, // ADDU_S_QB = 766 CEFBS_InMicroMips_HasDSP, // ADDU_S_QB_MM = 767 CEFBS_HasStdEnc_HasMSA, // ADDVI_B = 768 CEFBS_HasStdEnc_HasMSA, // ADDVI_D = 769 CEFBS_HasStdEnc_HasMSA, // ADDVI_H = 770 CEFBS_HasStdEnc_HasMSA, // ADDVI_W = 771 CEFBS_HasStdEnc_HasMSA, // ADDV_B = 772 CEFBS_HasStdEnc_HasMSA, // ADDV_D = 773 CEFBS_HasStdEnc_HasMSA, // ADDV_H = 774 CEFBS_HasStdEnc_HasMSA, // ADDV_W = 775 CEFBS_HasDSP, // ADDWC = 776 CEFBS_InMicroMips_HasDSP, // ADDWC_MM = 777 CEFBS_HasStdEnc_HasMSA, // ADD_A_B = 778 CEFBS_HasStdEnc_HasMSA, // ADD_A_D = 779 CEFBS_HasStdEnc_HasMSA, // ADD_A_H = 780 CEFBS_HasStdEnc_HasMSA, // ADD_A_W = 781 CEFBS_InMicroMips_NotMips32r6, // ADD_MM = 782 CEFBS_InMicroMips_HasMips32r6, // ADD_MMR6 = 783 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // ADDi = 784 CEFBS_InMicroMips_NotMips32r6, // ADDi_MM = 785 CEFBS_HasStdEnc_NotInMicroMips, // ADDiu = 786 CEFBS_InMicroMips_NotMips32r6, // ADDiu_MM = 787 CEFBS_HasStdEnc_NotInMicroMips, // ADDu = 788 CEFBS_InMicroMips_NotMips32r6, // ADDu_MM = 789 CEFBS_HasStdEnc_HasMips32r6, // ALIGN = 790 CEFBS_InMicroMips_HasMips32r6, // ALIGN_MMR6 = 791 CEFBS_HasStdEnc_HasMips32r6, // ALUIPC = 792 CEFBS_InMicroMips_HasMips32r6, // ALUIPC_MMR6 = 793 CEFBS_HasStdEnc_NotInMicroMips, // AND = 794 CEFBS_InMicroMips_NotMips32r6, // AND16_MM = 795 CEFBS_InMicroMips_HasMips32r6, // AND16_MMR6 = 796 CEFBS_NotInMips16Mode_IsGP64bit, // AND64 = 797 CEFBS_InMicroMips_NotMips32r6, // ANDI16_MM = 798 CEFBS_InMicroMips_HasMips32r6, // ANDI16_MMR6 = 799 CEFBS_HasStdEnc_HasMSA, // ANDI_B = 800 CEFBS_InMicroMips_HasMips32r6, // ANDI_MMR6 = 801 CEFBS_InMicroMips_NotMips32r6, // AND_MM = 802 CEFBS_InMicroMips_HasMips32r6, // AND_MMR6 = 803 CEFBS_HasStdEnc_HasMSA, // AND_V = 804 CEFBS_HasStdEnc_NotInMicroMips, // ANDi = 805 CEFBS_NotInMips16Mode_IsGP64bit, // ANDi64 = 806 CEFBS_InMicroMips_NotMips32r6, // ANDi_MM = 807 CEFBS_HasDSPR2, // APPEND = 808 CEFBS_InMicroMips_HasDSPR2, // APPEND_MMR2 = 809 CEFBS_HasStdEnc_HasMSA, // ASUB_S_B = 810 CEFBS_HasStdEnc_HasMSA, // ASUB_S_D = 811 CEFBS_HasStdEnc_HasMSA, // ASUB_S_H = 812 CEFBS_HasStdEnc_HasMSA, // ASUB_S_W = 813 CEFBS_HasStdEnc_HasMSA, // ASUB_U_B = 814 CEFBS_HasStdEnc_HasMSA, // ASUB_U_D = 815 CEFBS_HasStdEnc_HasMSA, // ASUB_U_H = 816 CEFBS_HasStdEnc_HasMSA, // ASUB_U_W = 817 CEFBS_HasStdEnc_HasMips32r6, // AUI = 818 CEFBS_HasStdEnc_HasMips32r6, // AUIPC = 819 CEFBS_InMicroMips_HasMips32r6, // AUIPC_MMR6 = 820 CEFBS_InMicroMips_HasMips32r6, // AUI_MMR6 = 821 CEFBS_HasStdEnc_HasMSA, // AVER_S_B = 822 CEFBS_HasStdEnc_HasMSA, // AVER_S_D = 823 CEFBS_HasStdEnc_HasMSA, // AVER_S_H = 824 CEFBS_HasStdEnc_HasMSA, // AVER_S_W = 825 CEFBS_HasStdEnc_HasMSA, // AVER_U_B = 826 CEFBS_HasStdEnc_HasMSA, // AVER_U_D = 827 CEFBS_HasStdEnc_HasMSA, // AVER_U_H = 828 CEFBS_HasStdEnc_HasMSA, // AVER_U_W = 829 CEFBS_HasStdEnc_HasMSA, // AVE_S_B = 830 CEFBS_HasStdEnc_HasMSA, // AVE_S_D = 831 CEFBS_HasStdEnc_HasMSA, // AVE_S_H = 832 CEFBS_HasStdEnc_HasMSA, // AVE_S_W = 833 CEFBS_HasStdEnc_HasMSA, // AVE_U_B = 834 CEFBS_HasStdEnc_HasMSA, // AVE_U_D = 835 CEFBS_HasStdEnc_HasMSA, // AVE_U_H = 836 CEFBS_HasStdEnc_HasMSA, // AVE_U_W = 837 CEFBS_InMips16Mode, // AddiuRxImmX16 = 838 CEFBS_InMips16Mode, // AddiuRxPcImmX16 = 839 CEFBS_InMips16Mode, // AddiuRxRxImm16 = 840 CEFBS_InMips16Mode, // AddiuRxRxImmX16 = 841 CEFBS_InMips16Mode, // AddiuRxRyOffMemX16 = 842 CEFBS_InMips16Mode, // AddiuSpImm16 = 843 CEFBS_InMips16Mode, // AddiuSpImmX16 = 844 CEFBS_InMips16Mode, // AdduRxRyRz16 = 845 CEFBS_InMips16Mode, // AndRxRxRy16 = 846 CEFBS_InMicroMips, // B16_MM = 847 CEFBS_HasCnMips, // BADDu = 848 CEFBS_HasStdEnc_HasMips32r6, // BAL = 849 CEFBS_HasStdEnc_HasMips32r6, // BALC = 850 CEFBS_InMicroMips_HasMips32r6, // BALC_MMR6 = 851 CEFBS_HasDSPR2, // BALIGN = 852 CEFBS_InMicroMips_HasDSPR2, // BALIGN_MMR2 = 853 CEFBS_HasCnMips, // BBIT0 = 854 CEFBS_HasCnMips, // BBIT032 = 855 CEFBS_HasCnMips, // BBIT1 = 856 CEFBS_HasCnMips, // BBIT132 = 857 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC = 858 CEFBS_InMicroMips_HasMips32r6, // BC16_MMR6 = 859 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1EQZ = 860 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1EQZC_MMR6 = 861 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1F = 862 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1FL = 863 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1F_MM = 864 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1NEZ = 865 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1NEZC_MMR6 = 866 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1T = 867 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1TL = 868 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1T_MM = 869 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2EQZ = 870 CEFBS_InMicroMips_HasMips32r6, // BC2EQZC_MMR6 = 871 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2NEZ = 872 CEFBS_InMicroMips_HasMips32r6, // BC2NEZC_MMR6 = 873 CEFBS_HasStdEnc_HasMSA, // BCLRI_B = 874 CEFBS_HasStdEnc_HasMSA, // BCLRI_D = 875 CEFBS_HasStdEnc_HasMSA, // BCLRI_H = 876 CEFBS_HasStdEnc_HasMSA, // BCLRI_W = 877 CEFBS_HasStdEnc_HasMSA, // BCLR_B = 878 CEFBS_HasStdEnc_HasMSA, // BCLR_D = 879 CEFBS_HasStdEnc_HasMSA, // BCLR_H = 880 CEFBS_HasStdEnc_HasMSA, // BCLR_W = 881 CEFBS_InMicroMips_HasMips32r6, // BC_MMR6 = 882 CEFBS_HasStdEnc_NotInMicroMips, // BEQ = 883 CEFBS_NotInMips16Mode_IsGP64bit, // BEQ64 = 884 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQC = 885 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQC64 = 886 CEFBS_InMicroMips_HasMips32r6, // BEQC_MMR6 = 887 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BEQL = 888 CEFBS_InMicroMips_NotMips32r6, // BEQZ16_MM = 889 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZALC = 890 CEFBS_InMicroMips_HasMips32r6, // BEQZALC_MMR6 = 891 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZC = 892 CEFBS_InMicroMips_HasMips32r6, // BEQZC16_MMR6 = 893 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQZC64 = 894 CEFBS_InMicroMips_NotMips32r6, // BEQZC_MM = 895 CEFBS_InMicroMips_HasMips32r6, // BEQZC_MMR6 = 896 CEFBS_InMicroMips_NotMips32r6, // BEQ_MM = 897 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEC = 898 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEC64 = 899 CEFBS_InMicroMips_HasMips32r6, // BGEC_MMR6 = 900 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEUC = 901 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEUC64 = 902 CEFBS_InMicroMips_HasMips32r6, // BGEUC_MMR6 = 903 CEFBS_HasStdEnc_NotInMicroMips, // BGEZ = 904 CEFBS_NotInMips16Mode_IsGP64bit, // BGEZ64 = 905 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZAL = 906 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZALC = 907 CEFBS_InMicroMips_HasMips32r6, // BGEZALC_MMR6 = 908 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZALL = 909 CEFBS_InMicroMips_NotMips32r6, // BGEZALS_MM = 910 CEFBS_InMicroMips_NotMips32r6, // BGEZAL_MM = 911 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZC = 912 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEZC64 = 913 CEFBS_InMicroMips_HasMips32r6, // BGEZC_MMR6 = 914 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZL = 915 CEFBS_InMicroMips_NotMips32r6, // BGEZ_MM = 916 CEFBS_HasStdEnc_NotInMicroMips, // BGTZ = 917 CEFBS_NotInMips16Mode_IsGP64bit, // BGTZ64 = 918 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZALC = 919 CEFBS_InMicroMips_HasMips32r6, // BGTZALC_MMR6 = 920 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZC = 921 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGTZC64 = 922 CEFBS_InMicroMips_HasMips32r6, // BGTZC_MMR6 = 923 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGTZL = 924 CEFBS_InMicroMips_NotMips32r6, // BGTZ_MM = 925 CEFBS_HasStdEnc_HasMSA, // BINSLI_B = 926 CEFBS_HasStdEnc_HasMSA, // BINSLI_D = 927 CEFBS_HasStdEnc_HasMSA, // BINSLI_H = 928 CEFBS_HasStdEnc_HasMSA, // BINSLI_W = 929 CEFBS_HasStdEnc_HasMSA, // BINSL_B = 930 CEFBS_HasStdEnc_HasMSA, // BINSL_D = 931 CEFBS_HasStdEnc_HasMSA, // BINSL_H = 932 CEFBS_HasStdEnc_HasMSA, // BINSL_W = 933 CEFBS_HasStdEnc_HasMSA, // BINSRI_B = 934 CEFBS_HasStdEnc_HasMSA, // BINSRI_D = 935 CEFBS_HasStdEnc_HasMSA, // BINSRI_H = 936 CEFBS_HasStdEnc_HasMSA, // BINSRI_W = 937 CEFBS_HasStdEnc_HasMSA, // BINSR_B = 938 CEFBS_HasStdEnc_HasMSA, // BINSR_D = 939 CEFBS_HasStdEnc_HasMSA, // BINSR_H = 940 CEFBS_HasStdEnc_HasMSA, // BINSR_W = 941 CEFBS_HasDSP, // BITREV = 942 CEFBS_InMicroMips_HasDSP, // BITREV_MM = 943 CEFBS_HasStdEnc_HasMips32r6, // BITSWAP = 944 CEFBS_InMicroMips_HasMips32r6, // BITSWAP_MMR6 = 945 CEFBS_HasStdEnc_NotInMicroMips, // BLEZ = 946 CEFBS_NotInMips16Mode_IsGP64bit, // BLEZ64 = 947 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZALC = 948 CEFBS_InMicroMips_HasMips32r6, // BLEZALC_MMR6 = 949 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZC = 950 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLEZC64 = 951 CEFBS_InMicroMips_HasMips32r6, // BLEZC_MMR6 = 952 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLEZL = 953 CEFBS_InMicroMips_NotMips32r6, // BLEZ_MM = 954 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTC = 955 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTC64 = 956 CEFBS_InMicroMips_HasMips32r6, // BLTC_MMR6 = 957 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTUC = 958 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTUC64 = 959 CEFBS_InMicroMips_HasMips32r6, // BLTUC_MMR6 = 960 CEFBS_HasStdEnc_NotInMicroMips, // BLTZ = 961 CEFBS_NotInMips16Mode_IsGP64bit, // BLTZ64 = 962 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZAL = 963 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZALC = 964 CEFBS_InMicroMips_HasMips32r6, // BLTZALC_MMR6 = 965 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZALL = 966 CEFBS_InMicroMips_NotMips32r6, // BLTZALS_MM = 967 CEFBS_InMicroMips_NotMips32r6, // BLTZAL_MM = 968 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZC = 969 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTZC64 = 970 CEFBS_InMicroMips_HasMips32r6, // BLTZC_MMR6 = 971 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZL = 972 CEFBS_InMicroMips_NotMips32r6, // BLTZ_MM = 973 CEFBS_HasStdEnc_HasMSA, // BMNZI_B = 974 CEFBS_HasStdEnc_HasMSA, // BMNZ_V = 975 CEFBS_HasStdEnc_HasMSA, // BMZI_B = 976 CEFBS_HasStdEnc_HasMSA, // BMZ_V = 977 CEFBS_HasStdEnc_NotInMicroMips, // BNE = 978 CEFBS_NotInMips16Mode_IsGP64bit, // BNE64 = 979 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEC = 980 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEC64 = 981 CEFBS_InMicroMips_HasMips32r6, // BNEC_MMR6 = 982 CEFBS_HasStdEnc_HasMSA, // BNEGI_B = 983 CEFBS_HasStdEnc_HasMSA, // BNEGI_D = 984 CEFBS_HasStdEnc_HasMSA, // BNEGI_H = 985 CEFBS_HasStdEnc_HasMSA, // BNEGI_W = 986 CEFBS_HasStdEnc_HasMSA, // BNEG_B = 987 CEFBS_HasStdEnc_HasMSA, // BNEG_D = 988 CEFBS_HasStdEnc_HasMSA, // BNEG_H = 989 CEFBS_HasStdEnc_HasMSA, // BNEG_W = 990 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BNEL = 991 CEFBS_InMicroMips_NotMips32r6, // BNEZ16_MM = 992 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZALC = 993 CEFBS_InMicroMips_HasMips32r6, // BNEZALC_MMR6 = 994 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZC = 995 CEFBS_InMicroMips_HasMips32r6, // BNEZC16_MMR6 = 996 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEZC64 = 997 CEFBS_InMicroMips_NotMips32r6, // BNEZC_MM = 998 CEFBS_InMicroMips_HasMips32r6, // BNEZC_MMR6 = 999 CEFBS_InMicroMips_NotMips32r6, // BNE_MM = 1000 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNVC = 1001 CEFBS_InMicroMips_HasMips32r6, // BNVC_MMR6 = 1002 CEFBS_HasStdEnc_HasMSA, // BNZ_B = 1003 CEFBS_HasStdEnc_HasMSA, // BNZ_D = 1004 CEFBS_HasStdEnc_HasMSA, // BNZ_H = 1005 CEFBS_HasStdEnc_HasMSA, // BNZ_V = 1006 CEFBS_HasStdEnc_HasMSA, // BNZ_W = 1007 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BOVC = 1008 CEFBS_InMicroMips_HasMips32r6, // BOVC_MMR6 = 1009 CEFBS_HasDSP_NotInMicroMips, // BPOSGE32 = 1010 CEFBS_InMicroMips_HasDSPR3, // BPOSGE32C_MMR3 = 1011 CEFBS_InMicroMips_NotMips32r6_HasDSP, // BPOSGE32_MM = 1012 CEFBS_HasStdEnc_NotInMicroMips, // BREAK = 1013 CEFBS_InMicroMips_NotMips32r6, // BREAK16_MM = 1014 CEFBS_InMicroMips_HasMips32r6, // BREAK16_MMR6 = 1015 CEFBS_InMicroMips, // BREAK_MM = 1016 CEFBS_InMicroMips_HasMips32r6, // BREAK_MMR6 = 1017 CEFBS_HasStdEnc_HasMSA, // BSELI_B = 1018 CEFBS_HasStdEnc_HasMSA, // BSEL_V = 1019 CEFBS_HasStdEnc_HasMSA, // BSETI_B = 1020 CEFBS_HasStdEnc_HasMSA, // BSETI_D = 1021 CEFBS_HasStdEnc_HasMSA, // BSETI_H = 1022 CEFBS_HasStdEnc_HasMSA, // BSETI_W = 1023 CEFBS_HasStdEnc_HasMSA, // BSET_B = 1024 CEFBS_HasStdEnc_HasMSA, // BSET_D = 1025 CEFBS_HasStdEnc_HasMSA, // BSET_H = 1026 CEFBS_HasStdEnc_HasMSA, // BSET_W = 1027 CEFBS_HasStdEnc_HasMSA, // BZ_B = 1028 CEFBS_HasStdEnc_HasMSA, // BZ_D = 1029 CEFBS_HasStdEnc_HasMSA, // BZ_H = 1030 CEFBS_HasStdEnc_HasMSA, // BZ_V = 1031 CEFBS_HasStdEnc_HasMSA, // BZ_W = 1032 CEFBS_InMips16Mode, // BeqzRxImm16 = 1033 CEFBS_InMips16Mode, // BeqzRxImmX16 = 1034 CEFBS_InMips16Mode, // Bimm16 = 1035 CEFBS_InMips16Mode, // BimmX16 = 1036 CEFBS_InMips16Mode, // BnezRxImm16 = 1037 CEFBS_InMips16Mode, // BnezRxImmX16 = 1038 CEFBS_InMips16Mode, // Break16 = 1039 CEFBS_InMips16Mode, // Bteqz16 = 1040 CEFBS_InMips16Mode, // BteqzX16 = 1041 CEFBS_InMips16Mode, // Btnez16 = 1042 CEFBS_InMips16Mode, // BtnezX16 = 1043 CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // CACHE = 1044 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // CACHEE = 1045 CEFBS_InMicroMips_HasEVA, // CACHEE_MM = 1046 CEFBS_InMicroMips_NotMips32r6, // CACHE_MM = 1047 CEFBS_InMicroMips_HasMips32r6, // CACHE_MMR6 = 1048 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // CACHE_R6 = 1049 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // CEIL_L_D64 = 1050 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_D_MMR6 = 1051 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_L_S = 1052 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_S_MMR6 = 1053 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D32 = 1054 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D64 = 1055 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_D_MMR6 = 1056 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CEIL_W_MM = 1057 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_S = 1058 CEFBS_InMicroMips_IsNotSoftFloat, // CEIL_W_S_MM = 1059 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_S_MMR6 = 1060 CEFBS_HasStdEnc_HasMSA, // CEQI_B = 1061 CEFBS_HasStdEnc_HasMSA, // CEQI_D = 1062 CEFBS_HasStdEnc_HasMSA, // CEQI_H = 1063 CEFBS_HasStdEnc_HasMSA, // CEQI_W = 1064 CEFBS_HasStdEnc_HasMSA, // CEQ_B = 1065 CEFBS_HasStdEnc_HasMSA, // CEQ_D = 1066 CEFBS_HasStdEnc_HasMSA, // CEQ_H = 1067 CEFBS_HasStdEnc_HasMSA, // CEQ_W = 1068 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CFC1 = 1069 CEFBS_InMicroMips_IsNotSoftFloat, // CFC1_MM = 1070 CEFBS_InMicroMips, // CFC2_MM = 1071 CEFBS_HasStdEnc_HasMSA, // CFCMSA = 1072 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS = 1073 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS32 = 1074 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS64_32 = 1075 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS_i32 = 1076 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_D = 1077 CEFBS_InMicroMips_HasMips32r6, // CLASS_D_MMR6 = 1078 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_S = 1079 CEFBS_InMicroMips_HasMips32r6, // CLASS_S_MMR6 = 1080 CEFBS_HasStdEnc_HasMSA, // CLEI_S_B = 1081 CEFBS_HasStdEnc_HasMSA, // CLEI_S_D = 1082 CEFBS_HasStdEnc_HasMSA, // CLEI_S_H = 1083 CEFBS_HasStdEnc_HasMSA, // CLEI_S_W = 1084 CEFBS_HasStdEnc_HasMSA, // CLEI_U_B = 1085 CEFBS_HasStdEnc_HasMSA, // CLEI_U_D = 1086 CEFBS_HasStdEnc_HasMSA, // CLEI_U_H = 1087 CEFBS_HasStdEnc_HasMSA, // CLEI_U_W = 1088 CEFBS_HasStdEnc_HasMSA, // CLE_S_B = 1089 CEFBS_HasStdEnc_HasMSA, // CLE_S_D = 1090 CEFBS_HasStdEnc_HasMSA, // CLE_S_H = 1091 CEFBS_HasStdEnc_HasMSA, // CLE_S_W = 1092 CEFBS_HasStdEnc_HasMSA, // CLE_U_B = 1093 CEFBS_HasStdEnc_HasMSA, // CLE_U_D = 1094 CEFBS_HasStdEnc_HasMSA, // CLE_U_H = 1095 CEFBS_HasStdEnc_HasMSA, // CLE_U_W = 1096 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLO = 1097 CEFBS_InMicroMips, // CLO_MM = 1098 CEFBS_InMicroMips_HasMips32r6, // CLO_MMR6 = 1099 CEFBS_HasStdEnc_HasMips32r6, // CLO_R6 = 1100 CEFBS_HasStdEnc_HasMSA, // CLTI_S_B = 1101 CEFBS_HasStdEnc_HasMSA, // CLTI_S_D = 1102 CEFBS_HasStdEnc_HasMSA, // CLTI_S_H = 1103 CEFBS_HasStdEnc_HasMSA, // CLTI_S_W = 1104 CEFBS_HasStdEnc_HasMSA, // CLTI_U_B = 1105 CEFBS_HasStdEnc_HasMSA, // CLTI_U_D = 1106 CEFBS_HasStdEnc_HasMSA, // CLTI_U_H = 1107 CEFBS_HasStdEnc_HasMSA, // CLTI_U_W = 1108 CEFBS_HasStdEnc_HasMSA, // CLT_S_B = 1109 CEFBS_HasStdEnc_HasMSA, // CLT_S_D = 1110 CEFBS_HasStdEnc_HasMSA, // CLT_S_H = 1111 CEFBS_HasStdEnc_HasMSA, // CLT_S_W = 1112 CEFBS_HasStdEnc_HasMSA, // CLT_U_B = 1113 CEFBS_HasStdEnc_HasMSA, // CLT_U_D = 1114 CEFBS_HasStdEnc_HasMSA, // CLT_U_H = 1115 CEFBS_HasStdEnc_HasMSA, // CLT_U_W = 1116 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLZ = 1117 CEFBS_InMicroMips, // CLZ_MM = 1118 CEFBS_InMicroMips_HasMips32r6, // CLZ_MMR6 = 1119 CEFBS_HasStdEnc_HasMips32r6, // CLZ_R6 = 1120 CEFBS_HasDSPR2, // CMPGDU_EQ_QB = 1121 CEFBS_InMicroMips_HasDSPR2, // CMPGDU_EQ_QB_MMR2 = 1122 CEFBS_HasDSPR2, // CMPGDU_LE_QB = 1123 CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LE_QB_MMR2 = 1124 CEFBS_HasDSPR2, // CMPGDU_LT_QB = 1125 CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LT_QB_MMR2 = 1126 CEFBS_HasDSP, // CMPGU_EQ_QB = 1127 CEFBS_InMicroMips_HasDSP, // CMPGU_EQ_QB_MM = 1128 CEFBS_HasDSP, // CMPGU_LE_QB = 1129 CEFBS_InMicroMips_HasDSP, // CMPGU_LE_QB_MM = 1130 CEFBS_HasDSP, // CMPGU_LT_QB = 1131 CEFBS_InMicroMips_HasDSP, // CMPGU_LT_QB_MM = 1132 CEFBS_HasDSP, // CMPU_EQ_QB = 1133 CEFBS_InMicroMips_HasDSP, // CMPU_EQ_QB_MM = 1134 CEFBS_HasDSP, // CMPU_LE_QB = 1135 CEFBS_InMicroMips_HasDSP, // CMPU_LE_QB_MM = 1136 CEFBS_HasDSP, // CMPU_LT_QB = 1137 CEFBS_InMicroMips_HasDSP, // CMPU_LT_QB_MM = 1138 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_D_MMR6 = 1139 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_S_MMR6 = 1140 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_D = 1141 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_D_MMR6 = 1142 CEFBS_HasDSP, // CMP_EQ_PH = 1143 CEFBS_InMicroMips_HasDSP, // CMP_EQ_PH_MM = 1144 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_S = 1145 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_S_MMR6 = 1146 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_D = 1147 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_S = 1148 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_D = 1149 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_D_MMR6 = 1150 CEFBS_HasDSP, // CMP_LE_PH = 1151 CEFBS_InMicroMips_HasDSP, // CMP_LE_PH_MM = 1152 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_S = 1153 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_S_MMR6 = 1154 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_D = 1155 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_D_MMR6 = 1156 CEFBS_HasDSP, // CMP_LT_PH = 1157 CEFBS_InMicroMips_HasDSP, // CMP_LT_PH_MM = 1158 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_S = 1159 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_S_MMR6 = 1160 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_D = 1161 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_D_MMR6 = 1162 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_S = 1163 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_S_MMR6 = 1164 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_D = 1165 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_D_MMR6 = 1166 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_S = 1167 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_S_MMR6 = 1168 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_D = 1169 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_D_MMR6 = 1170 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_S = 1171 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_S_MMR6 = 1172 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_D = 1173 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_D_MMR6 = 1174 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_S = 1175 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_S_MMR6 = 1176 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_D = 1177 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_D_MMR6 = 1178 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_S = 1179 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_S_MMR6 = 1180 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_D = 1181 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_D_MMR6 = 1182 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_S = 1183 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_S_MMR6 = 1184 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_D = 1185 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_D_MMR6 = 1186 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_S = 1187 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_S_MMR6 = 1188 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_D = 1189 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_D_MMR6 = 1190 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_S = 1191 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_S_MMR6 = 1192 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_D = 1193 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_D_MMR6 = 1194 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_S = 1195 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_S_MMR6 = 1196 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_D = 1197 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_D_MMR6 = 1198 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_S = 1199 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_S_MMR6 = 1200 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_D = 1201 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_D_MMR6 = 1202 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_S = 1203 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_S_MMR6 = 1204 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_D = 1205 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_D_MMR6 = 1206 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_S = 1207 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_S_MMR6 = 1208 CEFBS_HasStdEnc_HasMSA, // COPY_S_B = 1209 CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_S_D = 1210 CEFBS_HasStdEnc_HasMSA, // COPY_S_H = 1211 CEFBS_HasStdEnc_HasMSA, // COPY_S_W = 1212 CEFBS_HasStdEnc_HasMSA, // COPY_U_B = 1213 CEFBS_HasStdEnc_HasMSA, // COPY_U_H = 1214 CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_U_W = 1215 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32B = 1216 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CB = 1217 CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32CD = 1218 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CH = 1219 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CW = 1220 CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32D = 1221 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32H = 1222 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32W = 1223 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CTC1 = 1224 CEFBS_InMicroMips_IsNotSoftFloat, // CTC1_MM = 1225 CEFBS_InMicroMips, // CTC2_MM = 1226 CEFBS_HasStdEnc_HasMSA, // CTCMSA = 1227 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_S = 1228 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_S_MM = 1229 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_W = 1230 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_W_MM = 1231 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_D64_L = 1232 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_S = 1233 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_S_MM = 1234 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_W = 1235 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_W_MM = 1236 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_D_L_MMR6 = 1237 CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_D64 = 1238 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_D64_MM = 1239 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_D_MMR6 = 1240 CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_S = 1241 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_S_MM = 1242 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_S_MMR6 = 1243 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PS_PW64 = 1244 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_PS_S64 = 1245 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PW_PS64 = 1246 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D32 = 1247 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_S_D32_MM = 1248 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D64 = 1249 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_S_D64_MM = 1250 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_S_L = 1251 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_S_L_MMR6 = 1252 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PL64 = 1253 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PU64 = 1254 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_S_W = 1255 CEFBS_InMicroMips_IsNotSoftFloat, // CVT_S_W_MM = 1256 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_S_W_MMR6 = 1257 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D32 = 1258 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_W_D32_MM = 1259 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D64 = 1260 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_W_D64_MM = 1261 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_W_S = 1262 CEFBS_InMicroMips_IsNotSoftFloat, // CVT_W_S_MM = 1263 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_W_S_MMR6 = 1264 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D32 = 1265 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D32_MM = 1266 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D64 = 1267 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D64_MM = 1268 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_S = 1269 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_EQ_S_MM = 1270 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D32 = 1271 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D32_MM = 1272 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D64 = 1273 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D64_MM = 1274 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_S = 1275 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_F_S_MM = 1276 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D32 = 1277 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D32_MM = 1278 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D64 = 1279 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D64_MM = 1280 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_S = 1281 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LE_S_MM = 1282 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D32 = 1283 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D32_MM = 1284 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D64 = 1285 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D64_MM = 1286 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_S = 1287 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LT_S_MM = 1288 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D32 = 1289 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D32_MM = 1290 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D64 = 1291 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D64_MM = 1292 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_S = 1293 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGE_S_MM = 1294 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D32 = 1295 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D32_MM = 1296 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D64 = 1297 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D64_MM = 1298 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_S = 1299 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGLE_S_MM = 1300 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D32 = 1301 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D32_MM = 1302 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D64 = 1303 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D64_MM = 1304 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_S = 1305 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGL_S_MM = 1306 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D32 = 1307 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D32_MM = 1308 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D64 = 1309 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D64_MM = 1310 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_S = 1311 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGT_S_MM = 1312 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D32 = 1313 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D32_MM = 1314 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D64 = 1315 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D64_MM = 1316 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_S = 1317 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLE_S_MM = 1318 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D32 = 1319 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D32_MM = 1320 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D64 = 1321 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D64_MM = 1322 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_S = 1323 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLT_S_MM = 1324 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D32 = 1325 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D32_MM = 1326 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D64 = 1327 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D64_MM = 1328 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_S = 1329 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SEQ_S_MM = 1330 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D32 = 1331 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D32_MM = 1332 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D64 = 1333 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D64_MM = 1334 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_S = 1335 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SF_S_MM = 1336 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D32 = 1337 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D32_MM = 1338 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D64 = 1339 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D64_MM = 1340 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_S = 1341 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UEQ_S_MM = 1342 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D32 = 1343 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D32_MM = 1344 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D64 = 1345 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D64_MM = 1346 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_S = 1347 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULE_S_MM = 1348 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D32 = 1349 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D32_MM = 1350 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D64 = 1351 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D64_MM = 1352 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_S = 1353 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULT_S_MM = 1354 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D32 = 1355 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D32_MM = 1356 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D64 = 1357 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D64_MM = 1358 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_S = 1359 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UN_S_MM = 1360 CEFBS_InMips16Mode, // CmpRxRy16 = 1361 CEFBS_InMips16Mode, // CmpiRxImm16 = 1362 CEFBS_InMips16Mode, // CmpiRxImmX16 = 1363 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADD = 1364 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DADDi = 1365 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDiu = 1366 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDu = 1367 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAHI = 1368 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DALIGN = 1369 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DATI = 1370 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAUI = 1371 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DBITSWAP = 1372 CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLO = 1373 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLO_R6 = 1374 CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLZ = 1375 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLZ_R6 = 1376 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIV = 1377 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIVU = 1378 CEFBS_HasStdEnc_HasMips32_NotInMicroMips, // DERET = 1379 CEFBS_InMicroMips, // DERET_MM = 1380 CEFBS_InMicroMips_HasMips32r6, // DERET_MMR6 = 1381 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT = 1382 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT64_32 = 1383 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTM = 1384 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTU = 1385 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // DI = 1386 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINS = 1387 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSM = 1388 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSU = 1389 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIV = 1390 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIVU = 1391 CEFBS_InMicroMips_HasMips32r6, // DIVU_MMR6 = 1392 CEFBS_InMicroMips_HasMips32r6, // DIV_MMR6 = 1393 CEFBS_HasStdEnc_HasMSA, // DIV_S_B = 1394 CEFBS_HasStdEnc_HasMSA, // DIV_S_D = 1395 CEFBS_HasStdEnc_HasMSA, // DIV_S_H = 1396 CEFBS_HasStdEnc_HasMSA, // DIV_S_W = 1397 CEFBS_HasStdEnc_HasMSA, // DIV_U_B = 1398 CEFBS_HasStdEnc_HasMSA, // DIV_U_D = 1399 CEFBS_HasStdEnc_HasMSA, // DIV_U_H = 1400 CEFBS_HasStdEnc_HasMSA, // DIV_U_W = 1401 CEFBS_InMicroMips, // DI_MM = 1402 CEFBS_InMicroMips_HasMips32r6, // DI_MMR6 = 1403 CEFBS_HasStdEnc_HasMSA_HasMips64, // DLSA = 1404 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DLSA_R6 = 1405 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC0 = 1406 CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMFC1 = 1407 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC2 = 1408 CEFBS_HasCnMips, // DMFC2_OCTEON = 1409 CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMFGC0 = 1410 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMOD = 1411 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMODU = 1412 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DMT = 1413 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC0 = 1414 CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMTC1 = 1415 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC2 = 1416 CEFBS_HasCnMips, // DMTC2_OCTEON = 1417 CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMTGC0 = 1418 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUH = 1419 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUHU = 1420 CEFBS_HasCnMips, // DMUL = 1421 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULT = 1422 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULTu = 1423 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMULU = 1424 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUL_R6 = 1425 CEFBS_HasStdEnc_HasMSA, // DOTP_S_D = 1426 CEFBS_HasStdEnc_HasMSA, // DOTP_S_H = 1427 CEFBS_HasStdEnc_HasMSA, // DOTP_S_W = 1428 CEFBS_HasStdEnc_HasMSA, // DOTP_U_D = 1429 CEFBS_HasStdEnc_HasMSA, // DOTP_U_H = 1430 CEFBS_HasStdEnc_HasMSA, // DOTP_U_W = 1431 CEFBS_HasStdEnc_HasMSA, // DPADD_S_D = 1432 CEFBS_HasStdEnc_HasMSA, // DPADD_S_H = 1433 CEFBS_HasStdEnc_HasMSA, // DPADD_S_W = 1434 CEFBS_HasStdEnc_HasMSA, // DPADD_U_D = 1435 CEFBS_HasStdEnc_HasMSA, // DPADD_U_H = 1436 CEFBS_HasStdEnc_HasMSA, // DPADD_U_W = 1437 CEFBS_HasDSPR2, // DPAQX_SA_W_PH = 1438 CEFBS_InMicroMips_HasDSPR2, // DPAQX_SA_W_PH_MMR2 = 1439 CEFBS_HasDSPR2, // DPAQX_S_W_PH = 1440 CEFBS_InMicroMips_HasDSPR2, // DPAQX_S_W_PH_MMR2 = 1441 CEFBS_HasDSP, // DPAQ_SA_L_W = 1442 CEFBS_InMicroMips_HasDSP, // DPAQ_SA_L_W_MM = 1443 CEFBS_HasDSP, // DPAQ_S_W_PH = 1444 CEFBS_InMicroMips_HasDSP, // DPAQ_S_W_PH_MM = 1445 CEFBS_HasDSP, // DPAU_H_QBL = 1446 CEFBS_InMicroMips_HasDSP, // DPAU_H_QBL_MM = 1447 CEFBS_HasDSP, // DPAU_H_QBR = 1448 CEFBS_InMicroMips_HasDSP, // DPAU_H_QBR_MM = 1449 CEFBS_HasDSPR2, // DPAX_W_PH = 1450 CEFBS_InMicroMips_HasDSPR2, // DPAX_W_PH_MMR2 = 1451 CEFBS_HasDSPR2, // DPA_W_PH = 1452 CEFBS_InMicroMips_HasDSPR2, // DPA_W_PH_MMR2 = 1453 CEFBS_HasCnMips, // DPOP = 1454 CEFBS_HasDSPR2, // DPSQX_SA_W_PH = 1455 CEFBS_InMicroMips_HasDSPR2, // DPSQX_SA_W_PH_MMR2 = 1456 CEFBS_HasDSPR2, // DPSQX_S_W_PH = 1457 CEFBS_InMicroMips_HasDSPR2, // DPSQX_S_W_PH_MMR2 = 1458 CEFBS_HasDSP, // DPSQ_SA_L_W = 1459 CEFBS_InMicroMips_HasDSP, // DPSQ_SA_L_W_MM = 1460 CEFBS_HasDSP, // DPSQ_S_W_PH = 1461 CEFBS_InMicroMips_HasDSP, // DPSQ_S_W_PH_MM = 1462 CEFBS_HasStdEnc_HasMSA, // DPSUB_S_D = 1463 CEFBS_HasStdEnc_HasMSA, // DPSUB_S_H = 1464 CEFBS_HasStdEnc_HasMSA, // DPSUB_S_W = 1465 CEFBS_HasStdEnc_HasMSA, // DPSUB_U_D = 1466 CEFBS_HasStdEnc_HasMSA, // DPSUB_U_H = 1467 CEFBS_HasStdEnc_HasMSA, // DPSUB_U_W = 1468 CEFBS_HasDSP, // DPSU_H_QBL = 1469 CEFBS_InMicroMips_HasDSP, // DPSU_H_QBL_MM = 1470 CEFBS_HasDSP, // DPSU_H_QBR = 1471 CEFBS_InMicroMips_HasDSP, // DPSU_H_QBR_MM = 1472 CEFBS_HasDSPR2, // DPSX_W_PH = 1473 CEFBS_InMicroMips_HasDSPR2, // DPSX_W_PH_MMR2 = 1474 CEFBS_HasDSPR2, // DPS_W_PH = 1475 CEFBS_InMicroMips_HasDSPR2, // DPS_W_PH_MMR2 = 1476 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR = 1477 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR32 = 1478 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTRV = 1479 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSBH = 1480 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDIV = 1481 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSHD = 1482 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL = 1483 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL32 = 1484 CEFBS_NotInMips16Mode_IsGP64bit, // DSLL64_32 = 1485 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLLV = 1486 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA = 1487 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA32 = 1488 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRAV = 1489 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL = 1490 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL32 = 1491 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRLV = 1492 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUB = 1493 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUBu = 1494 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDIV = 1495 CEFBS_HasStdEnc_HasMips32r6, // DVP = 1496 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DVPE = 1497 CEFBS_InMicroMips_HasMips32r6, // DVP_MMR6 = 1498 CEFBS_InMips16Mode, // DivRxRy16 = 1499 CEFBS_InMips16Mode, // DivuRxRy16 = 1500 CEFBS_HasStdEnc_NotInMicroMips, // EHB = 1501 CEFBS_InMicroMips, // EHB_MM = 1502 CEFBS_InMicroMips_HasMips32r6, // EHB_MMR6 = 1503 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EI = 1504 CEFBS_InMicroMips, // EI_MM = 1505 CEFBS_InMicroMips_HasMips32r6, // EI_MMR6 = 1506 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EMT = 1507 CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // ERET = 1508 CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, // ERETNC = 1509 CEFBS_InMicroMips_HasMips32r6, // ERETNC_MMR6 = 1510 CEFBS_InMicroMips, // ERET_MM = 1511 CEFBS_InMicroMips_HasMips32r6, // ERET_MMR6 = 1512 CEFBS_HasStdEnc_HasMips32r6, // EVP = 1513 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EVPE = 1514 CEFBS_InMicroMips_HasMips32r6, // EVP_MMR6 = 1515 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EXT = 1516 CEFBS_HasDSP, // EXTP = 1517 CEFBS_HasDSP, // EXTPDP = 1518 CEFBS_HasDSP, // EXTPDPV = 1519 CEFBS_InMicroMips_HasDSP, // EXTPDPV_MM = 1520 CEFBS_InMicroMips_HasDSP, // EXTPDP_MM = 1521 CEFBS_HasDSP, // EXTPV = 1522 CEFBS_InMicroMips_HasDSP, // EXTPV_MM = 1523 CEFBS_InMicroMips_HasDSP, // EXTP_MM = 1524 CEFBS_HasDSP, // EXTRV_RS_W = 1525 CEFBS_InMicroMips_HasDSP, // EXTRV_RS_W_MM = 1526 CEFBS_HasDSP, // EXTRV_R_W = 1527 CEFBS_InMicroMips_HasDSP, // EXTRV_R_W_MM = 1528 CEFBS_HasDSP, // EXTRV_S_H = 1529 CEFBS_InMicroMips_HasDSP, // EXTRV_S_H_MM = 1530 CEFBS_HasDSP, // EXTRV_W = 1531 CEFBS_InMicroMips_HasDSP, // EXTRV_W_MM = 1532 CEFBS_HasDSP, // EXTR_RS_W = 1533 CEFBS_InMicroMips_HasDSP, // EXTR_RS_W_MM = 1534 CEFBS_HasDSP, // EXTR_R_W = 1535 CEFBS_InMicroMips_HasDSP, // EXTR_R_W_MM = 1536 CEFBS_HasDSP, // EXTR_S_H = 1537 CEFBS_InMicroMips_HasDSP, // EXTR_S_H_MM = 1538 CEFBS_HasDSP, // EXTR_W = 1539 CEFBS_InMicroMips_HasDSP, // EXTR_W_MM = 1540 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS = 1541 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS32 = 1542 CEFBS_InMicroMips_NotMips32r6, // EXT_MM = 1543 CEFBS_InMicroMips_HasMips32r6, // EXT_MMR6 = 1544 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D32 = 1545 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FABS_D32_MM = 1546 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D64 = 1547 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FABS_D64_MM = 1548 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FABS_S = 1549 CEFBS_InMicroMips_IsNotSoftFloat, // FABS_S_MM = 1550 CEFBS_HasStdEnc_HasMSA, // FADD_D = 1551 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D32 = 1552 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FADD_D32_MM = 1553 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D64 = 1554 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FADD_D64_MM = 1555 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FADD_PS64 = 1556 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FADD_S = 1557 CEFBS_InMicroMips_IsNotSoftFloat, // FADD_S_MM = 1558 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FADD_S_MMR6 = 1559 CEFBS_HasStdEnc_HasMSA, // FADD_W = 1560 CEFBS_HasStdEnc_HasMSA, // FCAF_D = 1561 CEFBS_HasStdEnc_HasMSA, // FCAF_W = 1562 CEFBS_HasStdEnc_HasMSA, // FCEQ_D = 1563 CEFBS_HasStdEnc_HasMSA, // FCEQ_W = 1564 CEFBS_HasStdEnc_HasMSA, // FCLASS_D = 1565 CEFBS_HasStdEnc_HasMSA, // FCLASS_W = 1566 CEFBS_HasStdEnc_HasMSA, // FCLE_D = 1567 CEFBS_HasStdEnc_HasMSA, // FCLE_W = 1568 CEFBS_HasStdEnc_HasMSA, // FCLT_D = 1569 CEFBS_HasStdEnc_HasMSA, // FCLT_W = 1570 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_D32 = 1571 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_D32_MM = 1572 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, // FCMP_D64 = 1573 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_S32 = 1574 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_S32_MM = 1575 CEFBS_HasStdEnc_HasMSA, // FCNE_D = 1576 CEFBS_HasStdEnc_HasMSA, // FCNE_W = 1577 CEFBS_HasStdEnc_HasMSA, // FCOR_D = 1578 CEFBS_HasStdEnc_HasMSA, // FCOR_W = 1579 CEFBS_HasStdEnc_HasMSA, // FCUEQ_D = 1580 CEFBS_HasStdEnc_HasMSA, // FCUEQ_W = 1581 CEFBS_HasStdEnc_HasMSA, // FCULE_D = 1582 CEFBS_HasStdEnc_HasMSA, // FCULE_W = 1583 CEFBS_HasStdEnc_HasMSA, // FCULT_D = 1584 CEFBS_HasStdEnc_HasMSA, // FCULT_W = 1585 CEFBS_HasStdEnc_HasMSA, // FCUNE_D = 1586 CEFBS_HasStdEnc_HasMSA, // FCUNE_W = 1587 CEFBS_HasStdEnc_HasMSA, // FCUN_D = 1588 CEFBS_HasStdEnc_HasMSA, // FCUN_W = 1589 CEFBS_HasStdEnc_HasMSA, // FDIV_D = 1590 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D32 = 1591 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FDIV_D32_MM = 1592 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D64 = 1593 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FDIV_D64_MM = 1594 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FDIV_S = 1595 CEFBS_InMicroMips_IsNotSoftFloat, // FDIV_S_MM = 1596 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FDIV_S_MMR6 = 1597 CEFBS_HasStdEnc_HasMSA, // FDIV_W = 1598 CEFBS_HasStdEnc_HasMSA, // FEXDO_H = 1599 CEFBS_HasStdEnc_HasMSA, // FEXDO_W = 1600 CEFBS_HasStdEnc_HasMSA, // FEXP2_D = 1601 CEFBS_HasStdEnc_HasMSA, // FEXP2_W = 1602 CEFBS_HasStdEnc_HasMSA, // FEXUPL_D = 1603 CEFBS_HasStdEnc_HasMSA, // FEXUPL_W = 1604 CEFBS_HasStdEnc_HasMSA, // FEXUPR_D = 1605 CEFBS_HasStdEnc_HasMSA, // FEXUPR_W = 1606 CEFBS_HasStdEnc_HasMSA, // FFINT_S_D = 1607 CEFBS_HasStdEnc_HasMSA, // FFINT_S_W = 1608 CEFBS_HasStdEnc_HasMSA, // FFINT_U_D = 1609 CEFBS_HasStdEnc_HasMSA, // FFINT_U_W = 1610 CEFBS_HasStdEnc_HasMSA, // FFQL_D = 1611 CEFBS_HasStdEnc_HasMSA, // FFQL_W = 1612 CEFBS_HasStdEnc_HasMSA, // FFQR_D = 1613 CEFBS_HasStdEnc_HasMSA, // FFQR_W = 1614 CEFBS_HasStdEnc_HasMSA, // FILL_B = 1615 CEFBS_HasStdEnc_HasMSA_HasMips64, // FILL_D = 1616 CEFBS_HasStdEnc_HasMSA, // FILL_H = 1617 CEFBS_HasStdEnc_HasMSA, // FILL_W = 1618 CEFBS_HasStdEnc_HasMSA, // FLOG2_D = 1619 CEFBS_HasStdEnc_HasMSA, // FLOG2_W = 1620 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_D64 = 1621 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_D_MMR6 = 1622 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_S = 1623 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_S_MMR6 = 1624 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D32 = 1625 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D64 = 1626 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_D_MMR6 = 1627 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FLOOR_W_MM = 1628 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_S = 1629 CEFBS_InMicroMips_IsNotSoftFloat, // FLOOR_W_S_MM = 1630 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_S_MMR6 = 1631 CEFBS_HasStdEnc_HasMSA, // FMADD_D = 1632 CEFBS_HasStdEnc_HasMSA, // FMADD_W = 1633 CEFBS_HasStdEnc_HasMSA, // FMAX_A_D = 1634 CEFBS_HasStdEnc_HasMSA, // FMAX_A_W = 1635 CEFBS_HasStdEnc_HasMSA, // FMAX_D = 1636 CEFBS_HasStdEnc_HasMSA, // FMAX_W = 1637 CEFBS_HasStdEnc_HasMSA, // FMIN_A_D = 1638 CEFBS_HasStdEnc_HasMSA, // FMIN_A_W = 1639 CEFBS_HasStdEnc_HasMSA, // FMIN_D = 1640 CEFBS_HasStdEnc_HasMSA, // FMIN_W = 1641 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D32 = 1642 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMOV_D32_MM = 1643 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D64 = 1644 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMOV_D64_MM = 1645 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_D_MMR6 = 1646 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMOV_S = 1647 CEFBS_InMicroMips_IsNotSoftFloat, // FMOV_S_MM = 1648 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_S_MMR6 = 1649 CEFBS_HasStdEnc_HasMSA, // FMSUB_D = 1650 CEFBS_HasStdEnc_HasMSA, // FMSUB_W = 1651 CEFBS_HasStdEnc_HasMSA, // FMUL_D = 1652 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D32 = 1653 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMUL_D32_MM = 1654 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D64 = 1655 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMUL_D64_MM = 1656 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FMUL_PS64 = 1657 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S = 1658 CEFBS_InMicroMips_IsNotSoftFloat, // FMUL_S_MM = 1659 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMUL_S_MMR6 = 1660 CEFBS_HasStdEnc_HasMSA, // FMUL_W = 1661 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D32 = 1662 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FNEG_D32_MM = 1663 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D64 = 1664 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FNEG_D64_MM = 1665 CEFBS_HasStdEnc_IsNotSoftFloat, // FNEG_S = 1666 CEFBS_InMicroMips_IsNotSoftFloat, // FNEG_S_MM = 1667 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FNEG_S_MMR6 = 1668 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // FORK = 1669 CEFBS_HasStdEnc_HasMSA, // FRCP_D = 1670 CEFBS_HasStdEnc_HasMSA, // FRCP_W = 1671 CEFBS_HasStdEnc_HasMSA, // FRINT_D = 1672 CEFBS_HasStdEnc_HasMSA, // FRINT_W = 1673 CEFBS_HasStdEnc_HasMSA, // FRSQRT_D = 1674 CEFBS_HasStdEnc_HasMSA, // FRSQRT_W = 1675 CEFBS_HasStdEnc_HasMSA, // FSAF_D = 1676 CEFBS_HasStdEnc_HasMSA, // FSAF_W = 1677 CEFBS_HasStdEnc_HasMSA, // FSEQ_D = 1678 CEFBS_HasStdEnc_HasMSA, // FSEQ_W = 1679 CEFBS_HasStdEnc_HasMSA, // FSLE_D = 1680 CEFBS_HasStdEnc_HasMSA, // FSLE_W = 1681 CEFBS_HasStdEnc_HasMSA, // FSLT_D = 1682 CEFBS_HasStdEnc_HasMSA, // FSLT_W = 1683 CEFBS_HasStdEnc_HasMSA, // FSNE_D = 1684 CEFBS_HasStdEnc_HasMSA, // FSNE_W = 1685 CEFBS_HasStdEnc_HasMSA, // FSOR_D = 1686 CEFBS_HasStdEnc_HasMSA, // FSOR_W = 1687 CEFBS_HasStdEnc_HasMSA, // FSQRT_D = 1688 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D32 = 1689 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSQRT_D32_MM = 1690 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D64 = 1691 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSQRT_D64_MM = 1692 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_S = 1693 CEFBS_InMicroMips_IsNotSoftFloat, // FSQRT_S_MM = 1694 CEFBS_HasStdEnc_HasMSA, // FSQRT_W = 1695 CEFBS_HasStdEnc_HasMSA, // FSUB_D = 1696 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D32 = 1697 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSUB_D32_MM = 1698 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D64 = 1699 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSUB_D64_MM = 1700 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FSUB_PS64 = 1701 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FSUB_S = 1702 CEFBS_InMicroMips_IsNotSoftFloat, // FSUB_S_MM = 1703 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FSUB_S_MMR6 = 1704 CEFBS_HasStdEnc_HasMSA, // FSUB_W = 1705 CEFBS_HasStdEnc_HasMSA, // FSUEQ_D = 1706 CEFBS_HasStdEnc_HasMSA, // FSUEQ_W = 1707 CEFBS_HasStdEnc_HasMSA, // FSULE_D = 1708 CEFBS_HasStdEnc_HasMSA, // FSULE_W = 1709 CEFBS_HasStdEnc_HasMSA, // FSULT_D = 1710 CEFBS_HasStdEnc_HasMSA, // FSULT_W = 1711 CEFBS_HasStdEnc_HasMSA, // FSUNE_D = 1712 CEFBS_HasStdEnc_HasMSA, // FSUNE_W = 1713 CEFBS_HasStdEnc_HasMSA, // FSUN_D = 1714 CEFBS_HasStdEnc_HasMSA, // FSUN_W = 1715 CEFBS_HasStdEnc_HasMSA, // FTINT_S_D = 1716 CEFBS_HasStdEnc_HasMSA, // FTINT_S_W = 1717 CEFBS_HasStdEnc_HasMSA, // FTINT_U_D = 1718 CEFBS_HasStdEnc_HasMSA, // FTINT_U_W = 1719 CEFBS_HasStdEnc_HasMSA, // FTQ_H = 1720 CEFBS_HasStdEnc_HasMSA, // FTQ_W = 1721 CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_D = 1722 CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_W = 1723 CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_D = 1724 CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_W = 1725 CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVI = 1726 CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVI_MMR6 = 1727 CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVT = 1728 CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVT_MMR6 = 1729 CEFBS_HasStdEnc_HasMSA, // HADD_S_D = 1730 CEFBS_HasStdEnc_HasMSA, // HADD_S_H = 1731 CEFBS_HasStdEnc_HasMSA, // HADD_S_W = 1732 CEFBS_HasStdEnc_HasMSA, // HADD_U_D = 1733 CEFBS_HasStdEnc_HasMSA, // HADD_U_H = 1734 CEFBS_HasStdEnc_HasMSA, // HADD_U_W = 1735 CEFBS_HasStdEnc_HasMSA, // HSUB_S_D = 1736 CEFBS_HasStdEnc_HasMSA, // HSUB_S_H = 1737 CEFBS_HasStdEnc_HasMSA, // HSUB_S_W = 1738 CEFBS_HasStdEnc_HasMSA, // HSUB_U_D = 1739 CEFBS_HasStdEnc_HasMSA, // HSUB_U_H = 1740 CEFBS_HasStdEnc_HasMSA, // HSUB_U_W = 1741 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // HYPCALL = 1742 CEFBS_InMicroMips_HasMips32r5_HasVirt, // HYPCALL_MM = 1743 CEFBS_HasStdEnc_HasMSA, // ILVEV_B = 1744 CEFBS_HasStdEnc_HasMSA, // ILVEV_D = 1745 CEFBS_HasStdEnc_HasMSA, // ILVEV_H = 1746 CEFBS_HasStdEnc_HasMSA, // ILVEV_W = 1747 CEFBS_HasStdEnc_HasMSA, // ILVL_B = 1748 CEFBS_HasStdEnc_HasMSA, // ILVL_D = 1749 CEFBS_HasStdEnc_HasMSA, // ILVL_H = 1750 CEFBS_HasStdEnc_HasMSA, // ILVL_W = 1751 CEFBS_HasStdEnc_HasMSA, // ILVOD_B = 1752 CEFBS_HasStdEnc_HasMSA, // ILVOD_D = 1753 CEFBS_HasStdEnc_HasMSA, // ILVOD_H = 1754 CEFBS_HasStdEnc_HasMSA, // ILVOD_W = 1755 CEFBS_HasStdEnc_HasMSA, // ILVR_B = 1756 CEFBS_HasStdEnc_HasMSA, // ILVR_D = 1757 CEFBS_HasStdEnc_HasMSA, // ILVR_H = 1758 CEFBS_HasStdEnc_HasMSA, // ILVR_W = 1759 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // INS = 1760 CEFBS_HasStdEnc_HasMSA, // INSERT_B = 1761 CEFBS_HasStdEnc_HasMSA_HasMips64, // INSERT_D = 1762 CEFBS_HasStdEnc_HasMSA, // INSERT_H = 1763 CEFBS_HasStdEnc_HasMSA, // INSERT_W = 1764 CEFBS_HasDSP, // INSV = 1765 CEFBS_HasStdEnc_HasMSA, // INSVE_B = 1766 CEFBS_HasStdEnc_HasMSA, // INSVE_D = 1767 CEFBS_HasStdEnc_HasMSA, // INSVE_H = 1768 CEFBS_HasStdEnc_HasMSA, // INSVE_W = 1769 CEFBS_InMicroMips_HasDSP, // INSV_MM = 1770 CEFBS_InMicroMips_NotMips32r6, // INS_MM = 1771 CEFBS_InMicroMips_HasMips32r6, // INS_MMR6 = 1772 CEFBS_HasStdEnc_NotInMicroMips, // J = 1773 CEFBS_HasStdEnc_NotInMicroMips, // JAL = 1774 CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALR = 1775 CEFBS_InMicroMips_NotMips32r6, // JALR16_MM = 1776 CEFBS_NotInMips16Mode_IsPTR64bit, // JALR64 = 1777 CEFBS_InMicroMips_HasMips32r6, // JALRC16_MMR6 = 1778 CEFBS_InMicroMips_HasMips32r6, // JALRC_HB_MMR6 = 1779 CEFBS_InMicroMips_HasMips32r6, // JALRC_MMR6 = 1780 CEFBS_InMicroMips_NotMips32r6, // JALRS16_MM = 1781 CEFBS_InMicroMips_NotMips32r6, // JALRS_MM = 1782 CEFBS_HasStdEnc_HasMips32, // JALR_HB = 1783 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // JALR_HB64 = 1784 CEFBS_InMicroMips_NotMips32r6, // JALR_MM = 1785 CEFBS_InMicroMips_NotMips32r6, // JALS_MM = 1786 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // JALX = 1787 CEFBS_InMicroMips_NotMips32r6, // JALX_MM = 1788 CEFBS_InMicroMips_NotMips32r6, // JAL_MM = 1789 CEFBS_HasStdEnc_HasMips32r6, // JIALC = 1790 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIALC64 = 1791 CEFBS_InMicroMips_HasMips32r6, // JIALC_MMR6 = 1792 CEFBS_HasStdEnc_HasMips32r6, // JIC = 1793 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIC64 = 1794 CEFBS_InMicroMips_HasMips32r6, // JIC_MMR6 = 1795 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // JR = 1796 CEFBS_InMicroMips_NotMips32r6, // JR16_MM = 1797 CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, // JR64 = 1798 CEFBS_InMicroMips_NotMips32r6, // JRADDIUSP = 1799 CEFBS_InMicroMips_NotMips32r6, // JRC16_MM = 1800 CEFBS_InMicroMips_HasMips32r6, // JRC16_MMR6 = 1801 CEFBS_InMicroMips_HasMips32r6, // JRCADDIUSP_MMR6 = 1802 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, // JR_HB = 1803 CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, // JR_HB64 = 1804 CEFBS_HasStdEnc_HasMips32r6, // JR_HB64_R6 = 1805 CEFBS_HasStdEnc_HasMips32r6, // JR_HB_R6 = 1806 CEFBS_InMicroMips_NotMips32r6, // JR_MM = 1807 CEFBS_InMicroMips_NotMips32r6, // J_MM = 1808 CEFBS_InMips16Mode, // Jal16 = 1809 CEFBS_InMips16Mode, // JalB16 = 1810 CEFBS_InMips16Mode, // JrRa16 = 1811 CEFBS_InMips16Mode, // JrcRa16 = 1812 CEFBS_InMips16Mode, // JrcRx16 = 1813 CEFBS_InMips16Mode, // JumpLinkReg16 = 1814 CEFBS_HasStdEnc_NotInMicroMips, // LB = 1815 CEFBS_NotInMips16Mode_IsGP64bit, // LB64 = 1816 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBE = 1817 CEFBS_InMicroMips_HasEVA, // LBE_MM = 1818 CEFBS_InMicroMips, // LBU16_MM = 1819 CEFBS_HasDSP, // LBUX = 1820 CEFBS_InMicroMips_HasDSP, // LBUX_MM = 1821 CEFBS_InMicroMips_HasMips32r6, // LBU_MMR6 = 1822 CEFBS_InMicroMips, // LB_MM = 1823 CEFBS_InMicroMips_HasMips32r6, // LB_MMR6 = 1824 CEFBS_HasStdEnc_NotInMicroMips, // LBu = 1825 CEFBS_NotInMips16Mode_IsGP64bit, // LBu64 = 1826 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBuE = 1827 CEFBS_InMicroMips_HasEVA, // LBuE_MM = 1828 CEFBS_InMicroMips, // LBu_MM = 1829 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LD = 1830 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC1 = 1831 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC164 = 1832 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // LDC1_D64_MMR6 = 1833 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // LDC1_MM_D32 = 1834 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // LDC1_MM_D64 = 1835 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LDC2 = 1836 CEFBS_InMicroMips_HasMips32r6, // LDC2_MMR6 = 1837 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LDC2_R6 = 1838 CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // LDC3 = 1839 CEFBS_HasStdEnc_HasMSA, // LDI_B = 1840 CEFBS_HasStdEnc_HasMSA, // LDI_D = 1841 CEFBS_HasStdEnc_HasMSA, // LDI_H = 1842 CEFBS_HasStdEnc_HasMSA, // LDI_W = 1843 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDL = 1844 CEFBS_HasStdEnc_HasMips64r6, // LDPC = 1845 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDR = 1846 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LDXC1 = 1847 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LDXC164 = 1848 CEFBS_HasStdEnc_HasMSA, // LD_B = 1849 CEFBS_HasStdEnc_HasMSA, // LD_D = 1850 CEFBS_HasStdEnc_HasMSA, // LD_H = 1851 CEFBS_HasStdEnc_HasMSA, // LD_W = 1852 CEFBS_HasStdEnc_NotInMicroMips, // LEA_ADDiu = 1853 CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, // LEA_ADDiu64 = 1854 CEFBS_InMicroMips, // LEA_ADDiu_MM = 1855 CEFBS_HasStdEnc_NotInMicroMips, // LH = 1856 CEFBS_NotInMips16Mode_IsGP64bit, // LH64 = 1857 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHE = 1858 CEFBS_InMicroMips_HasEVA, // LHE_MM = 1859 CEFBS_InMicroMips, // LHU16_MM = 1860 CEFBS_HasDSP, // LHX = 1861 CEFBS_InMicroMips_HasDSP, // LHX_MM = 1862 CEFBS_InMicroMips, // LH_MM = 1863 CEFBS_HasStdEnc_NotInMicroMips, // LHu = 1864 CEFBS_NotInMips16Mode_IsGP64bit, // LHu64 = 1865 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHuE = 1866 CEFBS_InMicroMips_HasEVA, // LHuE_MM = 1867 CEFBS_InMicroMips, // LHu_MM = 1868 CEFBS_InMicroMips_NotMips32r6, // LI16_MM = 1869 CEFBS_InMicroMips_HasMips32r6, // LI16_MMR6 = 1870 CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL = 1871 CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL64 = 1872 CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // LL64_R6 = 1873 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // LLD = 1874 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // LLD_R6 = 1875 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LLE = 1876 CEFBS_InMicroMips_HasEVA, // LLE_MM = 1877 CEFBS_InMicroMips_NotMips32r6, // LL_MM = 1878 CEFBS_InMicroMips_HasMips32r6, // LL_MMR6 = 1879 CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // LL_R6 = 1880 CEFBS_HasStdEnc_HasMSA, // LSA = 1881 CEFBS_InMicroMips_HasMips32r6, // LSA_MMR6 = 1882 CEFBS_HasStdEnc_HasMips32r6, // LSA_R6 = 1883 CEFBS_InMicroMips_HasMips32r6, // LUI_MMR6 = 1884 CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC1 = 1885 CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC164 = 1886 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // LUXC1_MM = 1887 CEFBS_HasStdEnc_NotInMicroMips, // LUi = 1888 CEFBS_NotInMips16Mode_IsGP64bit, // LUi64 = 1889 CEFBS_InMicroMips_NotMips32r6, // LUi_MM = 1890 CEFBS_HasStdEnc_NotInMicroMips, // LW = 1891 CEFBS_InMicroMips, // LW16_MM = 1892 CEFBS_NotInMips16Mode_IsGP64bit, // LW64 = 1893 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // LWC1 = 1894 CEFBS_InMicroMips_IsNotSoftFloat, // LWC1_MM = 1895 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWC2 = 1896 CEFBS_InMicroMips_HasMips32r6, // LWC2_MMR6 = 1897 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LWC2_R6 = 1898 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // LWC3 = 1899 CEFBS_NotInMips16Mode_HasDSP, // LWDSP = 1900 CEFBS_InMicroMips_HasDSP, // LWDSP_MM = 1901 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LWE = 1902 CEFBS_InMicroMips_HasEVA, // LWE_MM = 1903 CEFBS_InMicroMips, // LWGP_MM = 1904 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWL = 1905 CEFBS_NotInMips16Mode_IsGP64bit, // LWL64 = 1906 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWLE = 1907 CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWLE_MM = 1908 CEFBS_InMicroMips_NotMips32r6, // LWL_MM = 1909 CEFBS_InMicroMips_NotMips32r6, // LWM16_MM = 1910 CEFBS_InMicroMips_HasMips32r6, // LWM16_MMR6 = 1911 CEFBS_InMicroMips, // LWM32_MM = 1912 CEFBS_HasStdEnc_HasMips32r6, // LWPC = 1913 CEFBS_InMicroMips_HasMips32r6, // LWPC_MMR6 = 1914 CEFBS_InMicroMips, // LWP_MM = 1915 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWR = 1916 CEFBS_NotInMips16Mode_IsGP64bit, // LWR64 = 1917 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWRE = 1918 CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWRE_MM = 1919 CEFBS_InMicroMips_NotMips32r6, // LWR_MM = 1920 CEFBS_InMicroMips, // LWSP_MM = 1921 CEFBS_HasStdEnc_HasMips64r6, // LWUPC = 1922 CEFBS_InMicroMips_NotMips32r6, // LWU_MM = 1923 CEFBS_HasDSP, // LWX = 1924 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LWXC1 = 1925 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // LWXC1_MM = 1926 CEFBS_InMicroMips, // LWXS_MM = 1927 CEFBS_InMicroMips_HasDSP, // LWX_MM = 1928 CEFBS_InMicroMips, // LW_MM = 1929 CEFBS_InMicroMips_HasMips32r6, // LW_MMR6 = 1930 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LWu = 1931 CEFBS_InMips16Mode, // LbRxRyOffMemX16 = 1932 CEFBS_InMips16Mode, // LbuRxRyOffMemX16 = 1933 CEFBS_InMips16Mode, // LhRxRyOffMemX16 = 1934 CEFBS_InMips16Mode, // LhuRxRyOffMemX16 = 1935 CEFBS_InMips16Mode, // LiRxImm16 = 1936 CEFBS_InMips16Mode, // LiRxImmAlignX16 = 1937 CEFBS_InMips16Mode, // LiRxImmX16 = 1938 CEFBS_InMips16Mode, // LwRxPcTcp16 = 1939 CEFBS_InMips16Mode, // LwRxPcTcpX16 = 1940 CEFBS_InMips16Mode, // LwRxRyOffMemX16 = 1941 CEFBS_InMips16Mode, // LwRxSpImmX16 = 1942 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADD = 1943 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_D = 1944 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_D_MMR6 = 1945 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_S = 1946 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_S_MMR6 = 1947 CEFBS_HasStdEnc_HasMSA, // MADDR_Q_H = 1948 CEFBS_HasStdEnc_HasMSA, // MADDR_Q_W = 1949 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADDU = 1950 CEFBS_HasDSP, // MADDU_DSP = 1951 CEFBS_InMicroMips_HasDSP, // MADDU_DSP_MM = 1952 CEFBS_InMicroMips_NotMips32r6, // MADDU_MM = 1953 CEFBS_HasStdEnc_HasMSA, // MADDV_B = 1954 CEFBS_HasStdEnc_HasMSA, // MADDV_D = 1955 CEFBS_HasStdEnc_HasMSA, // MADDV_H = 1956 CEFBS_HasStdEnc_HasMSA, // MADDV_W = 1957 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D32 = 1958 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_D32_MM = 1959 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D64 = 1960 CEFBS_HasDSP, // MADD_DSP = 1961 CEFBS_InMicroMips_HasDSP, // MADD_DSP_MM = 1962 CEFBS_InMicroMips_NotMips32r6, // MADD_MM = 1963 CEFBS_HasStdEnc_HasMSA, // MADD_Q_H = 1964 CEFBS_HasStdEnc_HasMSA, // MADD_Q_W = 1965 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_S = 1966 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_S_MM = 1967 CEFBS_HasDSP, // MAQ_SA_W_PHL = 1968 CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHL_MM = 1969 CEFBS_HasDSP, // MAQ_SA_W_PHR = 1970 CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHR_MM = 1971 CEFBS_HasDSP, // MAQ_S_W_PHL = 1972 CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHL_MM = 1973 CEFBS_HasDSP, // MAQ_S_W_PHR = 1974 CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHR_MM = 1975 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_D = 1976 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_D_MMR6 = 1977 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_S = 1978 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_S_MMR6 = 1979 CEFBS_HasStdEnc_HasMSA, // MAXI_S_B = 1980 CEFBS_HasStdEnc_HasMSA, // MAXI_S_D = 1981 CEFBS_HasStdEnc_HasMSA, // MAXI_S_H = 1982 CEFBS_HasStdEnc_HasMSA, // MAXI_S_W = 1983 CEFBS_HasStdEnc_HasMSA, // MAXI_U_B = 1984 CEFBS_HasStdEnc_HasMSA, // MAXI_U_D = 1985 CEFBS_HasStdEnc_HasMSA, // MAXI_U_H = 1986 CEFBS_HasStdEnc_HasMSA, // MAXI_U_W = 1987 CEFBS_HasStdEnc_HasMSA, // MAX_A_B = 1988 CEFBS_HasStdEnc_HasMSA, // MAX_A_D = 1989 CEFBS_HasStdEnc_HasMSA, // MAX_A_H = 1990 CEFBS_HasStdEnc_HasMSA, // MAX_A_W = 1991 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_D = 1992 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_D_MMR6 = 1993 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_S = 1994 CEFBS_HasStdEnc_HasMSA, // MAX_S_B = 1995 CEFBS_HasStdEnc_HasMSA, // MAX_S_D = 1996 CEFBS_HasStdEnc_HasMSA, // MAX_S_H = 1997 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_S_MMR6 = 1998 CEFBS_HasStdEnc_HasMSA, // MAX_S_W = 1999 CEFBS_HasStdEnc_HasMSA, // MAX_U_B = 2000 CEFBS_HasStdEnc_HasMSA, // MAX_U_D = 2001 CEFBS_HasStdEnc_HasMSA, // MAX_U_H = 2002 CEFBS_HasStdEnc_HasMSA, // MAX_U_W = 2003 CEFBS_HasStdEnc_NotInMicroMips, // MFC0 = 2004 CEFBS_InMicroMips_HasMips32r6, // MFC0_MMR6 = 2005 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MFC1 = 2006 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MFC1_D64 = 2007 CEFBS_InMicroMips_IsNotSoftFloat, // MFC1_MM = 2008 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MFC1_MMR6 = 2009 CEFBS_HasStdEnc_NotInMicroMips, // MFC2 = 2010 CEFBS_InMicroMips_HasMips32r6, // MFC2_MMR6 = 2011 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFGC0 = 2012 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFGC0_MM = 2013 CEFBS_InMicroMips_HasMips32r6, // MFHC0_MMR6 = 2014 CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D32 = 2015 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MFHC1_D32_MM = 2016 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D64 = 2017 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MFHC1_D64_MM = 2018 CEFBS_InMicroMips_HasMips32r6, // MFHC2_MMR6 = 2019 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFHGC0 = 2020 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFHGC0_MM = 2021 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFHI = 2022 CEFBS_InMicroMips_NotMips32r6, // MFHI16_MM = 2023 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFHI64 = 2024 CEFBS_HasDSP, // MFHI_DSP = 2025 CEFBS_InMicroMips_HasDSP, // MFHI_DSP_MM = 2026 CEFBS_InMicroMips_NotMips32r6, // MFHI_MM = 2027 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFLO = 2028 CEFBS_InMicroMips_NotMips32r6, // MFLO16_MM = 2029 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFLO64 = 2030 CEFBS_HasDSP, // MFLO_DSP = 2031 CEFBS_InMicroMips_HasDSP, // MFLO_DSP_MM = 2032 CEFBS_InMicroMips_NotMips32r6, // MFLO_MM = 2033 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MFTR = 2034 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_D = 2035 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_D_MMR6 = 2036 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_S = 2037 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_S_MMR6 = 2038 CEFBS_HasStdEnc_HasMSA, // MINI_S_B = 2039 CEFBS_HasStdEnc_HasMSA, // MINI_S_D = 2040 CEFBS_HasStdEnc_HasMSA, // MINI_S_H = 2041 CEFBS_HasStdEnc_HasMSA, // MINI_S_W = 2042 CEFBS_HasStdEnc_HasMSA, // MINI_U_B = 2043 CEFBS_HasStdEnc_HasMSA, // MINI_U_D = 2044 CEFBS_HasStdEnc_HasMSA, // MINI_U_H = 2045 CEFBS_HasStdEnc_HasMSA, // MINI_U_W = 2046 CEFBS_HasStdEnc_HasMSA, // MIN_A_B = 2047 CEFBS_HasStdEnc_HasMSA, // MIN_A_D = 2048 CEFBS_HasStdEnc_HasMSA, // MIN_A_H = 2049 CEFBS_HasStdEnc_HasMSA, // MIN_A_W = 2050 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_D = 2051 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_D_MMR6 = 2052 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_S = 2053 CEFBS_HasStdEnc_HasMSA, // MIN_S_B = 2054 CEFBS_HasStdEnc_HasMSA, // MIN_S_D = 2055 CEFBS_HasStdEnc_HasMSA, // MIN_S_H = 2056 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_S_MMR6 = 2057 CEFBS_HasStdEnc_HasMSA, // MIN_S_W = 2058 CEFBS_HasStdEnc_HasMSA, // MIN_U_B = 2059 CEFBS_HasStdEnc_HasMSA, // MIN_U_D = 2060 CEFBS_HasStdEnc_HasMSA, // MIN_U_H = 2061 CEFBS_HasStdEnc_HasMSA, // MIN_U_W = 2062 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MOD = 2063 CEFBS_HasDSP, // MODSUB = 2064 CEFBS_InMicroMips_HasDSP, // MODSUB_MM = 2065 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MODU = 2066 CEFBS_InMicroMips_HasMips32r6, // MODU_MMR6 = 2067 CEFBS_InMicroMips_HasMips32r6, // MOD_MMR6 = 2068 CEFBS_HasStdEnc_HasMSA, // MOD_S_B = 2069 CEFBS_HasStdEnc_HasMSA, // MOD_S_D = 2070 CEFBS_HasStdEnc_HasMSA, // MOD_S_H = 2071 CEFBS_HasStdEnc_HasMSA, // MOD_S_W = 2072 CEFBS_HasStdEnc_HasMSA, // MOD_U_B = 2073 CEFBS_HasStdEnc_HasMSA, // MOD_U_D = 2074 CEFBS_HasStdEnc_HasMSA, // MOD_U_H = 2075 CEFBS_HasStdEnc_HasMSA, // MOD_U_W = 2076 CEFBS_InMicroMips_NotMips32r6, // MOVE16_MM = 2077 CEFBS_InMicroMips_HasMips32r6, // MOVE16_MMR6 = 2078 CEFBS_InMicroMips_NotMips32r6, // MOVEP_MM = 2079 CEFBS_InMicroMips_HasMips32r6, // MOVEP_MMR6 = 2080 CEFBS_HasStdEnc_HasMSA, // MOVE_V = 2081 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D32 = 2082 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVF_D32_MM = 2083 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D64 = 2084 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I = 2085 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I64 = 2086 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_I_MM = 2087 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_S = 2088 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_S_MM = 2089 CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_D64 = 2090 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I = 2091 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I64 = 2092 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_S = 2093 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D32 = 2094 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVN_I_D32_MM = 2095 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D64 = 2096 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I = 2097 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I64 = 2098 CEFBS_InMicroMips_NotMips32r6, // MOVN_I_MM = 2099 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_S = 2100 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVN_I_S_MM = 2101 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D32 = 2102 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVT_D32_MM = 2103 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D64 = 2104 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I = 2105 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I64 = 2106 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_I_MM = 2107 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_S = 2108 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_S_MM = 2109 CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_D64 = 2110 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I = 2111 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I64 = 2112 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_S = 2113 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D32 = 2114 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVZ_I_D32_MM = 2115 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D64 = 2116 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I = 2117 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I64 = 2118 CEFBS_InMicroMips_NotMips32r6, // MOVZ_I_MM = 2119 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_S = 2120 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVZ_I_S_MM = 2121 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUB = 2122 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_D = 2123 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_D_MMR6 = 2124 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_S = 2125 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_S_MMR6 = 2126 CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_H = 2127 CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_W = 2128 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUBU = 2129 CEFBS_HasDSP, // MSUBU_DSP = 2130 CEFBS_InMicroMips_HasDSP, // MSUBU_DSP_MM = 2131 CEFBS_InMicroMips_NotMips32r6, // MSUBU_MM = 2132 CEFBS_HasStdEnc_HasMSA, // MSUBV_B = 2133 CEFBS_HasStdEnc_HasMSA, // MSUBV_D = 2134 CEFBS_HasStdEnc_HasMSA, // MSUBV_H = 2135 CEFBS_HasStdEnc_HasMSA, // MSUBV_W = 2136 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D32 = 2137 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_D32_MM = 2138 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D64 = 2139 CEFBS_HasDSP, // MSUB_DSP = 2140 CEFBS_InMicroMips_HasDSP, // MSUB_DSP_MM = 2141 CEFBS_InMicroMips_NotMips32r6, // MSUB_MM = 2142 CEFBS_HasStdEnc_HasMSA, // MSUB_Q_H = 2143 CEFBS_HasStdEnc_HasMSA, // MSUB_Q_W = 2144 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_S = 2145 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_S_MM = 2146 CEFBS_HasStdEnc_NotInMicroMips, // MTC0 = 2147 CEFBS_InMicroMips_HasMips32r6, // MTC0_MMR6 = 2148 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MTC1 = 2149 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MTC1_D64 = 2150 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTC1_D64_MM = 2151 CEFBS_InMicroMips_IsNotSoftFloat, // MTC1_MM = 2152 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MTC1_MMR6 = 2153 CEFBS_HasStdEnc_NotInMicroMips, // MTC2 = 2154 CEFBS_InMicroMips_HasMips32r6, // MTC2_MMR6 = 2155 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTGC0 = 2156 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTGC0_MM = 2157 CEFBS_InMicroMips_HasMips32r6, // MTHC0_MMR6 = 2158 CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D32 = 2159 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MTHC1_D32_MM = 2160 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D64 = 2161 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTHC1_D64_MM = 2162 CEFBS_InMicroMips_HasMips32r6, // MTHC2_MMR6 = 2163 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTHGC0 = 2164 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTHGC0_MM = 2165 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTHI = 2166 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTHI64 = 2167 CEFBS_HasDSP, // MTHI_DSP = 2168 CEFBS_InMicroMips_HasDSP, // MTHI_DSP_MM = 2169 CEFBS_InMicroMips_NotMips32r6, // MTHI_MM = 2170 CEFBS_HasDSP, // MTHLIP = 2171 CEFBS_InMicroMips_HasDSP, // MTHLIP_MM = 2172 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTLO = 2173 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTLO64 = 2174 CEFBS_HasDSP, // MTLO_DSP = 2175 CEFBS_InMicroMips_HasDSP, // MTLO_DSP_MM = 2176 CEFBS_InMicroMips_NotMips32r6, // MTLO_MM = 2177 CEFBS_HasCnMips, // MTM0 = 2178 CEFBS_HasCnMips, // MTM1 = 2179 CEFBS_HasCnMips, // MTM2 = 2180 CEFBS_HasCnMips, // MTP0 = 2181 CEFBS_HasCnMips, // MTP1 = 2182 CEFBS_HasCnMips, // MTP2 = 2183 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MTTR = 2184 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUH = 2185 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUHU = 2186 CEFBS_InMicroMips_HasMips32r6, // MUHU_MMR6 = 2187 CEFBS_InMicroMips_HasMips32r6, // MUH_MMR6 = 2188 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MUL = 2189 CEFBS_HasDSP, // MULEQ_S_W_PHL = 2190 CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHL_MM = 2191 CEFBS_HasDSP, // MULEQ_S_W_PHR = 2192 CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHR_MM = 2193 CEFBS_HasDSP, // MULEU_S_PH_QBL = 2194 CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBL_MM = 2195 CEFBS_HasDSP, // MULEU_S_PH_QBR = 2196 CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBR_MM = 2197 CEFBS_HasDSP, // MULQ_RS_PH = 2198 CEFBS_InMicroMips_HasDSP, // MULQ_RS_PH_MM = 2199 CEFBS_HasDSPR2, // MULQ_RS_W = 2200 CEFBS_InMicroMips_HasDSPR2, // MULQ_RS_W_MMR2 = 2201 CEFBS_HasDSPR2, // MULQ_S_PH = 2202 CEFBS_InMicroMips_HasDSPR2, // MULQ_S_PH_MMR2 = 2203 CEFBS_HasDSPR2, // MULQ_S_W = 2204 CEFBS_InMicroMips_HasDSPR2, // MULQ_S_W_MMR2 = 2205 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // MULR_PS64 = 2206 CEFBS_HasStdEnc_HasMSA, // MULR_Q_H = 2207 CEFBS_HasStdEnc_HasMSA, // MULR_Q_W = 2208 CEFBS_HasDSP, // MULSAQ_S_W_PH = 2209 CEFBS_InMicroMips_HasDSP, // MULSAQ_S_W_PH_MM = 2210 CEFBS_HasDSPR2, // MULSA_W_PH = 2211 CEFBS_InMicroMips_HasDSPR2, // MULSA_W_PH_MMR2 = 2212 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULT = 2213 CEFBS_HasDSP, // MULTU_DSP = 2214 CEFBS_InMicroMips_HasDSP, // MULTU_DSP_MM = 2215 CEFBS_HasDSP, // MULT_DSP = 2216 CEFBS_InMicroMips_HasDSP, // MULT_DSP_MM = 2217 CEFBS_InMicroMips_NotMips32r6, // MULT_MM = 2218 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULTu = 2219 CEFBS_InMicroMips_NotMips32r6, // MULTu_MM = 2220 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MULU = 2221 CEFBS_InMicroMips_HasMips32r6, // MULU_MMR6 = 2222 CEFBS_HasStdEnc_HasMSA, // MULV_B = 2223 CEFBS_HasStdEnc_HasMSA, // MULV_D = 2224 CEFBS_HasStdEnc_HasMSA, // MULV_H = 2225 CEFBS_HasStdEnc_HasMSA, // MULV_W = 2226 CEFBS_InMicroMips_NotMips32r6, // MUL_MM = 2227 CEFBS_InMicroMips_HasMips32r6, // MUL_MMR6 = 2228 CEFBS_HasDSPR2, // MUL_PH = 2229 CEFBS_InMicroMips_HasDSPR2, // MUL_PH_MMR2 = 2230 CEFBS_HasStdEnc_HasMSA, // MUL_Q_H = 2231 CEFBS_HasStdEnc_HasMSA, // MUL_Q_W = 2232 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUL_R6 = 2233 CEFBS_HasDSPR2, // MUL_S_PH = 2234 CEFBS_InMicroMips_HasDSPR2, // MUL_S_PH_MMR2 = 2235 CEFBS_InMips16Mode, // Mfhi16 = 2236 CEFBS_InMips16Mode, // Mflo16 = 2237 CEFBS_InMips16Mode, // Move32R16 = 2238 CEFBS_InMips16Mode, // MoveR3216 = 2239 CEFBS_HasStdEnc_HasMSA, // NLOC_B = 2240 CEFBS_HasStdEnc_HasMSA, // NLOC_D = 2241 CEFBS_HasStdEnc_HasMSA, // NLOC_H = 2242 CEFBS_HasStdEnc_HasMSA, // NLOC_W = 2243 CEFBS_HasStdEnc_HasMSA, // NLZC_B = 2244 CEFBS_HasStdEnc_HasMSA, // NLZC_D = 2245 CEFBS_HasStdEnc_HasMSA, // NLZC_H = 2246 CEFBS_HasStdEnc_HasMSA, // NLZC_W = 2247 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D32 = 2248 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_D32_MM = 2249 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D64 = 2250 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_S = 2251 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_S_MM = 2252 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D32 = 2253 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_D32_MM = 2254 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D64 = 2255 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_S = 2256 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_S_MM = 2257 CEFBS_HasStdEnc_NotInMicroMips, // NOR = 2258 CEFBS_NotInMips16Mode_IsGP64bit, // NOR64 = 2259 CEFBS_HasStdEnc_HasMSA, // NORI_B = 2260 CEFBS_InMicroMips_NotMips32r6, // NOR_MM = 2261 CEFBS_InMicroMips_HasMips32r6, // NOR_MMR6 = 2262 CEFBS_HasStdEnc_HasMSA, // NOR_V = 2263 CEFBS_InMicroMips_NotMips32r6, // NOT16_MM = 2264 CEFBS_InMicroMips_HasMips32r6, // NOT16_MMR6 = 2265 CEFBS_InMips16Mode, // NegRxRy16 = 2266 CEFBS_InMips16Mode, // NotRxRy16 = 2267 CEFBS_HasStdEnc_NotInMicroMips, // OR = 2268 CEFBS_InMicroMips_NotMips32r6, // OR16_MM = 2269 CEFBS_InMicroMips_HasMips32r6, // OR16_MMR6 = 2270 CEFBS_NotInMips16Mode_IsGP64bit, // OR64 = 2271 CEFBS_HasStdEnc_HasMSA, // ORI_B = 2272 CEFBS_InMicroMips_HasMips32r6, // ORI_MMR6 = 2273 CEFBS_InMicroMips_NotMips32r6, // OR_MM = 2274 CEFBS_InMicroMips_HasMips32r6, // OR_MMR6 = 2275 CEFBS_HasStdEnc_HasMSA, // OR_V = 2276 CEFBS_HasStdEnc_NotInMicroMips, // ORi = 2277 CEFBS_NotInMips16Mode_IsGP64bit, // ORi64 = 2278 CEFBS_InMicroMips_NotMips32r6, // ORi_MM = 2279 CEFBS_InMips16Mode, // OrRxRxRy16 = 2280 CEFBS_HasDSP, // PACKRL_PH = 2281 CEFBS_InMicroMips_HasDSP, // PACKRL_PH_MM = 2282 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // PAUSE = 2283 CEFBS_InMicroMips, // PAUSE_MM = 2284 CEFBS_InMicroMips_HasMips32r6, // PAUSE_MMR6 = 2285 CEFBS_HasStdEnc_HasMSA, // PCKEV_B = 2286 CEFBS_HasStdEnc_HasMSA, // PCKEV_D = 2287 CEFBS_HasStdEnc_HasMSA, // PCKEV_H = 2288 CEFBS_HasStdEnc_HasMSA, // PCKEV_W = 2289 CEFBS_HasStdEnc_HasMSA, // PCKOD_B = 2290 CEFBS_HasStdEnc_HasMSA, // PCKOD_D = 2291 CEFBS_HasStdEnc_HasMSA, // PCKOD_H = 2292 CEFBS_HasStdEnc_HasMSA, // PCKOD_W = 2293 CEFBS_HasStdEnc_HasMSA, // PCNT_B = 2294 CEFBS_HasStdEnc_HasMSA, // PCNT_D = 2295 CEFBS_HasStdEnc_HasMSA, // PCNT_H = 2296 CEFBS_HasStdEnc_HasMSA, // PCNT_W = 2297 CEFBS_HasDSP, // PICK_PH = 2298 CEFBS_InMicroMips_HasDSP, // PICK_PH_MM = 2299 CEFBS_HasDSP, // PICK_QB = 2300 CEFBS_InMicroMips_HasDSP, // PICK_QB_MM = 2301 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLL_PS64 = 2302 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLU_PS64 = 2303 CEFBS_HasCnMips, // POP = 2304 CEFBS_HasDSP, // PRECEQU_PH_QBL = 2305 CEFBS_HasDSP, // PRECEQU_PH_QBLA = 2306 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBLA_MM = 2307 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBL_MM = 2308 CEFBS_HasDSP, // PRECEQU_PH_QBR = 2309 CEFBS_HasDSP, // PRECEQU_PH_QBRA = 2310 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBRA_MM = 2311 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBR_MM = 2312 CEFBS_HasDSP, // PRECEQ_W_PHL = 2313 CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHL_MM = 2314 CEFBS_HasDSP, // PRECEQ_W_PHR = 2315 CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHR_MM = 2316 CEFBS_HasDSP, // PRECEU_PH_QBL = 2317 CEFBS_HasDSP, // PRECEU_PH_QBLA = 2318 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBLA_MM = 2319 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBL_MM = 2320 CEFBS_HasDSP, // PRECEU_PH_QBR = 2321 CEFBS_HasDSP, // PRECEU_PH_QBRA = 2322 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBRA_MM = 2323 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBR_MM = 2324 CEFBS_HasDSP, // PRECRQU_S_QB_PH = 2325 CEFBS_InMicroMips_HasDSP, // PRECRQU_S_QB_PH_MM = 2326 CEFBS_HasDSP, // PRECRQ_PH_W = 2327 CEFBS_InMicroMips_HasDSP, // PRECRQ_PH_W_MM = 2328 CEFBS_HasDSP, // PRECRQ_QB_PH = 2329 CEFBS_InMicroMips_HasDSP, // PRECRQ_QB_PH_MM = 2330 CEFBS_HasDSP, // PRECRQ_RS_PH_W = 2331 CEFBS_InMicroMips_HasDSP, // PRECRQ_RS_PH_W_MM = 2332 CEFBS_HasDSPR2, // PRECR_QB_PH = 2333 CEFBS_InMicroMips_HasDSPR2, // PRECR_QB_PH_MMR2 = 2334 CEFBS_HasDSPR2, // PRECR_SRA_PH_W = 2335 CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_PH_W_MMR2 = 2336 CEFBS_HasDSPR2, // PRECR_SRA_R_PH_W = 2337 CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_R_PH_W_MMR2 = 2338 CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // PREF = 2339 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // PREFE = 2340 CEFBS_InMicroMips_HasEVA, // PREFE_MM = 2341 CEFBS_InMicroMips_NotMips32r6, // PREFX_MM = 2342 CEFBS_InMicroMips_NotMips32r6, // PREF_MM = 2343 CEFBS_InMicroMips_HasMips32r6, // PREF_MMR6 = 2344 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // PREF_R6 = 2345 CEFBS_HasDSPR2, // PREPEND = 2346 CEFBS_InMicroMips_HasDSPR2, // PREPEND_MMR2 = 2347 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUL_PS64 = 2348 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUU_PS64 = 2349 CEFBS_HasDSP, // RADDU_W_QB = 2350 CEFBS_InMicroMips_HasDSP, // RADDU_W_QB_MM = 2351 CEFBS_HasDSP, // RDDSP = 2352 CEFBS_InMicroMips_HasDSP, // RDDSP_MM = 2353 CEFBS_HasStdEnc_NotInMicroMips, // RDHWR = 2354 CEFBS_NotInMips16Mode_IsGP64bit, // RDHWR64 = 2355 CEFBS_InMicroMips_NotMips32r6, // RDHWR_MM = 2356 CEFBS_InMicroMips_HasMips32r6, // RDHWR_MMR6 = 2357 CEFBS_InMicroMips_HasMips32r6, // RDPGPR_MMR6 = 2358 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D32 = 2359 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RECIP_D32_MM = 2360 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D64 = 2361 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RECIP_D64_MM = 2362 CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_S = 2363 CEFBS_InMicroMips_IsNotSoftFloat, // RECIP_S_MM = 2364 CEFBS_HasDSP, // REPLV_PH = 2365 CEFBS_InMicroMips_HasDSP, // REPLV_PH_MM = 2366 CEFBS_HasDSP, // REPLV_QB = 2367 CEFBS_InMicroMips_HasDSP, // REPLV_QB_MM = 2368 CEFBS_HasDSP, // REPL_PH = 2369 CEFBS_InMicroMips_HasDSP, // REPL_PH_MM = 2370 CEFBS_HasDSP, // REPL_QB = 2371 CEFBS_InMicroMips_HasDSP, // REPL_QB_MM = 2372 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_D = 2373 CEFBS_InMicroMips_HasMips32r6, // RINT_D_MMR6 = 2374 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_S = 2375 CEFBS_InMicroMips_HasMips32r6, // RINT_S_MMR6 = 2376 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTR = 2377 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTRV = 2378 CEFBS_InMicroMips, // ROTRV_MM = 2379 CEFBS_InMicroMips, // ROTR_MM = 2380 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // ROUND_L_D64 = 2381 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_D_MMR6 = 2382 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_L_S = 2383 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_S_MMR6 = 2384 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D32 = 2385 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D64 = 2386 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_D_MMR6 = 2387 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // ROUND_W_MM = 2388 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_S = 2389 CEFBS_InMicroMips_IsNotSoftFloat, // ROUND_W_S_MM = 2390 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_S_MMR6 = 2391 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D32 = 2392 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RSQRT_D32_MM = 2393 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D64 = 2394 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RSQRT_D64_MM = 2395 CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_S = 2396 CEFBS_InMicroMips_IsNotSoftFloat, // RSQRT_S_MM = 2397 CEFBS_InMips16Mode, // Restore16 = 2398 CEFBS_InMips16Mode, // RestoreX16 = 2399 CEFBS_HasCnMipsP, // SAA = 2400 CEFBS_HasCnMipsP, // SAAD = 2401 CEFBS_HasStdEnc_HasMSA, // SAT_S_B = 2402 CEFBS_HasStdEnc_HasMSA, // SAT_S_D = 2403 CEFBS_HasStdEnc_HasMSA, // SAT_S_H = 2404 CEFBS_HasStdEnc_HasMSA, // SAT_S_W = 2405 CEFBS_HasStdEnc_HasMSA, // SAT_U_B = 2406 CEFBS_HasStdEnc_HasMSA, // SAT_U_D = 2407 CEFBS_HasStdEnc_HasMSA, // SAT_U_H = 2408 CEFBS_HasStdEnc_HasMSA, // SAT_U_W = 2409 CEFBS_HasStdEnc_NotInMicroMips, // SB = 2410 CEFBS_InMicroMips_NotMips32r6, // SB16_MM = 2411 CEFBS_InMicroMips_HasMips32r6, // SB16_MMR6 = 2412 CEFBS_NotInMips16Mode_IsGP64bit, // SB64 = 2413 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SBE = 2414 CEFBS_InMicroMips_HasEVA, // SBE_MM = 2415 CEFBS_InMicroMips, // SB_MM = 2416 CEFBS_InMicroMips_HasMips32r6, // SB_MMR6 = 2417 CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC = 2418 CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC64 = 2419 CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // SC64_R6 = 2420 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SCD = 2421 CEFBS_HasStdEnc_HasMips32r6, // SCD_R6 = 2422 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SCE = 2423 CEFBS_InMicroMips_HasEVA, // SCE_MM = 2424 CEFBS_InMicroMips_NotMips32r6, // SC_MM = 2425 CEFBS_InMicroMips_HasMips32r6, // SC_MMR6 = 2426 CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // SC_R6 = 2427 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // SD = 2428 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // SDBBP = 2429 CEFBS_InMicroMips_NotMips32r6, // SDBBP16_MM = 2430 CEFBS_InMicroMips_HasMips32r6, // SDBBP16_MMR6 = 2431 CEFBS_InMicroMips, // SDBBP_MM = 2432 CEFBS_InMicroMips_HasMips32r6, // SDBBP_MMR6 = 2433 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDBBP_R6 = 2434 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC1 = 2435 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC164 = 2436 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // SDC1_D64_MMR6 = 2437 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // SDC1_MM_D32 = 2438 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // SDC1_MM_D64 = 2439 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SDC2 = 2440 CEFBS_InMicroMips_HasMips32r6, // SDC2_MMR6 = 2441 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDC2_R6 = 2442 CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // SDC3 = 2443 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SDIV = 2444 CEFBS_InMicroMips_NotMips32r6, // SDIV_MM = 2445 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDL = 2446 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDR = 2447 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SDXC1 = 2448 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SDXC164 = 2449 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEB = 2450 CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEB64 = 2451 CEFBS_InMicroMips, // SEB_MM = 2452 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEH = 2453 CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEH64 = 2454 CEFBS_InMicroMips, // SEH_MM = 2455 CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELEQZ = 2456 CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELEQZ64 = 2457 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_D = 2458 CEFBS_InMicroMips_HasMips32r6, // SELEQZ_D_MMR6 = 2459 CEFBS_InMicroMips_HasMips32r6, // SELEQZ_MMR6 = 2460 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_S = 2461 CEFBS_InMicroMips_HasMips32r6, // SELEQZ_S_MMR6 = 2462 CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELNEZ = 2463 CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELNEZ64 = 2464 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_D = 2465 CEFBS_InMicroMips_HasMips32r6, // SELNEZ_D_MMR6 = 2466 CEFBS_InMicroMips_HasMips32r6, // SELNEZ_MMR6 = 2467 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_S = 2468 CEFBS_InMicroMips_HasMips32r6, // SELNEZ_S_MMR6 = 2469 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_D = 2470 CEFBS_InMicroMips_HasMips32r6, // SEL_D_MMR6 = 2471 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_S = 2472 CEFBS_InMicroMips_HasMips32r6, // SEL_S_MMR6 = 2473 CEFBS_HasCnMips, // SEQ = 2474 CEFBS_HasCnMips, // SEQi = 2475 CEFBS_HasStdEnc_NotInMicroMips, // SH = 2476 CEFBS_InMicroMips_NotMips32r6, // SH16_MM = 2477 CEFBS_InMicroMips_HasMips32r6, // SH16_MMR6 = 2478 CEFBS_NotInMips16Mode_IsGP64bit, // SH64 = 2479 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SHE = 2480 CEFBS_InMicroMips_HasEVA, // SHE_MM = 2481 CEFBS_HasStdEnc_HasMSA, // SHF_B = 2482 CEFBS_HasStdEnc_HasMSA, // SHF_H = 2483 CEFBS_HasStdEnc_HasMSA, // SHF_W = 2484 CEFBS_HasDSP, // SHILO = 2485 CEFBS_HasDSP, // SHILOV = 2486 CEFBS_InMicroMips_HasDSP, // SHILOV_MM = 2487 CEFBS_InMicroMips_HasDSP, // SHILO_MM = 2488 CEFBS_HasDSP, // SHLLV_PH = 2489 CEFBS_InMicroMips_HasDSP, // SHLLV_PH_MM = 2490 CEFBS_HasDSP, // SHLLV_QB = 2491 CEFBS_InMicroMips_HasDSP, // SHLLV_QB_MM = 2492 CEFBS_HasDSP, // SHLLV_S_PH = 2493 CEFBS_InMicroMips_HasDSP, // SHLLV_S_PH_MM = 2494 CEFBS_HasDSP, // SHLLV_S_W = 2495 CEFBS_InMicroMips_HasDSP, // SHLLV_S_W_MM = 2496 CEFBS_HasDSP, // SHLL_PH = 2497 CEFBS_InMicroMips_HasDSP, // SHLL_PH_MM = 2498 CEFBS_HasDSP, // SHLL_QB = 2499 CEFBS_InMicroMips_HasDSP, // SHLL_QB_MM = 2500 CEFBS_HasDSP, // SHLL_S_PH = 2501 CEFBS_InMicroMips_HasDSP, // SHLL_S_PH_MM = 2502 CEFBS_HasDSP, // SHLL_S_W = 2503 CEFBS_InMicroMips_HasDSP, // SHLL_S_W_MM = 2504 CEFBS_HasDSP, // SHRAV_PH = 2505 CEFBS_InMicroMips_HasDSP, // SHRAV_PH_MM = 2506 CEFBS_HasDSPR2, // SHRAV_QB = 2507 CEFBS_InMicroMips_HasDSPR2, // SHRAV_QB_MMR2 = 2508 CEFBS_HasDSP, // SHRAV_R_PH = 2509 CEFBS_InMicroMips_HasDSP, // SHRAV_R_PH_MM = 2510 CEFBS_HasDSPR2, // SHRAV_R_QB = 2511 CEFBS_InMicroMips_HasDSPR2, // SHRAV_R_QB_MMR2 = 2512 CEFBS_HasDSP, // SHRAV_R_W = 2513 CEFBS_InMicroMips_HasDSP, // SHRAV_R_W_MM = 2514 CEFBS_HasDSP, // SHRA_PH = 2515 CEFBS_InMicroMips_HasDSP, // SHRA_PH_MM = 2516 CEFBS_HasDSPR2, // SHRA_QB = 2517 CEFBS_InMicroMips_HasDSPR2, // SHRA_QB_MMR2 = 2518 CEFBS_HasDSP, // SHRA_R_PH = 2519 CEFBS_InMicroMips_HasDSP, // SHRA_R_PH_MM = 2520 CEFBS_HasDSPR2, // SHRA_R_QB = 2521 CEFBS_InMicroMips_HasDSPR2, // SHRA_R_QB_MMR2 = 2522 CEFBS_HasDSP, // SHRA_R_W = 2523 CEFBS_InMicroMips_HasDSP, // SHRA_R_W_MM = 2524 CEFBS_HasDSPR2, // SHRLV_PH = 2525 CEFBS_InMicroMips_HasDSPR2, // SHRLV_PH_MMR2 = 2526 CEFBS_HasDSP, // SHRLV_QB = 2527 CEFBS_InMicroMips_HasDSP, // SHRLV_QB_MM = 2528 CEFBS_HasDSPR2, // SHRL_PH = 2529 CEFBS_InMicroMips_HasDSPR2, // SHRL_PH_MMR2 = 2530 CEFBS_HasDSP, // SHRL_QB = 2531 CEFBS_InMicroMips_HasDSP, // SHRL_QB_MM = 2532 CEFBS_InMicroMips, // SH_MM = 2533 CEFBS_InMicroMips_HasMips32r6, // SH_MMR6 = 2534 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SIGRIE = 2535 CEFBS_InMicroMips_HasMips32r6, // SIGRIE_MMR6 = 2536 CEFBS_HasStdEnc_HasMSA, // SLDI_B = 2537 CEFBS_HasStdEnc_HasMSA, // SLDI_D = 2538 CEFBS_HasStdEnc_HasMSA, // SLDI_H = 2539 CEFBS_HasStdEnc_HasMSA, // SLDI_W = 2540 CEFBS_HasStdEnc_HasMSA, // SLD_B = 2541 CEFBS_HasStdEnc_HasMSA, // SLD_D = 2542 CEFBS_HasStdEnc_HasMSA, // SLD_H = 2543 CEFBS_HasStdEnc_HasMSA, // SLD_W = 2544 CEFBS_HasStdEnc_NotInMicroMips, // SLL = 2545 CEFBS_InMicroMips_NotMips32r6, // SLL16_MM = 2546 CEFBS_InMicroMips_HasMips32r6, // SLL16_MMR6 = 2547 CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_32 = 2548 CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_64 = 2549 CEFBS_HasStdEnc_HasMSA, // SLLI_B = 2550 CEFBS_HasStdEnc_HasMSA, // SLLI_D = 2551 CEFBS_HasStdEnc_HasMSA, // SLLI_H = 2552 CEFBS_HasStdEnc_HasMSA, // SLLI_W = 2553 CEFBS_HasStdEnc_NotInMicroMips, // SLLV = 2554 CEFBS_InMicroMips, // SLLV_MM = 2555 CEFBS_HasStdEnc_HasMSA, // SLL_B = 2556 CEFBS_HasStdEnc_HasMSA, // SLL_D = 2557 CEFBS_HasStdEnc_HasMSA, // SLL_H = 2558 CEFBS_InMicroMips, // SLL_MM = 2559 CEFBS_InMicroMips_HasMips32r6, // SLL_MMR6 = 2560 CEFBS_HasStdEnc_HasMSA, // SLL_W = 2561 CEFBS_HasStdEnc_NotInMicroMips, // SLT = 2562 CEFBS_NotInMips16Mode_IsGP64bit, // SLT64 = 2563 CEFBS_InMicroMips, // SLT_MM = 2564 CEFBS_HasStdEnc_NotInMicroMips, // SLTi = 2565 CEFBS_NotInMips16Mode_IsGP64bit, // SLTi64 = 2566 CEFBS_InMicroMips, // SLTi_MM = 2567 CEFBS_HasStdEnc_NotInMicroMips, // SLTiu = 2568 CEFBS_NotInMips16Mode_IsGP64bit, // SLTiu64 = 2569 CEFBS_InMicroMips, // SLTiu_MM = 2570 CEFBS_HasStdEnc_NotInMicroMips, // SLTu = 2571 CEFBS_NotInMips16Mode_IsGP64bit, // SLTu64 = 2572 CEFBS_InMicroMips, // SLTu_MM = 2573 CEFBS_HasCnMips, // SNE = 2574 CEFBS_HasCnMips, // SNEi = 2575 CEFBS_HasStdEnc_HasMSA, // SPLATI_B = 2576 CEFBS_HasStdEnc_HasMSA, // SPLATI_D = 2577 CEFBS_HasStdEnc_HasMSA, // SPLATI_H = 2578 CEFBS_HasStdEnc_HasMSA, // SPLATI_W = 2579 CEFBS_HasStdEnc_HasMSA, // SPLAT_B = 2580 CEFBS_HasStdEnc_HasMSA, // SPLAT_D = 2581 CEFBS_HasStdEnc_HasMSA, // SPLAT_H = 2582 CEFBS_HasStdEnc_HasMSA, // SPLAT_W = 2583 CEFBS_HasStdEnc_NotInMicroMips, // SRA = 2584 CEFBS_HasStdEnc_HasMSA, // SRAI_B = 2585 CEFBS_HasStdEnc_HasMSA, // SRAI_D = 2586 CEFBS_HasStdEnc_HasMSA, // SRAI_H = 2587 CEFBS_HasStdEnc_HasMSA, // SRAI_W = 2588 CEFBS_HasStdEnc_HasMSA, // SRARI_B = 2589 CEFBS_HasStdEnc_HasMSA, // SRARI_D = 2590 CEFBS_HasStdEnc_HasMSA, // SRARI_H = 2591 CEFBS_HasStdEnc_HasMSA, // SRARI_W = 2592 CEFBS_HasStdEnc_HasMSA, // SRAR_B = 2593 CEFBS_HasStdEnc_HasMSA, // SRAR_D = 2594 CEFBS_HasStdEnc_HasMSA, // SRAR_H = 2595 CEFBS_HasStdEnc_HasMSA, // SRAR_W = 2596 CEFBS_HasStdEnc_NotInMicroMips, // SRAV = 2597 CEFBS_InMicroMips, // SRAV_MM = 2598 CEFBS_HasStdEnc_HasMSA, // SRA_B = 2599 CEFBS_HasStdEnc_HasMSA, // SRA_D = 2600 CEFBS_HasStdEnc_HasMSA, // SRA_H = 2601 CEFBS_InMicroMips, // SRA_MM = 2602 CEFBS_HasStdEnc_HasMSA, // SRA_W = 2603 CEFBS_HasStdEnc_NotInMicroMips, // SRL = 2604 CEFBS_InMicroMips_NotMips32r6, // SRL16_MM = 2605 CEFBS_InMicroMips_HasMips32r6, // SRL16_MMR6 = 2606 CEFBS_HasStdEnc_HasMSA, // SRLI_B = 2607 CEFBS_HasStdEnc_HasMSA, // SRLI_D = 2608 CEFBS_HasStdEnc_HasMSA, // SRLI_H = 2609 CEFBS_HasStdEnc_HasMSA, // SRLI_W = 2610 CEFBS_HasStdEnc_HasMSA, // SRLRI_B = 2611 CEFBS_HasStdEnc_HasMSA, // SRLRI_D = 2612 CEFBS_HasStdEnc_HasMSA, // SRLRI_H = 2613 CEFBS_HasStdEnc_HasMSA, // SRLRI_W = 2614 CEFBS_HasStdEnc_HasMSA, // SRLR_B = 2615 CEFBS_HasStdEnc_HasMSA, // SRLR_D = 2616 CEFBS_HasStdEnc_HasMSA, // SRLR_H = 2617 CEFBS_HasStdEnc_HasMSA, // SRLR_W = 2618 CEFBS_HasStdEnc_NotInMicroMips, // SRLV = 2619 CEFBS_InMicroMips, // SRLV_MM = 2620 CEFBS_HasStdEnc_HasMSA, // SRL_B = 2621 CEFBS_HasStdEnc_HasMSA, // SRL_D = 2622 CEFBS_HasStdEnc_HasMSA, // SRL_H = 2623 CEFBS_InMicroMips, // SRL_MM = 2624 CEFBS_HasStdEnc_HasMSA, // SRL_W = 2625 CEFBS_HasStdEnc_NotInMicroMips, // SSNOP = 2626 CEFBS_InMicroMips, // SSNOP_MM = 2627 CEFBS_InMicroMips_HasMips32r6, // SSNOP_MMR6 = 2628 CEFBS_HasStdEnc_HasMSA, // ST_B = 2629 CEFBS_HasStdEnc_HasMSA, // ST_D = 2630 CEFBS_HasStdEnc_HasMSA, // ST_H = 2631 CEFBS_HasStdEnc_HasMSA, // ST_W = 2632 CEFBS_HasStdEnc_NotInMicroMips, // SUB = 2633 CEFBS_HasDSPR2, // SUBQH_PH = 2634 CEFBS_InMicroMips_HasDSPR2, // SUBQH_PH_MMR2 = 2635 CEFBS_HasDSPR2, // SUBQH_R_PH = 2636 CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_PH_MMR2 = 2637 CEFBS_HasDSPR2, // SUBQH_R_W = 2638 CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_W_MMR2 = 2639 CEFBS_HasDSPR2, // SUBQH_W = 2640 CEFBS_InMicroMips_HasDSPR2, // SUBQH_W_MMR2 = 2641 CEFBS_HasDSP, // SUBQ_PH = 2642 CEFBS_InMicroMips_HasDSP, // SUBQ_PH_MM = 2643 CEFBS_HasDSP, // SUBQ_S_PH = 2644 CEFBS_InMicroMips_HasDSP, // SUBQ_S_PH_MM = 2645 CEFBS_HasDSP, // SUBQ_S_W = 2646 CEFBS_InMicroMips_HasDSP, // SUBQ_S_W_MM = 2647 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_B = 2648 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_D = 2649 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_H = 2650 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_W = 2651 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_B = 2652 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_D = 2653 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_H = 2654 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_W = 2655 CEFBS_HasStdEnc_HasMSA, // SUBS_S_B = 2656 CEFBS_HasStdEnc_HasMSA, // SUBS_S_D = 2657 CEFBS_HasStdEnc_HasMSA, // SUBS_S_H = 2658 CEFBS_HasStdEnc_HasMSA, // SUBS_S_W = 2659 CEFBS_HasStdEnc_HasMSA, // SUBS_U_B = 2660 CEFBS_HasStdEnc_HasMSA, // SUBS_U_D = 2661 CEFBS_HasStdEnc_HasMSA, // SUBS_U_H = 2662 CEFBS_HasStdEnc_HasMSA, // SUBS_U_W = 2663 CEFBS_InMicroMips_NotMips32r6, // SUBU16_MM = 2664 CEFBS_InMicroMips_HasMips32r6, // SUBU16_MMR6 = 2665 CEFBS_HasDSPR2, // SUBUH_QB = 2666 CEFBS_InMicroMips_HasDSPR2, // SUBUH_QB_MMR2 = 2667 CEFBS_HasDSPR2, // SUBUH_R_QB = 2668 CEFBS_InMicroMips_HasDSPR2, // SUBUH_R_QB_MMR2 = 2669 CEFBS_InMicroMips_HasMips32r6, // SUBU_MMR6 = 2670 CEFBS_HasDSPR2, // SUBU_PH = 2671 CEFBS_InMicroMips_HasDSPR2, // SUBU_PH_MMR2 = 2672 CEFBS_HasDSP, // SUBU_QB = 2673 CEFBS_InMicroMips_HasDSP, // SUBU_QB_MM = 2674 CEFBS_HasDSPR2, // SUBU_S_PH = 2675 CEFBS_InMicroMips_HasDSPR2, // SUBU_S_PH_MMR2 = 2676 CEFBS_HasDSP, // SUBU_S_QB = 2677 CEFBS_InMicroMips_HasDSP, // SUBU_S_QB_MM = 2678 CEFBS_HasStdEnc_HasMSA, // SUBVI_B = 2679 CEFBS_HasStdEnc_HasMSA, // SUBVI_D = 2680 CEFBS_HasStdEnc_HasMSA, // SUBVI_H = 2681 CEFBS_HasStdEnc_HasMSA, // SUBVI_W = 2682 CEFBS_HasStdEnc_HasMSA, // SUBV_B = 2683 CEFBS_HasStdEnc_HasMSA, // SUBV_D = 2684 CEFBS_HasStdEnc_HasMSA, // SUBV_H = 2685 CEFBS_HasStdEnc_HasMSA, // SUBV_W = 2686 CEFBS_InMicroMips_NotMips32r6, // SUB_MM = 2687 CEFBS_InMicroMips_HasMips32r6, // SUB_MMR6 = 2688 CEFBS_HasStdEnc_NotInMicroMips, // SUBu = 2689 CEFBS_InMicroMips_NotMips32r6, // SUBu_MM = 2690 CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC1 = 2691 CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC164 = 2692 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // SUXC1_MM = 2693 CEFBS_HasStdEnc_NotInMicroMips, // SW = 2694 CEFBS_InMicroMips_NotMips32r6, // SW16_MM = 2695 CEFBS_InMicroMips_HasMips32r6, // SW16_MMR6 = 2696 CEFBS_NotInMips16Mode_IsGP64bit, // SW64 = 2697 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // SWC1 = 2698 CEFBS_InMicroMips_IsNotSoftFloat, // SWC1_MM = 2699 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWC2 = 2700 CEFBS_InMicroMips_HasMips32r6, // SWC2_MMR6 = 2701 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SWC2_R6 = 2702 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // SWC3 = 2703 CEFBS_NotInMips16Mode_HasDSP, // SWDSP = 2704 CEFBS_InMicroMips_HasDSP, // SWDSP_MM = 2705 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SWE = 2706 CEFBS_InMicroMips_HasEVA, // SWE_MM = 2707 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWL = 2708 CEFBS_NotInMips16Mode_IsGP64bit, // SWL64 = 2709 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWLE = 2710 CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWLE_MM = 2711 CEFBS_InMicroMips_NotMips32r6, // SWL_MM = 2712 CEFBS_InMicroMips_NotMips32r6, // SWM16_MM = 2713 CEFBS_InMicroMips_HasMips32r6, // SWM16_MMR6 = 2714 CEFBS_InMicroMips, // SWM32_MM = 2715 CEFBS_InMicroMips, // SWP_MM = 2716 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWR = 2717 CEFBS_NotInMips16Mode_IsGP64bit, // SWR64 = 2718 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWRE = 2719 CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWRE_MM = 2720 CEFBS_InMicroMips_NotMips32r6, // SWR_MM = 2721 CEFBS_InMicroMips_NotMips32r6, // SWSP_MM = 2722 CEFBS_InMicroMips_HasMips32r6, // SWSP_MMR6 = 2723 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SWXC1 = 2724 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // SWXC1_MM = 2725 CEFBS_InMicroMips, // SW_MM = 2726 CEFBS_InMicroMips_HasMips32r6, // SW_MMR6 = 2727 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // SYNC = 2728 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SYNCI = 2729 CEFBS_InMicroMips_NotMips32r6, // SYNCI_MM = 2730 CEFBS_InMicroMips_HasMips32r6, // SYNCI_MMR6 = 2731 CEFBS_InMicroMips, // SYNC_MM = 2732 CEFBS_InMicroMips_HasMips32r6, // SYNC_MMR6 = 2733 CEFBS_HasStdEnc_NotInMicroMips, // SYSCALL = 2734 CEFBS_InMicroMips, // SYSCALL_MM = 2735 CEFBS_InMips16Mode, // Save16 = 2736 CEFBS_InMips16Mode, // SaveX16 = 2737 CEFBS_InMips16Mode, // SbRxRyOffMemX16 = 2738 CEFBS_InMips16Mode, // SebRx16 = 2739 CEFBS_InMips16Mode, // SehRx16 = 2740 CEFBS_InMips16Mode, // ShRxRyOffMemX16 = 2741 CEFBS_InMips16Mode, // SllX16 = 2742 CEFBS_InMips16Mode, // SllvRxRy16 = 2743 CEFBS_InMips16Mode, // SltRxRy16 = 2744 CEFBS_InMips16Mode, // SltiRxImm16 = 2745 CEFBS_InMips16Mode, // SltiRxImmX16 = 2746 CEFBS_InMips16Mode, // SltiuRxImm16 = 2747 CEFBS_InMips16Mode, // SltiuRxImmX16 = 2748 CEFBS_InMips16Mode, // SltuRxRy16 = 2749 CEFBS_InMips16Mode, // SraX16 = 2750 CEFBS_InMips16Mode, // SravRxRy16 = 2751 CEFBS_InMips16Mode, // SrlX16 = 2752 CEFBS_InMips16Mode, // SrlvRxRy16 = 2753 CEFBS_InMips16Mode, // SubuRxRyRz16 = 2754 CEFBS_InMips16Mode, // SwRxRyOffMemX16 = 2755 CEFBS_InMips16Mode, // SwRxSpImmX16 = 2756 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TEQ = 2757 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TEQI = 2758 CEFBS_InMicroMips_NotMips32r6, // TEQI_MM = 2759 CEFBS_InMicroMips, // TEQ_MM = 2760 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGE = 2761 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEI = 2762 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEIU = 2763 CEFBS_InMicroMips_NotMips32r6, // TGEIU_MM = 2764 CEFBS_InMicroMips_NotMips32r6, // TGEI_MM = 2765 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGEU = 2766 CEFBS_InMicroMips, // TGEU_MM = 2767 CEFBS_InMicroMips, // TGE_MM = 2768 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINV = 2769 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINVF = 2770 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINVF_MM = 2771 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINV_MM = 2772 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGP = 2773 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGP_MM = 2774 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGR = 2775 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGR_MM = 2776 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWI = 2777 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWI_MM = 2778 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWR = 2779 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWR_MM = 2780 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINV = 2781 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINVF = 2782 CEFBS_InMicroMips_HasMips32r6, // TLBINVF_MMR6 = 2783 CEFBS_InMicroMips_HasMips32r6, // TLBINV_MMR6 = 2784 CEFBS_HasStdEnc_NotInMicroMips, // TLBP = 2785 CEFBS_InMicroMips, // TLBP_MM = 2786 CEFBS_HasStdEnc_NotInMicroMips, // TLBR = 2787 CEFBS_InMicroMips, // TLBR_MM = 2788 CEFBS_HasStdEnc_NotInMicroMips, // TLBWI = 2789 CEFBS_InMicroMips, // TLBWI_MM = 2790 CEFBS_HasStdEnc_NotInMicroMips, // TLBWR = 2791 CEFBS_InMicroMips, // TLBWR_MM = 2792 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLT = 2793 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TLTI = 2794 CEFBS_InMicroMips_NotMips32r6, // TLTIU_MM = 2795 CEFBS_InMicroMips_NotMips32r6, // TLTI_MM = 2796 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLTU = 2797 CEFBS_InMicroMips, // TLTU_MM = 2798 CEFBS_InMicroMips, // TLT_MM = 2799 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TNE = 2800 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TNEI = 2801 CEFBS_InMicroMips_NotMips32r6, // TNEI_MM = 2802 CEFBS_InMicroMips, // TNE_MM = 2803 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_D64 = 2804 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_D_MMR6 = 2805 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_S = 2806 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_S_MMR6 = 2807 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D32 = 2808 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D64 = 2809 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_D_MMR6 = 2810 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // TRUNC_W_MM = 2811 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_S = 2812 CEFBS_InMicroMips_IsNotSoftFloat, // TRUNC_W_S_MM = 2813 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_S_MMR6 = 2814 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TTLTIU = 2815 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // UDIV = 2816 CEFBS_InMicroMips_NotMips32r6, // UDIV_MM = 2817 CEFBS_HasCnMips, // V3MULU = 2818 CEFBS_HasCnMips, // VMM0 = 2819 CEFBS_HasCnMips, // VMULU = 2820 CEFBS_HasStdEnc_HasMSA, // VSHF_B = 2821 CEFBS_HasStdEnc_HasMSA, // VSHF_D = 2822 CEFBS_HasStdEnc_HasMSA, // VSHF_H = 2823 CEFBS_HasStdEnc_HasMSA, // VSHF_W = 2824 CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // WAIT = 2825 CEFBS_InMicroMips, // WAIT_MM = 2826 CEFBS_InMicroMips_HasMips32r6, // WAIT_MMR6 = 2827 CEFBS_HasDSP_NotInMicroMips, // WRDSP = 2828 CEFBS_InMicroMips_HasDSP, // WRDSP_MM = 2829 CEFBS_InMicroMips_HasMips32r6, // WRPGPR_MMR6 = 2830 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // WSBH = 2831 CEFBS_InMicroMips, // WSBH_MM = 2832 CEFBS_InMicroMips_HasMips32r6, // WSBH_MMR6 = 2833 CEFBS_HasStdEnc_NotInMicroMips, // XOR = 2834 CEFBS_InMicroMips_NotMips32r6, // XOR16_MM = 2835 CEFBS_InMicroMips_HasMips32r6, // XOR16_MMR6 = 2836 CEFBS_NotInMips16Mode_IsGP64bit, // XOR64 = 2837 CEFBS_HasStdEnc_HasMSA, // XORI_B = 2838 CEFBS_InMicroMips_HasMips32r6, // XORI_MMR6 = 2839 CEFBS_InMicroMips_NotMips32r6, // XOR_MM = 2840 CEFBS_InMicroMips_HasMips32r6, // XOR_MMR6 = 2841 CEFBS_HasStdEnc_HasMSA, // XOR_V = 2842 CEFBS_HasStdEnc_NotInMicroMips, // XORi = 2843 CEFBS_NotInMips16Mode_IsGP64bit, // XORi64 = 2844 CEFBS_InMicroMips_NotMips32r6, // XORi_MM = 2845 CEFBS_InMips16Mode, // XorRxRxRy16 = 2846 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // YIELD = 2847 }; assert(Opcode < 2848); FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Opcode]]; FeatureBitset MissingFeatures = (AvailableFeatures & RequiredFeatures) ^ RequiredFeatures; if (MissingFeatures.any()) { std::ostringstream Msg; Msg << "Attempting to emit " << &MipsInstrNameData[MipsInstrNameIndices[Opcode]] << " instruction but the "; for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) if (MissingFeatures.test(i)) Msg << SubtargetFeatureNames[i] << " "; Msg << "predicate(s) are not met"; report_fatal_error(Msg.str().c_str()); } #endif // NDEBUG } } // end namespace Mips_MC } // end namespace llvm #endif // ENABLE_INSTR_PREDICATE_VERIFIER #ifdef GET_INSTRMAP_INFO #undef GET_INSTRMAP_INFO namespace llvm { namespace Mips { enum Arch { Arch_dsp, Arch_mmdsp, Arch_mipsr6, Arch_micromipsr6, Arch_se, Arch_micromips }; // Dsp2MicroMips LLVM_READONLY int Dsp2MicroMips(uint16_t Opcode, enum Arch inArch) { static const uint16_t Dsp2MicroMipsTable[][3] = { { Mips::ABSQ_S_PH, Mips::ABSQ_S_PH, Mips::ABSQ_S_PH_MM }, { Mips::ABSQ_S_QB, Mips::ABSQ_S_QB, Mips::ABSQ_S_QB_MMR2 }, { Mips::ABSQ_S_W, Mips::ABSQ_S_W, Mips::ABSQ_S_W_MM }, { Mips::ADDQH_PH, Mips::ADDQH_PH, Mips::ADDQH_PH_MMR2 }, { Mips::ADDQH_R_PH, Mips::ADDQH_R_PH, Mips::ADDQH_R_PH_MMR2 }, { Mips::ADDQH_R_W, Mips::ADDQH_R_W, Mips::ADDQH_R_W_MMR2 }, { Mips::ADDQH_W, Mips::ADDQH_W, Mips::ADDQH_W_MMR2 }, { Mips::ADDQ_PH, Mips::ADDQ_PH, Mips::ADDQ_PH_MM }, { Mips::ADDQ_S_PH, Mips::ADDQ_S_PH, Mips::ADDQ_S_PH_MM }, { Mips::ADDQ_S_W, Mips::ADDQ_S_W, Mips::ADDQ_S_W_MM }, { Mips::ADDSC, Mips::ADDSC, Mips::ADDSC_MM }, { Mips::ADDUH_QB, Mips::ADDUH_QB, Mips::ADDUH_QB_MMR2 }, { Mips::ADDUH_R_QB, Mips::ADDUH_R_QB, Mips::ADDUH_R_QB_MMR2 }, { Mips::ADDU_PH, Mips::ADDU_PH, Mips::ADDU_PH_MMR2 }, { Mips::ADDU_QB, Mips::ADDU_QB, Mips::ADDU_QB_MM }, { Mips::ADDU_S_PH, Mips::ADDU_S_PH, Mips::ADDU_S_PH_MMR2 }, { Mips::ADDU_S_QB, Mips::ADDU_S_QB, Mips::ADDU_S_QB_MM }, { Mips::ADDWC, Mips::ADDWC, Mips::ADDWC_MM }, { Mips::APPEND, Mips::APPEND, Mips::APPEND_MMR2 }, { Mips::BALIGN, Mips::BALIGN, Mips::BALIGN_MMR2 }, { Mips::BITREV, Mips::BITREV, Mips::BITREV_MM }, { Mips::BPOSGE32, Mips::BPOSGE32, Mips::BPOSGE32_MM }, { Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB_MMR2 }, { Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB_MMR2 }, { Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB_MMR2 }, { Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB_MM }, { Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB_MM }, { Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB_MM }, { Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB_MM }, { Mips::CMPU_LE_QB, Mips::CMPU_LE_QB, Mips::CMPU_LE_QB_MM }, { Mips::CMPU_LT_QB, Mips::CMPU_LT_QB, Mips::CMPU_LT_QB_MM }, { Mips::CMP_EQ_PH, Mips::CMP_EQ_PH, Mips::CMP_EQ_PH_MM }, { Mips::CMP_LE_PH, Mips::CMP_LE_PH, Mips::CMP_LE_PH_MM }, { Mips::CMP_LT_PH, Mips::CMP_LT_PH, Mips::CMP_LT_PH_MM }, { Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH_MMR2 }, { Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH_MMR2 }, { Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W_MM }, { Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH_MM }, { Mips::DPAU_H_QBL, Mips::DPAU_H_QBL, Mips::DPAU_H_QBL_MM }, { Mips::DPAU_H_QBR, Mips::DPAU_H_QBR, Mips::DPAU_H_QBR_MM }, { Mips::DPAX_W_PH, Mips::DPAX_W_PH, Mips::DPAX_W_PH_MMR2 }, { Mips::DPA_W_PH, Mips::DPA_W_PH, Mips::DPA_W_PH_MMR2 }, { Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH_MMR2 }, { Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH_MMR2 }, { Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W_MM }, { Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH_MM }, { Mips::DPSU_H_QBL, Mips::DPSU_H_QBL, Mips::DPSU_H_QBL_MM }, { Mips::DPSU_H_QBR, Mips::DPSU_H_QBR, Mips::DPSU_H_QBR_MM }, { Mips::DPSX_W_PH, Mips::DPSX_W_PH, Mips::DPSX_W_PH_MMR2 }, { Mips::DPS_W_PH, Mips::DPS_W_PH, Mips::DPS_W_PH_MMR2 }, { Mips::EXTP, Mips::EXTP, Mips::EXTP_MM }, { Mips::EXTPDP, Mips::EXTPDP, Mips::EXTPDP_MM }, { Mips::EXTPDPV, Mips::EXTPDPV, Mips::EXTPDPV_MM }, { Mips::EXTPV, Mips::EXTPV, Mips::EXTPV_MM }, { Mips::EXTRV_RS_W, Mips::EXTRV_RS_W, Mips::EXTRV_RS_W_MM }, { Mips::EXTRV_R_W, Mips::EXTRV_R_W, Mips::EXTRV_R_W_MM }, { Mips::EXTRV_S_H, Mips::EXTRV_S_H, Mips::EXTRV_S_H_MM }, { Mips::EXTRV_W, Mips::EXTRV_W, Mips::EXTRV_W_MM }, { Mips::EXTR_RS_W, Mips::EXTR_RS_W, Mips::EXTR_RS_W_MM }, { Mips::EXTR_R_W, Mips::EXTR_R_W, Mips::EXTR_R_W_MM }, { Mips::EXTR_S_H, Mips::EXTR_S_H, Mips::EXTR_S_H_MM }, { Mips::EXTR_W, Mips::EXTR_W, Mips::EXTR_W_MM }, { Mips::INSV, Mips::INSV, Mips::INSV_MM }, { Mips::LBUX, Mips::LBUX, Mips::LBUX_MM }, { Mips::LHX, Mips::LHX, Mips::LHX_MM }, { Mips::LWDSP, Mips::LWDSP, Mips::LWDSP_MM }, { Mips::LWX, Mips::LWX, Mips::LWX_MM }, { Mips::MADDU_DSP, Mips::MADDU_DSP, Mips::MADDU_DSP_MM }, { Mips::MADD_DSP, Mips::MADD_DSP, Mips::MADD_DSP_MM }, { Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL_MM }, { Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR_MM }, { Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL_MM }, { Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR_MM }, { Mips::MFHI_DSP, Mips::MFHI_DSP, Mips::MFHI_DSP_MM }, { Mips::MFLO_DSP, Mips::MFLO_DSP, Mips::MFLO_DSP_MM }, { Mips::MODSUB, Mips::MODSUB, Mips::MODSUB_MM }, { Mips::MSUBU_DSP, Mips::MSUBU_DSP, Mips::MSUBU_DSP_MM }, { Mips::MSUB_DSP, Mips::MSUB_DSP, Mips::MSUB_DSP_MM }, { Mips::MTHI_DSP, Mips::MTHI_DSP, Mips::MTHI_DSP_MM }, { Mips::MTHLIP, Mips::MTHLIP, Mips::MTHLIP_MM }, { Mips::MTLO_DSP, Mips::MTLO_DSP, Mips::MTLO_DSP_MM }, { Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL_MM }, { Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR_MM }, { Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL_MM }, { Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR_MM }, { Mips::MULQ_RS_PH, Mips::MULQ_RS_PH, Mips::MULQ_RS_PH_MM }, { Mips::MULQ_RS_W, Mips::MULQ_RS_W, Mips::MULQ_RS_W_MMR2 }, { Mips::MULQ_S_PH, Mips::MULQ_S_PH, Mips::MULQ_S_PH_MMR2 }, { Mips::MULQ_S_W, Mips::MULQ_S_W, Mips::MULQ_S_W_MMR2 }, { Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH_MM }, { Mips::MULSA_W_PH, Mips::MULSA_W_PH, Mips::MULSA_W_PH_MMR2 }, { Mips::MULTU_DSP, Mips::MULTU_DSP, Mips::MULTU_DSP_MM }, { Mips::MULT_DSP, Mips::MULT_DSP, Mips::MULT_DSP_MM }, { Mips::MUL_PH, Mips::MUL_PH, Mips::MUL_PH_MMR2 }, { Mips::MUL_S_PH, Mips::MUL_S_PH, Mips::MUL_S_PH_MMR2 }, { Mips::PACKRL_PH, Mips::PACKRL_PH, Mips::PACKRL_PH_MM }, { Mips::PICK_PH, Mips::PICK_PH, Mips::PICK_PH_MM }, { Mips::PICK_QB, Mips::PICK_QB, Mips::PICK_QB_MM }, { Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL_MM }, { Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA_MM }, { Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR_MM }, { Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA_MM }, { Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL_MM }, { Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR_MM }, { Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL_MM }, { Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA_MM }, { Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR_MM }, { Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA_MM }, { Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH_MM }, { Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W_MM }, { Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH_MM }, { Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W_MM }, { Mips::PRECR_QB_PH, Mips::PRECR_QB_PH, Mips::PRECR_QB_PH_MMR2 }, { Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W_MMR2 }, { Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W_MMR2 }, { Mips::PREPEND, Mips::PREPEND, Mips::PREPEND_MMR2 }, { Mips::RADDU_W_QB, Mips::RADDU_W_QB, Mips::RADDU_W_QB_MM }, { Mips::RDDSP, Mips::RDDSP, Mips::RDDSP_MM }, { Mips::REPLV_PH, Mips::REPLV_PH, Mips::REPLV_PH_MM }, { Mips::REPLV_QB, Mips::REPLV_QB, Mips::REPLV_QB_MM }, { Mips::REPL_PH, Mips::REPL_PH, Mips::REPL_PH_MM }, { Mips::REPL_QB, Mips::REPL_QB, Mips::REPL_QB_MM }, { Mips::SHILO, Mips::SHILO, Mips::SHILO_MM }, { Mips::SHILOV, Mips::SHILOV, Mips::SHILOV_MM }, { Mips::SHLLV_PH, Mips::SHLLV_PH, Mips::SHLLV_PH_MM }, { Mips::SHLLV_QB, Mips::SHLLV_QB, Mips::SHLLV_QB_MM }, { Mips::SHLLV_S_PH, Mips::SHLLV_S_PH, Mips::SHLLV_S_PH_MM }, { Mips::SHLLV_S_W, Mips::SHLLV_S_W, Mips::SHLLV_S_W_MM }, { Mips::SHLL_PH, Mips::SHLL_PH, Mips::SHLL_PH_MM }, { Mips::SHLL_QB, Mips::SHLL_QB, Mips::SHLL_QB_MM }, { Mips::SHLL_S_PH, Mips::SHLL_S_PH, Mips::SHLL_S_PH_MM }, { Mips::SHLL_S_W, Mips::SHLL_S_W, Mips::SHLL_S_W_MM }, { Mips::SHRAV_PH, Mips::SHRAV_PH, Mips::SHRAV_PH_MM }, { Mips::SHRAV_QB, Mips::SHRAV_QB, Mips::SHRAV_QB_MMR2 }, { Mips::SHRAV_R_PH, Mips::SHRAV_R_PH, Mips::SHRAV_R_PH_MM }, { Mips::SHRAV_R_QB, Mips::SHRAV_R_QB, Mips::SHRAV_R_QB_MMR2 }, { Mips::SHRAV_R_W, Mips::SHRAV_R_W, Mips::SHRAV_R_W_MM }, { Mips::SHRA_PH, Mips::SHRA_PH, Mips::SHRA_PH_MM }, { Mips::SHRA_QB, Mips::SHRA_QB, Mips::SHRA_QB_MMR2 }, { Mips::SHRA_R_PH, Mips::SHRA_R_PH, Mips::SHRA_R_PH_MM }, { Mips::SHRA_R_QB, Mips::SHRA_R_QB, Mips::SHRA_R_QB_MMR2 }, { Mips::SHRA_R_W, Mips::SHRA_R_W, Mips::SHRA_R_W_MM }, { Mips::SHRLV_PH, Mips::SHRLV_PH, Mips::SHRLV_PH_MMR2 }, { Mips::SHRLV_QB, Mips::SHRLV_QB, Mips::SHRLV_QB_MM }, { Mips::SHRL_PH, Mips::SHRL_PH, Mips::SHRL_PH_MMR2 }, { Mips::SHRL_QB, Mips::SHRL_QB, Mips::SHRL_QB_MM }, { Mips::SUBQH_PH, Mips::SUBQH_PH, Mips::SUBQH_PH_MMR2 }, { Mips::SUBQH_R_PH, Mips::SUBQH_R_PH, Mips::SUBQH_R_PH_MMR2 }, { Mips::SUBQH_R_W, Mips::SUBQH_R_W, Mips::SUBQH_R_W_MMR2 }, { Mips::SUBQH_W, Mips::SUBQH_W, Mips::SUBQH_W_MMR2 }, { Mips::SUBQ_PH, Mips::SUBQ_PH, Mips::SUBQ_PH_MM }, { Mips::SUBQ_S_PH, Mips::SUBQ_S_PH, Mips::SUBQ_S_PH_MM }, { Mips::SUBQ_S_W, Mips::SUBQ_S_W, Mips::SUBQ_S_W_MM }, { Mips::SUBUH_QB, Mips::SUBUH_QB, Mips::SUBUH_QB_MMR2 }, { Mips::SUBUH_R_QB, Mips::SUBUH_R_QB, Mips::SUBUH_R_QB_MMR2 }, { Mips::SUBU_PH, Mips::SUBU_PH, Mips::SUBU_PH_MMR2 }, { Mips::SUBU_QB, Mips::SUBU_QB, Mips::SUBU_QB_MM }, { Mips::SUBU_S_PH, Mips::SUBU_S_PH, Mips::SUBU_S_PH_MMR2 }, { Mips::SUBU_S_QB, Mips::SUBU_S_QB, Mips::SUBU_S_QB_MM }, { Mips::SWDSP, Mips::SWDSP, Mips::SWDSP_MM }, }; // End of Dsp2MicroMipsTable unsigned mid; unsigned start = 0; unsigned end = 160; while (start < end) { mid = start + (end - start) / 2; if (Opcode == Dsp2MicroMipsTable[mid][0]) { break; } if (Opcode < Dsp2MicroMipsTable[mid][0]) end = mid; else start = mid + 1; } if (start == end) return -1; // Instruction doesn't exist in this table. if (inArch == Arch_dsp) return Dsp2MicroMipsTable[mid][1]; if (inArch == Arch_mmdsp) return Dsp2MicroMipsTable[mid][2]; return -1;} // MipsR62MicroMipsR6 LLVM_READONLY int MipsR62MicroMipsR6(uint16_t Opcode, enum Arch inArch) { static const uint16_t MipsR62MicroMipsR6Table[][3] = { { Mips::ADDIUPC, Mips::ADDIUPC, Mips::ADDIUPC_MMR6 }, { Mips::ALIGN, Mips::ALIGN, Mips::ALIGN_MMR6 }, { Mips::ALUIPC, Mips::ALUIPC, Mips::ALUIPC_MMR6 }, { Mips::AUI, Mips::AUI, Mips::AUI_MMR6 }, { Mips::AUIPC, Mips::AUIPC, Mips::AUIPC_MMR6 }, { Mips::BALC, Mips::BALC, Mips::BALC_MMR6 }, { Mips::BC, Mips::BC, Mips::BC_MMR6 }, { Mips::BEQC, Mips::BEQC, Mips::BEQC_MMR6 }, { Mips::BEQZALC, Mips::BEQZALC, Mips::BEQZALC_MMR6 }, { Mips::BEQZC, Mips::BEQZC, Mips::BEQZC_MMR6 }, { Mips::BGEC, Mips::BGEC, Mips::BGEC_MMR6 }, { Mips::BGEUC, Mips::BGEUC, Mips::BGEUC_MMR6 }, { Mips::BGEZALC, Mips::BGEZALC, Mips::BGEZALC_MMR6 }, { Mips::BGEZC, Mips::BGEZC, Mips::BGEZC_MMR6 }, { Mips::BGTZALC, Mips::BGTZALC, Mips::BGTZALC_MMR6 }, { Mips::BGTZC, Mips::BGTZC, Mips::BGTZC_MMR6 }, { Mips::BITSWAP, Mips::BITSWAP, Mips::BITSWAP_MMR6 }, { Mips::BLEZALC, Mips::BLEZALC, Mips::BLEZALC_MMR6 }, { Mips::BLEZC, Mips::BLEZC, Mips::BLEZC_MMR6 }, { Mips::BLTC, Mips::BLTC, Mips::BLTC_MMR6 }, { Mips::BLTUC, Mips::BLTUC, Mips::BLTUC_MMR6 }, { Mips::BLTZALC, Mips::BLTZALC, Mips::BLTZALC_MMR6 }, { Mips::BLTZC, Mips::BLTZC, Mips::BLTZC_MMR6 }, { Mips::BNEC, Mips::BNEC, Mips::BNEC_MMR6 }, { Mips::BNEZALC, Mips::BNEZALC, Mips::BNEZALC_MMR6 }, { Mips::BNEZC, Mips::BNEZC, Mips::BNEZC_MMR6 }, { Mips::BNVC, Mips::BNVC, Mips::BNVC_MMR6 }, { Mips::BOVC, Mips::BOVC, Mips::BOVC_MMR6 }, { Mips::CACHE_R6, Mips::CACHE_R6, Mips::CACHE_MMR6 }, { Mips::CLO_R6, Mips::CLO_R6, Mips::CLO_MMR6 }, { Mips::CLZ_R6, Mips::CLZ_R6, Mips::CLZ_MMR6 }, { Mips::CMP_EQ_D, Mips::CMP_EQ_D, Mips::CMP_EQ_D_MMR6 }, { Mips::CMP_EQ_S, Mips::CMP_EQ_S, Mips::CMP_EQ_S_MMR6 }, { Mips::CMP_F_D, Mips::CMP_F_D, Mips::CMP_AF_D_MMR6 }, { Mips::CMP_F_S, Mips::CMP_F_S, Mips::CMP_AF_S_MMR6 }, { Mips::CMP_LE_D, Mips::CMP_LE_D, Mips::CMP_LE_D_MMR6 }, { Mips::CMP_LE_S, Mips::CMP_LE_S, Mips::CMP_LE_S_MMR6 }, { Mips::CMP_LT_D, Mips::CMP_LT_D, Mips::CMP_LT_D_MMR6 }, { Mips::CMP_LT_S, Mips::CMP_LT_S, Mips::CMP_LT_S_MMR6 }, { Mips::CMP_SAF_D, Mips::CMP_SAF_D, Mips::CMP_SAF_D_MMR6 }, { Mips::CMP_SAF_S, Mips::CMP_SAF_S, Mips::CMP_SAF_S_MMR6 }, { Mips::CMP_SEQ_D, Mips::CMP_SEQ_D, Mips::CMP_SEQ_D_MMR6 }, { Mips::CMP_SEQ_S, Mips::CMP_SEQ_S, Mips::CMP_SEQ_S_MMR6 }, { Mips::CMP_SLE_D, Mips::CMP_SLE_D, Mips::CMP_SLE_D_MMR6 }, { Mips::CMP_SLE_S, Mips::CMP_SLE_S, Mips::CMP_SLE_S_MMR6 }, { Mips::CMP_SLT_D, Mips::CMP_SLT_D, Mips::CMP_SLT_D_MMR6 }, { Mips::CMP_SLT_S, Mips::CMP_SLT_S, Mips::CMP_SLT_S_MMR6 }, { Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D_MMR6 }, { Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S_MMR6 }, { Mips::CMP_SULE_D, Mips::CMP_SULE_D, Mips::CMP_SULE_D_MMR6 }, { Mips::CMP_SULE_S, Mips::CMP_SULE_S, Mips::CMP_SULE_S_MMR6 }, { Mips::CMP_SULT_D, Mips::CMP_SULT_D, Mips::CMP_SULT_D_MMR6 }, { Mips::CMP_SULT_S, Mips::CMP_SULT_S, Mips::CMP_SULT_S_MMR6 }, { Mips::CMP_SUN_D, Mips::CMP_SUN_D, Mips::CMP_SUN_D_MMR6 }, { Mips::CMP_SUN_S, Mips::CMP_SUN_S, Mips::CMP_SUN_S_MMR6 }, { Mips::CMP_UEQ_D, Mips::CMP_UEQ_D, Mips::CMP_UEQ_D_MMR6 }, { Mips::CMP_UEQ_S, Mips::CMP_UEQ_S, Mips::CMP_UEQ_S_MMR6 }, { Mips::CMP_ULE_D, Mips::CMP_ULE_D, Mips::CMP_ULE_D_MMR6 }, { Mips::CMP_ULE_S, Mips::CMP_ULE_S, Mips::CMP_ULE_S_MMR6 }, { Mips::CMP_ULT_D, Mips::CMP_ULT_D, Mips::CMP_ULT_D_MMR6 }, { Mips::CMP_ULT_S, Mips::CMP_ULT_S, Mips::CMP_ULT_S_MMR6 }, { Mips::CMP_UN_D, Mips::CMP_UN_D, Mips::CMP_UN_D_MMR6 }, { Mips::CMP_UN_S, Mips::CMP_UN_S, Mips::CMP_UN_S_MMR6 }, { Mips::CRC32B, Mips::CRC32B, (uint16_t)-1U }, { Mips::CRC32CB, Mips::CRC32CB, (uint16_t)-1U }, { Mips::CRC32CD, Mips::CRC32CD, (uint16_t)-1U }, { Mips::CRC32CH, Mips::CRC32CH, (uint16_t)-1U }, { Mips::CRC32CW, Mips::CRC32CW, (uint16_t)-1U }, { Mips::CRC32D, Mips::CRC32D, (uint16_t)-1U }, { Mips::CRC32H, Mips::CRC32H, (uint16_t)-1U }, { Mips::CRC32W, Mips::CRC32W, (uint16_t)-1U }, { Mips::DIV, Mips::DIV, Mips::DIV_MMR6 }, { Mips::DIVU, Mips::DIVU, Mips::DIVU_MMR6 }, { Mips::DVP, Mips::DVP, Mips::DVP_MMR6 }, { Mips::EVP, Mips::EVP, Mips::EVP_MMR6 }, { Mips::GINVI, Mips::GINVI, Mips::GINVI_MMR6 }, { Mips::GINVT, Mips::GINVT, Mips::GINVT_MMR6 }, { Mips::JIALC, Mips::JIALC, Mips::JIALC_MMR6 }, { Mips::JIC, Mips::JIC, Mips::JIC_MMR6 }, { Mips::LSA_R6, Mips::LSA_R6, Mips::LSA_MMR6 }, { Mips::LWPC, Mips::LWPC, Mips::LWPC_MMR6 }, { Mips::MOD, Mips::MOD, Mips::MOD_MMR6 }, { Mips::MODU, Mips::MODU, Mips::MODU_MMR6 }, { Mips::MUH, Mips::MUH, Mips::MUH_MMR6 }, { Mips::MUHU, Mips::MUHU, Mips::MUHU_MMR6 }, { Mips::MULU, Mips::MULU, Mips::MULU_MMR6 }, { Mips::MUL_R6, Mips::MUL_R6, Mips::MUL_MMR6 }, { Mips::PREF_R6, Mips::PREF_R6, Mips::PREF_MMR6 }, { Mips::SELEQZ, Mips::SELEQZ, Mips::SELEQZ_MMR6 }, { Mips::SELEQZ_D, Mips::SELEQZ_D, Mips::SELEQZ_D_MMR6 }, { Mips::SELEQZ_S, Mips::SELEQZ_S, Mips::SELEQZ_S_MMR6 }, { Mips::SELNEZ, Mips::SELNEZ, Mips::SELNEZ_MMR6 }, { Mips::SELNEZ_D, Mips::SELNEZ_D, Mips::SELNEZ_D_MMR6 }, { Mips::SELNEZ_S, Mips::SELNEZ_S, Mips::SELNEZ_S_MMR6 }, { Mips::SEL_D, Mips::SEL_D, Mips::SEL_D_MMR6 }, { Mips::SEL_S, Mips::SEL_S, Mips::SEL_S_MMR6 }, }; // End of MipsR62MicroMipsR6Table unsigned mid; unsigned start = 0; unsigned end = 96; while (start < end) { mid = start + (end - start) / 2; if (Opcode == MipsR62MicroMipsR6Table[mid][0]) { break; } if (Opcode < MipsR62MicroMipsR6Table[mid][0]) end = mid; else start = mid + 1; } if (start == end) return -1; // Instruction doesn't exist in this table. if (inArch == Arch_mipsr6) return MipsR62MicroMipsR6Table[mid][1]; if (inArch == Arch_micromipsr6) return MipsR62MicroMipsR6Table[mid][2]; return -1;} // Std2MicroMips LLVM_READONLY int Std2MicroMips(uint16_t Opcode, enum Arch inArch) { static const uint16_t Std2MicroMipsTable[][3] = { { Mips::ADD, Mips::ADD, Mips::ADD_MM }, { Mips::ADDi, Mips::ADDi, Mips::ADDi_MM }, { Mips::ADDiu, Mips::ADDiu, Mips::ADDiu_MM }, { Mips::ADDu, Mips::ADDu, Mips::ADDu_MM }, { Mips::AND, Mips::AND, Mips::AND_MM }, { Mips::ANDi, Mips::ANDi, Mips::ANDi_MM }, { Mips::BC1F, Mips::BC1F, Mips::BC1F_MM }, { Mips::BC1FL, Mips::BC1FL, (uint16_t)-1U }, { Mips::BC1T, Mips::BC1T, Mips::BC1T_MM }, { Mips::BC1TL, Mips::BC1TL, (uint16_t)-1U }, { Mips::BEQ, Mips::BEQ, Mips::BEQ_MM }, { Mips::BEQL, Mips::BEQL, (uint16_t)-1U }, { Mips::BGEZ, Mips::BGEZ, Mips::BGEZ_MM }, { Mips::BGEZAL, Mips::BGEZAL, Mips::BGEZAL_MM }, { Mips::BGEZALL, Mips::BGEZALL, (uint16_t)-1U }, { Mips::BGEZL, Mips::BGEZL, (uint16_t)-1U }, { Mips::BGTZ, Mips::BGTZ, Mips::BGTZ_MM }, { Mips::BGTZL, Mips::BGTZL, (uint16_t)-1U }, { Mips::BLEZ, Mips::BLEZ, Mips::BLEZ_MM }, { Mips::BLEZL, Mips::BLEZL, (uint16_t)-1U }, { Mips::BLTZ, Mips::BLTZ, Mips::BLTZ_MM }, { Mips::BLTZAL, Mips::BLTZAL, Mips::BLTZAL_MM }, { Mips::BLTZALL, Mips::BLTZALL, (uint16_t)-1U }, { Mips::BLTZL, Mips::BLTZL, (uint16_t)-1U }, { Mips::BNE, Mips::BNE, Mips::BNE_MM }, { Mips::BNEL, Mips::BNEL, (uint16_t)-1U }, { Mips::BREAK, Mips::BREAK, Mips::BREAK_MM }, { Mips::CACHE, Mips::CACHE, Mips::CACHE_MM }, { Mips::CACHEE, Mips::CACHEE, Mips::CACHEE_MM }, { Mips::CEIL_W_D32, Mips::CEIL_W_D32, Mips::CEIL_W_MM }, { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MM }, { Mips::CFC1, Mips::CFC1, Mips::CFC1_MM }, { Mips::CLO, Mips::CLO, Mips::CLO_MM }, { Mips::CLZ, Mips::CLZ, Mips::CLZ_MM }, { Mips::CTC1, Mips::CTC1, Mips::CTC1_MM }, { Mips::CVT_D32_S, Mips::CVT_D32_S, Mips::CVT_D32_S_MM }, { Mips::CVT_D32_W, Mips::CVT_D32_W, Mips::CVT_D32_W_MM }, { Mips::CVT_L_D64, Mips::CVT_L_D64, Mips::CVT_L_D64_MM }, { Mips::CVT_L_S, Mips::CVT_L_S, Mips::CVT_L_S_MM }, { Mips::CVT_S_D32, Mips::CVT_S_D32, Mips::CVT_S_D32_MM }, { Mips::CVT_S_W, Mips::CVT_S_W, Mips::CVT_S_W_MM }, { Mips::CVT_W_D32, Mips::CVT_W_D32, Mips::CVT_W_D32_MM }, { Mips::CVT_W_S, Mips::CVT_W_S, Mips::CVT_W_S_MM }, { Mips::C_EQ_D32, Mips::C_EQ_D32, Mips::C_EQ_D32_MM }, { Mips::C_EQ_D64, Mips::C_EQ_D64, Mips::C_EQ_D64_MM }, { Mips::C_EQ_S, Mips::C_EQ_S, Mips::C_EQ_S_MM }, { Mips::C_F_D32, Mips::C_F_D32, Mips::C_F_D32_MM }, { Mips::C_F_D64, Mips::C_F_D64, Mips::C_F_D64_MM }, { Mips::C_F_S, Mips::C_F_S, Mips::C_F_S_MM }, { Mips::C_LE_D32, Mips::C_LE_D32, Mips::C_LE_D32_MM }, { Mips::C_LE_D64, Mips::C_LE_D64, Mips::C_LE_D64_MM }, { Mips::C_LE_S, Mips::C_LE_S, Mips::C_LE_S_MM }, { Mips::C_LT_D32, Mips::C_LT_D32, Mips::C_LT_D32_MM }, { Mips::C_LT_D64, Mips::C_LT_D64, Mips::C_LT_D64_MM }, { Mips::C_LT_S, Mips::C_LT_S, Mips::C_LT_S_MM }, { Mips::C_NGE_D32, Mips::C_NGE_D32, Mips::C_NGE_D32_MM }, { Mips::C_NGE_D64, Mips::C_NGE_D64, Mips::C_NGE_D64_MM }, { Mips::C_NGE_S, Mips::C_NGE_S, Mips::C_NGE_S_MM }, { Mips::C_NGLE_D32, Mips::C_NGLE_D32, Mips::C_NGLE_D32_MM }, { Mips::C_NGLE_D64, Mips::C_NGLE_D64, Mips::C_NGLE_D64_MM }, { Mips::C_NGLE_S, Mips::C_NGLE_S, Mips::C_NGLE_S_MM }, { Mips::C_NGL_D32, Mips::C_NGL_D32, Mips::C_NGL_D32_MM }, { Mips::C_NGL_D64, Mips::C_NGL_D64, Mips::C_NGL_D64_MM }, { Mips::C_NGL_S, Mips::C_NGL_S, Mips::C_NGL_S_MM }, { Mips::C_NGT_D32, Mips::C_NGT_D32, Mips::C_NGT_D32_MM }, { Mips::C_NGT_D64, Mips::C_NGT_D64, Mips::C_NGT_D64_MM }, { Mips::C_NGT_S, Mips::C_NGT_S, Mips::C_NGT_S_MM }, { Mips::C_OLE_D32, Mips::C_OLE_D32, Mips::C_OLE_D32_MM }, { Mips::C_OLE_D64, Mips::C_OLE_D64, Mips::C_OLE_D64_MM }, { Mips::C_OLE_S, Mips::C_OLE_S, Mips::C_OLE_S_MM }, { Mips::C_OLT_D32, Mips::C_OLT_D32, Mips::C_OLT_D32_MM }, { Mips::C_OLT_D64, Mips::C_OLT_D64, Mips::C_OLT_D64_MM }, { Mips::C_OLT_S, Mips::C_OLT_S, Mips::C_OLT_S_MM }, { Mips::C_SEQ_D32, Mips::C_SEQ_D32, Mips::C_SEQ_D32_MM }, { Mips::C_SEQ_D64, Mips::C_SEQ_D64, Mips::C_SEQ_D64_MM }, { Mips::C_SEQ_S, Mips::C_SEQ_S, Mips::C_SEQ_S_MM }, { Mips::C_SF_D32, Mips::C_SF_D32, Mips::C_SF_D32_MM }, { Mips::C_SF_D64, Mips::C_SF_D64, Mips::C_SF_D64_MM }, { Mips::C_SF_S, Mips::C_SF_S, Mips::C_SF_S_MM }, { Mips::C_UEQ_D32, Mips::C_UEQ_D32, Mips::C_UEQ_D32_MM }, { Mips::C_UEQ_D64, Mips::C_UEQ_D64, Mips::C_UEQ_D64_MM }, { Mips::C_UEQ_S, Mips::C_UEQ_S, Mips::C_UEQ_S_MM }, { Mips::C_ULE_D32, Mips::C_ULE_D32, Mips::C_ULE_D32_MM }, { Mips::C_ULE_D64, Mips::C_ULE_D64, Mips::C_ULE_D64_MM }, { Mips::C_ULE_S, Mips::C_ULE_S, Mips::C_ULE_S_MM }, { Mips::C_ULT_D32, Mips::C_ULT_D32, Mips::C_ULT_D32_MM }, { Mips::C_ULT_D64, Mips::C_ULT_D64, Mips::C_ULT_D64_MM }, { Mips::C_ULT_S, Mips::C_ULT_S, Mips::C_ULT_S_MM }, { Mips::C_UN_D32, Mips::C_UN_D32, Mips::C_UN_D32_MM }, { Mips::C_UN_D64, Mips::C_UN_D64, Mips::C_UN_D64_MM }, { Mips::C_UN_S, Mips::C_UN_S, Mips::C_UN_S_MM }, { Mips::DERET, Mips::DERET, Mips::DERET_MM }, { Mips::DI, Mips::DI, Mips::DI_MM }, { Mips::EHB, Mips::EHB, Mips::EHB_MM }, { Mips::EI, Mips::EI, Mips::EI_MM }, { Mips::ERET, Mips::ERET, Mips::ERET_MM }, { Mips::ERETNC, Mips::ERETNC, (uint16_t)-1U }, { Mips::EXT, Mips::EXT, Mips::EXT_MM }, { Mips::FABS_D32, Mips::FABS_D32, Mips::FABS_D32_MM }, { Mips::FABS_S, Mips::FABS_S, Mips::FABS_S_MM }, { Mips::FADD_D32, Mips::FADD_D32, Mips::FADD_D32_MM }, { Mips::FADD_S, Mips::FADD_S, Mips::FADD_S_MM }, { Mips::FCMP_D32, Mips::FCMP_D32, Mips::FCMP_D32_MM }, { Mips::FCMP_S32, Mips::FCMP_S32, Mips::FCMP_S32_MM }, { Mips::FDIV_D32, Mips::FDIV_D32, Mips::FDIV_D32_MM }, { Mips::FDIV_S, Mips::FDIV_S, Mips::FDIV_S_MM }, { Mips::FLOOR_W_D32, Mips::FLOOR_W_D32, Mips::FLOOR_W_MM }, { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MM }, { Mips::FMOV_D32, Mips::FMOV_D32, Mips::FMOV_D32_MM }, { Mips::FMOV_S, Mips::FMOV_S, Mips::FMOV_S_MM }, { Mips::FMUL_D32, Mips::FMUL_D32, Mips::FMUL_D32_MM }, { Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM }, { Mips::FNEG_D32, Mips::FNEG_D32, Mips::FNEG_D32_MM }, { Mips::FNEG_S, Mips::FNEG_S, Mips::FNEG_S_MM }, { Mips::FSQRT_D32, Mips::FSQRT_D32, Mips::FSQRT_D32_MM }, { Mips::FSQRT_S, Mips::FSQRT_S, Mips::FSQRT_S_MM }, { Mips::FSUB_D32, Mips::FSUB_D32, Mips::FSUB_D32_MM }, { Mips::FSUB_S, Mips::FSUB_S, Mips::FSUB_S_MM }, { Mips::HYPCALL, Mips::HYPCALL, Mips::HYPCALL_MM }, { Mips::INS, Mips::INS, Mips::INS_MM }, { Mips::J, Mips::J, Mips::J_MM }, { Mips::JAL, Mips::JAL, Mips::JAL_MM }, { Mips::JALX, Mips::JALX, Mips::JALX_MM }, { Mips::JR, Mips::JR, Mips::JR_MM }, { Mips::LB, Mips::LB, Mips::LB_MM }, { Mips::LBE, Mips::LBE, Mips::LBE_MM }, { Mips::LBu, Mips::LBu, Mips::LBu_MM }, { Mips::LBuE, Mips::LBuE, Mips::LBuE_MM }, { Mips::LDC1, Mips::LDC1, Mips::LDC1_MM_D32 }, { Mips::LEA_ADDiu, Mips::LEA_ADDiu, Mips::LEA_ADDiu_MM }, { Mips::LH, Mips::LH, Mips::LH_MM }, { Mips::LHE, Mips::LHE, Mips::LHE_MM }, { Mips::LHu, Mips::LHu, Mips::LHu_MM }, { Mips::LHuE, Mips::LHuE, Mips::LHuE_MM }, { Mips::LLE, Mips::LLE, Mips::LLE_MM }, { Mips::LUXC1, Mips::LUXC1, Mips::LUXC1_MM }, { Mips::LUi, Mips::LUi, Mips::LUi_MM }, { Mips::LW, Mips::LW, Mips::LW_MM }, { Mips::LWC1, Mips::LWC1, Mips::LWC1_MM }, { Mips::LWE, Mips::LWE, Mips::LWE_MM }, { Mips::LWL, Mips::LWL, Mips::LWL_MM }, { Mips::LWLE, Mips::LWLE, Mips::LWLE_MM }, { Mips::LWR, Mips::LWR, Mips::LWR_MM }, { Mips::LWRE, Mips::LWRE, Mips::LWRE_MM }, { Mips::LWXC1, Mips::LWXC1, Mips::LWXC1_MM }, { Mips::LWu, Mips::LWu, Mips::LWU_MM }, { Mips::MADD, Mips::MADD, Mips::MADD_MM }, { Mips::MADDU, Mips::MADDU, Mips::MADDU_MM }, { Mips::MADD_D32, Mips::MADD_D32, Mips::MADD_D32_MM }, { Mips::MADD_S, Mips::MADD_S, Mips::MADD_S_MM }, { Mips::MFC1, Mips::MFC1, Mips::MFC1_MM }, { Mips::MFGC0, Mips::MFGC0, Mips::MFGC0_MM }, { Mips::MFHC1_D32, Mips::MFHC1_D32, Mips::MFHC1_D32_MM }, { Mips::MFHGC0, Mips::MFHGC0, Mips::MFHGC0_MM }, { Mips::MFHI, Mips::MFHI, Mips::MFHI_MM }, { Mips::MFLO, Mips::MFLO, Mips::MFLO_MM }, { Mips::MOVF_D32, Mips::MOVF_D32, Mips::MOVF_D32_MM }, { Mips::MOVF_I, Mips::MOVF_I, Mips::MOVF_I_MM }, { Mips::MOVF_S, Mips::MOVF_S, Mips::MOVF_S_MM }, { Mips::MOVN_I_D32, Mips::MOVN_I_D32, Mips::MOVN_I_D32_MM }, { Mips::MOVN_I_I, Mips::MOVN_I_I, Mips::MOVN_I_MM }, { Mips::MOVN_I_S, Mips::MOVN_I_S, Mips::MOVN_I_S_MM }, { Mips::MOVT_D32, Mips::MOVT_D32, Mips::MOVT_D32_MM }, { Mips::MOVT_I, Mips::MOVT_I, Mips::MOVT_I_MM }, { Mips::MOVT_S, Mips::MOVT_S, Mips::MOVT_S_MM }, { Mips::MOVZ_I_D32, Mips::MOVZ_I_D32, Mips::MOVZ_I_D32_MM }, { Mips::MOVZ_I_I, Mips::MOVZ_I_I, Mips::MOVZ_I_MM }, { Mips::MOVZ_I_S, Mips::MOVZ_I_S, Mips::MOVZ_I_S_MM }, { Mips::MSUB, Mips::MSUB, Mips::MSUB_MM }, { Mips::MSUBU, Mips::MSUBU, Mips::MSUBU_MM }, { Mips::MSUB_D32, Mips::MSUB_D32, Mips::MSUB_D32_MM }, { Mips::MSUB_S, Mips::MSUB_S, Mips::MSUB_S_MM }, { Mips::MTC1, Mips::MTC1, Mips::MTC1_MM }, { Mips::MTGC0, Mips::MTGC0, Mips::MTGC0_MM }, { Mips::MTHC1_D32, Mips::MTHC1_D32, Mips::MTHC1_D32_MM }, { Mips::MTHGC0, Mips::MTHGC0, Mips::MTHGC0_MM }, { Mips::MTHI, Mips::MTHI, Mips::MTHI_MM }, { Mips::MTLO, Mips::MTLO, Mips::MTLO_MM }, { Mips::MUL, Mips::MUL, Mips::MUL_MM }, { Mips::MULT, Mips::MULT, Mips::MULT_MM }, { Mips::MULTu, Mips::MULTu, Mips::MULTu_MM }, { Mips::NMADD_D32, Mips::NMADD_D32, Mips::NMADD_D32_MM }, { Mips::NMADD_S, Mips::NMADD_S, Mips::NMADD_S_MM }, { Mips::NMSUB_D32, Mips::NMSUB_D32, Mips::NMSUB_D32_MM }, { Mips::NMSUB_S, Mips::NMSUB_S, Mips::NMSUB_S_MM }, { Mips::NOR, Mips::NOR, Mips::NOR_MM }, { Mips::OR, Mips::OR, Mips::OR_MM }, { Mips::ORi, Mips::ORi, Mips::ORi_MM }, { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MM }, { Mips::PREF, Mips::PREF, Mips::PREF_MM }, { Mips::PREFE, Mips::PREFE, Mips::PREFE_MM }, { Mips::RDHWR, Mips::RDHWR, Mips::RDHWR_MM }, { Mips::RECIP_D32, Mips::RECIP_D32, Mips::RECIP_D32_MM }, { Mips::RECIP_D64, Mips::RECIP_D64, Mips::RECIP_D64_MM }, { Mips::RECIP_S, Mips::RECIP_S, Mips::RECIP_S_MM }, { Mips::ROTR, Mips::ROTR, Mips::ROTR_MM }, { Mips::ROTRV, Mips::ROTRV, Mips::ROTRV_MM }, { Mips::ROUND_W_D32, Mips::ROUND_W_D32, Mips::ROUND_W_MM }, { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MM }, { Mips::RSQRT_D32, Mips::RSQRT_D32, Mips::RSQRT_D32_MM }, { Mips::RSQRT_D64, Mips::RSQRT_D64, Mips::RSQRT_D64_MM }, { Mips::RSQRT_S, Mips::RSQRT_S, Mips::RSQRT_S_MM }, { Mips::SB, Mips::SB, Mips::SB_MM }, { Mips::SBE, Mips::SBE, Mips::SBE_MM }, { Mips::SCE, Mips::SCE, Mips::SCE_MM }, { Mips::SDBBP, Mips::SDBBP, Mips::SDBBP_MM }, { Mips::SDC1, Mips::SDC1, (uint16_t)-1U }, { Mips::SDIV, Mips::SDIV, Mips::SDIV_MM }, { Mips::SEB, Mips::SEB, Mips::SEB_MM }, { Mips::SEH, Mips::SEH, Mips::SEH_MM }, { Mips::SH, Mips::SH, Mips::SH_MM }, { Mips::SHE, Mips::SHE, Mips::SHE_MM }, { Mips::SLL, Mips::SLL, Mips::SLL_MM }, { Mips::SLLV, Mips::SLLV, Mips::SLLV_MM }, { Mips::SLT, Mips::SLT, Mips::SLT_MM }, { Mips::SLTi, Mips::SLTi, Mips::SLTi_MM }, { Mips::SLTiu, Mips::SLTiu, Mips::SLTiu_MM }, { Mips::SLTu, Mips::SLTu, Mips::SLTu_MM }, { Mips::SRA, Mips::SRA, Mips::SRA_MM }, { Mips::SRAV, Mips::SRAV, Mips::SRAV_MM }, { Mips::SRL, Mips::SRL, Mips::SRL_MM }, { Mips::SRLV, Mips::SRLV, Mips::SRLV_MM }, { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MM }, { Mips::SUB, Mips::SUB, Mips::SUB_MM }, { Mips::SUBu, Mips::SUBu, Mips::SUBu_MM }, { Mips::SUXC1, Mips::SUXC1, Mips::SUXC1_MM }, { Mips::SW, Mips::SW, Mips::SW_MM }, { Mips::SWC1, Mips::SWC1, Mips::SWC1_MM }, { Mips::SWE, Mips::SWE, Mips::SWE_MM }, { Mips::SWL, Mips::SWL, Mips::SWL_MM }, { Mips::SWLE, Mips::SWLE, Mips::SWLE_MM }, { Mips::SWR, Mips::SWR, Mips::SWR_MM }, { Mips::SWRE, Mips::SWRE, Mips::SWRE_MM }, { Mips::SWXC1, Mips::SWXC1, Mips::SWXC1_MM }, { Mips::SYNC, Mips::SYNC, Mips::SYNC_MM }, { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MM }, { Mips::SYSCALL, Mips::SYSCALL, Mips::SYSCALL_MM }, { Mips::TEQ, Mips::TEQ, Mips::TEQ_MM }, { Mips::TEQI, Mips::TEQI, Mips::TEQI_MM }, { Mips::TGE, Mips::TGE, Mips::TGE_MM }, { Mips::TGEI, Mips::TGEI, Mips::TGEI_MM }, { Mips::TGEIU, Mips::TGEIU, Mips::TGEIU_MM }, { Mips::TGEU, Mips::TGEU, Mips::TGEU_MM }, { Mips::TLBGINV, Mips::TLBGINV, Mips::TLBGINV_MM }, { Mips::TLBGINVF, Mips::TLBGINVF, Mips::TLBGINVF_MM }, { Mips::TLBGP, Mips::TLBGP, Mips::TLBGP_MM }, { Mips::TLBGR, Mips::TLBGR, Mips::TLBGR_MM }, { Mips::TLBGWI, Mips::TLBGWI, Mips::TLBGWI_MM }, { Mips::TLBGWR, Mips::TLBGWR, Mips::TLBGWR_MM }, { Mips::TLBP, Mips::TLBP, Mips::TLBP_MM }, { Mips::TLBR, Mips::TLBR, Mips::TLBR_MM }, { Mips::TLBWI, Mips::TLBWI, Mips::TLBWI_MM }, { Mips::TLBWR, Mips::TLBWR, Mips::TLBWR_MM }, { Mips::TLT, Mips::TLT, Mips::TLT_MM }, { Mips::TLTI, Mips::TLTI, Mips::TLTI_MM }, { Mips::TLTU, Mips::TLTU, Mips::TLTU_MM }, { Mips::TNE, Mips::TNE, Mips::TNE_MM }, { Mips::TNEI, Mips::TNEI, Mips::TNEI_MM }, { Mips::TRUNC_W_D32, Mips::TRUNC_W_D32, Mips::TRUNC_W_MM }, { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MM }, { Mips::TTLTIU, Mips::TTLTIU, Mips::TLTIU_MM }, { Mips::UDIV, Mips::UDIV, Mips::UDIV_MM }, { Mips::WAIT, Mips::WAIT, Mips::WAIT_MM }, { Mips::WSBH, Mips::WSBH, Mips::WSBH_MM }, { Mips::XOR, Mips::XOR, Mips::XOR_MM }, { Mips::XORi, Mips::XORi, Mips::XORi_MM }, }; // End of Std2MicroMipsTable unsigned mid; unsigned start = 0; unsigned end = 266; while (start < end) { mid = start + (end - start) / 2; if (Opcode == Std2MicroMipsTable[mid][0]) { break; } if (Opcode < Std2MicroMipsTable[mid][0]) end = mid; else start = mid + 1; } if (start == end) return -1; // Instruction doesn't exist in this table. if (inArch == Arch_se) return Std2MicroMipsTable[mid][1]; if (inArch == Arch_micromips) return Std2MicroMipsTable[mid][2]; return -1;} // Std2MicroMipsR6 LLVM_READONLY int Std2MicroMipsR6(uint16_t Opcode, enum Arch inArch) { static const uint16_t Std2MicroMipsR6Table[][3] = { { Mips::ADD, Mips::ADD, Mips::ADD_MMR6 }, { Mips::ADDiu, Mips::ADDiu, Mips::ADDIU_MMR6 }, { Mips::ADDu, Mips::ADDu, Mips::ADDU_MMR6 }, { Mips::AND, Mips::AND, Mips::AND_MMR6 }, { Mips::ANDi, Mips::ANDi, Mips::ANDI_MMR6 }, { Mips::BREAK, Mips::BREAK, Mips::BREAK_MMR6 }, { Mips::CEIL_W_D64, Mips::CEIL_W_D64, Mips::CEIL_W_D_MMR6 }, { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MMR6 }, { Mips::CVT_W_D64, Mips::CVT_W_D64, (uint16_t)-1U }, { Mips::DI, Mips::DI, Mips::DI_MMR6 }, { Mips::EI, Mips::EI, Mips::EI_MMR6 }, { Mips::EXT, Mips::EXT, Mips::EXT_MMR6 }, { Mips::FABS_D64, Mips::FABS_D64, (uint16_t)-1U }, { Mips::FLOOR_W_D64, Mips::FLOOR_W_D64, Mips::FLOOR_W_D_MMR6 }, { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MMR6 }, { Mips::FMOV_D64, Mips::FMOV_D64, Mips::FMOV_D_MMR6 }, { Mips::FNEG_D64, Mips::FNEG_D64, (uint16_t)-1U }, { Mips::FSQRT_D64, Mips::FSQRT_D64, (uint16_t)-1U }, { Mips::FSQRT_S, Mips::FSQRT_S, (uint16_t)-1U }, { Mips::INS, Mips::INS, Mips::INS_MMR6 }, { Mips::LDC1, Mips::LDC1, (uint16_t)-1U }, { Mips::LDC164, Mips::LDC164, Mips::LDC1_D64_MMR6 }, { Mips::LDC2, Mips::LDC2, Mips::LDC2_MMR6 }, { Mips::LW, Mips::LW, Mips::LW_MMR6 }, { Mips::LWC2, Mips::LWC2, Mips::LWC2_MMR6 }, { Mips::MFC1, Mips::MFC1, Mips::MFC1_MMR6 }, { Mips::MTC1, Mips::MTC1, Mips::MTC1_MMR6 }, { Mips::MTHC1_D32, Mips::MTHC1_D32, (uint16_t)-1U }, { Mips::NOR, Mips::NOR, Mips::NOR_MMR6 }, { Mips::OR, Mips::OR, Mips::OR_MMR6 }, { Mips::ORi, Mips::ORi, Mips::ORI_MMR6 }, { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MMR6 }, { Mips::ROUND_W_D64, Mips::ROUND_W_D64, Mips::ROUND_W_D_MMR6 }, { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MMR6 }, { Mips::SB, Mips::SB, Mips::SB_MMR6 }, { Mips::SDC164, Mips::SDC164, Mips::SDC1_D64_MMR6 }, { Mips::SDC2, Mips::SDC2, Mips::SDC2_MMR6 }, { Mips::SEB, Mips::SEB, (uint16_t)-1U }, { Mips::SEH, Mips::SEH, (uint16_t)-1U }, { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MMR6 }, { Mips::SUB, Mips::SUB, Mips::SUB_MMR6 }, { Mips::SUBu, Mips::SUBu, Mips::SUBU_MMR6 }, { Mips::SW, Mips::SW, Mips::SW_MMR6 }, { Mips::SWC2, Mips::SWC2, Mips::SWC2_MMR6 }, { Mips::SYNC, Mips::SYNC, Mips::SYNC_MMR6 }, { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MMR6 }, { Mips::TRUNC_W_D64, Mips::TRUNC_W_D64, Mips::TRUNC_W_D_MMR6 }, { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MMR6 }, { Mips::WAIT, Mips::WAIT, Mips::WAIT_MMR6 }, { Mips::XOR, Mips::XOR, Mips::XOR_MMR6 }, { Mips::XORi, Mips::XORi, Mips::XORI_MMR6 }, }; // End of Std2MicroMipsR6Table unsigned mid; unsigned start = 0; unsigned end = 51; while (start < end) { mid = start + (end - start) / 2; if (Opcode == Std2MicroMipsR6Table[mid][0]) { break; } if (Opcode < Std2MicroMipsR6Table[mid][0]) end = mid; else start = mid + 1; } if (start == end) return -1; // Instruction doesn't exist in this table. if (inArch == Arch_se) return Std2MicroMipsR6Table[mid][1]; if (inArch == Arch_micromipsr6) return Std2MicroMipsR6Table[mid][2]; return -1;} } // end namespace Mips } // end namespace llvm #endif // GET_INSTRMAP_INFO