# nvram for USI G6 SKU3 module(4390B0) V2.5 2023.11.17
# nvram copied and edited from bcm94390f10ref.txt
# SSID generated using Alberto's boardssid.py script:
#********************SUMMARY********************
#Board Name: bcm94390b0GGmodUSIG6BB
#SSID: 0x0af4
#macmid: 0x0597
#Successfully made SSID entry in sromdefs.tcl.
#Successfully made macmid entry in sromdefs.tcl.
#Successfully made SSID entry in tblssid.py.
#*************************************************
# $ Copyright Broadcom $
#
#
# <<Broadcom-WL-IPTag/Vendor1007>>
#
#
#
NVRAMRev=$Rev: 947350 $
#
#
sromrev=11
boardrev=0x1205
boardtype=0x0af4
boardflags=0x10401001
boardflags2=0x00800000
boardflags3=0x40002900
boardflags4=0x200000
#boardnum=57410
macaddr=00:90:4c:59:70:01
jtag_irw=38

#Regulatory specific
ccode=0
regrev=0

# Board specific
vendid=0x14e4
devid=0x4438
manfid=0x2d0
antswitch=0
pdgain5g=0
pdgain2g=0
aa2g=3
aa5g=3
agbg0=0
agbg1=0
aga0=0
aga1=0
ag6ga0=0
ag6ga1=0
extpagain5g=0
slice/1/extpagain2g=0
rxgains2gelnagaina0=16
rxgains2gtrisoa0=17
rxgains2gtrelnabypa0=1
rxgains5gelnagaina0=15
rxgains5gtrisoa0=17
rxgains5gtrelnabypa0=1
rxgains5gmelnagaina0=15
rxgains5gmtrisoa0=17
rxgains5gmtrelnabypa0=1
rxgains5ghelnagaina0=15
rxgains5ghtrisoa0=17
rxgains5ghtrelnabypa0=1
rxgains2gelnagaina1=16
rxgains2gtrisoa1=17
rxgains2gtrelnabypa1=1
rxgains5gelnagaina1=15
rxgains5gtrisoa1=17
rxgains5gtrelnabypa1=1
rxgains5gmelnagaina1=15
rxgains5gmtrisoa1=17
rxgains5gmtrelnabypa1=1
rxgains5ghelnagaina1=15
rxgains5ghtrisoa1=17
rxgains5ghtrelnabypa1=1

rxgains2gfelossa0=2
rxgains2gfelossa1=2
rxgains5gfelossa0=2
rxgains5gfelossa1=2
rxgains5gmfelossa0=1
rxgains5gmfelossa1=1
rxgains5ghfelossa0=1
rxgains5ghfelossa1=1

rxgains6gelnagaina0=15
rxgains6gtrisoa0=17
rxgains6gtrelnabypa0=1
rxgains6gmelnagaina0=15
rxgains6gmtrisoa0=17
rxgains6gmtrelnabypa0=1
rxgains6ghelnagaina0=15
rxgains6ghtrisoa0=17
rxgains6ghtrelnabypa0=1
rxgains6gfelossa0=1
#rxgains6gbkoffa0=16

rxgains6gelnagaina1=15
rxgains6gtrisoa1=17
rxgains6gtrelnabypa1=1
rxgains6gmelnagaina1=15
rxgains6gmtrisoa1=17
rxgains6gmtrelnabypa1=1
rxgains6ghelnagaina1=15
rxgains6ghtrisoa1=17
rxgains6ghtrelnabypa1=1
rxgains6gfelossa1=1
#rxgains6gbkoffa1=16

#RSSI related for dedicated mode in qdBm (Calibrated on USI 60 pin EVB 2023/10/31)
rssi_cal_freq_grp_2g=0x08,0x01,0x91,0x2a,0x23,0xb3,0xc4
rssi_cal_rev=1
rxgaincal_rssical=1
rssi_delta_2gb0=1,2,2,0,1,2,2,0,0,4,2,1,0,4,2,1
rssi_delta_2gb1=1,2,2,0,1,2,2,0,1,4,2,1,1,4,2,1
rssi_delta_2gb2=1,2,2,0,1,2,2,0,0,4,2,1,0,4,2,1
rssi_delta_2gb3=1,2,2,0,1,2,2,0,1,5,3,1,1,5,3,1
rssi_delta_2gb4=1,2,2,0,1,2,2,0,1,5,3,2,1,5,3,2
rssi_delta_2gb0_fbc=1,1,2,0,1,1,2,0,1,1,2,0,1,1,2,0
rssi_delta_2gb1_fbc=1,1,2,0,1,1,2,0,1,1,2,0,1,1,2,0
rssi_delta_2gb2_fbc=0,1,2,0,0,1,2,0,0,1,2,0,0,1,2,0
rssi_delta_2gb3_fbc=1,1,2,0,1,1,2,0,1,1,2,0,1,1,2,0
rssi_delta_2gb4_fbc=1,2,2,0,1,2,2,0,1,2,2,0,1,2,2,0
rssi_delta_5gl=-10, 1, -6, -5, -10, 1, -6, -5, -10, 1, -6, -5, -10, 1, -6, -5, -13, 1, -8, -6, -13, 1, -8, -6, -13, 1, -8, -6, -13, 1, -8, -6
rssi_delta_5gml=-5, 5, -2, -1, -5, 5, -2, -1, -5, 5, -2, -1, -5, 5, -2, -1, -5, 8, 0, 2, -5, 8, 0, 2, -5, 8, 0, 2, -5, 8, 0, 2
rssi_delta_5gmu=-6, 6, -1, 0, -6, 6, -1, 0, -6, 6, -1, 0, -6, 6, -1, 0, -8, 7, -2, 0, -8, 7, -2, 0, -8, 7, -2, 0, -8, 7, -2, 0
rssi_delta_5gh=-5, 7, 1, 2, -5, 7, 1, 2, -5, 7, 1, 2, -5, 7, 1, 2, -8, 7, -2, 1, -8, 7, -2, 1, -8, 7, -2, 1, -8, 7, -2, 1
rssi_delta_6gb0=-6,8,2,3,-6,8,2,3,-6,8,2,3,-6,8,2,3,-8,8,1,3,-8,8,1,3,-8,8,1,3,-8,8,1,3
rssi_delta_6gb1=-6, 9, 3, 4, -6, 9, 3, 4, -6, 9, 3, 4, -6, 9, 3, 4, -7, 10, 2, 4, -7, 10, 2, 4, -7, 10, 2, 4, -7, 10, 2, 4
rssi_delta_6gb2=-3, 12, 6, 7, -3, 12, 6, 7, -3, 12, 6, 7, -3, 12, 6, 7, -6, 11, 4, 5, -6, 11, 4, 5, -6, 11, 4, 5, -6, 11, 4, 5
rssi_delta_6gb3=-3, 12, 6, 6, -3, 12, 6, 6, -3, 12, 6, 6, -3, 12, 6, 6, -4, 12, 6, 6, -4, 12, 6, 6, -4, 12, 6, 6, -4, 12, 6, 6
rssi_delta_6gb4=0, 13, 9, 8, 0, 13, 9, 8, 0, 13, 9, 8, 0, 13, 9, 8, 3, 16, 11, 11, 3, 16, 11, 11, 3, 16, 11, 11, 3, 16, 11, 11
rssi_delta_6gb5=1, 14, 10, 9, 1, 14, 10, 9, 1, 14, 10, 9, 1, 14, 10, 9, 2, 14, 10, 10, 2, 14, 10, 10, 2, 14, 10, 10, 2, 14, 10, 10
slice/2/rssicorrnorm5g_c0=3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3
slice/2/rssicorrnorm6g_c0=8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8
slice/1/tone_to_pkt_rssi_offset=-4,-4,-4,-4
tone_to_pkt_rssi_offset=-12,-8,-12,-8,-8,-8,-8,-4,-12,-8,-12,-8,-8,-8,-8,-4
tone_to_pkt_rssi_offset_6g=-8,-8,-8,-8,-8,-8,-8,-4,-8,-8,-8,-8,-8,-8,-8,-4
gain_cal_temp=36
slice/1/rxgain_tempcoeff2g_sub=0,0,0,0,0,0,0,0,0,0
rxgain_tempcoeff5gl=0,0
rxgain_tempcoeff5gml=0,0
rxgain_tempcoeff5gmu=0,0
rxgain_tempcoeff5gh=0,0
slice/1/rxgain_tempcoeff2g_sub_elnaoff=0,0,0,0,0,0,0,0,0,0
rxgain_tempcoeff5gl_elnaoff=0,0
rxgain_tempcoeff5gml_elnaoff=0,0
rxgain_tempcoeff5gmu_elnaoff=0,0
rxgain_tempcoeff5gh_elnaoff=0,0

#TSSI Related
low_adc_rate_en=0
slice/1/low_adc_rate_en=0

nocrc=1
otpimagesize=502

xtalfreq=76800

txchain=3
rxchain=3

## --- 11b ANT selection Diversity ---
cck_onecore_tx=1

cckdigfilttype=0

bandcap=6
slice/1/bandcap=1
slice/3/bandcap=1


#FDSS Related
fdss_level_5g=0,0
fdss_level_6g=0,0
slice/1/fdss_level_2g=0,0
slice/1/fdss_profile_2g=7,0,0,16,20,28,36,44,48,169,-500,-590,70,0,-70,590,500,128
slice/1/fdss_profile_11ax_2g=7,0,0,28,56,120,136,200,228,128,-64,-64,-32,0,20,40,40,164,165

paprdis=1
slice/1/paprdis=1

#Tempsense Related
tempthresh=255
tempoffset=32
rawtempsense=0x1ff
phycal_tempdelta=15
temps_period=15
temps_hysteresis=0xf

#olpc
olpc_idx_in_use=1
disable_olpc=1
olpc_thresh5g=40
olpc_anchor5g=40
olpc_anchor6g=40
olpc_thresh6g=40
slice/1/olpc_idx_in_use=1
slice/1/disable_olpc=1
slice/1/olpc_thresh2g=28
slice/1/olpc_anchor2g=28
slice/1/olpc_thresh2g_hi=0x7f7f
# 20231128 Updated on the module socket board
hwolpc_offset_c0=0x00,0x03000101,0x03FF0001,0x04000101,0x02000102
hwolpc_offset6g_c0=0x04010201,0x03FF0000,0x03FF0001,0x02FF0000,0x03000101,0x04000001
hwolpc_offset_c1=0x01,0x02000101,0x02FF0001,0x04000101,0x02FF0001
hwolpc_offset6g_c1=0x05FF0001,0x02000101,0x03000000,0x03000001,0x02FF0100,0x03FF0101
# Disable Idle TSSI for both Aux and Main slice
idletssi_disable=1
disable_tpc=0

### To delay TSSI sampling, in nvram:
tssisampledelayen=1

tssipos2g=1
tssipos5g=0

etssi_inv_gain=420,420,354,354
AvVmid_c0=0,178,0,178,0,179,0,185,0,191
AvVmid_c1=0,180,0,180,0,181,0,186,0,191
AvVmid_6g_c0=0,194,0,199,0,200,0,200,0,202,0,202
AvVmid_6g_c1=0,194,0,200,0,200,0,201,0,205,0,203
slice/1/AvVmid_c0=0,173
slice/1/AvVmid_c1=0,188

pacalver_nvram=0x1
#11/23 Generated with 7 modules on module socket board and optimized by BRCM
#slice/1/pa2ga0=-12,8863,-1090
slice/1/pa2ga0=-12,8735,-1089
slice/1/pa2ga1=-24,8950,-1056
#pa5ga0=96,8410,-1280,103,8469,-1315,89,8308,-1269,91,8305,-1280
#pa5ga1=90,8380,-1304,87,8369,-1327,86,8501,-1284,95,8569,-1290
pa5ga0=96,8282,-1286,103,8469,-1315,89,8372,-1266,91,8369,-1277
pa5ga1=90,8316,-1307,87,8433,-1325,86,8437,-1287,95,8441,-1296
pa6ga0=100,8386,-1271,101,8512,-1283,100,8451,-1258,105,8558,-1271,111,8421,-1276,116,8514,-1292
pa6ga1=82,8251,-1274,81,8279,-1291,71,8231,-1263,76,8387,-1272,78,7997,-1273,76,8174,-1279
# Max power and offsets
slice/1/powoffs2gtna0=0,0,0,0,0,0,0,0,0,0,0,0,0,0
slice/1/powoffs2gtna1=0,0,0,0,0,0,0,0,0,0,0,0,0,0
slice/1/pdoffsetcckma0=5
slice/1/pdoffsetcckma1=5

maxp2ga0=97
maxp2ga1=95
maxp5ga0=90,90,91,91
maxp5ga1=89,90,90,88
maxp6ga0=84,84,86,86,88,88
maxp6ga1=83,83,84,84,84,84
subband5gver=0x4
subband6gver=0x3
paparambwver=3

#11/21 updated on the module socket board
pdoffset40ma0=0x7666
pdoffset80ma0=0x7667
pdoffset160ma0=0x7677
pdoffset40ma1=0x6555
pdoffset80ma1=0x4254
pdoffset160ma1=0x5555
pdoffset6g40ma0=0x777777
pdoffset6g40ma1=0x666667
pdoffset6g80ma0=0x555555
pdoffset6g80ma1=0x774455
pdoffset6g160ma0=0x335544
pdoffset6g160ma1=0x555555

slice/1/pdoffset20mRU_c0=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
slice/1/pdoffset20mRU_c1=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset20mRU_c0=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset20mRU_c1=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset40mRU_c0=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset40mRU_c1=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset80mRUset1_c0=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset80mRUset2_c0=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset80mRUset1_c1=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset80mRUset2_c1=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset6g20mRU_c0=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset6g20mRU_c1=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset6g40mRU_c0=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset6g40mRU_c1=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset6g80mRUset1_c0=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset6g80mRUset2_c0=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset6g80mRUset1_c1=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
pdoffset6g80mRUset2_c1=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0

#2G/5G related PPR params
cckbw202gpo=0x0000
mcsbw202gpo=0xDA975422
dot11agofdmhrbw202gpo=0x7432
ofdmlrbw202gpo=0x3000
mcs1024qam2gpo=0x00
mcsbw205glpo=0xCB975422
mcsbw405glpo=0xFDA99655
mcsbw805glpo=0xDBA88555
mcsbw1605glpo=0xEDBBB888
mcsbw205gmpo=0xBB975422
mcsbw405gmpo=0xCB998655
mcsbw805gmpo=0xBBA99777
mcsbw1605gmpo=0xDDBBBAAA
mcsbw205ghpo=0xA9753200
mcsbw405ghpo=0x99766333
mcsbw805ghpo=0xA9766444
mcsbw1605ghpo=0xB8777554
mcs1024qam5glpo=0x00FF22FF
mcs1024qam5gmpo=0x00EE11DD
mcs1024qam5ghpo=0x00CC11CB
mcs4096qam5glpo=0x33335021
mcs4096qam5gmpo=0x00000000
mcs4096qam5ghpo=0x00000000
mcs8poexp=0
mcs9poexp=0
## For both 2G and 5G
mcs10poexp=0xfff1fff1
mcs11poexp=0xfff1fff1
mcs12poexp=0xffffffff
mcs13poexp=0xffffffff

# 5G power offset per channel for band edge channel
powoffs5g20mtna0=0,0,0,0,0,0,0
powoffs5g20mtna1=0,0,0,0,0,0,0
powoffs5g40mtna0=0,0,0,0,0
powoffs5g40mtna1=0,0,0,0,0
powoffs5g80mtna0=0,0,0,0,0
powoffs5g80mtna1=0,0,0,0,0

## 6G related PPR params
mcsbw206gb1po=0xA8653200
mcsbw406gb1po=0xA9875332
mcsbw806gb1po=0xA9866444
mcsbw1606gb1po=0xBA988555
mcsbw206gb2po=0xA8653200
mcsbw406gb2po=0xA9875332
mcsbw806gb2po=0xA9866444
mcsbw1606gb2po=0xBA988555
mcsbw206gb3po=0xBA875422
mcsbw406gb3po=0xBA976554
mcsbw806gb3po=0xBA988666
mcsbw1606gb3po=0xCCAAA777
mcsbw206gb4po=0xBA875422
mcsbw406gb4po=0xBA976554
mcsbw806gb4po=0xBA988666
mcsbw1606gb4po=0xCCAAA777
mcsbw206gb5po=0xECA97644
mcsbw406gb5po=0xDCBA9776
mcsbw806gb5po=0xDCBBB999
mcsbw1606gb5po=0xDDCCCAAA
mcsbw206gb6po=0xECA97644
mcsbw406gb6po=0xDCBA9776
mcsbw806gb6po=0xDCBBB999
mcsbw1606gb6po=0xDDCCCAAA
mcs1024qam6gb1po=0xCCCCCBBB
mcs1024qam6gb2po=0xCCCCCBBB
mcs1024qam6gb3po=0xDDDDCCBB
mcs1024qam6gb4po=0xDDDDCCBB
mcs1024qam6gb5po=0xFFFFFFFF
mcs1024qam6gb6po=0xFFFFFFFF
mcs4096qam6gb1po=0x00000000
mcs4096qam6gb2po=0x00000000
mcs4096qam6gb3po=0x00000000
mcs4096qam6gb4po=0x00000000
mcs4096qam6gb5po=0x00000000
mcs4096qam6gb6po=0x00000000

## For 6G only
mcs10poexp6g=0x00000000
mcs11poexp6g=0x00000000
mcs12poexp6g=0xffffffff
mcs13poexp6g=0xffffffff

## ULOFDMA Board limit PPRs for 2g20 ##
ruppr2g20bpsk=0x1c718c63,0x070c31c7
ruppr2g20qpsk=0x1c721084,0x071041c7
ruppr2g20qam16=0x1c7294a5,0x071451c7
ruppr2g20qam64=0x1c739ce7,0x071c71c7
ruppr2g20qam256=0x1c76b5ad,0x0734d1c7
ruppr2g20qam1024=0x1c77bdef,0x074511c7
ruppr2g20qam4096=0x1c739ce7,0x071c71c7
## ULOFDMA Board limit PPRs for 5g20 ##
ruppr5g20bpsk=0x08208421,0x02041082
ruppr5g20qpsk=0x08210842,0x02082082
ruppr5g20qam16=0x08218c63,0x020c3082
ruppr5g20qam64=0x082294a5,0x02145082
ruppr5g20qam256=0x0824a529,0x02249082
ruppr5g20qam1024=0x0826b5ad,0x0234d082
ruppr5g20qam4096=0x0827bdef,0x02451082
## ULOFDMA Board limit PPRs for 5g40 ##
ruppr5g40bpsk=0x08318c63,0x030c3082
ruppr5g40qpsk=0x08421084,0x04104082
ruppr5g40qam16=0x085294a5,0x05145082
ruppr5g40qam64=0x08842108,0x08208082
ruppr5g40qam256=0x08b5ad6b,0x0b2cb082
ruppr5g40qam1024=0x08d6b5ad,0x0d34d082
ruppr5g40qam4096=0x0927bdef,0x12492082
## ULOFDMA Board limit PPRs for 5g80 ##
ruppr5g80bpsk=0x10421084,0x04104082
ruppr5g80qpsk=0x10421084,0x04104082
ruppr5g80qam16=0x186318c6,0x06186082
ruppr5g80qam64=0x20842108,0x08208082
ruppr5g80qam256=0x2cb5ad6b,0x0b2cb082
ruppr5g80qam1024=0x38e739ce,0x0e38e082
ruppr5g80qam4096=0x4927bdef,0x12492082
## ULOFDMA Board limit PPRs for 5g160 ##
ruppr5g160bpsk=0x1c739ce7,0x071c7087,0x02082000
ruppr5g160qpsk=0x1c739ce7,0x071c7087,0x02082082
ruppr5g160qam16=0x20842108,0x08208088,0x02082104
ruppr5g160qam64=0x30c6318c,0x0c30c08c,0x02082186
ruppr5g160qam256=0x3cf7bdef,0x0f3cf08f,0x02082208
ruppr5g160qam1024=0x4517bdef,0x11451091,0x0208228a
ruppr5g160qam4096=0x4d37bdef,0x134d3093,0x0208238e
## ULOFDMA Board limit PPRs for 6g20 ##
ruppr6g20bpsk=0x04108421,0x01041041
ruppr6g20qpsk=0x04108421,0x01041041
ruppr6g20qam16=0x04118c63,0x030c3041
ruppr6g20qam64=0x04139ce7,0x071c7041
ruppr6g20qam256=0x0414a529,0x09249041
ruppr6g20qam1024=0x0415294a,0x0a28a041
ruppr6g20qam4096=0x0417bdef,0x10410041
## ULOFDMA Board limit PPRs for 6g40 ##
ruppr6g40bpsk=0x04210842,0x02082041
ruppr6g40qpsk=0x04318c63,0x030c3041
ruppr6g40qam16=0x045294a5,0x05145041
ruppr6g40qam64=0x04739ce7,0x071c7041
ruppr6g40qam256=0x0494a529,0x09249041
ruppr6g40qam1024=0x04c6318c,0x0c30c041
ruppr6g40qam4096=0x0517bdef,0x11451041
## ULOFDMA Board limit PPRs for 6g80 ##
ruppr6g80bpsk=0x0c318c63,0x030c3041
ruppr6g80qpsk=0x145294a5,0x05145041
ruppr6g80qam16=0x1c739ce7,0x071c7041
ruppr6g80qam64=0x28a5294a,0x0a28a041
ruppr6g80qam256=0x30c6318c,0x0c30c041
ruppr6g80qam1024=0x38e739ce,0x0e38e041
ruppr6g80qam4096=0x4927bdef,0x12492041
## ULOFDMA Board limit PPRs for 6g160 ##
ruppr6g160bpsk=0x186318c6,0x06186046,0x01041186
ruppr6g160qpsk=0x1c739ce7,0x071c7047,0x010411c7
ruppr6g160qam16=0x2494a529,0x09249049,0x01041249
ruppr6g160qam64=0x28a5294a,0x0a28a04a,0x0104128a
ruppr6g160qam256=0x30c6318c,0x0c30c04c,0x0104130c
ruppr6g160qam1024=0x38e739ce,0x0e38e04e,0x0104138e
ruppr6g160qam4096=0x4927bdef,0x12492052,0x01041492

#OOB params
#device_wake_opt=1
host_wake_opt=0
# temporarily disable deepsleep health check
ds_hc_enable=0

# SWCTRL Format - TXHEc1TXHEc0(16+16 bits), TXHLc1TXHLc0(16+16 bits),
#        RXHGc1RXHGc0(16+16 bits), RXBYPc1RXBYPc0(16+16 bits), Mask(16 bits)
# SWCTRL Ext Format - TXHEc1TXHEc0(4+4 bits), TXHLc1TXHLc0(4+4 bits), RXHGc1RXHGc0(4+4 bits),
#        RXBYPc1RXBYPc0(4+4 bits), Mask(4 bits)

# 5G Main SWCTRL
swctrlmap_5g=0x00000020,0x00000020,0x00000020,0x00040024,0xFFFF
swctrlmapext_5g=0x11,0x11,0x11,0x00,0xF

# 6G Main SWCTRL
swctrlmap_6g=0x00000020,0x00000020,0x00000020,0x00040024,0xFFFF
swctrlmapext_6g=0x11,0x11,0x11,0x00,0xF

# 2G Aux SWCTRL
slice/1/swctrlmap_2g=0x80008000,0x80008000,0x80008000,0x00010001,0xFFFF
slice/1/swctrlmapext_2g=0x0,0x0,0x0,0x00,0xF

# 5G WL Scan SWCTRL
slice/2/swctrlmap_5g=0x00000000,0x00000000,0x00000020,0x00040024,0xFFFF
slice/2/swctrlmapext_5g=0x11,0x11,0x11,0x00,0xF

# 6G WL Scan SWCTRL
slice/2/swctrlmap_6g=0x00000000,0x00000000,0x00000020,0x00040024,0xFFFF
slice/2/swctrlmapext_6g=0x11,0x11,0x11,0x00,0xF

# 2G WL Scan SWCTRL
slice/2/swctrlmap_2g=0x00000000,0x00000000,0x80008000,0x00010001,0xFFFF
slice/2/swctrlmapext_2g=0x0,0x0,0x0,0x00,0xF

# Init (default) values for FEM Control LUT Entries - 2G, 5G, 6G
fem_table_init_val=0x00010001,0x00040024,0x00040024
fem_table_init_val_ext=0x00,0x00,0x00

# Slice0=WLMain, Slice1=Aux, Slice2=WLScan
clb5gslice0core0=0x10024
clb5gslice0core1=0x10024
clb5gslice2core0=0x10024
clb5gslice2core1=0x10024

clb2gslice1core0=0x08001
clb2gslice1core1=0x08001
clb2gslice2core0=0x08001
clb2gslice2core1=0x08001

# rfem CMAPT
rFEM_hw_mppc_en_2g=1
rFEM_cmapt_swpt_pwr_thresh_qdBm_2g=-128,20
#slice/1/mppc_gaindelta_pa1=44
slice/1/mppc_gaindelta_pa1=42

rFEM_hw_mppc_en_5g=1
rFEM_cmapt_swpt_pwr_thresh_qdBm_5g=-128,12
#mppc_gaindelta_pa0=0,14,14,14,14,16,16,16,16,16,16
#Based on CLPC power delta
mppc_gaindelta_pa0=0,15,17,17,20,24,25,24,27,27,20
mppc_gaindelta_pa1=0,30,30,29,29,30,26,27,26,29,27

# Gen9 5G/6G rFEM States:
# OFFc1_OFFc0_TX1c1_TX1c0, TX2c1_TX2c0_TX4c1_TX4c0, TX5c1_TX5c0_TX10c1_TX10c0,
# RX1c1_RX1c0_RX2Bc1_RX2Bc0, RX2c1_RX2c0_TX3c1_TX3c0, TX7c1_TX7c0_TX8c1_TX8c0,
# IDLEc1_IDLEc0_TEMPc1_TEMPc0, SISOc1_SISOc0_BTNc1_BTNc0, TX6c1_TX6c0_TX9c1_TX9c0
# BRCM rFEM EMLSR - Link0 uses TX1,TX4,TX7 config, Link1 uses TX2,TX5,TX8 config
remoteFEMlut_5g=0x93938181, 0xA0A08484, 0xA1A18A8A, 0x8B8B8D8D, 0x8C8C8383, 0x8484A1A1, 0x8E8E8F8F, 0x90909191, 0x86868989

# Gen9 2G rFEM States:
# OFFc1_OFFc0_TX1c1_TX1c0, 00_00_TX2c1_TX2c0, 00_00_BTTX1c1_BTTX1c0, RXHGc1_RXHGc0_RXHGSCANc1_RXHGSCANc0,
# 00_00_00_00, TX3c1_TX3c0_00_00, 00_00_TEMPc1_TEMPc0, 00_00_BTNc1_BTNc0, 00_00_00_00
remoteFEMlut_2g=0x80808181, 0x00008383, 0x00008787, 0x85858686, 0x00000000, 0x83830000, 0x00008484, 0x00008A8A, 0x00000000

# rFEM Type: 1 = BRCM rFEMs, 2 = BRCM Gen9 rFEMs, 3 = Gen8 Murata/Skyworks rFEMs, 4 = Gen9 Murata/Skyworks rFEMs
rFEM_2G_type=2
rFEM_5G_type=2

# RFFE VIO SWCTRL Number: 5GC1,5GC0,2GC1,2GC0
# 23 is actual line but GCI needs 23+4
# 22 is actual line but GCI needs 22+4
rFEM_VIO_swctrl=27,10,26,9

# Drives strength of core 0,1 rffe pads at attach
rffe_drive_strength_init=0x2

muxenab=1

# [31:24] - rts; [23:16] - cts; [15:8] - Tx; [7:0] - Rx;
fuart_sig2pin_map=0x0b0a0908

###Comment out BT section for initial bringup
#BT Coex
btc_mode=0x1
#btc_params82=0x1a0
# BT shared ant configuration
btc_prisel_ant_mask=0x0
btc_prisel_mask=0x1
clb_swctrl_smask_ant0=0x18025
clb_swctrl_smask_ant1=0x18025

# energy detect threshold
ed_thresh2g=-63
ed_thresh5g=-63
ed_thresh6g=-71,-71
ed_thresh_sec5g=-72
ed_thresh_sec6g=-71,-71
# energy detect threshold for EU
eu_edthresh2g=-59
eu_edthresh5g=-65
eu_edthresh6g=-68,-59
eu_edthresh_sec5g=-64
eu_edthresh_sec6g=-69,-59

#Feature flags
femctrl=17

# FE Loss comp parameters
slice/1/felossTx2ga0=8,8,8,8,8,8,8,8,8,9,9,10,10,10
slice/1/felossTx2ga1=7,7,7,7,7,7,7,7,7,7,7,7,7,7
slice/1/felossRx2ga0=7,7,7,7,4,4,4,4,6,6,9,10,10,10
slice/1/felossRx2ga1=4,4,4,4,4,4,4,4,4,4,6,6,6,6
felossTx5ga0=10,10,11,11
felossTx5ga1=9,10,10,8
felossRx5ga0=12,11,8,11
felossRx5ga1=11,8,4,8
felossTx6ga0=6,6,8,8,10,10
felossTx6ga1=5,5,6,6,6,6
felossRx6ga0=9,11,10,10,13,15
felossRx6ga1=8,8,12,12,10,8
slice/2/felossRx2ga0=0,0,0,0,0,0,0,0,0,0,0,0,0,0
slice/2/felossRx2ga1=0,0,0,0,0,0,0,0,0,0,0,0,0,0
slice/2/felossRx5ga0=0,0,0,0
slice/2/felossRx5ga1=0,0,0,0
slice/2/felossRx6ga0=0,0,0,0,0,0
slice/2/felossRx6ga1=0,0,0,0,0,0

# Spur canceller DTX spurs for some channels in Main slice
txspurcan_en=1
slice/1/txspurcan_en=0

# PAPDcal params
papd_multi_lut_en=0
epacal5g=1

# ABUCK Votage mapping check (BCM4397_switcher_tbls in pmu.tcl)
# 0 --> 0.87V, 1--> 0.88V, 2-->0.89V,..,5-->0.92V.,.., 15 --> 1.02V
# -1 --> 0.86V, -2 --> 0.85V, -3 --> 0.67V, -4 --> 0.66V,.. -16 --> 0.54
abuck_volt=5
slice/1/abuck_volt=5
slice/2/abuck_volt=5
# CBUCK Votage mapping check (BCM4397_switcher_tbls in pmu.tcl)
# 0 --> 0.60V, 1--> 0.61V, 2-->0.62V,...., 15 --> 0.75V, 16 --> 0.76V
# 31 --> 0.59V, 30 --> 0.58V, 29 --> 0.57V, 28 --> 0.56V,.. 22 --> 0.50V
# 21 --> 0.83V, 20 --> 0.81V, 19 --> 0.79V, 18 --> 0.78V, 17 --> 0.77V
#cbuck_volt=21

##Dynamic SAR related Params
dynsar_fcc_rev=0xFF

###LPC EPABYPASS MODE
lpc_epabypass_en=1
lpc_epabypass_maxpwr=-10
lpc_epagain=60

#LESI desense
lesi_desoffset=49,48,48
lesi_desoffset_20MHzextra=1,1,1

#scan5g elnabyp
slice/2/scan_ebyp_ncc=1

#tvpm params
tvpm=1
slice/1/tvpm=1
tvpm_dc_cltm=100,100,90,90,80,80,70,70,60,60,50,50,40,40,30,30,20,20,1,1

## List of duty cycle temperature thresholds in descending order (num = 3)
tvpm_dc_temp_threshold=110,105,100
slice/1/tvpm_dc_temp_threshold=110,105,100

# 5G K values for 11AZ Update on 20240506
az_offset_perbw=0,0,0,0,0
az_160mkval=13737,14382
az_80mkval=12621,11747,12891,12307,12541,12500
az_40mkval=18345,17772,17749,17042,18066,18821,18682,17671,18330,17408,17483,17593
az_20mkval=47443,47052,46332,46341,45992,46793,45675,46296,47196,47288,47311,47001,46873,47148,46399,45777,46325,46876,46793,45582,46126,46074,46261,46328,46362
# 6G K values for 11AZ
az_offset_perbw_6g=0,0,0,0,0
az_160mkval_6g=13313,12772,13233,13233,13525,13233,13233
az_80mkval_6g=12150,12054,10236,11790,11639,11702,11702,11702,12193,12009,11884,11884,11884,11884
az_40mkval_6g=17294,16270,16763,16505,15815,14806,15882,16717,16194,16066,16522,16138,16138,16138,16598,17219,16648,16889,16534,16687,15896,15993,15993,15993,15993,15993,15993,15993,15993
az_low_20mkval_6g=46788,46239,45908,45320,45462,45998,45870,46330,45678,44962,44340,46036,45767,46061,45936,45888
az_mid1_20mkval_6g=45761,45834,45997,45195,46005,46635,45753,45518,45518,45518,45518,45518,45518,46581,46121,46365
az_mid2_20mkval_6g=46183,46890,46410,47017,46796,46276,45979,46298,46663,46456,46029,45569,45632,46386,46386,46386
az_high_20mkval_6g=46386,46386,46386,46386,46386,46386,46386,46386,46386,46386,46386
# Base K Values (For the VHT case 5G 160 & 5G80/40/20/2G20)
proxd_basekival_5g_160=15539
proxd_basektval_5g_160=15539
proxd_basekival=12578,17825,47486,0
proxd_basektval=12578,17825,47486,0
# Offsets across channels (Upper nibble for target, lower nibble for initiator - saved in hex)
proxd_160mkval=0x0101,0x0000
proxd_80mkval=0x0202,0x0101,0x0000,0x0101,0x0505,0x0101
proxd_40mkval=0x0303,0x0303,0x0202,0x0202,0x0000,0x0202,0x0202,0x0303,0x0505,0x0404,0x0202,0x0303
proxd_20mkval=0x0505,0x0606,0x0505,0x0202,0x0202,0x0202,0x0101,0x0000,0x0404,0x0202,0x0505,0x0303,0x0101,0x0404,0x0404,0x0303,0x0505,0x0606,0x0606,0x0505,0x0505,0x0303,0x0404,0x0303,0x0303
proxd_2gkval=0
# Offsets across frame formats @ Initiator
# Only for non-VHT frame (Leg6, Leg non-6, mcs0, non-mcs0)
# Delta between the base values are adjusted here
proxdi_rate80m=0,0,0,0
proxdi_rate40m=0,0,0,0
proxdi_rate20m=0,0,0,0
proxdi_rate2g=0,0,0,0
proxdi_ack=0,0,0,0
# Offsets across frame formats @ Responder
proxdt_rate80m=0,0,0,0
proxdt_rate40m=0,0,0,0
proxdt_rate20m=0,0,0,0
proxdt_rate2g=0,0,0,0
proxdt_ack=0,0,0,0
# Offsets for sub-bands (VHT, Leg6, Leg non-6, mcs0, non-mcs0)
proxd_sub80m40m=0,0,0,0,0
proxd_sub80m20m=0,0,0,0,0
proxd_sub40m20m=0,0,0,0,0
proxd_sub80m40m_ch_off=-206,19525,18144,18762,22935,-230
proxd_sub80m20m_ch_off=-194,9574,8212,9629,9695,-255
proxd_sub40m20m_ch_off=-200,-119,-353,-1210,-1938,-1604,451,-68,-646,-1120,-218
proxd_sub160m80m_ch_off=4741,7126
proxd_sub160m40m_ch_off=18779,20913
proxd_sub160m20m_ch_off=10464,11070

# olpc temp offset
slice/1/olpc_tempslope2g=-78,-78
olpc_tempslope5g=-78,-78
olpc_tempslope6g=-78,-78